TWI337001B - Methods and systems for clock control - Google Patents

Description

1337001, IX, invention description:

«I [Technical Field to Be Invented by the Invention] In particular, the present invention relates to a clock control method and a system related to a clock control method and system for a clock chip:, '[Prior Art] Use - clock control unit or clock (four) day ^ ^ for a variety of different clock output, to control different components in the system, such as medium = management order _u), plus _ transfer material ((10) ed edqing (10) p〇rt , I week red component interface (pe away from the element component interface, PCI) or = prss (clear) interface, etc. Traditional clock chip can provide a number ^ ^ ^ (doc. scce), output 'for - for The use of components, for example, the clock source cpucLK can provide a wide-day deleted clock output. For traditional clock chips, control::峨: (4) can be used to control two:::: Control a 'two or three hardware pins to control each, however, as the design of the system becomes more and more complex, the number of clock sources of the clock chip will also increase. At that time ^: increase or need to add more The dynamic control of the components: two: the traditional financial control type is bound to be mixed (four) and bribes must follow .

Client's Dockei No.: VHO6-0118-TW ΓΓ-s Docket N〇〇608-A41〇63-TW/Final/Jasonlcung/ 5 1337001, [Summary of the Invention] «> In view of this, the object of the present invention is The invention provides a clock control method 4 and a related control system, which realizes control of the group clock source with a small number of hardware pins, and is advantageous for future expansion. ^The above object 'The present invention provides a clock control method for controlling a complex clock source-clock control unit, comprising the following steps: providing a ^^t±t#(cl〇ck stop data), ^ =I stop and refer to the clock to generate a complex clock (four) signal to the output of the clock source. Wherein, each of the clock sources has a corresponding clock control - the invention further provides a seed control (10) system, including at least - a clock control list::: to control the complex clock source, and the clock control unit includes at least one The multiplexed module is based on a clock stop data and a reference time signal to produce the output of the clock sources. Shi: The source has a corresponding clock control signal. One of the sources provides r-type clock control method 'stabbing to the money-time pulse', and the clock-based control method includes receiving: a clock stop data, a reference clock signal, a solution, a first time pulse control The other number, (a) = time ^ to generate at least the clock sources - the first clock control signal corresponds to the signal, control the clock of the first - clock source | ^ according to w The above and other objects, features, and advantages of the Excise 2 can be more clearly described below. a case' and with the drawings, for details

Client's Docket N〇.:VIT06-0118-TW ΊΤ s Docket No^6〇8-A41063-TW/FinaI/Jas〇nkung/ 6

«I «I1337001 [Embodiment] Embodiments of the present invention provide a method for controlling a M-day of a clock unit to which the method is applied, and a pulse control method for a system having a complex clock source, which is particularly suitable for use. . According to the material of the material (4) method and system" design and decoding of a multiplexed module, the control signal controls the clock output of the corresponding clock source, and the pulse foot controls more clock sources. 'Even if the source of the pulse is increased in the future, the connection of ± ο: the hardware pin of the second 卜' is as long as the format of the clock stop data is changed: t 1st 帛 1 shows a clock control unit 1 command. The clock control unit includes a vibrating unit, a frequency division number = a control board group 130, and a stop logic circuit 14 (), wherein the vibration 110 is coupled to the frequency division H 120, and the stop logic circuit 140 is The oscillator 11 is coupled to the control module 13A. The oscillator 11 receives the external parameters X and X2 to generate a reference frequency, and is divided into a plurality of sub-frequency by the frequency divider and (10)=the reference frequency. An array clock sfl number having different frequencies is provided. The control module 13 receives the externally input control signals CPUSTOP, pCIST0P, and PCIEST〇p, and outputs a selection signal to the stop logic circuit 140 according to the control signals. Stop logic circuit 140 has an array clock source (ci〇ck s〇urce), when After receiving the selection signal from the control module I%, the clock output corresponding to the clock source of the selection signal is controlled according to the selection signal. In this embodiment, the stop logic circuit 140 has three clock sources respectively. CPUCLK, pciclk, and

Client's Docket N〇.:VIT06-0118-TW TT's Docket No:〇6〇8-A41〇63-TW/Final/Jasonkung/ 7 1337001 , PCIECLK '·, and a set of clock sources can provide the same frequency but different phases The two clock outputs, for example, the clock source CPUCLK can generate two clock outputs of CPUCLK1 and CPUCLK2, and the frequency of CPUCLK2 is the same as the frequency of CPUCLK1, but CPUCLK2 has a phase difference with CPUCLK1. For example, CPUCLK2 can be the inverted output of CPUCLK1. For example, if the control module 130 receives the control signal CPUSTOP, the stop logic circuit 140 outputs a selection signal of the clock source CPUCLK to control the clock source CPUCLK corresponding to the control signal CPUSTOP according to the level of the selection signal. Clock output, such as the clock output of the pulse source CPUCLK when starting or starting. In other words, the control signal CPUSTOP can control the clock output of the clock source CPUCLK. Similarly, the control signals PCISTOP and PCIESTOP can be used to control the clock output of the clock source PCICLK and PCIECLK, respectively. See Figure 2. Fig. 2 shows a timing chart of the clock control unit 100 shown in Fig. 1. In this embodiment, the control signals CPUSTOP and PCISTOP are respectively used to control the clock source CPUCLK and PCICLK', and the clock source CPUCLK in the embodiment can generate the clock required for the CPU operation, and the clock source PCICLK can be Produces the clocks needed to comply with PCI operations. As shown in the figure, before time 11, the output voltage levels of the control signals CPUSTOP and PCISTOP are in the high level state, so the clock sources CPUCLK and PCICLK respectively provide the clock output of the predetermined frequency. At time t1, the output voltage level of the control signal CPUSTOP changes from the 咼 level state to the low level state, so the clock source CPUCLK stops the clock output accordingly. Similarly, at time t2, the control signal

Client's Docket N0/.VITO6-OI 18-TW TT s Docket No:0608,A41063-TW/Final/Jasonkung/ 8 1337001 -PCISTOP #Input voltage level also changes from high level state to low level state, The clock source PCICLK stops the clock output accordingly. Thereafter, at the time u', the output voltage level of the control signal CPUST0P changes from the low level state to the quasi-only state, and then the clock source CPUCLK re-outputs the clock accordingly. Similarly, at time t2', the output voltage level of the control signal PCIST0P also changes from the low level state to the high level state, so that the clock source PCICLK re-outputs the clock accordingly. It can be seen from the above that when it is necessary to control the _ one-time pulse source, it is only necessary to change its corresponding control signal. In this embodiment, the set of clock sources requires a different control signal to control. If the clock control unit 100 wants to add more sets of clock sources, it is necessary to add a lot of control signals, and more hardware pins can be used to achieve the goal', so that the number of pins and the volume of the wafers are relatively increased. Figure 3A shows a schematic illustration of a clock control unit 300 in accordance with an embodiment of the present invention. The clock control unit 300 includes an oscillator 310, a frequency divider 320, a control module 33A, a stop logic circuit 34, and a demultiplexing module 350. The oscillator 310 is coupled to the frequency divider 320, the demultiplexing module 350 is coupled to the control module 33A, and the stop logic circuit 34 is coupled to the frequency divider 320 and the control module 33A. The functions of the oscillator 31A, the frequency division 320, the control module 330, and the stop logic circuit 34A in FIG. 3 are similar to the oscillator 110, the frequency divider 12, and the control module 13 in FIG. And the function of the stop logic circuit 140, so the details are omitted here. The stop logic circuit 340 has a clock source CLK1-CLKM, M>1, and each clock source CLKx includes two clock outputs CLKx(〇) and CLKx(1), where CLKx(1) and CLKx(〇) are the same frequency but different phases. Two kinds of clocks

Clients Docket N〇.:VIT06-0118-TW TT^s Docket No:0608-A41063-TW/FinaI/JasonIcung/ No. 9. The multi-mode modulo 4, and the M round-out Γ /, one clock input end, one data input end can be used to connect the data, and the clock input end is coupled to a reference clock signal MCLK, and the two are obtained. The input data CLK-STOP solves the stone horse, among which, one of the M output outputs. The connection to (4) is related to the total number of clock sources. The first wheel-out terminal system 350 solves the work ^ 330, so that the control module can generate the -select signal to stop CLh when the control signal - corresponding control signal according to the multiplexer stop logic circuit ST 〇 PX ST〇PX clock source stop data 2 where 'input data CLK_ST〇1^ is - when - Nanlin Day μ secret clock control unit - chip group (example β, I曰曰矣 and 360) Provided as shown in Figure 3. It is worth noting that the second-line 2 control unit 3〇0 and the south-bridge chipset 360 can be placed in the same--the invention. Therefore, the present invention (4) can be implemented in a control system having a clock control unit and a chipset according to ▲. Included as a fixed material CLK-ST0P is a fixed type of data, including f &, _ start segment and - end segment, and the data segment is between the start segment and the end segment of the start segment It is used to indicate the end position of the clock 1 stop gong, and the start and end segments are a smashing content. When the demultiplexing module 350 in the current pulse control unit 300 receives the clock stop data, it can ride and decode on the rising edge or the falling edge of the reference clock signal MCLK according to the fixed mode. The data segment of the clock stop data is related to the total number of time-exaggerated pulse sources. For example, when the total number of clock sources is 4, the length of the data segment is 4, and when the total number of pulse sources becomes 16, the material The length of the segment becomes 16. Each control signal is ordered (10) in the data segment - corresponding control

Client's Docket N〇.:VIT06-0118-TW TT's Docket N〇:0608-A41063-TW/Finaiyjasonkung/ 10 1337001 The signal ST 〇Px's round-robin health level, when the control system πΐ ST〇i = ·Χ The output voltage level also changes. Control voltage level can be controlled - corresponding to (four) pulse source TM output " ° so ' can be used to control the clock source of the clock source by this control data because the 丨 4 group (South Bridge chip 'group 360) can get the source of the clock source Information about pulse control needs, such as when to start/stop at that point in time

(4) - The established clock control requirement 'generates the appropriate clock stop data CLK_S1OP in accordance with the established format to reach the clock source of the control clock control unit (4). For example, the chipset can arrange the position and content of the control body in each data segment according to the start/stop sequence of each clock = to meet the established clock control requirements.凊同h refers to FIG. 3A and FIG. 4 . Fig. 4 is a view showing a method of clock control according to an embodiment of the present invention. (4), in step S4H)j, the clock stop data and the reference clock signal are supplied to the pulse control unit 3G0. Please note that 'this reference clock signal can be an external air number or directly generated from the inside of the clock control unit, and the clock stop data is generated by a chip set, and the format of the clock stop data is as described above. A control signal in the data segment has a corresponding bit. In this embodiment, a total of three clock sources CLK1_CLK3 need to be controlled, and the clock stop I data CLK_STOP is represented by a bit B〇_B6 from left to right, wherein the bit B0-B1 represents In the beginning, the bit B2_B4 represents the data segment, the bit as shame indicates the end segment, and the bit B2 represents the control data of the clock source CLK1, the bit B3 represents the control data of the clock source CLK2, and the bit B4 represents the Japanese

Client’s Docket No.: VIT06-0118-TW TT5s Docket N〇: 〇608-A41063-TW/Final/Jasonkung/ 1337001 • Source CLK3, control data. Then, at the beginning of the step, the clock control unit 300 stops the hopper (10) and the enthalpy MCLK according to the received clock, and generates a clock control signal ST〇pi~ST〇pM, and the bean Μ indicates the clock control signal. The number is related to the total number of sources. The clock control signal ST〇PX is used to control the clock output of a corresponding clock source CLKx, for example, the clock control signal ST〇P1帛 to control the clock output of the clock source clki, the clock control signal ST〇P2 Used to control the clock output of the source source rainbow 2, and so on. Then, in step _, the clock control unit 3 can control the clock output of the clock source clkx of the clock control unit 300 according to the clock control signals & ST〇px. For example, when the clock source of the clock source CLK1 is to be output, the bit το B2 of the clock stop data cLK_sTOp can be set to “1”, so that the output level of the clock control signal ST〇pi is a local level. The pulse source CLK1 outputs a clock CK1; when the clock of the clock source clki is stopped, the bit of the clock stop data CLK_ST〇p can be set to '〇,', the clock control signal ST0P1 The output level is reduced to a low level, and the clock source CLK1 stops the output of the clock CK1. Fig. 5 shows another schematic diagram of a clock control method in accordance with an embodiment of the present invention. Please refer to both Figure 3A and Figure 3B. In step S51, the south bridge chipset 360 generates a clock stop data CLK_STOP according to a predetermined clock control request. For example, the clock stop data CLK_ST〇p is a fixed format data, including a data segment, a start segment, and an end segment. Then, in step S520, the multiplex module 35 receives the clock stop data CLK. - STOP, and generate a corresponding control signal according to a reference clock signal MCLK and the content of the clock stop data CLK - STOP

Client's Docket No.: VIT06-0118-TW . TT's Docket N〇: 0608-A41063-TW/Final/Jasonkung/ 12 1337001 STC> PX ° Assume that the reference clock signal MCLK is a clock signal with a fixed period, and the initial At the time, the output level of the clock stop data CLK_STOP is at a high level. Since the demultiplexing module 350 is coupled to the control module 330, the control signal sT〇px generated in step S520 is sent to the control swap group 330. Then, in step s53, the control module 33 generates a -select signal to the stop logic circuit 340 according to the received control signal STOPx to control the clock output corresponding to the clock source of the control signal. Refer to Figure 6 for the δ month. Fig. 6 is a timing chart showing the timing of a clock control unit it according to an embodiment of the present invention for explaining the relationship between signals. In the timing diagram 600, CLK_ST〇p represents the signal output of an input data terminal, MCLK represents a reference clock signal, cLKx represents the clock source of the clock control unit '❿CLKx_ST0P represents the clock source, and the clock control corresponding to CLKx §fi唬. Before time t1, the voltage level of CLKx_ST〇p is in the 冋 state, so the clock sources CLK1, CLK2, and CLK3 respectively output specific clock signals. Please note that the clock source CLK1 > CLK2 and CLK3 are for illustrative purposes only, and the present invention is applicable to clock control of various clock sources of the same or different sources, and is not limited thereto. At time u, the south bridge chipset 360 is required to perform clock control, and then generates a clock stop data 61〇 according to the clock control requirements provided by the system. The clock stop data 610 has a start segment a, a data segment B, and an end segment c, and wherein the contents of the start segment A and the end segment c are fixed. In this embodiment, the length of the data iron B is 8, indicating that there are eight clock sources CLK1-CLK8' in the clock control unit and that the control data 1_8 correspond to the clock sources CLK1-CLK8, respectively.

Client's Docket N〇.;VIT06-0118-TW TT's Docket No:0608-A41063-TW/Final/Jasonkung/ 13 1337001 , the start segment A of the clock stop data 61〇 causes the output voltage of the input data terminal CLK_STOP to be in time When u is changed from the high-level state to the low-level state and remains at the low-level state at time t2, it indicates that the data segment B having the control data 1-8 is about to start to be transmitted. At time t3, the level of the input terminal CLK_STOP is a low level state, indicating that the control data i = stops the clock of the corresponding clock source CLK1, thus changing the control signal CLK1_ST0P to the low level. At this time, since the control signal CLK1_ST0P is at a low level, the clock source CLK1 stops the clock output, and the clock outputs of the clock sources CLK2 and CLK3 are not affected. At time t4, the control data 2 is to be controlled. The corresponding clock source acLK2 clock output is stopped, and at time t5, the control data 3 stops outputting the corresponding clock source CLK3 clock, so the control \ hole numbers CLK2_STOP and CLK3_ST〇p are respectively changed. The low level causes the clocks CLK2 and CLK3 to stop the clock output at times t4 and t5, respectively. Thus, at time t6-tl0, the clock sources CLK1, CLK2, and CLK3 are compared to the clock output. At time t1, the data segment B has been transmitted, because: the end segment C is transmitted, so that the output voltage of the input data terminal CLK_ST〇p is at the time of the time til from the high level state to the low level state. And at time ^ tl2 changes from the low level state to the high level state, indicating that the clock stop data = the transmission has ended. Thus, the demultiplexing module 35 stops the decoding operation. In this embodiment, although the clock control unit 3 has 8 clock sources, only 2 physical pins are needed for transmitting a pulse stop data and a reference clock signal, which can be separately controlled. There are 8 clock sources, which can be used by six physical entities. Even if the clock control unit needs to be increased in the future

Client's Docket N〇.:VIT06-0118-TW TT's Docket No:0608-A41063-TW/Final/Jasonkung/ 11337001 - Control of the clock source of the group, no need to add extra pins, just change the clock stop data The length of the data segment is very easy to expand. It is assumed that after a period of time, when the clock of the clock source CLK1-CLK3 is to be re-outputted, 'the chipset can provide a clock stop data 620' as shown in the figure and arrange the contents of the data segment to stop the data. The control data 1-3 in 62〇 is set to "1", respectively, so that the control signals CLK1_ST0P, CLK2_STOP, and CLK3_STOP can become high level at times t3, t4, and t5', respectively, so that the clock source The clock of CLK1-CLK3 is re-output. For example, please refer to Figure 7. Figure 7 shows another timing diagram 700 in accordance with an embodiment of the present invention. In this embodiment, it is assumed that there are three clock sources CPUCLK, PCICLK and PCIECLK in the clock control unit, which can be controlled by the clock control signals CPUSTOP, PCISTOP and PCIESTOP respectively, wherein the clock sources CPUCLK, PCICLK and PCIECLK can be respectively generated. Complies with the clock required for cpu, pci, and PCIE interface operation Φ. As shown in the figure, before the time t1, the voltage levels of the clock control signals CPUSTOP, PCISTOP and PCIESTOP are in the high level state, so the clock sources CLIO, CLK2 and CLK3 respectively output specific clock signals. At time t1, the south bridge chipset 36〇 generates a clock stop data 71〇 according to the clock control requirements provided by the control system. In this embodiment, the length of the data segment of the clock stop data 71〇 is 3, indicating that there are three clock sources in the clock control unit that need to be controlled, and the first control data in the data corresponds to the clock source CpuCLK. The second control data corresponds to the clock source PCIECLK and the third control data corresponds to the time

Client's Docket N〇.:VIT06-01I8^TW TT's Docket No:0608-A41063-TW/Final/Jasonkung/ 1337001 * Pulse source PCICLK. The clock pulse, Bu Shen, 1, the first segment of the stop 710 causes the output voltage of the input data terminal CLK_STOP to be at the time u from the high level state to the low level state and remains at time 12 It is a low-level state, indicating that the data segment with control data is about to start to be transmitted. At time t3, the level of the input data terminal CLK_ST〇P is in the low level state, and the corresponding control signal CPUSTQP is changed to the low level. At this time, since the control signal cpusT〇p is at a low level, the clock source CPUCLK stops the clock output, and the clock source of the clock source PCIECLK and PCICLK is not affected. Similarly, when t4 and time t5 between the temples, the level of the input data terminal CLK_sT〇p is

The low level is sad, so the control signals pciEST〇p and PCISTOP are respectively changed to the low level so that the clock sources PCIECLK and PCICLK stop the clock output at times t4 and t5, respectively. At time t6, the data segment has been transmitted, so the output voltage level of the input data terminal CLK_STOP changes from the south level state to the low level state and from the low level state to the high level state at time t7. Indicates that the transmission of the clock stop data 71〇 has ended. Thus, the demultiplexing module 350 stops the decoding operation.

Similarly, after time t', the chipset wants to re-output the clock source of the clock source as shown in the figure, and provides a clock stop data 720, so that the output voltage of the input data terminal CLK_STOP is located at time ti. The high level state changes to the low level state, and remains at the low level state at time t2', and the demultiplexing module 350 then starts decoding, and stops according to the clock at times t3, t4, and t5'. The contents of the data 720 cause the control signals CPUSTOP, PCIESTOP, and PCISTOP to become high levels at times t3, t4, and t5', respectively, so that the clock source CPUCLK, PCIECLK

Client's Docket N〇.:VIT06-0118-TW TT*s Docket No:0608-A41063-TW/Final/Jasonkung/ 1337001 - and the clock of PCICLK is re-rounded. In summary, with the clock control method and the clock control unit of the embodiment of the present invention, although the clock source is increased, the pin and the volume of the clock control unit need not be increased, and the time to be controlled can be easily expanded. Pulse source. The above description provides several different embodiments or different methods of applying the invention. The specific devices and methods in the examples are intended to help explain the main spirit and purpose of the invention, and the invention is not limited thereto. Therefore, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention, and any one skilled in the art can make some changes and refinements without departing from the spirit and scope of the invention. ^ The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an embodiment of a clock control unit. Figure 2 shows a timing diagram of the clock control unit not shown in Figure 1. Figure 3A is a diagram showing a pulse control in accordance with an embodiment of the present invention. Second morning

Figure 3B is a schematic diagram showing a clock control system in accordance with an embodiment of the present invention. The Fig. 4 is a view showing a clock control method according to an embodiment of the present invention. FIG. 5 is a view showing another clock control method according to an embodiment of the present invention. Figure 6 is a timing diagram showing a clock control unit in accordance with an embodiment of the present invention.

Client's Docket N〇.: VIT06-0118-TW TT^ Docket Ν〇: 0608-Α41063-TW/Final/Jasonkung/ 1337001 Figure 7 shows a timing diagram in accordance with an embodiment of the present invention. [Main component symbol description] 1 〇〇 ~ clock control unit; 110 ~ oscillator; 120 ~ frequency divider; 130 ~ control module; 140 ~ stop logic circuit;

X Bu X2 ~ reference signal; CPUSTOP, pciSTOP, PCIESTOP ~ control signal; CPUCLK, PCICLK, PCIECLK, CLKx ~ clock source; CLKx (0), CLKx (1) ~ clock wheel out · CPUCLIQ, CPUCLK2, tl_tl2, ~ time; 00~clock control unit; 310~vibration unit; 320~divider; 330~control module; 340~stop logic circuit; 350~solution multiplex module; 360~ south bridge chip set; MCLK~ reference clock Signal; CLK_STOP~clock stop data; STOPx, CLKx_STOPx~ control signal; SELx~select signal; S410-S430~ step;

Client’s Docket No.: VIT06-0118-TW XT's Docket No: 0608-A41063-TW/Final/Jasonkung/ 18 1337001 S510-S530~Lifeline; 610, 620, 710, 720~clock stop data.

Client’s Docket N〇.:VIT06-0118-TW TT’s Docket No:0608-A41063-TW/Final/Jasonkung/

Claims (1)

1337001 1337001 Amendment to the case number 096113008 July 7th, 1999 10 application for patents: a clock control method for (4) and ancient - S0_) - clock control unit, including the lower step of the town has a complex clock source (cl〇ck number; clock 停 卿 o o o o o o o o o o o o o o o o o o o o o o _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The source has a corresponding axis control signal. Material B#r/肖专· (4) The method of the clock (4), wherein the step of connecting the data for the age and the reference clock includes: · private, according to the demand of the clock control The clock stops the data. The clock control method as described in the π patent scope item has a data segment, and the data segment of the clock stop data is related to the total number of the clock sources. , as in the case of the clock (4) as described in the 3rd item of Shen Yu (4), the = source of the clock is in the data section of the clock stop material - corresponding to ^ 5. As in the third paragraph of the patent application scope In the clock control method, the pulse stop data has a - start segment and an end segment, and the data segment is between the start segment and the end segment at the second time. The time-sharing method of the third item, wherein the test clock signal has a-level, and the clock control signal is generated according to the clock stop data and the reference clock signal to control the clock sources. The steps involved in the second step include: Wheel VIT06-0118-TW/0608-A41063-TW/Final 1 20 13,37001 . ~~~—— ..- &quot; . 彳%%======================= The level of the signal is changed; and the w$code_pulse stop is based on the output of the decoding number of one of the clock stop data.夂β海荨蛉脉控控7. If the time control signal is as low as the level mentioned in the sixth paragraph of the patent application, stop the clock source and the one of the control signals Source clock output. ',, ... the clock 8 · If the clock described in item 7 of the patent application is controlled after the clock of the one-time source is stopped, the use of the first includes: re-converting the clock-like clock. The information is as follows: 9. If the full-time (4) item is the clock (4), the source of the clock is generated by the vibrator and the _. Among them, the clock stop data is generated by the chipset as described in the application for the special plant. The financial method 'which makes the 11' clock control system, at least includes a clock control unit for controlling the copy unit to include at least: wherein the time pulse control-solution multi-module, according to the - clock stop The data and the pulse of the heart's generation of complex clock control signals, / test output, the city] ° Hai 荨 clock source of each - these clock sources have a corresponding time pulse control 12. If the patent application _ The clock control described in item u is controlled. The clock control unit further includes a _ and "Silicon" to generate the clock sources. ', member, for production VIT06-0118-TW/0608-A41063-TW/Finall 21 1337001 • Only The clock control system described in the U.S. Patent Application Serial No. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; And a stop logic circuit coupled to the control module, wherein the control P, 'based on the clock control signals, so that the stop logic circuit controls the clock output of the clock sources. The clock control system described in the scope of patents further includes a chipset 'for generating a clock stop data according to a predetermined clock control requirement. a 15. As stated in the scope of claim 帛u The clock control system has a data path that has a data segment and the length of the data segment of the clock stop data is related to the total number of the clock sources. A 16. For example, please patent scope 帛15 The clock control system of the item, wherein each of the clock sources stops the data at the clock There is a corresponding control data in the data segment. 17. The clock control system according to claim 15 of the patent application, wherein the clock stop data has a start segment and an end segment, and the data segment is Between the start segment and the end segment. lj. A clock control method for a clock control unit having a complex clock source, comprising the steps of: receiving a clock stop data; and - reference clock signal Decoding the clock stop data to generate a first-clock control signal, wherein the first-clock control signal corresponds to one of the first clock sources of the clock sources; and according to the first Clock control signal, controlling the clock of the first clock source VIT06-0118-TW/0608-A41063-TW/Final 1 22 ui/υυι作广) Month) R correction exchange page The clock control method described in 18 items is more rounded. I9. If the scope of the patent application includes: 2 According to the clock control requirements of the two, the clock stop is generated. 20. The clock control party as described in claim 18 of the patent scope goes: There is a data segment, and the length of the greedy segment of the clock stop data is related to the total number of the clock sources. In the clock control method described in item 2 of the patent application, the source of the clock source has the control data in the data segment of the clock stop data. VIT06-0118-TW/0608-A41063-TW/Final 1 23