TWI335630B - Pad configuration of die and manufacturing method thereof - Google Patents

Description

1335630

达达编号号: TW3008PA IX. Description of the Invention: [Technical Field] The present invention relates to a wafer pad configuration and a method of fabricating the same, and more particularly to an interleaved wafer pad configuration using conductive bumps And its manufacturing method. [Prior Art] As the size of electronic components is shrinking, the pitch of the wafer pads needs to be continuously reduced. However, if the pad is coupled to the outside, the pad may be misaligned or touched by different signal wires when the wire is connected or flipped. In order to avoid this problem, the original linearly arranged wafer pads (including metal pads and conductive bumps) are often changed to a staggered configuration. However, the wafer area may increase and the layout of the electronic components needs to be fully adjusted. SUMMARY OF THE INVENTION The present invention relates to a wafer pad configuration and a method of fabricating the same, which can retain a metal pad of an original linear configuration, and realize a staggered wafer pad with conductive bumps without increasing the wafer area and not comprehensively. Under the premise of adjusting the layout of each layer of electronic components, the problem of wafer misalignment or different signal line touches is solved. According to the present invention, a wafer pad arrangement is provided, including a substrate, a protective layer, and a plurality of staggered first conductive bumps and second conductive bumps 1335630

Sanda number: TW3008PA block. The substrate has an active surface on which a plurality of linearly arranged metal pads are disposed. The protective layer covers the active surface and the metal pad, and the protective layer forms a plurality of contact holes, and the contact holes respectively correspond to the metal pads, thereby exposing a part of the metal pads. Each of the first conductive bumps and the second conductive bumps respectively correspond to a contact hole, wherein the first conductive bump is coupled to the metal pad through the corresponding contact hole, and the second conductive bump is coupled to the metal pad through the corresponding contact hole Connected and extended to the inside of the wafer. In accordance with the present invention, a method of fabricating a wafer pad arrangement is provided, including the following steps. First, a substrate is provided having an active surface. Next, a plurality of linearly arranged metal pads are formed on the active surface. Then, a protective layer is formed on the active surface, the protective layer covers the metal pad, and the protective layer forms a plurality of contact holes exposing the metal pad. Then, a plurality of staggered first conductive bumps and second conductive bumps are formed, and each of the first conductive bumps is coupled to a metal pad through a contact hole, and each of the second conductive bumps includes a coupling metal pad and One of the wiring portions extending inside the wafer and one of the connecting portions formed on the inner side of the wafer. In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings. FIG. 1 A wafer pad configuration of the preferred embodiment. The wafer 100 includes a substrate 110, a protective layer 120, and a plurality of staggered first conductive bumps and second conductive bumps 140. The substrate 110 has an active surface 112, and a plurality of 1335630 are disposed on the active surface 112.

Three-sided: TW3008PA • Linear mat 114. The protective layer 120 covers the active surface 12 and the metal pad 114, and the protective layer 120 forms a plurality of contact holes 122. The contact holes 122 correspond to the metal pads 114, thereby exposing a portion of the metal pads 114. The contact hole 122 includes a first contact hole i22a and a second contact hole 122b'. The first contact hole 122a and the second contact hole 122b correspond to the first conductive bump 130 and the second conductive bump 140, respectively. The first contact hole 122a and the second contact hole 122b are formed on the outer side and the inner side of the wafer, respectively. Each of the first φ conductive bumps 130 and the second conductive bumps 14 对应 respectively correspond to a first contact hole 122a and a second contact hole 122b. In addition, each of the second conductive bumps 140 has a wire connecting portion 142 coupled to the second contact hole 122b and extending to the inner side of the wafer, and a connecting portion 144 connecting the wire portion 42 and formed on the inner side of the wafer. The width of the routing portion 142 can be designed to be smaller than the width of the connecting portion 144 <lt; to save material. In addition, the width D2 of the second contact hole 122b may also be designed to be smaller than the width D1 of the first contact hole 122a to correspond to the width of the small trace portion 142. • Refer to Figures 2A and 2B, which respectively show cross-sectional views of the line 8' and the line BB' along the line in Figure 1. As shown in Fig. 2A, the first conductive bump 13 is rotated through the corresponding first contact hole 122a and the metal pad 114. As shown in FIG. 2B, the trace portion H2 of the second conductive bump 140 is coupled to the metal pad 114 via the corresponding second contact hole 122b. Between the traces 142 of the first conductive bumps 130 and the second conductive bumps 140 and the metal pads 114, an under bump metal (UBM) 'Y is preferably provided to ensure conductive bumps and metal pads. The adhesion between 114. By staggering the first conductive bumps 130 and the second conductive bumps 1335630

The three-dimensional number: TW3008PA 140, coupled with the linearly arranged metal pads 114 through the staggered first contact holes 122a and second contact holes 122b, can form a staggered wafer pad. Since the metal pads 114 on the substrate 110 are still linearly arranged, the wafer area is not additionally increased and the layout of the electronic components is not required to be fully adjusted. The wiring portion 142 of the second conductive bump 140 is extended on the insulating protective layer 120 toward the inside of the wafer and pulled apart from the first conductive bump 130. Therefore, with this embodiment, it is possible to effectively reduce the problem of wafer misalignment or different signal lines touching each other without additionally increasing the wafer area. Preferably, the routing portion 142 and the connecting portion 144 of the second conductive bump 140 can be formed of the same material and formed in the same process step to save cost. The material of the metal pad can be made of a metal having good electrical conductivity, such as aluminum. Next, a method of manufacturing the wafer pad arrangement of the present invention will be described. Please refer to FIG. 3, which is a flow chart showing a method for fabricating a wafer pad according to a preferred embodiment of the present invention, and also refers to the component numbers of FIG. First, as shown in Φ, step 301, a substrate 110 is provided. The substrate 110 has an active surface 112. Next, as shown in step 302, a plurality of metal pads 114 are formed on the active surface 112. Then, as shown in step 303, a protective layer 120 is formed on the active surface 112. The protective layer 120 covers the metal pad 114. The protective layer 120 is formed with a plurality of contact holes 122 exposing the metal pads 114. The protective layer 120 can be formed in the following steps. First, a layer of protective material is formed on the active surface 112. Next, a patterned photoresist layer is formed on the protective material layer. Then, according to 1335630

Sanda number: TW3008PA The patterned photoresist layer etches the protective material layer to form the protective layer 120. Then, as shown in step 304, a plurality of first conductive bumps 13A are formed, and each of the first conductive bumps 130 is coupled to a metal germanium 114 through a contact hole 122. Then, as shown in step 305, a plurality of second conductive bumps 14 are formed, and the second conductive bumps 14 are interleaved with the first conductive bumps 13 on the protective layer 120. Each of the second conductive bumps 140 includes a trace portion 142 and a connecting portion 144. The trace portion 142 is coupled to a metal pad 114 through a contact hole 122 and extends to the inner side of the wafer. The connection portion 144 is connected to the trace portion 142. Formed on the inside of the wafer. The contact hole 122 includes a first contact hole 122a and a second contact hole 122b. The first contact hole 122a and the second contact hole 122b correspond to the first conductive bump 130 and the second conductive bump 140, respectively. The first contact hole 122a and the second contact hole 122b are formed on the protective layer 120 in a staggered arrangement. The width of each of the second contact holes 122b is smaller than the width of each of the first contact holes 122a. The width of each of the trace portions 142 is larger than the width of each of the second contact holes 122b. The width of the connecting portion 144 may be greater than the width of the routing portion 142 to save material cost and reduce the probability of the first conductive bump 130 and the second conductive bump 140 touching each other. Preferably, the wiring portion 142 and the connecting portion 144 can be formed of the same material and in the same process step, so that the wiring portion 142 and the connecting portion 144 can be simultaneously formed by the same mask process. The wafer pad arrangement and the manufacturing method thereof disclosed in the above embodiments of the present invention can be effectively avoided by forming staggered contact holes on the protective layer and staggering the conductive bumps and connecting the metal pads through the contact holes. Misalignment of the wafer and over-tightening of the wires cause different signal line collisions. And 1335630

• Sanda number: TW3008PA 'The second conductive bump is extended internally by an appropriate distance through the wiring portion of the second conductive bump to ensure the reliability of the overall component. The wiring portion 142 and the connecting portion 144 can be formed in the same reticle process by the same material, so that the number of reticle processes is not increased and the manufacturing cost is increased. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is defined by the scope of the appended claims.

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No. TW3008PA [Simple description of the drawings] ^1, 曰, 曰 本 — — — — — — — — — — — 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片The first figure shows the section along the section line BB in Figure 1, and the flow diagram 3. Figure (4) The material 1 New Zealand #_ pure (four) manufacturing method

[Main component symbol description] 100: Wafer 110 substrate 112 Active surface 114 Metal 塾 120 Protective layer 122 Contact hole 122a: First contact hole 122b: Second contact hole 130 First conductive bump 140 Second conductive bump 142 Trace Portion 144 Connection 150 : Metal lining

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Claims (1)

1335630 . 达达编号·· TW3008PA X. Patent application scope: 1. A wafer interface configuration comprising: a substrate having an active surface on which a plurality of linearly arranged metal pads are disposed; a protective layer covering The active surface and the metal pads, the protective layer forms a plurality of contact holes, the contact holes are corresponding to the metal pads, thereby exposing a portion of the metal pads; and I are a plurality of staggered first conductive bumps a bump and a second conductive bump respectively corresponding to the contact holes, wherein the first conductive bumps are coupled to the metal pads through the corresponding contact holes, and the second conductive bumps are in contact with each other The holes are coupled to the metal pads and extend to the inside of the wafer. 2. The wafer pad arrangement of claim 1, wherein the contact holes comprise a plurality of staggered first contact holes and second contact holes, the first contact holes and the second contacts The holes respectively correspond to the first conductive bumps and the second conductive bumps, and the first contact holes and the second contact holes are respectively formed on the outer side and the inner side of the wafer. 3. The wafer pad arrangement of claim 2, wherein the width of the second contact holes is smaller than the width of the first contact holes. 4. The wafer pad arrangement of claim 2, wherein the second conductive bumps respectively have a second contact hole coupled to the one of the inner side of the wafer, and the connection The wiring portion is formed on one of the inner sides of the wafer, and the width of the wiring portion is smaller than the width of the connecting portion. i 12 1335630 A. The wafer pad configuration of claim 1, wherein the wire portion and the connecting portion are the same material. 6. The wafer pad configuration of claim 1, wherein the first conductive bumps and the second conductive bumps and the metal pads further comprise a plurality of metal pads. 7. The wafer pad arrangement of claim 1, wherein the metal pads are made of aluminum. 8. The wafer pad configuration of claim 1, wherein the protective layer is made of tantalum nitride or tantalum oxide. 9. A method of fabricating a wafer pad arrangement, comprising: (a) providing a substrate having an active surface; (b) forming a plurality of metal pads on the active surface; (c) forming a protective layer thereon On the active surface, the protective layer covers the metal pads, and the protective layer forms a plurality of contact Ls exposing the metal pads; $ (d) forming a plurality of first conductive bumps, each of the first conductive bumps passing through The contact holes are coupled to one of the metal pads; and (e) forming a plurality of second conductive bumps, the first conductive bumps are staggered on the protective layer, and each of the second conductive bumps comprises a transparent conductive layer The contact holes are coupled to the corresponding metal pad and extend to one of the wiring portions inside the wafer, and are connected to the wire portion and formed at one of the inner sides of the wafer. 10. The manufacturing method of claim 9, wherein the contact holes comprise a plurality of first contact holes and a plurality of second contact holes, and the first contact holes and the second contact holes respectively correspond to And the first contact hole and the second contact holes are staggered on the protective layer. The first contact 13 1335630. The three-digit number: TW3008PA' electric bump and the second conductive bump are staggered on the protective layer. 11. The manufacturing method according to claim 10, wherein the width of each of the second contact holes is smaller than the width of each of the first contact holes. 12. The manufacturing method according to claim 10, wherein the width of each of the trace portions is larger than the width of each of the second contact holes, and the width of the connection portion is greater than the width of the trace portion. 13. The manufacturing method according to claim 9, wherein the ® wire portion and the connecting portion are formed of the same material. 14. The manufacturing method of claim 9, wherein the step (c) further comprises: (cl) forming a protective material layer on the active surface; (c2) forming a patterned photoresist layer thereon. And protecting (c3) the protective material layer according to the patterned photoresist layer to form the protective layer.