1303885 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種液晶顯示器元件，特別是有關於 一種薄膜電晶體陣列基板及其製造方法。 【先前技術】 一般液晶顯示器之製造可大致區分為薄膜電晶體陣列 基板製程、彩色濾光片基板製程、液晶注入及液晶顯示器 模組組裝。為了避免液晶顯示器背光源發出之光線從液晶 顯示面板之非顯示區散射至顯示區，因此常於非顯示區形 成一遮光結構，此遮光結構環繞顯示區之周邊設置，用以 防止因背光源之漏光造成顯示區之顯示畫質降低。 遮光結構可以設置於薄膜電晶體陣列基板，亦可以設 置於彩色濾光片基板，於一習知技藝，此遮光結構係與黑 色矩陣（Black Matrix)同時形成於彩色濾光片基板，此黑色 矩陣之材料通常使用鉻金屬，然而鉻金屬容易造成環境污 染。因此，於另一習知技藝，是以黑色樹脂取代鉻金屬， 此方法雖然可以改善環境污染的問題，但是黑色樹脂的遮 光性卻不如鉻金屬，因此可能產生顯示品質降低的問題。 於另一習知技藝，係於薄膜電晶體陣列基板之非顯示 區形成一遮光結構。參照第1圖，第1圖繪示一習知薄膜 電晶體陣列基板之上視示意圖，遮光結構114是一片狀的 金屬層，位於薄膜電晶體陣列基板11 〇之非顯示區i i 2，雖 然此遮光結構114具有良好的遮光效果，但是卻容易造成 片狀剝落的缺陷。另一習知薄膜電晶體陣列基板之遮光詰 1303885 構是形成複數個孔洞於一片狀金屬層上，此些孔洞是用以 避免遮光結構產生片狀剝落的情形，然而此些孔洞卻容易 造成漏光的現象。 如何改善遮光結構的設計，以兼顧環境保護、結構附 著性及遮光效果，是目前急需克服的問題。 【發明内容】1303885 IX. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display element, and more particularly to a thin film transistor array substrate and a method of fabricating the same. [Prior Art] The manufacture of a general liquid crystal display can be roughly classified into a thin film transistor array substrate process, a color filter substrate process, a liquid crystal injection, and a liquid crystal display module assembly. In order to prevent the light emitted by the backlight of the liquid crystal display from scattering from the non-display area of the liquid crystal display panel to the display area, a light-shielding structure is often formed in the non-display area, and the light-shielding structure is disposed around the periphery of the display area to prevent the backlight from being Light leakage causes the display quality of the display area to decrease. The light-shielding structure may be disposed on the thin film transistor array substrate or on the color filter substrate. According to a conventional technique, the light-shielding structure is formed on the color filter substrate simultaneously with the black matrix (Black matrix). The material is usually made of chrome metal, but chrome metal is liable to cause environmental pollution. Therefore, in another conventional technique, chrome metal is replaced by a black resin. Although this method can improve the problem of environmental pollution, the black resin is less opaque than chrome metal, and thus there is a problem that display quality is lowered. Another conventional technique is to form a light-shielding structure in the non-display area of the thin film transistor array substrate. Referring to FIG. 1 , FIG. 1 is a schematic top view of a conventional thin film transistor array substrate. The light shielding structure 114 is a sheet metal layer located on the non-display area ii 2 of the thin film transistor array substrate 11 , although This light-shielding structure 114 has a good light-shielding effect, but is liable to cause a defect of exfoliation. Another conventional thin film transistor array substrate has a plurality of holes formed on a piece of metal layer. The holes are used to prevent the light-shielding structure from being exfoliated. However, the holes are easily caused. Light leakage phenomenon. How to improve the design of the shading structure to take into account environmental protection, structural attachment and shading effect is an urgent problem to be overcome. [Summary of the Invention]
本發明之目的就是在提供一種薄膜電晶體陣列基板， 此薄膜電晶體陣列基板在非顯示區具有一遮光結構，此遮 光結構可以改善習知技藝產生環境污染的問題。 本發明之另一目的就是在提供一種薄膜電晶體陣列基 板，此薄膜電晶體陣列基板在非顯示區具有一遮光結構， 此遮光結構具有較佳之遮光效果及結構附著性。 本發明之又一目的就是在提供一種薄膜電晶體陣列基 板，此薄膜電晶體陣列基板在非顯示區具有一遮光結構， 此遮光結構可以提高共通電壓的穩定性。 很像以上所述之目的，提出_種薄膜電晶體陣列基 板’具有-顯示區及一非顯示區並且包括有一透明基板、 複數:畫素單元及-具有複數個遮光層之遮光結構。該些 畫素單元設置於該顯示區，每一該晝素單元包括有一薄膜 =晶體及-畫素電極。該遮光結構設置於該非顯示區/，其 該些遮光層具有複數個孔洞，且二相鄰之該些遮的 孔洞交錯設置。 曰 很據本發明一較佳實施例所述 /寻膜電晶體陣列基 板，其中該遮光結構包括有-第一遮光層與_第二遮光 1303885 層且該第一遮光層與该第一遮光層之孔洞交錯設置。 根據本發明一較佳實施例所述之薄膜電晶體陣列基 板’其中該薄膜電晶體具有一閘極層，該閘極層與該第一 遮光層位於同一膜層。 根據本發明一較佳實施例所述之薄膜電晶體陣列基 板，其中該薄膜電晶體具有一源極與汲極層，該源極與二 極層與該第二遮光層位於同一膜層。SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate having a light-shielding structure in a non-display area, which can improve the environmental pollution caused by the prior art. Another object of the present invention is to provide a thin film transistor array substrate having a light-shielding structure in a non-display area, the light-shielding structure having a better light-shielding effect and structural adhesion. It is still another object of the present invention to provide a thin film transistor array substrate having a light-shielding structure in a non-display area, which can improve the stability of the common voltage. Much like the above, it is proposed that a thin film transistor array substrate has a display area and a non-display area and includes a transparent substrate, a plurality of pixel units, and a light blocking structure having a plurality of light shielding layers. The pixel units are disposed in the display area, and each of the pixel units includes a film=crystal and a pixel electrode. The light shielding structure is disposed in the non-display area/, and the light shielding layers have a plurality of holes, and the adjacent holes of the two adjacent holes are staggered. According to a preferred embodiment of the present invention, the light-shielding structure includes a first light-shielding layer and a second light-shielding layer 1303885, and the first light-shielding layer and the first light-shielding layer. The holes are staggered. A thin film transistor array substrate according to a preferred embodiment of the present invention, wherein the thin film transistor has a gate layer, and the gate layer and the first light shielding layer are located in the same film layer. A thin film transistor array substrate according to a preferred embodiment of the present invention, wherein the thin film transistor has a source and a drain layer, and the source and the second layer and the second light shielding layer are located in the same film layer.
根據本發明一較佳實施例所述之薄膜電晶體陣列基 板，其中該非顯示區具有一連接層，該連接層與該畫素電 極位於同一膜層。 根據本發明一較佳實施例所述之薄膜電晶體陣列基 板，其中該連接層電性連接該第—遮光層及該第二遮光層。 根據以上所述之目的，更提出一種薄膜電晶體陣列基 板之製造方法，其步驟包括有：首先，形成_閘極層於一 透明基板之-顯㈣上，且同_成具有複數個孔洞之一 第一遮光層於透明基板之—非顯示區。接著，形成一絕緣 層覆蓋該閘極層與該第—遮光層。接著，形成―通道層於 “ Ά極層及該絕緣層上。接著，形成_源極與没極層於該 層^且同時形成具有複數個孔洞之—第二遮光層於 該非，不區，其中該第—遮光層之孔洞與該第二遮光層之 孔=乂錯认置°接著’形成-介電層於該顯示區及該非顯 不區。接著’形成複數個顯示區開口於該介電層，以暴露 §n、及極層。接著，形成—晝素電極於該介 之上。 晶體陣列基板 根據本發明一較佳實施例所述之薄膜電 1303885 之製造方法，其中該絕緣層與該介電層之材料相同。 根據本發明一較佳實施例所述之薄膜電晶體陣列基板 之製造方法，其中形成顯示區開口之步驟更包括形成複數 個非顯示區開口，該些非顯示區開口暴露出該第一遮光層 及該第二遮光層。 根據本發明一較佳實施例所述之薄膜電晶體陣列基板 之製造方法，其中形成晝素電極層之步驟更包括形成一連 接層，該連接層透過非顯示區開口電性連接該第一遮光層 及該第二遮光層。 根據以上所述之目的，更提出一種液晶顯示面板，具 有一顯示區及一非顯示區，該非顯示區包括一遮光區，該 液晶顯示面板包括有一彩色濾光片基板、一薄膜電晶體陣 列基板及一液晶層。其中該薄膜電晶體陣列基板具有複數 個晝素單元，該晝素單元位於該顯示區，每一該些畫素單 7G包含一薄膜電晶體及一晝素電極，該薄膜電晶體陣列基 板於該遮光區具有一第一遮光層及一第二遮光層，其中該 第遮光層及該第二遮光層分別具有複數個孔洞，並且該 第遮光層之孔洞與該第二遮光層之孔洞交錯設置。該液 日日層a又置於該彩色濾光片基板與該薄膜電晶體陣列基板之 間。 根據本發明一較佳實施例所述之液晶顯示面板，其中 該薄膜電晶體陣列基板包括有一透明基板、_第—圖案化 t電層、一絕緣層、一通道層、一第二圖案化導電層、一 介電層及一晝素電極層。該第一圖案化導電層形成於該顯 不區及該非顯不區，該第一圖案化導電層包括有該薄膜電 1303885 :ι:層及該第一遮光層。該絕緣層覆蓋該 ^第第^光層。該通道層形成於該閉極及該絕緣層上。 圖案化導電層形成於該顯示區及該非顯示區，該第 ^ I導電層包括有該薄膜電晶體之—源極與沒極層及 光層。該介電層形成於該顯示區及該非顯示區， k 電層具有複數個顯示區開口，該些 露出該源極與汲極層。該畫素電極層設置於:介電二暴 根據本發明-較佳實_所述之液晶顯示面板，其中 :二：：具有複數個非顯示區開口’該些非顯示區開口暴 路出該苐一遮光層及該第二遮光層。 根據本發明-較佳實施例所述之液晶顯示面板，更包 括有-連接層，形成於該非顯示區，該連接層透過該非顯 不區開D電性連接該第—遮光層及該第二遮光層。 /艮據本發明—較佳實施例所述之液晶顯示面板，其中 該第一圖案化導電層及該第二圖案化導電層之材料是金 =一根據本發明一較佳實施例所述之液晶顯示面板，其中 該彩色濾、光片基板於該遮光區具有—第三遮光層。 根據本發明一較佳實施例所述之液晶顯示面板，其中 其中該第三遮光層之材料是黑色樹脂。 本發明之薄膜電晶體陣列基板之非顯示區具有一第一 遮光層及一第二遮光層，該第一遮光層及該第二遮光層分 別具有複數個孔洞，因此可以避免遮光層產生片狀剝落的 情形。 本發明之薄膜電晶體陣列基板，由於該第二遮光層之 1303885 孔洞與該第一遮光層之孔洞交錯設置，因此不易產生漏光 現象。 本發明之薄膜電晶體陣列基板，由於該連接層電性連 接該第一遮光層及該第二遮光層，使該第一遮光層及該第 二遮光層之電位皆為共通電壓，因此可以增加共通電壓的 穩定性，進而增進液晶顯示面板之品質。 本發明之液晶顯示面板，該第三遮光層之材料例如採 用黑色樹脂，因此可以改善環境污染的問題。 【實施方式】 第2圖繪示根據本發明一較佳實施例之薄膜電晶體陣 列基板之上視示意圖。請參照第2圖，此薄膜電晶體陣列 基板200具有一顯示區230及一非顯示區232,並且包括有 一透明基板210、複數個晝素單元236及一遮光結構234， 其中畫素單元236設置於顯示區230,並且包括有一薄膜電 晶體238及一畫素電極224。遮光結構234位於薄膜電晶體 陣列基板200之非顯示區232。 更詳細而言，透明基板210例如是一玻璃基板，顯示 區230例如是位於玻璃基板中央之一矩形區域，非顯示區 232例如是一環繞顯示區230之一框形區域。顯示區230 内設置有複數條相互平行之資料線244及掃描線242,資料 線244與掃描線242垂直，並且此些資料線與掃描線定義 出複數個畫素單元236。在每個畫素單元236中，可藉由控 制薄膜電晶體238,使資料線244傳輸一信號電壓至晝素電 極 224 〇 1303885 第2A圖繪示第2圖之局部區域201放大圖。請同時參 照第2圖及第2A圖，遮光結構234具有複數個孔洞，例如 局部區域201包括複數個孔洞203，此些孔洞203是用以避 免遮光結構產生片狀剝落的情形。 第2B圖繪不第2圖之A_A’剖面圖。請同時參照第2 圖及第2B圖，遮光結構234具有一第一遮光層212a及第 二遮光層220a’第一遮光層212a及第二遮光層220a分別A thin film transistor array substrate according to a preferred embodiment of the present invention, wherein the non-display area has a connection layer, and the connection layer is located on the same film layer as the pixel electrode. The thin film transistor array substrate according to the preferred embodiment of the present invention, wherein the connection layer is electrically connected to the first light shielding layer and the second light shielding layer. According to the above object, a method for fabricating a thin film transistor array substrate is further provided. The steps include: firstly, forming a gate layer on a transparent substrate, and having a plurality of holes. A first light shielding layer is on the non-display area of the transparent substrate. Next, an insulating layer is formed to cover the gate layer and the first light shielding layer. Next, a “channel layer” is formed on the “drain layer” and the insulating layer. Then, a source and a bottom layer are formed on the layer and a plurality of holes are formed at the same time—the second light shielding layer is in the non-region, The hole of the first light-shielding layer and the hole of the second light-shielding layer are erroneously recognized, and then the 'form-dielectric layer is formed in the display area and the non-display area. Then, a plurality of display areas are formed to open in the medium An electric layer to expose the §n, and the pole layer. Then, a halogen electrode is formed on the dielectric layer substrate. The crystal array substrate according to a preferred embodiment of the present invention, the method of manufacturing the thin film electric 1303885, wherein the insulating layer The method of manufacturing the thin film transistor array substrate according to the preferred embodiment of the present invention, wherein the step of forming the opening of the display area further comprises forming a plurality of non-display area openings, the non-displays The method of manufacturing the thin film transistor array substrate according to the preferred embodiment of the present invention, wherein the step of forming the halogen electrode layer further comprises forming a first light shielding layer and the second light shielding layer. The connection layer is electrically connected to the first light shielding layer and the second light shielding layer through the non-display area opening. According to the above object, a liquid crystal display panel having a display area and a non-display area is further provided. The non-display area includes a light-shielding area, and the liquid crystal display panel comprises a color filter substrate, a thin film transistor array substrate and a liquid crystal layer, wherein the thin film transistor array substrate has a plurality of halogen units, and the halogen unit is located In the display area, each of the pixel sheets 7G includes a thin film transistor and a halogen electrode, and the thin film transistor array substrate has a first light shielding layer and a second light shielding layer in the light shielding region, wherein the first light shielding layer The layer and the second light shielding layer respectively have a plurality of holes, and the holes of the first light shielding layer are interlaced with the holes of the second light shielding layer. The liquid daily layer a is placed on the color filter substrate and the thin film. A liquid crystal display panel according to a preferred embodiment of the present invention, wherein the thin film transistor array substrate comprises a transparent substrate, An electric layer, an insulating layer, a channel layer, a second patterned conductive layer, a dielectric layer and a halogen electrode layer. The first patterned conductive layer is formed in the display area and the non-display area The first patterned conductive layer includes the thin film 1303885: ι: layer and the first light shielding layer. The insulating layer covers the second light layer. The channel layer is formed on the closed electrode and the insulating layer A patterned conductive layer is formed on the display region and the non-display region, the first conductive layer includes a source and a gate layer and a light layer of the thin film transistor. The dielectric layer is formed on the display region and the non-display layer a display area, the k electrical layer has a plurality of display area openings, the exposed source and the drain layer. The pixel electrode layer is disposed on: the dielectric second storm according to the present invention - preferably the liquid crystal display panel , wherein: two:: having a plurality of non-display area openings, wherein the non-display area openings violently exit the first light shielding layer and the second light shielding layer. The liquid crystal display panel according to the preferred embodiment of the present invention further includes a connection layer formed in the non-display area, the connection layer electrically connecting the first light shielding layer and the second through the non-display area D Shading layer. The liquid crystal display panel according to the preferred embodiment of the present invention, wherein the material of the first patterned conductive layer and the second patterned conductive layer is gold=one according to a preferred embodiment of the present invention. In the liquid crystal display panel, the color filter and the light substrate have a third light shielding layer in the light shielding region. A liquid crystal display panel according to a preferred embodiment of the present invention, wherein the material of the third light shielding layer is a black resin. The non-display area of the thin film transistor array substrate of the present invention has a first light shielding layer and a second light shielding layer, and the first light shielding layer and the second light shielding layer respectively have a plurality of holes, thereby preventing the light shielding layer from being formed into a sheet shape. The situation of peeling off. In the thin film transistor array substrate of the present invention, since the 1303885 hole of the second light shielding layer is interlaced with the hole of the first light shielding layer, light leakage is less likely to occur. In the thin film transistor array substrate of the present invention, since the connection layer is electrically connected to the first light shielding layer and the second light shielding layer, the potentials of the first light shielding layer and the second light shielding layer are both common voltages, so The stability of the common voltage further enhances the quality of the liquid crystal display panel. In the liquid crystal display panel of the present invention, the material of the third light shielding layer is, for example, a black resin, so that the problem of environmental pollution can be improved. [Embodiment] FIG. 2 is a top view of a thin film transistor array substrate according to a preferred embodiment of the present invention. Referring to FIG. 2, the thin film transistor array substrate 200 has a display area 230 and a non-display area 232, and includes a transparent substrate 210, a plurality of pixel units 236, and a light shielding structure 234, wherein the pixel unit 236 is disposed. The display area 230 includes a thin film transistor 238 and a pixel electrode 224. The light shielding structure 234 is located in the non-display area 232 of the thin film transistor array substrate 200. In more detail, the transparent substrate 210 is, for example, a glass substrate, and the display area 230 is, for example, a rectangular area located at the center of the glass substrate, and the non-display area 232 is, for example, a frame-shaped area surrounding the display area 230. A plurality of data lines 244 and scan lines 242 parallel to each other are disposed in the display area 230. The data lines 244 are perpendicular to the scan lines 242, and the data lines and the scan lines define a plurality of pixel units 236. In each of the pixel units 236, the data line 244 can be caused to transmit a signal voltage to the halogen electrode 224 〇 1303885 by controlling the thin film transistor 238. Fig. 2A is an enlarged view of a partial area 201 of Fig. 2. Referring to FIG. 2 and FIG. 2A simultaneously, the light-shielding structure 234 has a plurality of holes. For example, the partial region 201 includes a plurality of holes 203 for preventing sheet-like peeling of the light-shielding structure. Fig. 2B is a cross-sectional view taken along line A_A' of Fig. 2; Referring to FIG. 2 and FIG. 2B simultaneously, the light shielding structure 234 has a first light shielding layer 212a and a second light shielding layer 220a'. The first light shielding layer 212a and the second light shielding layer 220a respectively.
具有複數個孔洞213、221，此些孔洞213、221是用以避免 遮光層212a、220a產生片狀剝落的情形。值得注意的是， 位於第一遮光層212a與第二遮光層220a之孔洞交錯設 置，如此，可避免背光源所發出之光線215通過第一遮光 層212a及第一遮光層220a，進而改善遮光結構234之遮光 性能。 遮光結構234之製作可以與畫素單元236整合於同一 製程，以下將配合圖示進行說明。第2〇圖繪示第2圖之 B-B’剖面圖。同時參照第2圖、第2B圖及第2c圖，薄 膜電晶體陣列基板200之製造方法例如是；首先，形成一 閘極層212b於透明基板21〇之顯示區23〇上，且同時形成 具有複數個孔洞213之一第一遮光層212a於透明基板21〇 之非顯示區232 〇例如可採用沈積、微影、蝕刻等製程形成 -圖案化導電層於透明基板210之上，此圖案化導電層於 顯示區23〇包含閘極層212b，並且於非顯示區232包含第 -遮光層212a’並且，此圖案化導電層之材料例如是鋁鈥 :金（AlNd)°接著’形成一絕緣層214覆蓋閘極層"η與 第-遮光層212a’此絕緣層214之材料例如是氮化： 1303885 . (SiNx)。接著，形成一通道層216於閘極層212b及絕緣層 214上，此通道層216之材料例如是非晶石夕。 形成通道層216之後，接著形成一源極與汲極層220b 於通道層216上，且同時形成具有複數個孔洞221之一第 二遮光層220a於非顯示區232。例如可採用沈積、微影、 蝕刻等製程形成另一圖案化導電層，此圖案化導電層於顯 示區230與非顯示區232分別包含源極與汲極層220b與第 二遮光層220a，並且，此圖案化導電層之材料例如是鋁、 _ 鈦、鶴、錮。此外，源極與汲極層220b與通道層216之間 例如更包含一歐姆接觸層218。值得注意的是，第二遮光層 220a之孔洞221與第一遮光層212a之孔洞213交錯設置， 因此通過孔洞213的光線215，將被第二遮光層220a所遮 檔。於本較佳實施例，第一遮光層212a與第二遮光層220a 之材料例如皆為具有高反射率之金屬，因此具有較佳之遮 光性能。 繼續參照第2B圖，接著，形成一介電層222覆蓋絕緣 • 層214、源極與汲極層220b及第二遮光層220a，介電層222 之材料例如與絕緣層214相同，為氮化矽（SiNx)。接著，形 成複數個顯示區開口 226b及複數個非顯示區開口 226a於 介電層222，其中顯示區開口 226b暴露出源極與汲極層 220b，非顯示區開口 226a暴露出第一遮光層212a及第二 遮光層220a。 接著，形成一晝素電極層224b於介電層222之上，且 同時形成一連接層224a於非顯示區232。晝素電極層224b 透過顯示區開口 226b與源極與汲極層220b電性連接，連 12 1303885 接層224a透過非顯示區開口 226a電性連接第一遮光層 212a及第二遮光層22〇a。換言之，畫素電極層224b與連 接層224a位於同一膜層，此膜層是一透明導電層，其材料 例如是銦錫氧化物（ITO)或銦鋅氧化物（IZ〇)。值得注意的 疋’由於連接層224a電性連接第一遮光層212a及第二遮 光層220a，使得第一遮光層212a及第二遮光層22〇a之電 位皆為共通電壓（VC0m)，如此，可以降低共通電壓之訊號 阻值，進而增加共通電壓的穩定性。 第3圖繪示根據本發明一較佳實施例之液晶顯示面板 之上視示意圖，第3A圖繪示第3圖之C-C，剖面圖。請同 時參照第3圖及第3A圖，液晶顯示面板300具有一顯示區 330及一非顯示區332。此液晶顯示面板3〇〇包括有一彩色 渡光片基板310、一薄膜電晶體陣列基板2〇〇及一液晶層 320,其中液晶層320設置於彩色濾光片基板31〇與薄膜電 晶體陣列基板200之間。一遮光區334設置於非顯示區332 内’薄膜電晶體陣列基板200於遮光區334具有一第一遮 光層212a及一第二遮光層220a，第一遮光層212a及第二 遮光層220a分別具有複數個孔洞213、221，並且第二遮光 層220a之孔洞與第一遮光層212a之孔洞交錯設置。彩色 濾光片基板於遮光區334具有一第三遮光層312,此第三遮 光層312之材料可以避免採用含鉻材料，例如採用黑色樹 脂，因此可以改善環境污染的問題。由於具有第一遮光層 212a、第二遮光層220a及第三遮光層312，相較於習知技 藝’本發明之液晶顯示面板具有較佳之遮光效果。 雖然本創作已以較佳實施例揭露如上，然其並非用以There are a plurality of holes 213, 221 which are used to prevent sheet-like peeling of the light-shielding layers 212a, 220a. It should be noted that the holes of the first light shielding layer 212a and the second light shielding layer 220a are staggered, so that the light 215 emitted by the backlight can be prevented from passing through the first light shielding layer 212a and the first light shielding layer 220a, thereby improving the light shielding structure. 234 shading performance. The fabrication of the light-shielding structure 234 can be integrated with the pixel unit 236 in the same process, and will be described below with reference to the drawings. Fig. 2 is a cross-sectional view taken along line B-B' of Fig. 2. Referring to FIGS. 2, 2B, and 2c, the manufacturing method of the thin film transistor array substrate 200 is, for example, first, a gate layer 212b is formed on the display region 23A of the transparent substrate 21, and simultaneously formed with The first light shielding layer 212a of the plurality of holes 213 is formed on the non-display area 232 of the transparent substrate 21, for example, by using a process such as deposition, lithography, etching, etc., to form a patterned conductive layer on the transparent substrate 210. The layer includes a gate layer 212b in the display region 23, and includes a first light-shielding layer 212a' in the non-display region 232. The material of the patterned conductive layer is, for example, aluminum germanium: gold (AlNd), and then 'forms an insulating layer. 214 covers the gate layer "n and the first light-shielding layer 212a'. The material of the insulating layer 214 is, for example, nitrided: 1303885. (SiNx). Next, a channel layer 216 is formed on the gate layer 212b and the insulating layer 214. The material of the channel layer 216 is, for example, amorphous. After the channel layer 216 is formed, a source and drain layer 220b is formed on the channel layer 216, and a second light shielding layer 220a having a plurality of holes 221 is formed in the non-display area 232. For example, another patterned conductive layer may be formed by a process such as deposition, lithography, etching, etc., and the patterned conductive layer includes a source and drain layer 220b and a second light shielding layer 220a in the display region 230 and the non-display region 232, respectively, and The material of the patterned conductive layer is, for example, aluminum, titanium, crane, or ruthenium. In addition, an ohmic contact layer 218 is further included between the source and drain layers 220b and the channel layer 216. It should be noted that the holes 221 of the second light shielding layer 220a are interlaced with the holes 213 of the first light shielding layer 212a, so that the light rays 215 passing through the holes 213 will be blocked by the second light shielding layer 220a. In the preferred embodiment, the materials of the first light shielding layer 212a and the second light shielding layer 220a are, for example, metals having high reflectivity, and thus have better light shielding properties. Continuing to refer to FIG. 2B, a dielectric layer 222 is formed to cover the insulating layer 214, the source and drain layers 220b, and the second light shielding layer 220a. The material of the dielectric layer 222 is the same as that of the insulating layer 214, for example.矽 (SiNx). Then, a plurality of display area openings 226b and a plurality of non-display area openings 226a are formed in the dielectric layer 222, wherein the display area opening 226b exposes the source and drain layers 220b, and the non-display area opening 226a exposes the first light shielding layer 212a. And a second light shielding layer 220a. Next, a halogen electrode layer 224b is formed over the dielectric layer 222, and a connection layer 224a is formed at the same time in the non-display area 232. The pixel electrode layer 224b is electrically connected to the source and drain layers 220b through the display region opening 226b, and the 12 1303885 bonding layer 224a is electrically connected to the first light shielding layer 212a and the second light shielding layer 22a through the non-display region opening 226a. . In other words, the pixel electrode layer 224b and the connection layer 224a are located in the same film layer, and the film layer is a transparent conductive layer made of, for example, indium tin oxide (ITO) or indium zinc oxide (IZ〇). It is noted that the connection layer 224a is electrically connected to the first light shielding layer 212a and the second light shielding layer 220a, so that the potentials of the first light shielding layer 212a and the second light shielding layer 22a are common voltages (VC0m), and thus, It can reduce the signal resistance of the common voltage, thereby increasing the stability of the common voltage. 3 is a top view of a liquid crystal display panel according to a preferred embodiment of the present invention, and FIG. 3A is a cross-sectional view taken along line C-C of FIG. Referring to FIG. 3 and FIG. 3A simultaneously, the liquid crystal display panel 300 has a display area 330 and a non-display area 332. The liquid crystal display panel 3 includes a color light-receiving substrate 310, a thin film transistor array substrate 2, and a liquid crystal layer 320. The liquid crystal layer 320 is disposed on the color filter substrate 31 and the thin film transistor array substrate. Between 200. A light-shielding region 334 is disposed in the non-display area 332. The thin film transistor array substrate 200 has a first light-shielding layer 212a and a second light-shielding layer 220a. The first light-shielding layer 212a and the second light-shielding layer 220a have respectively A plurality of holes 213 and 221 are formed, and holes of the second light shielding layer 220a are interlaced with holes of the first light shielding layer 212a. The color filter substrate has a third light shielding layer 312 in the light shielding region 334. The material of the third light shielding layer 312 can avoid the use of a chromium-containing material, for example, a black resin, so that the problem of environmental pollution can be improved. Since the first light-shielding layer 212a, the second light-shielding layer 220a, and the third light-shielding layer 312 are provided, the liquid crystal display panel of the present invention has a better light-shielding effect as compared with the prior art. Although the present disclosure has been disclosed above in the preferred embodiment, it is not intended to be used
13 1303885 限定本創作，任何熟習此技藝者，在不脫離本創作之精神 和範圍内，當可作各種之更動與潤飾，因此本創作之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下··13 1303885 Qualifying this creation, anyone who is familiar with this art can make various changes and refinements without departing from the spirit and scope of this creation. Therefore, the scope of protection of this creation is defined by the scope of the patent application attached. quasi. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.
第1圖繪示一習知薄膜電晶體陣列基板之上視示意圖。 弟2圖繪示根據本發明一較佳實施例之薄膜電晶體陣 列基板之上視示意圖。 第2A圖繪示第2圖之局部區域放大圖。 第2B圖纟會不第2圖之A-A’剖面圖。 弟2C圖繪不弟2圖之剖面圖。 第3圖繪示根據本發明一較佳實施例之液晶顯示面板 之上視示意圖。 弟3A圖繪不第3圖之C-C 剖面圖。FIG. 1 is a schematic top view of a conventional thin film transistor array substrate. Figure 2 is a top plan view of a thin film transistor array substrate in accordance with a preferred embodiment of the present invention. Fig. 2A is an enlarged view of a partial area of Fig. 2. Figure 2B will not be a cross-sectional view of A-A' in Figure 2. Brother 2C picture is not a cross-section of the 2 picture. FIG. 3 is a top plan view of a liquid crystal display panel according to a preferred embodiment of the present invention. Brother 3A draws a C-C section view of Figure 3.
【主要元件符號說明】 224a :連接層 224b :晝素電極層 226a :非顯示區開口 226b :顯示區開口 230 :顯示區 232 :非顯示區 234 :遮光結構 11〇 :薄膜電晶體陣列基板 112 :非顯示區 114 :遮光結構 201 :局部區域 203 :孔洞 210 :透明基板 212a·第一遮光層 14 1303885 212b :閘極層 236 ： 畫素單元 213 :孔洞 238 ： 薄膜電晶體 214 :絕緣層 242 ： 掃描線 215 :光線 244 ： 資料線 216 :通道層 300 ： 液晶顯不面板 218 :歐姆接觸層 310 ： 彩色濾光片基板 220a :第二遮光層 320 ： 液晶層 220b :源極與汲極層 330 ： 顯不區 221 :孔洞 332 ： 非顯示區 222 :介電層 334 ： 遮光區 224 :畫素電極 15[Main component symbol description] 224a: connection layer 224b: halogen electrode layer 226a: non-display area opening 226b: display area opening 230: display area 232: non-display area 234: light shielding structure 11: thin film transistor array substrate 112: Non-display area 114: light-shielding structure 201: partial area 203: hole 210: transparent substrate 212a, first light-shielding layer 14 1303885 212b: gate layer 236: pixel unit 213: hole 238: thin film transistor 214: insulating layer 242: Scanning line 215: light 244: data line 216: channel layer 300: liquid crystal display panel 218: ohmic contact layer 310: color filter substrate 220a: second light shielding layer 320: liquid crystal layer 220b: source and drain layer 330 : Display area 221 : Hole 332 : Non-display area 222 : Dielectric layer 334 : Shading area 224 : Photoelectrode 15