TWI298456B - - Google Patents
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- TWI298456B TWI298456B TW092118539A TW92118539A TWI298456B TW I298456 B TWI298456 B TW I298456B TW 092118539 A TW092118539 A TW 092118539A TW 92118539 A TW92118539 A TW 92118539A TW I298456 B TWI298456 B TW I298456B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Description
1298456
【發明所屬之技術領域】 本發明其係有關於一種用於減少 的控制裝置及方法,女、女 处里中_次數 控制裝置。 制。口及一緩衝器的 【先前技術】 在一般即時系統中(請參閱圖一),當外 如I /0裝置或匯流排,對一執行單 ^ , rrDTT, ^ J丁早几iul,如中央處理單元 j 、數位訊號處理器(DSP)提出一中斷要求時,該 執行單元101接收到該中斷,會立即去執行該中斷要求^ φ 相對應的中斷服務常式(Interrupt Service R〇utine, ISR )。 e 但當外部裝置1 〇 〇 —再地提出許多的中斷要求時,而 這些中斷要求並不一定都是需要執行單元馬上處理,並且 若是該執行單元101 —再的處理中斷要求和執行相對應的 中斷服務常式時,容易造成CPU執行運作過程或是DSP處理 私序一再被干擾,導致系統效能降低並且提高除錯的困難 度’會對整個系統造成不可預知的干擾並且可能景彡響整個 系統的運作效能。 【發明内容】 鑒於上述問題,本發明之主要目的係提供一種用於減 少對一處理器中斷次數的控制裝置及方法,以提高系統之 效能。該控制裝置包括一緩衝器、一中斷控制器及一輔助
1298456 五、發明說明(2) 表。該中斷控制器耦接至該緩衝器,用以接收一中斷並且 選擇性地送出一中斷信號,並包含一計時器,該計時器具 有一初始值。該緩衝器可儲存該中斷之相關資訊。該輔助 表則耦接至該中斷控制器,用以儲存該緩衝器内各中斷所 個別對應之一中斷期限和一執行時間。 當該中斷控制器接收該中斷時,即將該中斷之相關資 訊存入該緩衝器,並計算該中斷之中斷期限與該緩衝器内 各中斷之執行時間總和兩者的差值,再依計算結果選擇是 否送出該中斷信號。 該控制方法則包括下列步驟: a. 提供一控制裝置,其係包括有一計時器、一緩衝器和一 輔助表,該計時器具有一初始值; b. 該控制裝置接收外部裝置的一中斷,並存入該緩衝器; c. 該控制裝置從該輔助表讀取該中斷之相對應的一中斷期 限和一執行時間; d. 檢查該計時器之值是否為初始值,若為否時,又該中斷 之中斷期限小於該緩衝器内各中斷之執行時間總和,則 送出該中斷信號,而當該中斷之中斷期限不小於該緩衝 器内各中斷之執行時間總和,則比較中斷期限和緩衝器 内各中斷之執行時間總和之差值與計時器之值,將兩者 中較小之值存入計時器中; e. 若計時器為初始值時,將計時器之值設定為該中斷之中 斷期限與執行時間兩者之差值; f. 檢查計時器是否計數到一第二預設值,若否則等待一預
1298456 五、發明說明(3) 定時間並重複步驟f ; g·该控制裝置發 之值重設為初=中斷信號觸發一中斷程序,並將計時器 利用鈾述的^告丨丨壯、 / 少被頻繁的中斷 衣置及方法,可使得系統在運作中減 藉由緩衝器不合、▲ Γ擾之次數,系統將變得更有效率而且 卜曰遭失任何中斷。 【實施方式】 本發明係提中—# m 制裴置及方法,乂種用於減少對一處理器中斷次數的控 結在一起,以# η ^影響系統運作下,將多個中斷要求連 請參閱圖;L中斷次數之目的。 :數Γ系統,該系統對一, 及一控制裝置1。 卜⑷衣置3、一執行單元2 圖-係為圖-it Ϊ 處所示係為控制^幻制衣內置人之/佳實施例的方塊圖,虛線 衝器12、一中斷於 内3有先進先出(FIFO)緩 11,包含有-:=1及,個,13。中斷控制器 三連接端,第—連:’並且中斷控制器11又包含至少 斷,第二連接端送出部裝置3所發出之中 斷,筮r 4 中斷^ 5虎來觸發執行單元?舳 > 山 二連接端用來存取FIF〇緩衝 +執仃中 ―初始值、Μ々和一第二預設值二。:;2/,计時器:U具有 I數計時器,每經—預設的單位 ^器111為 下數-次。二個輔助表13中分別存有器⑴ • 甲斷要求之相對 1298456
應的:I斷期限和-執行時間 是否要即送丨+斷信號。 雄4::間間隔β,執行單 統會ΐ生不可預知的錯誤,而 也許有不同的期限,所以選一 ΐί 隔’定義此執行期 制衣置觸务執行單元2執行中 中斷執行時間,而且該中斷要 不同的中斷執行時間,選擇一 所需之要求1義此執行時間 間,,,並且最短執行期限必須 在此較佳貫施例中,我們 期限減去一常數值,以及定義 時間。 ’以提供中斷控制器1 1判斷 元2必須完成中斷,否則系 且該中斷在不同系統狀態下 最短的執行期限恰可滿足所 限為、、最短執行期限〃。控 斷到該中斷完成的時間稱為 求在不同系統狀態下也許有 最長的中斷執行時間以滿足 為一、'最長中斷執行時 大於最長中斷執行時間。 疋義该中斷期限為最短執行 該執行時間為最長中斷執行
、圖四係顯示本發明之用於減少對一處理器中斷次數方 法之;/驟"IL程的較佳貫施例。該方法係二 構中。如圖四所示,該方法包括下列步驟:木 步驟40 :控制裝置1接收外部裝置3的一中斷,先將該 中斷之相關資料例如中斷要求的類型、向量…等資料依序 存入先進先出緩衝器12中; 步驟41 :控制裝置1從輔助表1 3讀取該中斷之相對應 的一中斷期限和一最長中斷執行時間; 步驟4 2 ·檢查計時器111之值是否為初始值、、—1 /,, 若為 ''否時,執行步驟44 ;
1298456 五、發明說明(5) 〜 --—------ 步驟43 :若計時器ln為初始值、、 一 ^ 111之值設定為該中斷之中斷期盥曰 卞將计日π态 者之差值,計時器111開始計數^ 取、中斷執行時間兩 步驟44 ·比較中斷的中斷曰 中斷之執行時間總和,若為否則3緩衝器12内各 則立即執行步驟45 ; 、 執仃乂驟50,若為是 步驟4 5 而當该中斷之中偷里服/ 中斷之最長中斷執行時間總和,則: 衝器12内— 前計時器111之值,若為是則、心此差值疋否小於丨 立即執行步驟47 ; 、]立即執订步驟46,若為否則
y ·、、λ •若此差值小於計時器111之值,則將計日士哭 111之值更新為此差值,計時器111開始計數;、、才的 步驟4 7 :計時器丨丨1繼續計數; 步驟48 :檢查計時器1丨1是否計數到” 〇” ,若„否,, 行步驟4 9 ’然後重複步驟4 7,直到計時器1 1 1計數到” 〇,, 步驟49 :等待一預設的單位時間; 步驟50 :當計時器^1計數到〇時,控制裝置1發出 斷信號觸發—中斷程序,並將計時器111之值重設為初 值。 請參閱圖五,其係本發明之用於減少處理器中斷次 的中斷服務常式之步驟流程圖。提供一執行單元2,係 為一數位信號處理器(DSP)或一中央處理單元(CPU),如 五所示,包括下列步驟·· 回 步驟51 :執行單元2收到中斷信號;
1298456 五、發明說明(6) 步驟52 :執行單元2會查看該先進先出緩衝器12中是 否有中斷要求之相關資料,若〜否〃則執行步驟54 ; 步驟53 :若 ''是〃則讀取中斷要求之相關資料,並執行步 驟5 5,直到緩衝器内之中斷要求之相關資料都被執行完畢 為止; 步驟5 4 :結束; 步驟5 5 :執行該中斷要求所相對應的中斷服務常式 (Interrupt Service Routine,I SR ) ° 以上所述者,僅為本發明較佳實施例而已,當不能用 來限定本發明所實施之範圍。即凡屬於本發明申請專利範 圍所作之均等變化與修飾皆因屬於本發明專利涵蓋之範圍 内〇
第9頁 1298456 圖式簡單說明 【圖式簡單說明】 圖一係為習知之中斷執行示意圖。 圖二係為本發明之用於減少對一處理器中斷次數的系 統之示意圖。 圖三係為本發明之用於減少對一處理器中斷次數的控 制裝置方塊圖。 圖四係為本發明之用於減少對一處理器中斷次數的方 法步驟流程圖。 « 圖五係為本發明之一種用於減少處理器中斷次數的中 斷服務常式之流程圖。 圖式之圖號說明: I -控制裝置 II -中斷控制器 III -計時器 12-FIFO緩衝器 1 3 -輔助表 2 -執行單元 3 -外部裝置 4 0〜5 0 -本發明之用於減少對一處理器中斷次數的方法步 驟流程 51〜5 5 -本發明之用於減少處理器中斷次數的中斷服務常 式之流程
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Claims (1)
1298456 案號 92118539 ^............0 補充 修正 六、申請專利範圍 1. 一種用於減少對一處理器中斷次數的控制裝置,包括 有: 緩衝器 中斷控 中斷,並選擇 一輔助表 器内各中斷所 其中當該 一中斷之相關 限與該緩 再依計算 斷期 值, 器。 2·如申 係為 3. 如申 所儲 量。 4. 如申 制器 aa 早兀 5 ·如申 斷之 則該 6 ·如申 ,可儲存至少一中斷之相關資訊; 制器,耦接至該緩衝器,用以接收一第一 性地送出一中斷信號至該處理器;以及 ,耦接至該中斷控制器,用以儲存該緩衝 個別對應之一中斷期限和一執行時間; 中斷控制器接收該第一中斷時,即將該第 資訊存入該緩衝器,並計算第一中斷之中 衝器内各中斷之執行時間總和兩者的差 結果選擇是否送出該中斷信號至該處理 請專利範圍第1項所述之控制裝置,其中該緩衝器 一先進先出(FIFO)的緩衝器。 圍第1項所述之控制裝置,其中該緩衝器 斷的相關資訊至少包含中斷類型與中斷向 請專利範 存之各中 請專利範 係選擇性 則用以處 請專利範 中斷期限 中斷控制 請專利範 圍第1項所述之控制裝置,其中該中斷控 地將該中斷信號送至一執行單元,該執行 理該緩衝器所儲存之各中斷。 圍第1項所述之控制裝置,其中若第一中 大於該緩衝器内各中斷之執行時間總和, 器不送出該中斷訊號。 圍第5項所述之控制裝置,其中若第一中
第11頁 1298456 案號 92118539 _η 曰 修正 六、申請專利範圍 斷之中斷期限不大於該緩衝器内各中斷之執行時間總 和,則該中斷控制器送出該中斷訊號。 7. 如申請專利範圍第1項所述之控制裝置,其中該中斷控 制器包含一計時器,該計時器之初始值為一第一值,當 該計時器之值不等於該第一值時,每經一預設的單位時 間,即將該計時器加上一第二值。 8. 如申請專利範圍第7項所述之控制裝置,其中當該中斷 控制器接收該第一中斷時,若該計時器之值為該第一 值,則以該差值來更新該計時器。 9 ·如申請專利範圍第7項所述之控制裝置,其中當該中斷 控制器接收該第一中斷時,若該計時器之值不等於該第 一值且大於該差值,則以該差值來更新該計時器。 1 0.如申請專利範圍第7項所述之控制裝置,其中若該差值 不大於一第三值,則該中斷控制器送出該中斷訊號, 並將該計時器重置為該第一值。 11. 一種用於減少中斷次數之方法,其係包括有: a. 提供一控制裝置,其係包括有一計時器、一緩衝器 和一輔助表,該計時器具有一初始值; b. 控制裝置接收一中斷,並存入該緩衝器; c. 控制裝置從該輔助表讀取該中斷之相對應的一中斷 期限和一執行時間; d. 該計時器之值是否為初始值,若為否時,又該中斷 之中斷期限小於該緩衝器内各中斷之執行時間總 和,則送出該中斯信號,而當該中斷之中斷期限不
1298456 _案號92118539_年月曰 修正_ 六、申請專利範圍 小於該緩衝器内各中斷之執行時間總和,則比較中 斷期限和緩衝器内各中斷之執行時間總和之差值與 計時器之值和計時器之值,將兩者中較小之值存入 計時器中; e. 計時器為初始值時,將計時器之值設定為該中斷之 中斷期限與執行時間兩者之差值; f. 計時器是否計數到一第二預設值,若否則等待一預 定時間並重複步驟f ;以及 g. 控制裝置發出中斷信號觸發一中斷程序,並將計時 器之值重設為初始值。 1 2. —種可減少中斷次數之系統,其係包括有: 一外部裝置,可提出一中斷; 一控制裝置,耦接至該外部裝置,其係包括有: 一緩衝器,可儲存該中斷之相關資訊; 一中斷控制器,耦接至該緩衝器,用以接收該 中斷,並選擇性地送出一中斷信號;以及 一輔助表,耦接至該中斷控制器,用以儲存該 緩衝器内各中斷所個別對應之一中斷期限和一執行時 間;以及 一執行單元,耦接至該控制裝置,並且執行該中 斷; 其中,當該外部裝置送出中斷至該控制裝置,該 控制裝置將該中斷之相關資訊存入該緩衝器,並計算 該中斷之中斷期限與該緩衝器内各中斷之執行時間總
第13頁 1298456 案號 92118539 年 月 曰 修正 六、申請專利範圍 和兩者之 號給該執 1 3.如申請專 統,其中 buffer)( 1 4.如申請專 統,其中 含中斷類 1 5.如申請專 統,其中 之執行時 號。 1 6.如申請專 統,其中 之執行時 1 7.如申請專 統,其中 始值為一 時,每經 二值。 1 8.如申請專 統,其中 之值為該 1 9.如申請專 差值,再依計算結果選擇是否送出該中斷信 行單元。 利範圍第1 2項所述之可減少中斷次數之系 該緩衝器係為一先進先出之緩衝器(F I F0 利範圍第1 2項所述之用於減少中斷 該緩衝器所儲存之各中斷的相關資 型與中斷向量。 利範圍第1 2項所述之可減少中斷次 若該中斷之中斷期限大於該緩衝器 間總和,則該中斷控制器不送出該 利範圍第1 2項所述之可減少中斷次 若該中斷之中斷期限小於該缓衝器 間總和,則該中斷控制器送出該中 利範圍第1 2項所述之可減少中斷次 該中斷控制器包含一計時器,該計 第一值,當該計時器之值不等於該 一預設的單位時間,即將該計時器 利範圍第1 7項所述之可減少中斷次 當該中斷控制器接收該中斷時,若 第一值,則以該差值來更新該計時 利範圍第1 7項所述之可減少中斷次 次數之系 訊至少包 數之系 内各中斷 中斷訊 數之系 内各中斷 斷訊號。 數之系 時器之初 第一值 加上一第 數之糸 該計時器 器。 數之系
第14頁 1298456 _案號92118539_年月曰 修正_ 六、申請專利範圍 統,其中當該中斷控制器接收該中斷時,若該計時器 之值不等於該第一值且大於該差值,則以該差值來更 新該計時器。 2 0.如申請專利範圍第1 7項所述之可減少中斷次數之系 統,其中若該差值不大於一第三值,則該中斷控制器 送出該中斷訊號,並將該計時器重置為該第一值。 2 1.如申請專利範圍第1 2項所述之可減少中斷次數之系 統,其中該執行單元其係為一中央處理單元(CPU)。 2 2.如申請專利範圍第1 2項所述之可減少中斷次數之系 統,其中該執行單元其係為一數位信號處理器(DSP ) ◦
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8930603B2 (en) | 2008-10-21 | 2015-01-06 | International Business Machines Corporation | Interruption facility for adjunct processor queues |
Families Citing this family (123)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4856983B2 (ja) * | 2006-03-02 | 2012-01-18 | 株式会社日立製作所 | ストレージシステム及びスケジューリング方法 |
US8799687B2 (en) | 2005-12-30 | 2014-08-05 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates |
US20080147905A1 (en) * | 2006-12-15 | 2008-06-19 | Infineon Technologies Ag | Method and system for generating a DMA controller interrupt |
US7743195B2 (en) * | 2006-12-27 | 2010-06-22 | Intel Corporation | Interrupt mailbox in host memory |
US7917784B2 (en) | 2007-01-07 | 2011-03-29 | Apple Inc. | Methods and systems for power management in a data processing system |
US8667198B2 (en) * | 2007-01-07 | 2014-03-04 | Apple Inc. | Methods and systems for time keeping in a data processing system |
WO2008096208A1 (en) * | 2007-02-08 | 2008-08-14 | Freescale Semiconductor, Inc. | Request controller, processing unit, method for controlling requests and computer program product |
US9524256B2 (en) * | 2007-02-16 | 2016-12-20 | Nxp Usa, Inc. | Request controller, processing unit, arrangement, method for controlling requests and computer program product |
US8645740B2 (en) * | 2007-06-08 | 2014-02-04 | Apple Inc. | Methods and systems to dynamically manage performance states in a data processing system |
US7711864B2 (en) | 2007-08-31 | 2010-05-04 | Apple Inc. | Methods and systems to dynamically manage performance states in a data processing system |
US20090150696A1 (en) * | 2007-12-10 | 2009-06-11 | Justin Song | Transitioning a processor package to a low power state |
US8024590B2 (en) | 2007-12-10 | 2011-09-20 | Intel Corporation | Predicting future power level states for processor cores |
US8239873B2 (en) * | 2008-08-12 | 2012-08-07 | Verizon Patent And Licensing Inc. | Speedy event processing |
JP5308383B2 (ja) * | 2010-03-18 | 2013-10-09 | パナソニック株式会社 | 仮想マルチプロセッサシステム |
US8943334B2 (en) | 2010-09-23 | 2015-01-27 | Intel Corporation | Providing per core voltage and frequency control |
JP5625710B2 (ja) * | 2010-10-05 | 2014-11-19 | 富士通セミコンダクター株式会社 | シミュレーション装置、方法、及びプログラム |
US9069555B2 (en) | 2011-03-21 | 2015-06-30 | Intel Corporation | Managing power consumption in a multi-core processor |
US8793515B2 (en) | 2011-06-27 | 2014-07-29 | Intel Corporation | Increasing power efficiency of turbo mode operation in a processor |
US8769316B2 (en) | 2011-09-06 | 2014-07-01 | Intel Corporation | Dynamically allocating a power budget over multiple domains of a processor |
US8688883B2 (en) | 2011-09-08 | 2014-04-01 | Intel Corporation | Increasing turbo mode residency of a processor |
US8914650B2 (en) | 2011-09-28 | 2014-12-16 | Intel Corporation | Dynamically adjusting power of non-core processor circuitry including buffer circuitry |
US8954770B2 (en) | 2011-09-28 | 2015-02-10 | Intel Corporation | Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin |
US9074947B2 (en) | 2011-09-28 | 2015-07-07 | Intel Corporation | Estimating temperature of a processor core in a low power state without thermal sensor information |
US9026815B2 (en) | 2011-10-27 | 2015-05-05 | Intel Corporation | Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor |
US8832478B2 (en) | 2011-10-27 | 2014-09-09 | Intel Corporation | Enabling a non-core domain to control memory bandwidth in a processor |
US8943340B2 (en) | 2011-10-31 | 2015-01-27 | Intel Corporation | Controlling a turbo mode frequency of a processor |
US9158693B2 (en) | 2011-10-31 | 2015-10-13 | Intel Corporation | Dynamically controlling cache size to maximize energy efficiency |
US9239611B2 (en) | 2011-12-05 | 2016-01-19 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme |
US8972763B2 (en) | 2011-12-05 | 2015-03-03 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state |
US9052901B2 (en) | 2011-12-14 | 2015-06-09 | Intel Corporation | Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum processor current |
US9098261B2 (en) | 2011-12-15 | 2015-08-04 | Intel Corporation | User level control of power management policies |
US9372524B2 (en) | 2011-12-15 | 2016-06-21 | Intel Corporation | Dynamically modifying a power/performance tradeoff based on processor utilization |
US9436245B2 (en) | 2012-03-13 | 2016-09-06 | Intel Corporation | Dynamically computing an electrical design point (EDP) for a multicore processor |
WO2013137862A1 (en) | 2012-03-13 | 2013-09-19 | Intel Corporation | Dynamically controlling interconnect frequency in a processor |
US9354689B2 (en) | 2012-03-13 | 2016-05-31 | Intel Corporation | Providing energy efficient turbo operation of a processor |
US9547027B2 (en) | 2012-03-30 | 2017-01-17 | Intel Corporation | Dynamically measuring power consumption in a processor |
WO2013162589A1 (en) | 2012-04-27 | 2013-10-31 | Intel Corporation | Migrating tasks between asymmetric computing elements of a multi-core processor |
US9063727B2 (en) | 2012-08-31 | 2015-06-23 | Intel Corporation | Performing cross-domain thermal control in a processor |
US8984313B2 (en) | 2012-08-31 | 2015-03-17 | Intel Corporation | Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator |
US9342122B2 (en) | 2012-09-17 | 2016-05-17 | Intel Corporation | Distributing power to heterogeneous compute elements of a processor |
US9423858B2 (en) | 2012-09-27 | 2016-08-23 | Intel Corporation | Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain |
US9575543B2 (en) | 2012-11-27 | 2017-02-21 | Intel Corporation | Providing an inter-arrival access timer in a processor |
US9183144B2 (en) | 2012-12-14 | 2015-11-10 | Intel Corporation | Power gating a portion of a cache memory |
US9292468B2 (en) | 2012-12-17 | 2016-03-22 | Intel Corporation | Performing frequency coordination in a multiprocessor system based on response timing optimization |
US9405351B2 (en) | 2012-12-17 | 2016-08-02 | Intel Corporation | Performing frequency coordination in a multiprocessor system |
US9075556B2 (en) | 2012-12-21 | 2015-07-07 | Intel Corporation | Controlling configurable peak performance limits of a processor |
US9235252B2 (en) | 2012-12-21 | 2016-01-12 | Intel Corporation | Dynamic balancing of power across a plurality of processor domains according to power policy control bias |
US9164565B2 (en) | 2012-12-28 | 2015-10-20 | Intel Corporation | Apparatus and method to manage energy usage of a processor |
US9081577B2 (en) | 2012-12-28 | 2015-07-14 | Intel Corporation | Independent control of processor core retention states |
US9335803B2 (en) | 2013-02-15 | 2016-05-10 | Intel Corporation | Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores |
US9367114B2 (en) | 2013-03-11 | 2016-06-14 | Intel Corporation | Controlling operating voltage of a processor |
US9395784B2 (en) | 2013-04-25 | 2016-07-19 | Intel Corporation | Independently controlling frequency of plurality of power domains in a processor system |
US9377841B2 (en) | 2013-05-08 | 2016-06-28 | Intel Corporation | Adaptively limiting a maximum operating frequency in a multicore processor |
US9823719B2 (en) | 2013-05-31 | 2017-11-21 | Intel Corporation | Controlling power delivery to a processor via a bypass |
US9348401B2 (en) | 2013-06-25 | 2016-05-24 | Intel Corporation | Mapping a performance request to an operating frequency in a processor |
US9471088B2 (en) | 2013-06-25 | 2016-10-18 | Intel Corporation | Restricting clock signal delivery in a processor |
US9348407B2 (en) | 2013-06-27 | 2016-05-24 | Intel Corporation | Method and apparatus for atomic frequency and voltage changes |
US9377836B2 (en) | 2013-07-26 | 2016-06-28 | Intel Corporation | Restricting clock signal delivery based on activity in a processor |
US9495001B2 (en) | 2013-08-21 | 2016-11-15 | Intel Corporation | Forcing core low power states in a processor |
US10386900B2 (en) | 2013-09-24 | 2019-08-20 | Intel Corporation | Thread aware power management |
US9594560B2 (en) | 2013-09-27 | 2017-03-14 | Intel Corporation | Estimating scalability value for a specific domain of a multicore processor based on active state residency of the domain, stall duration of the domain, memory bandwidth of the domain, and a plurality of coefficients based on a workload to execute on the domain |
US9405345B2 (en) | 2013-09-27 | 2016-08-02 | Intel Corporation | Constraining processor operation based on power envelope information |
JP5867482B2 (ja) * | 2013-11-08 | 2016-02-24 | 日本電気株式会社 | 情報処理装置、情報処理方法、プログラム、計算処理装置、計算処理方法 |
US9494998B2 (en) | 2013-12-17 | 2016-11-15 | Intel Corporation | Rescheduling workloads to enforce and maintain a duty cycle |
US9459689B2 (en) | 2013-12-23 | 2016-10-04 | Intel Corporation | Dyanamically adapting a voltage of a clock generation circuit |
US9323525B2 (en) | 2014-02-26 | 2016-04-26 | Intel Corporation | Monitoring vector lane duty cycle for dynamic optimization |
US10108454B2 (en) | 2014-03-21 | 2018-10-23 | Intel Corporation | Managing dynamic capacitance using code scheduling |
US9665153B2 (en) | 2014-03-21 | 2017-05-30 | Intel Corporation | Selecting a low power state based on cache flush latency determination |
US10417149B2 (en) | 2014-06-06 | 2019-09-17 | Intel Corporation | Self-aligning a processor duty cycle with interrupts |
US9760158B2 (en) | 2014-06-06 | 2017-09-12 | Intel Corporation | Forcing a processor into a low power state |
US9513689B2 (en) | 2014-06-30 | 2016-12-06 | Intel Corporation | Controlling processor performance scaling based on context |
US9606602B2 (en) | 2014-06-30 | 2017-03-28 | Intel Corporation | Method and apparatus to prevent voltage droop in a computer |
JP6201921B2 (ja) * | 2014-07-14 | 2017-09-27 | 株式会社デンソー | マイクロコンピュータ |
US9575537B2 (en) | 2014-07-25 | 2017-02-21 | Intel Corporation | Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states |
US9760136B2 (en) | 2014-08-15 | 2017-09-12 | Intel Corporation | Controlling temperature of a system memory |
US9671853B2 (en) | 2014-09-12 | 2017-06-06 | Intel Corporation | Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency |
US10339023B2 (en) | 2014-09-25 | 2019-07-02 | Intel Corporation | Cache-aware adaptive thread scheduling and migration |
US9977477B2 (en) | 2014-09-26 | 2018-05-22 | Intel Corporation | Adapting operating parameters of an input/output (IO) interface circuit of a processor |
US9684360B2 (en) | 2014-10-30 | 2017-06-20 | Intel Corporation | Dynamically controlling power management of an on-die memory of a processor |
US9703358B2 (en) | 2014-11-24 | 2017-07-11 | Intel Corporation | Controlling turbo mode frequency operation in a processor |
US9710043B2 (en) | 2014-11-26 | 2017-07-18 | Intel Corporation | Controlling a guaranteed frequency of a processor |
US20160147280A1 (en) | 2014-11-26 | 2016-05-26 | Tessil Thomas | Controlling average power limits of a processor |
US10048744B2 (en) | 2014-11-26 | 2018-08-14 | Intel Corporation | Apparatus and method for thermal management in a multi-chip package |
US10877530B2 (en) | 2014-12-23 | 2020-12-29 | Intel Corporation | Apparatus and method to provide a thermal parameter report for a multi-chip package |
US20160224098A1 (en) | 2015-01-30 | 2016-08-04 | Alexander Gendler | Communicating via a mailbox interface of a processor |
US9639134B2 (en) | 2015-02-05 | 2017-05-02 | Intel Corporation | Method and apparatus to provide telemetry data to a power controller of a processor |
US10234930B2 (en) | 2015-02-13 | 2019-03-19 | Intel Corporation | Performing power management in a multicore processor |
US9910481B2 (en) | 2015-02-13 | 2018-03-06 | Intel Corporation | Performing power management in a multicore processor |
US9874922B2 (en) | 2015-02-17 | 2018-01-23 | Intel Corporation | Performing dynamic power control of platform devices |
US9842082B2 (en) | 2015-02-27 | 2017-12-12 | Intel Corporation | Dynamically updating logical identifiers of cores of a processor |
US9710054B2 (en) | 2015-02-28 | 2017-07-18 | Intel Corporation | Programmable power management agent |
US9760160B2 (en) | 2015-05-27 | 2017-09-12 | Intel Corporation | Controlling performance states of processing engines of a processor |
US9710041B2 (en) | 2015-07-29 | 2017-07-18 | Intel Corporation | Masking a power state of a core of a processor |
US10001822B2 (en) | 2015-09-22 | 2018-06-19 | Intel Corporation | Integrating a power arbiter in a processor |
CN105204939B (zh) * | 2015-11-03 | 2019-02-01 | 浪潮(北京)电子信息产业有限公司 | 一种中断请求的处理方法 |
US9983644B2 (en) | 2015-11-10 | 2018-05-29 | Intel Corporation | Dynamically updating at least one power management operational parameter pertaining to a turbo mode of a processor for increased performance |
US9910470B2 (en) | 2015-12-16 | 2018-03-06 | Intel Corporation | Controlling telemetry data communication in a processor |
US10146286B2 (en) | 2016-01-14 | 2018-12-04 | Intel Corporation | Dynamically updating a power management policy of a processor |
US10289188B2 (en) | 2016-06-21 | 2019-05-14 | Intel Corporation | Processor having concurrent core and fabric exit from a low power state |
US10281975B2 (en) | 2016-06-23 | 2019-05-07 | Intel Corporation | Processor having accelerated user responsiveness in constrained environment |
US10324519B2 (en) | 2016-06-23 | 2019-06-18 | Intel Corporation | Controlling forced idle state operation in a processor |
US10379596B2 (en) | 2016-08-03 | 2019-08-13 | Intel Corporation | Providing an interface for demotion control information in a processor |
US10379904B2 (en) | 2016-08-31 | 2019-08-13 | Intel Corporation | Controlling a performance state of a processor using a combination of package and thread hint information |
US10234920B2 (en) | 2016-08-31 | 2019-03-19 | Intel Corporation | Controlling current consumption of a processor based at least in part on platform capacitance |
US10423206B2 (en) | 2016-08-31 | 2019-09-24 | Intel Corporation | Processor to pre-empt voltage ramps for exit latency reductions |
US10168758B2 (en) | 2016-09-29 | 2019-01-01 | Intel Corporation | Techniques to enable communication between a processor and voltage regulator |
US10429919B2 (en) | 2017-06-28 | 2019-10-01 | Intel Corporation | System, apparatus and method for loose lock-step redundancy power management |
US11593544B2 (en) | 2017-08-23 | 2023-02-28 | Intel Corporation | System, apparatus and method for adaptive operating voltage in a field programmable gate array (FPGA) |
JP2019096243A (ja) * | 2017-11-28 | 2019-06-20 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその故障検出方法 |
US10620266B2 (en) | 2017-11-29 | 2020-04-14 | Intel Corporation | System, apparatus and method for in-field self testing in a diagnostic sleep state |
US10620682B2 (en) | 2017-12-21 | 2020-04-14 | Intel Corporation | System, apparatus and method for processor-external override of hardware performance state control of a processor |
US10620969B2 (en) | 2018-03-27 | 2020-04-14 | Intel Corporation | System, apparatus and method for providing hardware feedback information in a processor |
US10739844B2 (en) | 2018-05-02 | 2020-08-11 | Intel Corporation | System, apparatus and method for optimized throttling of a processor |
US10955899B2 (en) | 2018-06-20 | 2021-03-23 | Intel Corporation | System, apparatus and method for responsive autonomous hardware performance state control of a processor |
US10976801B2 (en) | 2018-09-20 | 2021-04-13 | Intel Corporation | System, apparatus and method for power budget distribution for a plurality of virtual machines to execute on a processor |
US10860083B2 (en) | 2018-09-26 | 2020-12-08 | Intel Corporation | System, apparatus and method for collective power control of multiple intellectual property agents and a shared power rail |
US11656676B2 (en) | 2018-12-12 | 2023-05-23 | Intel Corporation | System, apparatus and method for dynamic thermal distribution of a system on chip |
US11256657B2 (en) | 2019-03-26 | 2022-02-22 | Intel Corporation | System, apparatus and method for adaptive interconnect routing |
US11442529B2 (en) | 2019-05-15 | 2022-09-13 | Intel Corporation | System, apparatus and method for dynamically controlling current consumption of processing circuits of a processor |
US11698812B2 (en) | 2019-08-29 | 2023-07-11 | Intel Corporation | System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor |
US11366506B2 (en) | 2019-11-22 | 2022-06-21 | Intel Corporation | System, apparatus and method for globally aware reactive local power control in a processor |
US11132201B2 (en) | 2019-12-23 | 2021-09-28 | Intel Corporation | System, apparatus and method for dynamic pipeline stage control of data path dominant circuitry of an integrated circuit |
US11921564B2 (en) | 2022-02-28 | 2024-03-05 | Intel Corporation | Saving and restoring configuration and status information with reduced latency |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2507833B2 (ja) * | 1990-12-25 | 1996-06-19 | 三菱電機株式会社 | マイクロコンピュ−タ |
JPH07244649A (ja) * | 1994-03-08 | 1995-09-19 | Fujitsu Ltd | 割込処理分散方式 |
US5944840A (en) * | 1997-09-10 | 1999-08-31 | Bluewater Systems, Inc. | Continuous monitor for interrupt latency in real time systems |
US6185639B1 (en) * | 1998-06-05 | 2001-02-06 | International Business Machines Corporation | System and method to reduce a computer system's interrupt processing overhead |
US6633942B1 (en) * | 1999-08-12 | 2003-10-14 | Rockwell Automation Technologies, Inc. | Distributed real-time operating system providing integrated interrupt management |
US20020116563A1 (en) * | 2000-12-12 | 2002-08-22 | Lever Paul D. | Apparatus and method to reduce interrupt latency in shared interrupt systems |
US20050015766A1 (en) * | 2003-07-01 | 2005-01-20 | Brian Nash | Time deadline based operating system |
-
2003
- 2003-07-08 TW TW092118539A patent/TW200502847A/zh unknown
-
2004
- 2004-07-08 US US10/885,628 patent/US7124225B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8930603B2 (en) | 2008-10-21 | 2015-01-06 | International Business Machines Corporation | Interruption facility for adjunct processor queues |
TWI484408B (zh) * | 2008-10-21 | 2015-05-11 | Ibm | 用於附屬處理器佇列之中斷設備 |
US9251106B2 (en) | 2008-10-21 | 2016-02-02 | International Business Machines Corporation | Interruption facility for adjunct processor queues |
US10019393B2 (en) | 2008-10-21 | 2018-07-10 | International Business Machines Corporation | Interruption facility for adjunct processor queues |
US10409745B2 (en) | 2008-10-21 | 2019-09-10 | International Business Machines Corporation | Interruption facility for adjunct processor queues |
US10657085B2 (en) | 2008-10-21 | 2020-05-19 | International Business Machines Corporation | Interruption facility for adjunct processor queues |
Also Published As
Publication number | Publication date |
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TW200502847A (en) | 2005-01-16 |
US7124225B2 (en) | 2006-10-17 |
US20050033881A1 (en) | 2005-02-10 |
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