TWI294634B - Semiconductor device and manufacture method thereof - Google Patents

Semiconductor device and manufacture method thereof Download PDF

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TWI294634B
TWI294634B TW91117635A TW91117635A TWI294634B TW I294634 B TWI294634 B TW I294634B TW 91117635 A TW91117635 A TW 91117635A TW 91117635 A TW91117635 A TW 91117635A TW I294634 B TWI294634 B TW I294634B
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semiconductor device
source
gate
drain
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TW91117635A
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Chinese (zh)
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Huang Weng-Hsing
Kent Kuohua Chang
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Macronix Int Co Ltd
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1294634 修正1294634 amendment

------案號 91117635 五、發明說明(1) 、 本發明是有關於一種半導體元件之結構及其製造方 法’且特別是有關於一種可以改善元件可信度之半導轉一 件之結構及其製造方法。 % 金氧半導體元件(MOS)除了具備閘氧化層以及間極結 構之外,在閘極結構兩旁的基底中更包括具備有電性與石夕 基底相反的半導體區,其稱為源極/汲極。在超大型積體 電路(VLSI )的領域裡,金氧半導體元件的應用相當廣泛, 舉凡邏輯電路以及記憶體元件等等,金氧半導體元件都曰’ 不可或缺的一種半導體元件。 %------ Case No. 91917635 V. Description of the Invention (1) The present invention relates to a structure of a semiconductor element and a method of manufacturing the same, and in particular to a semi-conducting piece which can improve the reliability of the element The structure and its manufacturing method. In addition to the gate oxide layer and the interpole structure, the MOS device includes a semiconductor region having electrical properties opposite to that of the Shixia substrate, which is called a source/汲 in the substrate on both sides of the gate structure. pole. In the field of ultra-large integrated circuits (VLSI), the application of MOS devices is quite extensive, and MOS devices are indispensable for semiconductor devices such as logic circuits and memory devices. %

第1圖所示,其繪示為習知一種半導體元件之結椹 面示意圖。 J /請參照第1圖,習知半導體元件包括一基底丨〇 〇、一閑 .氧化層1 0 2、一閘極1 0 4以及一源極/汲極! 〇 6。其中,閘^ 化層1 0 2係配置在部分基底1 〇 〇之表面上,閘極丨〇 4係配置 在閘氡化層1 0 2上,而源極/汲極丨〇 6係配置在閘極1 〇 4兩側 之基底1 0 0中。 當元件之尺寸隨著積體電路積集度之提高而逐漸縮小 之後,半導體元件之源極/汲極的尺寸亦必須隨之縮小。 然而,源極/汲極尺寸的縮小會造成其阻值之上升,使得 元件之電流變小而導致過高的負載(Over Loading)。倘若 利用增加源極/沒極的接面深度(J u n c t i ο n D e p t h ),以解 決源極/汲極阻值提高之問題,不但會衍生短通道效應 (Short Channel Effect),還容易產生接面漏電 (Junction Leakage)等問題。倘若是利用高濃度之摻雜來 製作淺接面的源極/汲極,以避免因接面過深而引起的短Fig. 1 is a schematic view showing a junction of a conventional semiconductor device. J / Please refer to FIG. 1 . The conventional semiconductor device includes a substrate 〇 , a free oxide layer 1 0 2 , a gate 1 0 4 , and a source/drainage! 〇 6. Wherein, the gate layer 10 2 is disposed on the surface of the portion of the substrate 1 , the gate electrode 4 is disposed on the gate layer 1 0 2 , and the source/drain electrodes 6 are disposed in the gate layer The base of the gate 1 〇4 is 1 0 0. After the size of the device is gradually reduced as the integrated circuit is increased, the size of the source/drain of the semiconductor device must also be reduced. However, the reduction in source/drain size causes an increase in its resistance, which causes the current of the component to become smaller and cause excessive loading. If you increase the source/drain junction depth (J uncti ο n D epth ) to solve the problem of increasing the source/drain resistance, not only will the Short Channel Effect be derived, but it will also be easy to generate. Problems such as Junction Leakage. If high concentration doping is used to make the source/drain of the shallow junction to avoid short due to the junction being too deep

9165twfl.ptd 第4頁 1294634 案號 9Π17635 Λ_η 曰 修正 五、發明說明(2) 通道效應以及接面漏電等問題,則又會因固態溶解度之限 制,而無法克服源極/汲極負載過高的問題。此外,在習 知方法中,更有利用縮小間隙壁並形成淺接面之源極/汲 極的方式以解決短通道效應,但是此種方法卻容易使淺接 面源極/汲極上之金屬矽化物層產生無法接受的接面漏 電。 因此,本發明的目的就是在提供一種半導體元件之結 構及其製造方法,以降低源極/汲極之電阻值。 本發明的另一目的是提供一種半導體元件之結構及其 製造方法,以使源極/汲極之接面能作淺,進而避免產生 短通道效應及接面漏電等問題。 本發明提出一種半導體元件之結構,其包括一基底、 一石夕化錯層(SUed、一緊石夕層(Strained Silicon L a y e r )、一閘氧化層、一閘極以及一源極/沒極。其中, 矽化鍺層係配置在基底之表面上,且緊矽層係配置在矽化 錯層之表面上,在此,緊石夕層之厚度例如是200埃〜1000 埃。另外,閘氧化層係配置在緊矽層上,且閘極係配置在 閘氧化層上。而源極/汲極則是配置在閘極兩側之緊矽層 中,其中源極/汲極可以是N型摻雜區或是P型摻雜區。值 得注意的是,本發明之源極/汲極亦可以配置在閘極兩側 之緊矽層與矽化鍺層中。由於本發明之半導體元件之源極 /汲極係配置在閘極兩側之緊矽層中,因此本發明之半導 體元件之通道區係配置在緊矽層中。 本發明提出一種半導體元件的製造方法,此方法係首 先在一基底上形成一矽化鍺層,並且在矽化鍺層上形成一9165twfl.ptd Page 4 1294463 Case No. 9Π17635 Λ_η 曰 Amendment 5, Invention Description (2) Channel effects and junction leakage, etc., due to solid solubility limitations, can not overcome the source / bungee load is too high problem. In addition, in the conventional method, the method of reducing the gap and forming the source/drain of the shallow junction is used to solve the short channel effect, but this method is easy to make the metal on the shallow junction source/drain The telluride layer produces an unacceptable junction leakage. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a structure of a semiconductor device and a method of fabricating the same to reduce the source/drain resistance value. Another object of the present invention is to provide a structure of a semiconductor device and a method of fabricating the same, so that the junction of the source/drain can be made shallow, thereby avoiding problems such as short channel effects and junction leakage. The invention provides a structure of a semiconductor device, which comprises a substrate, a sinusoidal layer (Seded Silicon Layer), a gate oxide layer, a gate electrode and a source/drain electrode. Wherein, the bismuth telluride layer is disposed on the surface of the substrate, and the layer adjacent to the layer is disposed on the surface of the bismuth layer, wherein the thickness of the layer is, for example, 200 angstroms to 1000 angstroms. It is disposed on the next layer, and the gate is disposed on the gate oxide layer, and the source/drain is disposed in the next layer on both sides of the gate, wherein the source/drain may be N-doped. a region or a P-doped region. It is noted that the source/drain of the present invention can also be disposed in the next layer and the germanium layer on both sides of the gate. Due to the source of the semiconductor device of the present invention / The drain is disposed in the next layer on both sides of the gate, so that the channel region of the semiconductor device of the present invention is disposed in the next layer. The present invention provides a method for fabricating a semiconductor device, which is first performed on a substrate. Forming a tantalum layer and forming a layer on the tantalum layer

916.5twfl.ptd 第5頁 1294634 案號 91117635 Λ_η a 修正 五、發明說明(3) 緊矽層。其中,在基底上形成矽化鍺層,以及在矽化鍺層 上形成緊矽層之方法例如是利用一超高真空化學氣相沈積 法(Ultra High Vacuum-CVD,UHV-CVD),且此超高真空化 學氣相沈積法之一反應氣體係如是S i2H6/GeH4混合氣體。而 所形成之緊矽層的厚度例如是2 0 0埃〜1 0 0 0埃。接著,在 緊矽層上形成一閘氧化層,並且在閘氧化層上形成一閘 極。之後,以閘極為一植入罩幕進行一離子植入步驟,以 在閘極兩側之緊矽層中形成一源極/汲極。在本發明中, 此源極/汲極亦可以形成在閘極兩側之緊矽層與矽化鍺層 中。其中,源極/汲極中所摻雜之離子可以是N型離子或是 P型離子。而由於本發明之半導體元件之源極/汲極係形成 在閘極兩側之緊矽層中,因此本發明之半導體元件之通道 區係位於緊矽層中。 本發明之半導體元件之結構及其製造方法,由於其源 極/汲極係形成在具有較佳導電性之緊矽層或緊矽層與矽 化鍺層中,因此可有效降低源極/汲極之電阻值。 本發明之半導體元件之結構及其製造方法,由於源極 /汲極之電阻值可有效的降低,因此其源極/汲極之接面可 以作淺,以避免短通道效應以及接面漏電等問題。 本發明之半導體元件之結構及其製造方法,非但可使 元件之效能提高,而且還可以提高元件之可信度。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳 細說明如下: 圖式之標示說明:916.5twfl.ptd Page 5 1294634 Case No. 91117635 Λ_η a Amendment V. Description of invention (3) Close to the layer. Wherein, the method of forming a tantalum layer on the substrate and forming the layer on the tantalum layer is, for example, an ultra high vacuum-CVD (UHV-CVD) method, and the ultra high One of the reactive gas systems of the vacuum chemical vapor deposition method is a Si 2 H 6 /GeH 4 mixed gas. The thickness of the layer formed next is, for example, 200 Å to 1 00 Å. Next, a gate oxide layer is formed on the next layer, and a gate is formed on the gate oxide layer. Thereafter, an ion implantation step is performed with the gate as an implant mask to form a source/drain in the immediately adjacent layer on both sides of the gate. In the present invention, the source/drain may also be formed in the next layer and the tantalum layer on both sides of the gate. The ions doped in the source/drain may be N-type ions or P-type ions. Further, since the source/drain electrodes of the semiconductor device of the present invention are formed in the immediately adjacent layers on both sides of the gate, the channel region of the semiconductor device of the present invention is located in the next layer. The structure of the semiconductor device of the present invention and the method for fabricating the same are effective in reducing the source/drainage because the source/drain electrodes are formed in the next layer or the next layer and the tantalum layer having better conductivity. The resistance value. In the structure of the semiconductor device of the present invention and the method of manufacturing the same, since the source/drain resistance can be effectively reduced, the source/drain junction can be shallow to avoid short channel effects and junction leakage. problem. The structure of the semiconductor device of the present invention and the method of fabricating the same can not only improve the performance of the device, but also improve the reliability of the device. The above and other objects, features, and advantages of the present invention will become more apparent and understood.

9165twfl.ptd 第6頁 1294634 案號 91117635 jf:_η a 修正 五、發明說明(4) 100 '200 102 104 106 202 204 212 基底 206 208 210 閘氧化層 閘極 源極/丨及極 石夕化錯層 緊矽層 通道區 實施例 第2 A圖至第2E圖,其繪示為依照本發明一較佳實施例 之半導體元件的製造流程剖面示意圖。 請參照第2 A圖,首先提供一基底2 〇 〇。接著,在基底 2 0 0之表面上形成一矽化鍺層2 0 2,之後在矽化鍺層2 0 2上 形成一緊石夕層2 0 4。而所形成之緊石夕層2 0 4之厚度例如是 2 0 0埃至1 0 0 0埃。 其中,形成矽化鍺層2 〇 2與緊矽層2 0 4之方法例如是利 用一超高真空化學氣相沈積法(Ultra High Vacuum-CVD, UHV-CVD),以在基底200上磊晶成長矽化鍺202層,並且在 矽化鍺層202上磊晶成長緊矽層204。此超高真空化學氣相 沈積法之一反應氣體係如是S i2H6/GeH4混合氣體。此超高真 空化學氣相沈積法之一基本壓力(Base Pressure)例如為2 X 1 Ο-1。Torr,而超高真空化學氣相沈積法之一沈積壓力例 如是小於1 mTorr。另外,此超高真空化學氣相沈積法义 一升溫梯度例如為攝氏1 5 0度/分鐘。 在本發明中,由於所形成之緊矽層2 0 4會有晶格錯位 (Lattice Mismatch)之情形,因此緊石夕層204在雙轴張應9165twfl.ptd Page 6 1294463 Case No. 91917635 jf: _η a Amendment 5, Invention Description (4) 100 '200 102 104 106 202 204 212 Substrate 206 208 210 Gate Oxide Gate Source/丨 and 极石夕化Layer 2 Channel to Channel 2, FIG. 2A to FIG. 2E are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with a preferred embodiment of the present invention. Please refer to Figure 2A for the first step of providing a substrate 2 〇 〇. Next, a tantalum layer 2 2 2 is formed on the surface of the substrate 200, and then a compact layer 2 0 4 is formed on the tantalum layer 2 0 2 . The thickness of the formed tight layer 220 is, for example, 200 Å to 1 00 Å. Wherein, the method of forming the germanium telluride layer 2 〇 2 and the close layer 220 is, for example, an epitaxial growth on the substrate 200 by using an ultra high vacuum-CVD (UHV-CVD) method. The layer 202 is formed and epitaxially grown on the tantalum layer 202 to form the layer 204. One of the reaction gas systems of this ultra-high vacuum chemical vapor deposition method is a Si 2 H6/GeH 4 mixed gas. One of the base pressures of this ultra-high vacuum chemical vapor deposition method is, for example, 2 X 1 Ο-1. Torr, and one of the deposition pressures of ultra-high vacuum chemical vapor deposition is, for example, less than 1 mTorr. Further, the ultra-high vacuum chemical vapor deposition method has a temperature rise gradient of, for example, 1,500 degrees Celsius per minute. In the present invention, since the formed close layer 206 has a lattice mismatch, the compact layer 204 is in the biaxial tension.

9165twfl.ptd 第7頁 1294634 ---案號91117635_年月曰__ 五、發明說明(5) 變(Biaxial Tensile Strain)之情形下,會使得緊矽層 2 0 4之鍵結結構有所修飾。而且,緊矽層2 〇 4之張應變可以 使其所謂表面粗糙度之分散限制(Surface Roughness9165twfl.ptd Page 7 1294463 --- Case No. 91917635_年月曰__ V. Inventive Note (5) In the case of Biaxial Tensile Strain, the bonding structure of the next layer of 2 0 4 will be Modification. Moreover, the strain of the layer 2 〇 4 can limit the so-called surface roughness (Surface Roughness)

Scattering-Limited)獲得改善。 之後,請參照第2B圖,在緊砍層2 04之表面上形成一 閘氧化層2 0 6。其中,形成閘氧化層2 0 6之方法例如是一熱 氧化法,且所形成之閘氧化層2 〇 6之厚度例如是2 0埃至3 5 埃。 值得注意的是,在形成閘氧化層2 0 6之步驟中’其底 部之緊矽層2 0 4會被消耗而變得較薄。而且,由於閘氧化 層206係形成在緊矽層204之表面,因此閘氧化層206與緊 石夕層2 0 4之間的介面會非常的爭滑且均勻。 之後,在閘氧化層2 0 6上形成一閘極2 0 8。其中,閘極 2 0 8之材質例如是多晶石夕,且形成閘極2 0 8之方法例如是先 在閘氧化層206上沈積一層多晶石夕層之後’再圖案化多晶 矽層以形成閘極2 0 8。 繼之,請參照第2 C圖,在形成閘極2 〇 8之後,將未被 閘極2 0 8覆蓋之閘氧化層2 0 6移除,而僅留下閘極2 〇 8底部 之閘氧化層2 0 6 a。 然後,請參照第2 D圖,在閘極2 0 8兩侧之緊石夕層2 0 4中 形成一源極/沒極2 1 0。其中,形成源極/汲極2 1 0之方法例 如是利用閘極2 0 8為一植入罩幕進行一離子植入步驟,以 在閘極2 0 8兩側之緊矽層2 〇 4中形成源極/汲極2 1 0。另外, 本發明之源極/汲極2 1 〇亦可以形成在閘極2 0 8兩側之緊矽 層204與矽化鍺層202中(如第2E圖所示)。其中,對Scattering-Limited) improved. Thereafter, referring to Fig. 2B, a gate oxide layer 206 is formed on the surface of the undercut layer 206. The method of forming the gate oxide layer 206 is, for example, a thermal oxidation method, and the thickness of the gate oxide layer 2 〇 6 formed is, for example, 20 Å to 35 Å. It is to be noted that in the step of forming the gate oxide layer 206, the bottom layer of the bottom layer 2 0 4 is consumed and becomes thinner. Moreover, since the gate oxide layer 206 is formed on the surface of the next layer 204, the interface between the gate oxide layer 206 and the compact layer 206 is very smooth and uniform. Thereafter, a gate 2 0 8 is formed on the gate oxide layer 206. Wherein, the material of the gate electrode 202 is, for example, polycrystalline stone, and the method of forming the gate electrode 202 is, for example, first depositing a layer of polycrystalline silicon on the gate oxide layer 206 to 'repattern the polysilicon layer to form Gate 2 0 8. Then, referring to Figure 2C, after forming the gate 2 〇8, the gate oxide layer 206 that is not covered by the gate 2 0 8 is removed, leaving only the gate at the bottom of the gate 2 〇8. The oxide layer is 2 0 6 a. Then, referring to Figure 2D, a source/dimpole 2 1 0 is formed in the tight layer 2 0 4 on both sides of the gate 2 0 8 . The method for forming the source/drain 2 1 0 is, for example, performing an ion implantation step using the gate electrode 202 as an implant mask to close the layer 2 〇 4 on both sides of the gate 2 0 8 . The source/drain 2 1 0 is formed. Alternatively, the source/drain 2 1 本 of the present invention may be formed in the next layer 204 and the tantalum layer 202 on both sides of the gate 206 (as shown in Fig. 2E). Among them, right

9165twfl.ptd 第8頁 1294634 #:_η 曰9165twfl.ptd Page 8 1294634 #:_η 曰

案號 91117635 五、發明說明(6) Ρ-MOSFET元件而言,於源極/汲極210中所植入之 是侧或BF2+離子,而對N-MOSFET元件而言,於源離子例如 2 1 0中所植入之離子例如是磷或砷離子。值的注|及極 倘若源極/汲極2 1 〇中所植入之離子係為磷或坤離^的是, 石夕化鍺層2 0 2中之源極/汲極210較容易會有擴散之情’妒位於 而偶若源極/汲極2 1 0中所植入之離子係為硼或B F 2+ ^ , 則可抑制位在矽化鍺層2 0 2中之源極/汲極2 1 〇擴散之情 形0Case No. 91917635 V. Description of Invention (6) For Ρ-MOSFET components, side or BF2+ ions are implanted in source/drain 210, and source ions such as 2 1 are used for N-MOSFET components. The ions implanted in 0 are, for example, phosphorus or arsenic ions. The value of the source | and if the source / bungee 2 1 所 implanted in the ion system is phosphorus or Kun away ^, the source of the Shi Xihua 锗 layer 2 0 2 / bungee 210 is easier If there is a diffusion phenomenon, the ion system implanted in the source/dip pole 2 1 0 is boron or BF 2+ ^ , which can suppress the source/汲 in the bismuth telluride layer 202. Extreme 2 1 〇 diffusion situation 0

特別值得一提的是,由於本發明之半導體元件之源極 />及極2 1 〇係配置在閘極2 〇 8兩側之緊矽層2 〇 4中,或是配置 在閘極2 0 8兩側之緊矽層2 0 4與矽化鍺層2 0 2中,因此本發 明之半導體元件之通道區2 1 2係位於緊矽層2 0 4中。 另外’由於形成在較鬆散的矽化鍺層2 〇 2上之緊矽層 2 0 4會有晶格錯位之情形,因此緊矽層2 〇 4在雙軸張應變 (Biaxial Tensile Strain)之情形下,會使得緊矽層204It is particularly worth mentioning that since the source/> and the pole 2 1 of the semiconductor device of the present invention are disposed in the immediately adjacent layer 2 〇 4 on both sides of the gate 2 〇 8 or in the gate 2 The 0 2 and the bismuth layer 2 0 2 on both sides of the 0 8 are, therefore, the channel region 2 1 2 of the semiconductor device of the present invention is located in the immediately adjacent layer 204. In addition, due to the fact that the close layer 2 0 4 formed on the looser tantalum layer 2 〇 2 has a lattice misalignment, the layer 2 〇 4 is in the case of Biaxial Tensile Strain. Will make the layer 204

之鍵結結構有所修飾。因此,緊矽層2 〇 4非但有增進傳輸 載子之能力,而且緊矽層2〇4之張應變還可改善所謂表面 粗链度之分散限制。因此,形成在矽化鍺層2 〇 2表面上之 緊石夕層204具有可提高電子移動率以及減少聲子分散 (Ph〇non Scattering)等功效。在本發明之半導體元件 ^ ’由於源極/沒極2 1 〇係形成在緊矽層2 〇 4中,且其通道 區2 1 2亦位於緊矽層中2 〇 4,因此,本發明之半導體元件非 但可使凡件驅動電流提高,而且還可增進元件之效能。 除此之外,由於矽化鍺層2 0 2之導電性以及緊矽層2 0 4 之電子移動率都較傳統矽基底佳,因此本發明之源極/汲The bonding structure is modified. Therefore, the layer 2 〇 4 not only has the ability to enhance the transport of the carrier, but the strain of the layer 2〇4 can also improve the dispersion limit of the so-called surface thick chain. Therefore, the compact layer 204 formed on the surface of the bismuth telluride layer 2 has an effect of improving electron mobility and reducing phonon dispersion (Ph〇non Scattering). In the semiconductor device of the present invention, since the source/drain 2 1 is formed in the next layer 2 〇 4, and the channel region 2 1 2 is also located in the next layer 2 〇 4, therefore, the present invention The semiconductor component not only increases the drive current of the device, but also enhances the performance of the component. In addition, since the conductivity of the bismuth telluride layer 202 and the electron mobility of the next layer 205 are better than those of the conventional germanium substrate, the source/汲 of the present invention

II Μ 1294634 案號 91117635 曰 修正 五、發明說明(7) 極210之電阻值可以有效的降低。而由於之源極/汲極210 之電阻值可以有效的降低,因此源極/汲極之接面可以作 淺,以避免短通道效應以及接面漏電等問題。如此一來, 非但元件之效能可以提高,而且還可以提高元件之可信 度。因此,本發明之具有緊矽層之半導體元件,在次-0. 1 微米(Sub-0· 1 #m)的CMOS技術中係為一種相當具潛力的元 件結構設計。 綜合以上所述,本發明具有下列優點: 1. 本發明之半導體元件之結構及其製造方法,由於其 源極/汲極係形成在具有較佳導電性之緊矽層或緊矽層與 矽化鍺層中,因此可以有效降低源極/汲極之電阻值。 2. 本發明之半導體元件之結構及其製造方法,由於源 極/汲極之電阻值可有效的降低,因此其源極/汲極之接面 可以作淺,以避免短通道效應以及接面漏電等問題。 3. 本發明之半導體元件之結構及其製造方法,非但可 使元件之效能提高,而且還可以提高元件之可信度。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。II Μ 1294634 Case No. 91117635 修正 Amendment 5. Inventive Note (7) The resistance value of pole 210 can be effectively reduced. Since the resistance of the source/drain 210 can be effectively reduced, the source/drain junction can be shallow to avoid short-channel effects and junction leakage. In this way, not only the performance of the component can be improved, but also the reliability of the component can be improved. Therefore, the semiconductor element of the present invention having a close-knit layer is a relatively promising element structure design in the sub-0.1 micron (Sub-0·1 #m) CMOS technology. In summary, the present invention has the following advantages: 1. The structure of the semiconductor device of the present invention and the method of fabricating the same, since the source/drainage system is formed in a tight layer or a close layer with better conductivity In the germanium layer, the source/drain resistance value can be effectively reduced. 2. The structure of the semiconductor device of the present invention and the method of fabricating the same, since the source/drain resistance can be effectively reduced, the source/drain junction can be shallow to avoid short channel effects and junctions. Leakage and other issues. 3. The structure of the semiconductor device of the present invention and the method of manufacturing the same can not only improve the performance of the device, but also improve the reliability of the device. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

9165twfl.ptd 第10頁 1294634 案號 91117635 年月曰 修正 圖式簡單說明 第1圖為習知一種半導體元件的結構剖面示意圖;以 及 第2 A圖至第2 E圖為依照本發明一較佳實施例之半導體 元件的製造流程剖面示意圖。9165twfl.ptd Page 10 1294463 Case No. 91917635 曰 曰 曰 曰 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 911 A schematic cross-sectional view of a manufacturing process of a semiconductor device.

9165twfl.ptd 第11頁9165twfl.ptd Page 11

Claims (1)

1294634 修正 包括 案號 91117635 六、申請專利範圍 1 . 一種半導體元件之結構 一基底; 一石夕化鍺層,配置在該基底上; 一緊石夕層(strained silicon layer),酉己置在該石夕化 條遍 !无 ,配置在該石夕 鍺層之表面上,其中該緊矽層係為雙軸張應變; 一閘氧化層,配置在部分該緊矽層上; 一閘極,配置在該閘氧化層上;以及 一源極/沒極,配置在該閘極兩側之該緊石夕層中。 2 ·如申請專利範圍第1項所述之半導體元件之結構, 其中該源極/汲極係配置在該閘極兩側之該緊矽層與該矽 化鍺層中。 3. 如申請專利範圍第1項所述之半導體元件之結構, 其中該緊矽層之厚度係為2 0 0埃〜1 0 0 0埃。 4. 如申請專利範圍第1項所述之半導體元件之結構, 其中該源極/汲極係為一 N型摻雜區。 5. 如申請專利範圍第1項所述之半導體元件之結構, 其中該源極/汲極係為一P型摻雜區。 6 .如申請專利範圍第1項所述之半導體元件之結構, 其中該閘氧化層之厚度係為2 0埃〜3 5埃。 7. 如申請專利範圍第1項所述之半導體元件之結構, 其中該閘極之材質包括多晶矽。 8. —種半導體元件的製造方法,包括: 在一基底上形成一 &夕化鍺層; 在該石夕化錯層上形成一緊石夕層(strained silicon1294634 The amendment includes the case number 91917635. VI. Patent application scope 1. A structure of a semiconductor component; a stone layer on the substrate; a strained silicon layer, which is placed on the stone夕化条过! None, disposed on the surface of the stone layer, wherein the layer is a biaxial tensile strain; a gate oxide layer is disposed on a portion of the layer; the gate is disposed in The gate oxide layer; and a source/no pole are disposed in the tight layer on both sides of the gate. 2. The structure of the semiconductor device of claim 1, wherein the source/drain is disposed in the next layer on both sides of the gate and the germanium layer. 3. The structure of the semiconductor device according to claim 1, wherein the thickness of the layer is 200 Å to 1 Å. 4. The structure of the semiconductor device of claim 1, wherein the source/drain is an N-type doped region. 5. The structure of the semiconductor device of claim 1, wherein the source/drain is a P-type doped region. 6. The structure of the semiconductor device according to claim 1, wherein the gate oxide layer has a thickness of 20 Å to 35 Å. 7. The structure of the semiconductor device of claim 1, wherein the material of the gate comprises polysilicon. 8. A method of fabricating a semiconductor device, comprising: forming an & enamel layer on a substrate; forming a tight silicon layer on the stone layer 9165t.wf2.ptc 第12頁 1294634 _案號91117635_年月日__ 六、申請專利範圍 layer),其中該緊矽層係為雙軸張應變; 在該緊矽層上形成一閘氧化層; 在該閘氧化層上形成一閘極;以及 在該閘極兩側之該緊矽層中形成一源極/汲極。 9.如申請專利範圍第8項所述之半導體元件的製造方 法,其中該源極/汲極係形成在該閘極兩側之該緊矽層與 該石夕化鍺層中。 1 0 .如申請專利範圍第8項所述之半導體元件的製造方 法,其中該緊矽層之厚度係為2 〇 〇埃〜1 〇 〇 〇埃。 1 1 .如申請專利範圍第8項所述之半導體元件的製造方 法,其中在該基底上形成該矽化鍺層以及在該矽化鍺層之 表面形成該緊矽層之方法包括一超高真空化學氣相沈積 法。 1 2 .如申請專利範圍第1 1項所述之半導體元件的製造 方法,其中該超高真空化學氣相沈積法之一反應氣體包括 S i 2 Η 6 / G e Η 4混合氣體。 1 3 .如申請專利範圍第1 1項所述之半導體元件的製造 方法,其中該超高真空化學氣相沈積法之一基本壓力係為 2x10-10 Torr 〇 1 4.如申請專利範圍第1 1項所述之半導體元件的製造 方法,其中該超高真空化學氣相沈積法之一沈積壓力係小 於 1 m T 〇 r r 。 1 5.如申請專利範圍第1 1項所述之半導體元件的製造 方法,其中該超高真空化學氣相沈積法之一升溫梯度係為9165t.wf2.ptc Page 12 1294463 _ Case No. 91917635_年月日日__ Six, application patent scope layer), wherein the tight layer is biaxial tensile strain; forming a gate oxide layer on the next layer Forming a gate on the gate oxide layer; and forming a source/drain in the immediately adjacent layer on both sides of the gate. 9. The method of fabricating a semiconductor device according to claim 8, wherein the source/drain is formed in the next layer on both sides of the gate and the layer. The method of manufacturing a semiconductor device according to claim 8, wherein the thickness of the layer is 2 〇 〜 〜1 〇 〇 〇. The method of manufacturing a semiconductor device according to claim 8, wherein the method of forming the germanium telluride layer on the substrate and forming the compact layer on the surface of the germanium telluride layer comprises an ultra-high vacuum chemistry Vapor deposition method. The method of manufacturing a semiconductor device according to the above aspect of the invention, wherein the reaction gas of the ultra-high vacuum chemical vapor deposition method comprises a mixed gas of S i 2 Η 6 / G e Η 4 . The method for manufacturing a semiconductor device according to claim 11, wherein one of the basic pressure systems of the ultra-high vacuum chemical vapor deposition method is 2×10 −10 Torr 4.1 4. A method of fabricating a semiconductor device according to any one of the preceding claims, wherein a deposition pressure system of the ultra-high vacuum chemical vapor deposition method is less than 1 m T 〇rr . 1 . The method of manufacturing a semiconductor device according to claim 1 , wherein a temperature gradient of the ultra-high vacuum chemical vapor deposition method is 9165twf2.ptc 第13頁 1294634 _案號91117635_年月日 修正_ 六、申請專利範圍 攝氏1 50度/分鐘。 1 6 ·如申請專利範圍第8項所述之半導體元件的製造方 法,其中形成該源極/沒極之方法包括以該閘極為一植入 罩幕進行一離子植入步驟,而形成該源極/沒極。 1 7.如申請專利範圍第8項所述之半導體元件的製造方 法,其中該源極/汲極中所掺雜之離子包括砷離子或磷離 子。 1 8.如申請專利範圍第8項所述之半導體元件的製造方 ’ 法,其中該源極/汲極中所摻雜之離子包括硼離子或BF 2+ ‘ 離子。 1 9.如申請專利範圍第8項所述之半導體元件的製造方 _ 法,其中形成該閘氧化層之方法包括利用一熱氧化法以在 該緊矽層之表面上形成厚度為2 0埃〜3 5埃之該閘氧化層。9165twf2.ptc Page 13 1294634 _ Case No. 91917635_Yearly Date Correction _ VI. Patent application range: 50 degrees Celsius/minute. The method of manufacturing a semiconductor device according to claim 8, wherein the method of forming the source/drainage comprises performing an ion implantation step by using the gate as an implant mask to form the source Extreme / no pole. 1. The method of fabricating a semiconductor device according to claim 8, wherein the ions doped in the source/drain include arsenic ions or phosphorus ions. The method of fabricating a semiconductor device according to claim 8, wherein the ions doped in the source/drain include boron ions or BF 2+ ions. 1. The method of fabricating a semiconductor device according to claim 8, wherein the method of forming the gate oxide layer comprises using a thermal oxidation method to form a thickness of 20 Å on the surface of the immediately adjacent layer ~ 3 5 angstroms of the gate oxide layer. 9165twf2. pt.c 第14頁9165twf2. pt.c第14页
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