TWI292195B - Semiconductor chip assembly with metal containment wall and solder terminal - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor wafer package structure, and more particularly to a semiconductor chip package structure having a metal end of a solder end and a method of fabricating the semiconductor chip package structure. [First as technology] _ The current semiconductor chip has input/output pads, which must be connected to external circuits to achieve some of the functions of the electronic system. The medium to be connected is primarily an array of metal wires (e.g., a lead frame) or a support circuit (e.g., a substrate substrate), although the medium of the connection can be directly connected to a circuit operation panel (e.g., a motherboard). Many connection technologies are widely used, including wire bonding, tape automated bonding (TAB), and flip-chip I bonding. During the next layer of assembly, the semiconductor chip package structure is continuously connected to other circuits such as a printed circuit board (PCB) or motherboard. Different semiconductor chip packages are combined in the next layer in different ways. For example, a ball grid array (BGA) includes a solder ball array, and the planar grid array (LGA) system includes a metal pin array, the metal pin array, It receives traces of tin on the printed circuit board. 5 1292195 • 'The ball format array consists mainly of tin balls melted on the metal surface of the nickel end, so the solder balls are the contact ends of the next layer combination. When the solder ball is separated from the surface of the metal element, the ball format array structure becomes inaccessible or ineffective. The traditional solder ball contact technology is designed to allow the solder balls to be easily fused to the surface of the metal 70. For example, a continuous thin money record and a thin layer of gold on the surface of the f-elements have a smooth and flat surface that allows the tin ball to be fused on the surface of the metal enamel, but the problem of separation of the solder ball cannot be avoided. The traditional solder ball contact technology is combined with a contact insulator. For example, BT tree moon day (diaza bismuth polyamine, poxy) on the solder ball enhances the mechanical contact of the solder ball. However, the ball is easily separated from the resin and has the same problem as the surface of the aforementioned metal element. The semiconductor chip package structure has different limitations. It needs to be developed on the semiconductor chip package structure to be more economical, reliable, and capable of providing superior mechanical and electronic features: The advantages of the known application range. SUMMARY OF THE INVENTION The main object of the present invention is to provide a soldering end metal structure and to provide a low cost, high economy 6 1292195 and high reliability package. The present invention is based on the method of manufacturing a semiconductor wafer package structure which is convenient and economical. In summary, the present invention provides a semiconductor wafer comprising a semiconductor wafer having a V-pin position, a conductive trace having a winding, a metal wall and a fresh terminal, and a power supply between the winding and the conductive pin. Connection connection. The metal wall system includes a hole that is in contact with and is isolated from the metal wall in the hole. The invention also provides a method for fabricating the semiconductor chip package structure comprising a metal substrate, a wire, a metal wall and a solder layer, wherein the metal wall has a hole for the fresh terminal and the hole Contacting the metal wall and connecting the semiconductor wafer to the route, and forming a 2 joint portion for electrically connecting the winding and the conductive pin, and then 'minding the metal substrate to reduce the metal substrate •, winding, and the contact area between the metal substrate and the metal wall, and the soldering end of the solder layer. According to the content of the present invention, the semiconductor chip package structure has a first vertical direction and an opposite second vertical direction, and includes a first surface corresponding to a lateral * σ, parent semiconductor chip package structure. And a second planar semiconductor wafer, wherein the first plane of the semiconductor bonding comprises a conductive pin, and the conductive trace comprises a second wire, a metal wall and a soldering end, wherein the route is connected from the metal wall The end k extends, the metal wall comprises a hole, and has a 7 1292195 a:::<§# "the gold f wall system is the only one in the semiconductor chip package structure" n casting contact Contacting the inner wall and the wall of the hole can electrically connect the wire between the winding and the conductive pin. The sealing agent is in contact with the semiconductor wafer, and a winding wire and a metal wall are in contact. The semiconductor wafer is embedded in the (four) agent. The metal wall is embedded in the (four) insulating substrate, extending perpendicularly from the first direction of the soldering end and extending perpendicularly from the second side t of the winding. In the insulating substrate, the splicing 1 extends into the insulating substrate but is not covered by the semiconductor chip package structure in the second direction of the soldering end, and the overall soldering extends to the insulating substrate (4). In the surface area, the metal wall is not entangled in the welding end H direction. The semiconductor wafer can be embedded in the encapsulant as a single wafer or embedded in the encapsulant. The first plane of the semiconductor wafer faces the first direction and the second plane of the semiconductor wafer faces the second direction 'or the first flat = the second direction of the semiconductor wafer and the second plane of the semiconductor wafer The facing semiconductor wafer is vertically extended from the winding, the metal wall, the soldering end and the insulating substrate in a first direction. = The conductive trace extends vertically in the first direction. In addition, the inside of the sealant can be vertically extended from the conductive trace. 1292195, the winding system can extend laterally from the metal wall and the solder end and face the semiconductor wafer. The winding system can extend perpendicularly from the metal wall and the soldering end in a first direction and can extend vertically from the semiconductor wafer in a second direction. The winding can extend inside and outside the edge of the semiconductor wafer or can be placed outside the edge of the semiconductor wafer. The winding is also flat and parallel to the second plane of the germanium semiconductor wafer. The winding system can be in contact with the metal wall but is not integrated with the metal wall and can be isolated from the metal wall. Moreover, the winding is between the metal wall and any semiconductor wafer embedded in the encapsulant, and the soldering end has a conductive path between the semiconductor wafer and any semiconductor wafer embedded in the encapsulant. Any semiconductor wafer embedded in a sealant can have a conductive connection between the metal wall and the soldered end by a conductive path containing the force of the winding. The metal wall can be embedded in the insulating substrate. The metal wall is vertically extending in the first direction and can extend perpendicularly from the semi-crystal 1, the winding: the connecting portion and the encapsulant in the second direction, and outside the edge of the conductor wafer or outside the edge thereof. The metal wall 2: the only conductor in the solar package structure and is in contact with the solder, and is transverse to the extension and the periphery is rotated 360 degrees. 1 The entire soldered end of the substrate is Γυ-shaped and parallel to the first direction and the first The two-direction plane is - round, a rectangle or a positive direction and the ^ direction is orthogonal, and is at the mouth of the job. The gold 1292195 • The thickness of the wall can be simultaneously thinner than the thickness of the wire and can be a single metal such as nickel and can include a continuous single surface to define the hole. The metal wall is only in contact with the winding, the soldering end and the insulating substrate, or only with a metal post, the soldering end and the insulating substrate. The hole can extend through a height and a diameter of a majority of the metal wall and can be covered by the metal wall in a first direction and a lateral direction, and includes an opening facing the second direction, the hole being a concave shape . Spring The welded end can extend inside or outside the hole or can be placed in the hole. The solder end can extend perpendicularly from the semiconductor wafer, the wire, the connection and the encapsulant in a second direction and be placed within or outside the edge of the semiconductor wafer. For example, the soldering end can extend inside and outside the hole, and extends perpendicularly from the metal wall and the insulating substrate in the second direction, and is covered by the metal wall in the second direction. The welded end can fill the hole. Further, a portion of the soldering end extending into the insulating base is in the hole and is only in contact with the metal wall and is restricted in the first direction and the lateral direction by the metal. Moreover, all contact between the welded end and the metal wall is in the hole. The connecting portion extends between the winding and the conductive pin and electrically connects the winding and the conductive pin. The joint can be an electrometallic metal, an electroless metal, a tin, a conductive adhesive or a wire. The encapsulant can cover the semiconductor wafer, the winding, the metal wall, the fused end, the connecting portion and the insulating substrate in the first direction, and can be isolated from the metal wall and the soldering end. a μ 1292195 • the insulating substrate can extend straight from the metal wall and the fresh terminal to the first side, and vertically extend from the semiconductor wafer, the winding, the connecting portion and the sealant=the second direction, and cover the semiconductor wafer In the second direction, and can be isolated from the soldering end. The insulating substrate can be rotated 360 degrees transverse to the periphery of the metal wall. Moreover, the insulating substrate can be laterally arranged with the metal wall in a plane facing the second direction, and the soldering end can be placed in the hole and laterally arranged in the direction facing the second direction or the soldering end can Extending inside and outside the hole, ^ extends perpendicularly from the plane toward the second direction toward the second direction. "The conductive trace can comprise a metal post that is in contact with the wire and the metal wall and provides electrical connection between the winding and the metal wall, but is not integrated with the winding and the metal wall, and Isolating from the metal wall and extending laterally from the metal column. ·, '' The metal pillar can extend from the metal wall and the soldering end to the first direction from the semiconductor wafer, the winding, the connecting portion and the sealing - extending vertically and capable of being placed on the semiconductor wafer = and 1 = can be covered by the winding in the first direction (four) / metal wall and the known end covering the second direction. The thickness of the simultaneous winding Thicker, and _ gold two gold = a conical shape whose diameter is the surface area of the plane = the second plane of the second I292195, the first of the metal walls is at least larger than the surface area of the second plane of the metal wall. The area sealing body chip packaging structure can comprise an insulating substrate with a semiconductor wafer, the insulating substrate extending perpendicularly from the semiconductor chip in the second direction. The dry body 曰曰»海 semiconductor chip package structure transmission end Power guide = package In the foot position and recording, the person J control, the conductive path requires a turntable, a wall and a connecting portion, and the winding (four) can be used for the conductive foot: a horizontal winding is provided between the ends of the f but not vertical Winding, the gold wall is attached to the soldering end and other conductive _ no winding. ', the semiconductor chip packaging structure is a first-level structure or a multi-chip package. According to other aspects of the present invention The method for manufacturing a semiconductor wafer package structure includes (1) providing a metal substrate, a winding, a metal wall, and a solder layer, wherein the metal substrate includes a first plane and an opposite second plane, The first plane of the metal substrate faces the first direction 'the second plane of the metal substrate faces the second direction, and the metal wall extends into the metal substrate from the first plane of the metal substrate toward the metal substrate a plane extending and including a hole extending from a second plane of the metal substrate toward the first plane to the metal substrate and opening in the direction, the solder layer contacting the metal wall in the hole (2) Mechanically connecting the semiconductor wafer to the winding, the semiconductor 12 1292195 wafer system includes a conductive pin, and (3) forming a connection portion for electrically connecting the winding and the conductive pin, (4) Etching the metal substrate by a wet chemical etching method, thereby reducing a contact area between the metal substrate and the winding and the metal substrate and the metal wall, and (5) h· providing a soldering end, the zinc terminal The metal layer in the hole is in contact with and includes the solder layer. The method includes forming a winding system by depositing the winding on the metal substrate. For example, the method may include forming a plating mask. On the metal substrate, the plating mask includes an opening to partially expose the metal substrate, and then the wire passing through the plating mask is plated on the exposed portion of the metal substrate.

The method includes forming a metal wall by depositing the metal wall on a metal substrate, wherein the method comprises forming an electric ore mask on the metal substrate, the plating mask having an opening to make the metal The substrate is partially exposed and then the metal wall is plated through the opening in the plating mask to the exposed portion of the metal substrate. The method includes forming the metal wall by etching the metal base: forming a via hole, extending from a second plane of the metal substrate toward the first plane of the gold: substrate to the metal substrate, and then making the gold The wall deposits and enters the via. For example, the via hole can be a two-hole 'passing through the gold; the substrate is exposed, and the metal wire can pass through the metal substrate to contact the winding and utilize the thirst Chemistry (4) The metal substrate is subjected to a smattering of H between the metal substrate 13 1292195 and the winding, between the metal substrate and the winding, and between the gold eyebrow substrate and the metal wall. Or the via hole has a recess extending into the metal substrate but not penetrating, and is isolated from the first plane and the winding of the metal substrate, and the metal wall can extend into the metal substrate But not penetrating and isolating from the first plane and the winding of the metal substrate, etching the metal substrate by wet chemical etching and forming a metal pillar from the unetched portion of the metal substrate, the metal substrate is not etched The portion is defined by a metal wall that is in contact with the winding and the metal wall. The method includes forming a solder layer formed by depositing the solder layer on the metal wall. Similarly, the solder layer is formed such that the solder layer is in contact only with the metal wall. The method of forming the soldered end is by forming the solder layer or forming the solder layer and then forming a soldered end. For example, forming the solder joint end can include depositing a solder paste on the metal wall, then reflowing the solder paste to form a far solder layer and a solder end, or depositing the solder paste on the metal wall, and then reflowing the solder paste to form the solder layer. Then, a solder material is deposited on the fresh joint layer, and the solder material and the solder layer are reflowed to form the solder joint. The method includes forming a metal wall and a solder layer by etching the metal substrate to form the via hole, then depositing the metal wall on the metal substrate and in the via hole, and then depositing the solder layer on the metal wall. For example, the metal wall and the solder layer are formed in sequence, including: 1.292195. The metal substrate is formed to form the via hole, and the metal wall is plated on the exposed portion of the metal substrate and in the via hole, and then A solder paste is deposited on the metal wall, and then the solder paste is reflowed to form the solder layer. Moreover, sequentially forming the via hole and the metal wall comprises: forming an opening on the metal substrate, partially exposing the metal substrate, and then etching the metal substrate through the opening of the mask to form The via hole is then plated through the opening of the mask to plate the metal wall in the portion of the metal substrate and in the via hole, and the mask is removed, or an etch mask is formed on the opening On the metal substrate, the metal substrate is partially exposed, and the metal substrate is etched through the opening of the etch mask to form the via hole, and then the etch mask is removed, and then an open plating mask is formed. The metal substrate is partially exposed and exposed to the via hole, and then the metal wall is plated through the opening of the plating mask to the exposed portion of the metal substrate and the via hole. And removing the plating mask. In addition, sequentially forming the solder layer includes: passing the mask having an opening (providing an etch mask to the via hole and providing a plating mask to the metal wall) to deposit the solder paste thereon On the metal wall, the solder paste is reflowed, and then the mask is removed; or the mask is removed, the solder paste is deposited on the base metal wall, and the solder paste is reflowed. Similarly, sequentially forming the solder layer includes: passing the plated mask with the opening (the plated mask attached to the metal wall and the etch mask after the via hole is removed) to make the tin Paste depositing the metal wall, reflowing the solder paste, and removing the electro-mineral mask or removing the electro-mineral mask, depositing the solder paste on the metal pillar, and allowing the solder paste to reflow . The second bonding method is to bond the semiconductor wafer to the winding system to place the semiconductor wafer between the semiconductor wafer and the metal substrate, and then harden the adhesive. The method includes forming a joint by electrowetting the joint between the winding and the conductive foot. For example, the connection portion is wired between the winding and the conductive pin by means of electroplating or electroless ore. Or ❿ ♦ The method of forming the joint is such that a non-solid material is deposited between the winding and the conductive foot and then the non-solid material is hardened. For example: the solder paste can be deposited between the winding and the conductive pad and then reflowed and hardened by the fact that the conductive adhesive can be placed between the winding and the conductive pin and then hardened. The method of forming the joint is formed by wire bonding. The method includes etching the metal substrate by wet chemical etching, thereby exposing the wire and removing the metal substrate in the conductive pin and the edge of the semiconductor wafer. For example, etching the metal substrate by wet chemical etching can remove the contact area between the metal substrate and the winding and the metal substrate and the metal wall, and can remove the metal substrate, or use wet chemical etching. Etching the metal substrate, and forming a metal pillar from the unetched portion of the metal substrate, wherein the un-etched portion of the metal substrate is defined by the metal wall, and the metal pillar is in contact with the winding and the metal wall And to have a power connection between the winding and the metal wall' and remove most of the metal substrate. Moreover, etching the metal substrate by wet 1292195 type chemical etching enables the winding to be electrically isolated from other windings in contact with the substrate, and the conductive pin is electrically connected to other conductive pins of the semiconductor wafer. Ground isolation. For example, the method of forming the connecting portion is performed by wire bonding, and then the metal substrate is engraved by the wet and the nickname, so that the winding is electrically isolated from the other windings, and the conductive pin is Other conductive feet are electrically isolated. Or the method of forming the connection portion is electroplating and using the metal substrate as an electroplating bus bar, and then the metal substrate is surnamed by wet chemical remnant, thereby electrically isolating the winding from other windings, and The conductive pin is electrically isolated from the other conductive pins. Or the method of etching the metal substrate is performed by wet chemical etching, thereby electrically isolating the winding from other windings, and then forming the connecting portion by electroless plating, wherein the conductive pin can still be electrically conductive with other conductive places. The feet are electrically isolated. The method includes forming a winding before forming the metal wall, or the winding is formed simultaneously with the metal wall, or forming the winding after the metal wall is formed. The method includes forming the metal wall prior to forming the solder layer. The method comprises forming a metal wall before the semiconductor wafer is connected to the metal substrate and the winding, or forming a metal wall after the semiconductor wafer is connected to the metal substrate and the winding. The method comprises forming a solder layer before the semiconductor wafer is connected to the metal substrate and the winding, or forming a solder layer after the semiconductor wafer is connected to the metal 17 1292195 substrate and the winding. The soldering layer is formed before the soldering end is formed, or the solder joint is formed as the soldering end. a front-formed metal substrate (4) the metal substrate is formed by the wet chemical (4) method (4), and the semiconductor wafer is connected to the metal substrate to form the soldering end, or the semiconductor wafer is connected to the metal substrate and the winding The soldered end is formed later. The method includes forming the soldering end before forming the connecting portion, or forming the soldering end after forming the connecting portion. The method is carried out by forming the soldered end on the metal substrate by wet chemical (4) or by etching the metal substrate by wet chemical characterization. The method includes forming the metal wall, then forming the solder layer 'and then connecting the semiconductor wafer to the metal substrate, the winding, the metal wall, and the recording layer' and then etching the gold substrate by wet chemistry (4). The method includes forming the metal wall, then joining the semiconductor wafer to the base metal substrate, the winding and the metal wall, and then forming the solder layer' and etching the metal substrate by wet chemical etching. 1292195 The method includes joining the semiconductor wafer to the metal substrate and the rim and then forming the metal wall, then forming the solder layer, and etching the metal substrate by wet chemical etching. The method includes forming a sealant after connecting the semiconductor wafer to the metal substrate, and the sealing agent is connected to the semiconductor wafer. And covering the semiconductor crystal chip in the first direction. The sealant is formed by transfer molding or hardening. The method comprises the steps of: forming an insulating substrate after forming the sealing agent, the insulating substrate contacting the winding, the metal wall and the soldering layer and covering the winding, the metal wall and the soldering layer in the second direction and then removing one Part of the insulating substrate such that the insulating substrate no longer covers the solder layer in the second direction. The method includes: (1) providing a metal substrate having a first surface and a first plane, wherein the first plane of the metal substrate faces the first direction, and the second plane of the metal substrate faces the second direction (2) then forming a winding on the first plane of the metal substrate, wherein the winding wire is in contact with the first plane of the metal substrate and is isolated from the first plane of the metal substrate, (3) then utilizing a wet chemical etching etches the metal substrate to form a via hole in the metal substrate, and the via hole extends from the second plane of the metal substrate to the first plane of the metal substrate to the base metal substrate, and then forms a a metal wall on the metal substrate, wherein the metal wall is in contact with the metal substrate in the via hole, and extends from the second plane of the metal substrate to the first substrate of the metal substrate to the metal substrate, and includes a hole extending from a second plane of the metal substrate to a first plane of the metal substrate into the metal substrate, and covered by the metal wall in a first direction, and including Opening to the opening in the third direction, (7) forming a fresh contact and contacting the metal wall in the hole, and isolating the winding, (6) mechanically connecting a semiconductor wafer to the metal substrate and the winding, wherein The semiconductor wafer includes a conductive pin, (7) forming a connection portion, and electrically connecting the winding and the conductive pin, and (8) etching the metal substrate by first wet chemical etching to connect the semiconductor After the wafer reaches the metal wall and the winding and forming the metal wall and the soldering layer, thereby reducing the contact area between the metal substrate and the winding and the metal wall and the metal substrate, and (9) providing a soldering end, the soldering The end system is in contact with the metal wall in the hole and includes the solder layer. The method includes: (1) providing a metal substrate, wherein the metal substrate comprises an opposite first plane and a second plane, wherein the metal substrate a first plane facing the first direction and a second plane of the metal substrate facing the second direction relative to the second direction 'and then (2) forming a winding on the first plane of the metal-resistant substrate, wherein the winding Contacting the first plane of the metal substrate and isolating the second plane of the metal substrate, (3) the metal J is etched by the first wet chemical etching, thereby forming a via hole in the metal substrate The via hole extends from the second plane of the metal storm plate to the first plane of the metal substrate to the metal substrate ('4) forming a metal wall on the metal substrate, wherein 20 1292195 the metal wall and The metal substrate in the via hole contacts and extends from the second plane of the metal substrate to the first plane of the metal substrate into the metal substrate, and includes a hole from the second plane of the metal substrate a first plane of the metal substrate extends into the metal substrate and is covered by the metal wall in a first direction, and includes an opening facing the second direction, and (5) forming a solder joint layer, the solder layer Contacting the metal wall in the hole, isolating the winding, (6) connecting the semiconductor wafer to the metal substrate and the winding, wherein the semiconductor chip system comprises: a conductive pin '(7) forming a connecting portion, The connecting portion electrically connects the winding and the conductive pin, and (8) forms a sealing agent after connecting the semiconductor wafer to the metal substrate and the winding, wherein the sealing agent is in contact with the semiconductor wafer And from the semiconductor

The wafer, the metal substrate and the winding extend perpendicularly in a first direction, the gold substrate extends perpendicularly from the semiconductor wafer and the winding to the second direction, and (9) the metal substrate is etched by the second wet chemical etching After forming the metal wall, the solder layer and the sealant, thereby reducing the contact area between the word metal substrate and the winding and the metal substrate and the metal wall, (10) forming an insulating substrate, the insulating substrate and the winding Contacting the metal wall and the soldering layer, and covering the winding, the metal wall and the fresh layer in the second direction, after performing the (4) on the metal substrate by using the second wet chemical etch, (1)) removing - A portion of the insulating substrate is such that the insulating substrate no longer covers the solder layer in the second direction and (12) provides a material end that is in contact with the metal wall of the hole and includes the solder layer. 21 1292195 </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The solder paste is deposited on the far metal wall, and then the solder paste is reflowed to form the solder layer. The method includes forming the soldering end by forming the soldering layer, or by depositing a solder material on the soldering layer, after etching the metal substrate by using a second wet chemical etching, and then The solder material and the solder layer are reflowed together to form the solder end. The method includes connecting the semiconductor wafer to the metal wall and the winding (if the metal wall and the solder layer have been formed) by placing the insulating adhesive between the semiconductor wafer and the metal substrate, and then bonding the metal The agent hardens. The method includes etching the metal substrate by using a first wet chemical etching to form the via hole, the via hole is a through hole, the _ system extends through the metal substrate, and the wire is exposed, and then the first The second wet chemical etching etches the metal substrate by removing the contact area between the metal substrate and the winding and between the metal substrate and the metal wall, and removing the metal substrate, or using the first wet chemical Forming the via hole by the metal substrate, the via hole may be a recess and extending into the metal substrate without passing through the metal substrate, and then etching the metal substrate by using a second wet chemical etching And forming a metal pillar from the unetched portion of the metal substrate, the metal pillar is electrically connected between the winding and the metal wall, and removes most of the metal substrate of 22 1292195. The method includes removing the insulating substrate from the portion by grinding, laser ablation, plasma etching or photolithography. In addition, the method includes removing the insulating substrate from the entire insulating substrate, and the insulating substrate of the portion refers to the insulating substrate covering the metal wall and the soldering layer in the second direction, and the metal wall and the soldering The layer is exposed in the first direction, but the winding is not exposed. For example, the method includes polishing the insulating substrate by grinding, but not grinding the metal wall and the soldering layer, and then grinding the insulating substrate, the metal wall, and soldering The layer is stopped until the insulating substrate and the metal wall and the solder layer are laterally arranged on a plane facing the second direction, and the metal wall and the solder layer are exposed. And after the grinding is stopped, the soldering end is composed of the soldering layer and can be laterally arranged on the plane, or the method includes depositing a fresh tin material on the soldering layer, and then reflowing the soldering material and the soldering layer together. And forming the soldering end, the soldering end extends perpendicularly from the gold-wall and the insulating substrate in the second direction. The method includes etching the metal substrate by using a first wet chemical etching to form the via hole, then forming the metal wall, and then forming the solder layer, and then connecting the semiconductor wafer to the metal substrate, the winding, and the metal wall And soldering the layer, then forming the encapsulant, then etching the metal substrate by the second wet chemical etching, then forming the insulating substrate, and finally removing a portion of the insulating substrate. 23 1292195 The method includes etching the metal substrate by using a first wet chemical etching to form the via hole, then forming the metal wall, and then connecting the semiconductor wafer to the metal substrate, the winding and the metal wall, and then forming the The encapsulant is then formed into the solder layer, and then the metal substrate is etched using the second wet chemical residue, followed by forming an insulating substrate, and finally removing a portion of the insulating substrate. The method includes connecting the semiconductor wafer to the metal substrate and the wound metal wall, and then forming the sealant, and then forming the via hole by using the first wet chemical surname to form the via hole, and then forming the metal wall Then, the solder layer is formed, and then the metal substrate is etched by the second wet chemical etching, then the insulating substrate is formed, and finally the portion of the insulating substrate is removed.

Rely on. Another good virtual injury left uncle can therefore reduce the separation of the material and improve the reliability. The H is because the connecting material can be made of various materials. The advantage of the invention is that the semiconductor chip packaging structure can be easily manufactured and economical. Sex. Another advantage of the present invention is that the metal substrate can be reduced in contact area between the metal substrate and the metal wall by (4), thereby reinforcing the mechanical support and protecting the winding. Another benefit is that the metal (4) can be improved by _ formation compared to electroplating or electroless ore and reduces manufacturing time and cost. Another (iv) 24 1292195 material and process manufacturing are formed, so that mature joining techniques can be utilized to facilitate manufacturing and to improve manufacturing methods. Another benefit is that the semiconductor wafer package structure does not include wire bond or tape automated bond wires, although the process is elastic and compatible with other techniques. Another advantage is that the semiconductor chip package structure is fabricated using low temperature processing to reduce stress and improve reliability. In addition to the above, the present invention has an advantage in that, for example, the semiconductor chip package structure can be manufactured by a well-controlled process, and can be easily built into a circuit board, a lead frame, and a tape reel. Still other benefits are that the semiconductor chip package structure is capable of fabricating a semi-conductor wafer such as copper and a wireless environment using compatible materials. The features and advantages of the present invention will be further described in the embodiments of the present invention. [Embodiment] 1A to 27 (Fig. 1A is a first embodiment of the semiconductor wafer package, and the first embodiment is shown in Fig. 1A, FIG. 7A is a schematic plan view, and the first to the second embodiment are shown in FIG. ^ 1 ^之丰: See "1st", and 1. Figure is a schematic view of a two-conductor wafer structure, a schematic view of the semiconductor crystal structure of the present invention, and a semiconductor wafer structure of the present invention. As shown in the figure, the present invention is a 25 1292195 conductor chip package structure for soldering end metal walls, wherein the semiconductor wafer 11 is an integrated circuit and is composed of a plurality of transistors, circuits, connections and The semiconductor wafer 11A includes a corresponding first plane 112 and a second plane 114, and the thickness between the first plane 112 and the plane 114 is ls 〇 micrometer. The first plane 'n' is an active surface and includes a conductive pin ι6 and a passivation layer. In essence, the conductive pin 116 is aligned with the protective layer 118, so that The table of the first plane 112 The conductive pin U6 can extend over the protective layer 18 or be embedded in the protective layer 118. The conductive pin 116 provides a connection between the junction and the external portion of the semiconductor wafer 11 . Therefore, the conductive pin ι6 can be an input/output pin or a power/ground pin. The length and width of the conductive pin Π6 are each 1 μm. The conductive pin 116 has an aluminum. The substrate, the conductive pin 116 is cleaned by immersing the semiconductor wafer 11 at room temperature t〇〇5m 4酉1, and then cleaning with steaming water. The conductive pin 116 can view the aluminum substrate a first surface layer, or the conductive pin layer 6 includes a surface layer covering the aluminum substrate and contacting the surface layer according to the nature of the connecting portion. In the first embodiment, the connection The 4 series is a metal gold wire (&amp;8〇1(1一^1)〇11(1). Therefore, the conductive pin position 6 cannot be regarded as accommodating the connection portion, or the conductive pin position 116 can be at least More than one metal layer is stacked on the aluminum substrate 26 1292195. The pin position π 6 may be chromium / steel layer / gold layer, or titanium layer / recording layer / gold layer on the contact substrate, wherein the chromium layer or the layer provides a substrate barrier (a barrier) and the upper metal layer and the Ming substrate door a toxic smear agent. However, the metal layer stacking system is selectively deposited by utilizing a mask for acetabulum, electroplating, or sputtering. Alternatively, the conductive pin 116 can also be formed on the substrate by forming a nickel surface layer, such as the semiconductor wafer 11 can be immersed in a zinc solution 'deposited-zinc layer (four)|s substrate, the method is For lexification (zmcation). Furthermore, the zinc solution described above comprises 15 g/L of sodium hydroxide (NaOH), 25 g/L of zinc oxide (Zn〇) and 1 g/L of sodium nitrite (NaN〇3), just like Tartaric acid reduces the decomposition rate of the aluminum substrate. Thereafter, the nickel surface layer is electrolessly deposited on the zincated aluminum substrate, and a suitable electroless nickel plating solution is Enthone Enplate NI-424 at 85 degrees Celsius. The semiconductor wafer 110 includes at least one or more conductive pins on the first plane 112, but only a single conductive pin Η 6 is shown in the figure for convenience of illustration and description. In addition, the semiconductor wafer 11 has been separated from other semiconductor wafers, and the semiconductor wafer is originally attached to a wafer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2A, 2B and 2C are schematic cross-sectional views showing a metal substrate structure of the present invention, a plan view of a metal substrate structure of the present invention, and a bottom view of the metal substrate of the present invention. As shown in FIG. 27 1292195, the metal substrate 120 includes a corresponding first major plane 122 and a second major plane 124. The metal substrate 120 is a metal copper plate having a thickness of 150 μm. Please refer to the drawings of FIGS. 3A, 3B and 3C for a schematic cross-sectional view of the photoresist layer and the metal substrate structure of the present invention, a schematic plan view of the photoresist layer and the metal substrate structure of the present invention, and a photoresist layer of the present invention. The metal substrate structure is a bottom view. As shown in the figure, the first photoresist layer 126 and the second photoresist layer 128 are formed on the metal substrate 120. The first photoresist layer 126 and the second photoresist layer 128 are deposited by a dry film lamination process (a dry fihn laminati Qn), and simultaneously the first photoresist layer 126 and the second photoresist layer i28 are respectively The geothermal roll is printed on the first major plane 122 and the second major plane 124. A reticle (not shown) is placed adjacent to the second photoresist layer 128. Thereafter, the second photoresist layer 128 is printed with a pattern by selectively passing light through the mask, and removing the photoresist portion using a de- ing solvent (a deVeloper), and by light The light = partially soluble and then dried (hard(10)(4)). The second photoresist layer 128 includes an opening having a diameter of micrometers and selectively exposing the second major plane 124, and the first photoresist layer 126 is not patterned. The first photoresist layer 126 and the second photoresist layer 128 have a thickness of 25 μm, which are calculated from the first main plane (2) and the second main plane 丨24, respectively. 28 1292195 Please refer to the schematic diagram of the scraping surface of the metal substrate structure of the notch of the present invention, the top view of the metal substrate structure with the notch of the present invention, and the notched portion of the present invention, as shown in "4A, 4C, and 4C" The metal substrate structure is a bottom view. As shown in the figure: the notch m is = on the metal substrate 120. The formation of the recess 130 is by

A back_side wet chemicaI: The exposed portion of the second major plane 124 is etched, and the second photoresist layer 128 is the remaining mask. Because of the first, the barrier 126 can protect one side of the metal substrate 120, for example, a m nozzle (not shown) can spray the wet chemical etching solution at the time, and is a top nozzle (in the figure) Not shown) is not used when the photoresist L is immersed in the wet chemical (iv) solution and the second 3 = factory end protection. The wetted side solution is made of selective copper, and the metal substrate 120 is engraved with 80 micrometers: to = 130 is a blind hole (ablindvia), and from the second principal capital of the ten faces of the two main planes Inside, but did not penetrate the metal substrate. Extending to the second major plane 124 2 / recess 13 of the plane of the metal substrate 120, the second port 130 is 300 micrometers relative to the second plane, the recess is 8 micrometers, and the depth of the first plane flute - the main plane 124 For micrometers. The main plane 122 is 70 water apart. 29 1292195 The ideal etching time for substrate 120 to be exposed to the chemical etching solution is established by a repeat test. Referring to FIG. 5A, FIG. 5B and FIG. 5C, the metal wall of the present invention is a schematic cross-sectional view of a metal substrate, the metal wall of the present invention is formed on a metal substrate structure, and the metal wall of the present invention is formed. The metal substrate structure is a bottom view. As shown, the metal wall 132 is formed in the recess 1邗 of the metal substrate 12 and conforms to the contour of the pocket 130. The metal wall covers the recess 130 in a downward direction and is deposited in the recess 13 but does not fill the recess 130. The metal wall 132 is electrically connected to the metal substrate 120, but is not integrated with the metal substrate 12. The metal wall 132 is composed of a nickel layer plated on the metal substrate 12 and a gold layer plated on the nickel layer (not shown). The nickel layer is sandwiched between the metal substrate 120 and the gold layer and buried with the metal substrate 12, and the gold layer is in contact with the nickel layer and isolated from the metal substrate 120. Therefore, the recording layer is covered by the gold layer, and the gold layer is exposed. The metal niche 32 has a thickness of 丨 0.1 μm. Specifically, the thickness of the nickel layer is Η) microns, and the thickness of the gold layer is G l microns. For the sake of convenience, the nickel layer and the gold layer are only shown as a single layer in the figure. . The formation of the ruthenium metal 132 is performed by using the first photoresist layer and the second photoresist 28 as an electric hood. Therefore, the metal wall 132 is formed. Initially, an electric clock bus &amp; 1292195 plating bus (not shown) is connected to the metal substrate 12A, and a current generated from an external power source is used for the plating busbar, and the metal substrate 120 is used. / Remaining in an electrolytic recording solution ((10) eiectr〇iyfjc nickel plating solution), such as Technic TechniNickel "S" at room temperature. Finally, the nickel layer is plated on the exposed portion of the recess 130 of the metal substrate 12. However, the nickel plating process is continued until the nickel layer reaches the desired thickness. Thereafter, the overall structure is removed from the electrolytic nickel plating solution, and then immersed in an electrolytic gold plating solution, such as Technic Orotemp at room temperature, while current obtained by an external power source is used for the plating busbar to make the gold layer It is plated on the nickel layer and gold plating is continued until the gold layer reaches the desired thickness. However, the overall structure is removed from the electrolytic gold plating solution and the water is flushed to remove the contaminants. 4 The shape of the wall 132 is a bowl shape, the vertical plane of which is a concave shape, and the second main plane, the first circle, and the upward direction == plane to the upward direction and the downward direction. The shape can be 夕古方6 and orthogonal to the downward direction. The metal wall 132 has a surface of 80 micro-seeking, and the ancient one has a diameter of 300. The diameter of the main plane 124 is "the thickness of the gold (four) 132 is i (M micron. But the whole 2 has a slight thickness variation) It may be better than the second main 芈... The 蜀 蜀 土 132 is thicker near the second main plane 丨 24, because the metal wall 132 near the ten sides 124 is dissolved by _ ”. The first nickel layer of the joint and the tantalum and the continuous single gold layer 31 1292195. The metal wall 132 has a hole 134, the hole 134 is ... the metal substrate is separated and extends to the concave The hole 134 extends toward the metal wall 132 and passes through most of the height and diameter of the metal wall 132. The hole η# is covered by the metal wall j32 in the upward direction and the lateral direction, and includes an opening 136. 4, the opening is oriented downward, and forms a concave surface, the shape of the pothole. As shown in the figure 6A, 6B and 6C, which is the invention, the structure of the raft is covered by the second photoresist layer. The cross-sectional schematic view, the weight of the present invention is repeated on the junction of the second photoresist layer A top view and a schematic view of the template of the present invention disposed on the second photoresist layer are shown in the figure. The thickness of the blank plate 138 is 8 μm and includes an opening of two pemng. 2 μm, the opening of the first photoresist layer 128 of the template β, the metal wall I” and the hole I)* are vertically arranged. For the convenience of illustration, the metal substrate 12 is drawn on the die&gt; Above, and maintaining a fixed orientation can be conveniently compared with the previous figure, although the overall architectural direction is collapsed, and the gravity system will help the template 138 to cover the second photoresist layer 128. Please refer to "7th, 7th, Β" And the 7C diagram is a schematic cross-sectional view of the structure of the present invention, which is deposited on the metal wall, the tin used in the present invention, and the top view of the structure of the metal wall and the solder paste of the present invention deposited on the metal wall. The structure is a bottom view. As shown in the figure, the solder paste contains powdered titanium-silver-copper tin particles mixed in a viscous resin solvent containing 32 1292195 resin, which contains a flux. The solder paste 140 utilizes a template. Printing to be deposited on the gold On the wall 132. In the stencil printing process, a squeegee (not shown) squeezes the solder paste! 4 〇 along the template 138 relative to the surface of the metal substrate 12 (), through the The opening of the second photoresist layer 28 and the opening of the template 138 are extruded into the metal wall 132 and the hole 134. The solder paste 14 can be formed into any shape at room temperature, so the solder paste 140 can be filled. The hole 134 is in the opening of the second photoresist layer 128 and the opening of the template 丨 388. However, the solder paste 140 is separated from the metal substrate 12 然而. However, the solder paste 140 and the metal substrate 12 〇 Isolation. For ease of illustration, the metal substrate 12 is drawn above the tindan 140 and kept in a fixed orientation in order to be compared with the previous figure. Although the overall structure is reversed, gravity can help the solder paste 14 sink. Referring to FIG. 8A, FIG. 8B and FIG. 8C, it is a schematic cross-sectional view of the structure after removing the raft of the present invention, a schematic view of the 2-frame after removing the template of the present invention, and a template after removing the template of the present invention. The structure does not reflect on the picture. As shown in the figure, it is a schematic diagram of the template 138 being removed from the second photoresist layer 128. For the convenience of illustration, the metal substrate 12 (M will be made above the tin '140, the sub-maintaining direction is to be compared with the previous figure, and the overall structure is reversed' when the template 138 is removed. The tin is covered with 140 by gravity to help cover the structure. 33 1292195 9B and 9C are shown in the cross section of the t structure of the present invention, and the tin of the present invention is referred to as "the formation of the solder paste of the 9A, 9B". After the solder layer

A schematic top view of the structure after the paste is formed into a solder layer and a schematic view of the structure of the solder paste of the present invention after forming a fresh joint layer. As shown in the figure, the singer layer 142 is in contact with the metal wall 132 and has an electrical connection, but is not integrated with the metal wall 132 and is isolated from the metal substrate 120. Moreover, 'the soldering layer 142 fills the hole 134 and has a thickness of 30 micrometers' with respect to the metal substrate 12, the metal 璧 132 ' w... eight from I, and the tin particles in the tin lean 140 react. And removing oxides from the metal walls 132 and the tin particles in the solder paste 14 to melt the solder particles, and the tin particles are combined and organic in the solder paste 14 Resin #瘵发' Therefore, the solder paste 140 is smaller than its original size and produces tin reflow. In addition, the gold layer of the metal nib 32 provides a wettable surface. In order to reflow the tin material and decompose the molten tin, the metal wall 132 is a double metal layer composed of a nickel layer and The structure of the gold layer is changed by a nickel layer of a single piece of metal. Moreover, the second photoresist layer 128 restricts the solder from flowing back to the metal wall 132 and prevents the solder from contacting the metal substrate 丨2(). Thereafter, the heating is stopped and the melted tin particles are cooled and solidified, and when hardened, 34 1292195 becomes the solder layer 142. The solder layer 142 has a diameter of 280 μm and is arranged perpendicular to the opening of the second photoresist layer 128, the metal walls 132, and the holes 34. For ease of illustration, the metal substrate 12 is drawn over the solder layer 142 and maintained in a fixed orientation in order to be aligned with the previous figure. Although the overall structure is reversed, when the solder layer 142 is formed, the tin material Reflow by gravity. Please refer to FIG. 10A, FIG. 10B and FIG. 10C for a schematic cross-sectional view of the first photoresist layer and the second photoresist layer after stripping, the first photoresist layer and the second photoresist of the present invention. After the layer is stripped, the schematic view and the structure of the first photoresist layer and the second photoresist layer of the present invention are taken up from the bottom. As shown in the figure: the first photoresist layer 126 and the second photoresist layer 128 are removed by using a solvent, which is an alkaline solution of brewing 5, and has a pH of 9, which is when the light is The resist agent is suitable for copper, nickel, and tin, so the metal substrate 120, the metal wall 132, or the tin metal layer 142 is not removed. ^ 凊 "11A, 11B, and 11C", which is a schematic cross-sectional view of the third photoresist layer and the fourth photoresist layer formed on the metal substrate, the third photoresist layer of the present invention, and The top view of the structure in which the fourth photoresist layer is formed on the metal substrate, and the structure in which the third=resist layer and the fourth photoresist layer of the present invention are formed on the metal substrate are shown in a bottom view as shown in the figure. The resistive layer 144 and the fourth photoresist layer 140 35 1292195 = the third photoresist layer i44 and the fourth main resist layer 146 are respectively hot-rolled on the first main plane 122 and the second surface 124 by a dry film lamination process. . An reticle (not shown) is placed adjacent to the photoresist layer 144. Thereafter, the third photoresist layer has a pattern by selectively passing light through the mask, and removing the *block portion using a developing solvent (adeveloper), and causing the photoresist to be bruised by light. Is soluble, then baked (hard bakin magic. So the Lu third photoresist layer 144 has an opening and selectively exposes the first major planar first major plane 22), and the fourth light The second photoresist layer M4 and the fourth photoresist layer 146 have a thickness of 50 micrometers, and are respectively from the first main plane, the first main plane 122, and the second main plane, the second main plane. Referring to the "12A, 12B, and 12C", it is a schematic cross-sectional view of the structure of the present invention when the winding is attached to the metal substrate, and the structure of the present invention is attached to the metal substrate. A schematic view of the structure of the φ winding of the present invention attached to the metal substrate. As shown in the drawing, the winding 150 is formed on the first main plane 122 of the metal substrate 12 () and the second main plane 124, the metal wall 132 and the solder layer 142 are isolated. The winding 150 is comprised of one a nickel layer of the metal substrate 12 and a copper layer plated with a nickel metal layer, the nickel layer is in contact with the metal substrate 120 and sandwiched between the metal substrate 12 and the copper layer, and the copper The layer is in contact with the nickel layer and is isolated from the metal substrate 12. Therefore, the nickel layer is covered by the copper layer, and the copper layer is exposed by the storm 36 1292195. The thickness of the winding 150 is 3 μm. In particular, the thickness of the recording layer is 5 micrometers, and the thickness of the copper layer is 25 micrometers. For convenience of illustration, the recording layer and the steel layer are not shown in the figure, and only a single metal layer is formed. The third photoresist layer 144 and the fourth photoresist layer 146 are formed by electro-mineral treatment for the electric ore mask. Initially, an electric ore® flow row (not shown) is connected to the metal substrate. 2〇, provided by Lu external power supply (4) can be expected to flow (4), and the metal substrate 120 is immersed in the -electrolytic solution, such as Technic Techni Nicke s" at room temperature. Therefore, the recording layer is deposited (deposited or lengthened) on the exposed portion of the metal substrate 12G, and then the plating is continued. After the nickel layer reaches the required thickness, the structure is removed from the electrolytic bismuth plating solution and immersed in an electrolytic copper electroplating solution, such as Se丨-Rex CUBath μτμ at room temperature. Current can be used for the electroplating busbar, so that the copper layer is plated on the nickel layer, and copper plating is continued until the copper layer reaches the required thickness. After that, the carcass structure is removed from the electrolytic copper plating solution and washed with (4) water = The line 150 is a flat plane that includes an elongated routing portion 152 and an enlarged circular portion 154 (enlarged circu丨ar p〇rti〇n) . The elongated winding portion (5) and the larger circular portion 154 are adjacent to each other and on the same plane. The elongated winding portion 152 has a width of $100 μm, and the larger circle "37 1292195 / u彳^ _ micron." and the elongated winding portion 152 is lateral from the larger circular portion 154. The metal wall 132 and the solder layer 142 are arranged perpendicular to the larger circular portion 154. Please refer to the "3A, 13B, and 13c" diagrams for the third photoresist layer. And a structure of the fourth photoresist layer after peeling off. The third photoresist layer and the fourth light-resist layer peeled off junction, the top view and the third photoresist layer and the fourth photoresist of the present invention. The structure of the layered stripped structure is shown in a bottom view. As shown in the figure, the third photoresist layer 144 and the fourth photoresist layer 146 are removed by using a solvent, which is a warm alkaline solution, and the pH thereof is 9. When the photoresist is applied to copper, nickel and tin, the metal substrate 12, the metal wall 132, the solder layer 142 or the winding 15 are not removed. Please refer to "14A, MB and MC". Figure 2 is a schematic cross-sectional view showing the structure of the welding mask of the present invention on a metal substrate and a winding, and the welding mask of the present invention is applied to a metal base. And a schematic top view of the structure when the winding is wound and a schematic view of the structure of the welding mask of the present invention on the metal substrate and the winding. As shown in the figure: the welding mask l56 (S〇lda mask) is a liquid resin, which is Deposited on the metal substrate 12 and the winding 150. After that, the liquid resin can be solidified or hardened at a relatively low temperature, and the relative temperature ranges from 1 degree Celsius to 250 degrees Celsius. The liquid resin forms a solid insulative epoxy layer having a thickness of 50 micrometers and is in contact with and wound from the metal substrate 12 and the winding 38 1292195 150. The line ι5〇 extends upwards by a micron. Thereafter, the upper portion of the solder mask 156 is removed by grinding. Specifically, a rotating diamond wheel (a such as a jamond sand wheel) and distilled water are used for the soldering cover. The front side of the cover i56. Initially, the diamond grinding wheel only grinds the welding mask i56, and when the grinding is continued, the welding mask 156 is thinned when the surface to be polished migrates downward. The stone grinding wheel contact _ to ° Hai, the % line 150 hits 'so the grinding 150 is started to be ground, and when the grinding is continued, the winding 150 &amp; welding mask 156 is simultaneously thinned when the surface to be ground migrates downward. Until the winding 150 and the soldering mask 156 reach the required thickness and contact with the metal substrate before stopping = grinding ', then the whole body is steamed and cleaned and the sweat is removed. When the grinding is completed, the winding 150 and The solder mask 156 extends 25 microns upward from the /metal substrate 20. Thus, the polishing process removes the upper portion of the 5 micron thick wire 15 turns and the upper portion of the 25 micrometer thick solder mask 156. At this stage, the money cover w is continuous and in contact with the winding 150 and covers the edge side of the winding 150. However, the solder material 156 is no longer covered in the upward direction of the winding 150, so that the winding 150 and the solder mask 156 are exposed. Moreover, the winding 150 and the welding mask 156 are laterally arranged on an upwardly facing plane. Thus, an exposed horizontal surface includes the winding 150 39 Ϊ 292195 and the solder mask 156 and faces upward. Referring to FIG. 15A, FIG. 15B and FIG. 15C, FIG. 15 is a cross-sectional view showing the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention, and the fifth photoresist layer and the sixth photoresist of the present invention. A schematic plan view of the structure after the layer is formed and a schematic view of the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are formed. As shown in the figure, the fifth photoresist layer is formed on the winding 150 and the solder mask 156, and the sixth photo-progenit layer 160 is formed on the metal substrate 12 and the metal wall I. And the soldering layer 142. The fifth photoresist layer 158 and the sixth photoresist layer 16 are deposited in a liquid form and are respectively deposited on the corresponding plane by roll coating. A retide (not shown) is placed in the vicinity of the fifth photoresist layer 158. Thereafter, the sixth photoresist layer 16 is printed with a pattern, and selectively transmits light through the mask, and uses a developing The developer removes the photoresist portion and makes the photoresist portion soluble by light, and then hardbaking. Therefore, the fifth photoresist layer 58 has an opening. The winding 15〇 is selectively exposed, and the sixth photoresist layer 160 is not printed with a pattern. The fifth photoresist layer 158 and the sixth photoresist layer 160 have a thickness of 5 μm and are respectively wound from the winding. Line 150 and metal substrate 丨2〇 are calculated. Please refer to “Figures 16A, 16B and 16C” for the winding of the rabbit. A schematic cross-sectional view of the structure, a schematic view of the structure in which the electroplated contacts of the present invention are formed after winding, and a schematic view of the structure in which the electroplated contacts of the present invention are formed after winding, as shown in FIG. 1292195. The plated contact is in contact with the winding 150 and has an electrical connection, but is not integrated with the winding 15〇 and is isolated from the metal substrate 120. The plating contact 162 is plated by the winding. a nickel plating layer of 150 and a gold layer plated with a nickel layer, the nickel layer being in contact with the winding 15 and the gold layer, and sandwiched between the winding 150 and the gold layer, and the gold layer The nickel layer is in contact with and is isolated from the winding 150. Therefore, the nickel layer is covered by the gold layer, and the gold layer is exposed. The plating contact 162 has a thickness of 3.5 micrometers, in particular, The thickness of the nickel layer is 3 micrometers, and the thickness of the gold layer is 〇·5 micrometers. For convenience of illustration, the nickel layer and the gold layer are not shown, and only a single metal layer is drawn. The fifth photoresist layer 158 and the sixth photoresist layer '6' are formed by plating a plating mask. First, a mine bus (not shown) is connected to the metal substrate, and is immersed in an electrolytic nickel plating solution from the outer plate, and the solution is continuously electroplated as in the chamber rJt5rrJCTechniNickeI^ Until the recording layer reaches the liquid shift: and = degree. However, 'the whole structure is removed from the electrolytic nickel electroplating solution, and the solution is electrolyzed, and the solution is discharged at room temperature, so that the 兮 no motor can be used for the electroplating. The confluence reaches the nickel layer' and continues to pay for the gold layer until the gold layer is occupied. The whole difficult structure is then removed from the electrolysis copper electrocatalyst 41 1292195 and washed with distilled water to remove contaminants. Please read "Dimensions, 〗 7B and 17C" as shown in the figure: the schematic diagram of the structure of the fifth photoresist layer and the sixth photoresist layer after peeling off, the fifth photoresist layer of the present invention and the The junction of the six photoresist layers is a top view and the fifth photoresist layer and the sixth photoresist layer of the present invention: a schematic view of the structure of Luo. As shown, the fifth photoresist layer US, the /, and the photoresist layer 160 are removed by using a solvent which is an alkaline bath of a dish having a pH of 9, Applicable when the photoresist is applied to copper, nickel, tin and epoxy. Therefore, the metal substrate 12, the metal wall 132, the solder layer 142, the winding 15 〇, the fresh mask 156 or the plating contact 162 are not removed. Please refer to FIG. 18A, (10) and FIG. 18C for a schematic cross-sectional view of the structure in which the adhesive of the present invention is formed after the solder mask, and a schematic plan view of the structure in which the adhesive of the present invention is formed after the solder mask and the present invention. The structure in which the adhesive is formed after the zinc-shield mask is shown in a bottom view. As shown in the figure: the adhesive 164 may contain an organic surface pr〇tectant, such as hk 2000, and the adhesive 164 is attached to the fifth photoresist layer 及58 and sixth. The light layer 160 is removed for use in the overall structure to reduce the generation of natural emulsions on the exposed steel layer surface. The semiconductor wafer package structure assembly process uses the organic surface protectant in the insulating adhesion technique. Then, a latent resin such as polyamic acid is deposited on the solder mask 156 by stencil printing using a 42 1292195 stencil, and a template (not shown) is placed on the winding 15 during stencil printing. On the solder mask 156, a stencii opening is arranged in a row with the metal substrate and offset from the winding 15 and then a squeegee (not shown) Squeezing the liquid resin along the surface of the stencil toward the corresponding solder mask 156, through the stencil opening, over the solder mask 156, but not the metal substrate 12, the winding 15 〇 or the plating Point 162. The liquid resin can be molded into any shape at room temperature. Therefore, the liquid resin can flow and cover a portion of the solder mask 156' but still be isolated from the metal substrate 120, the wire 150, and the plated joint 162. Referring to the drawings of Figs. 19A, 19B and 19C, there are shown a schematic cross-sectional view of a semiconductor wafer of the present invention, a schematic plan view of a semiconductor wafer of the present invention, and a bottom view of the structure of the semiconductor wafer of the present invention. As shown in the figure, the adhesive 164 is in contact with the semiconductor wafer 110 and the solder mask 156, and extends between the semiconductor wafer 110 and the solder mask 156, but still with the metal substrate 120, the winding 150, and The plating contacts 162 are isolated. The first plane n2 of the semiconductor wafer 110 is oriented upward and away from the solder mask 156 and exposed; and the second plane 114 of the semiconductor wafer H is facing down and facing the solder mask I 56 and is The adhesive wafer 16 is covered by the semiconductor wafer 11 and the metal substrate 12, and the semiconductor wafer 11 and the windings 50 are not in contact with each other, and the semiconductor wafer 110 and the solder mask 156 are 436. They are not in contact with each other. The adhesive 164 is sandwiched between the semiconductor wafer 11 and the solder mask 156 by using a relatively low pressure on the pick-up head (pick_up heacj), which is placed on the adhesive wafer 64 and needs to be pressed. The semiconductor wafer 110 is applied to the adhesive for 5 seconds and then the semiconductor sa sheet 1 1 放松 is relaxed. The pick-up head is heated to a relatively low temperature, such as 150 degrees relative to a low temperature, and the adhesive 164 receives heat from the pick-up head and passes it to the semiconductor wafer 11A. Thus, the adhesive 164 is specifically polymerized next to the semiconductor wafer system and forms a colloid but is not completely solidified, and the adhesive 164 is specifically polymerized and provides a soft mechanical joint (a 1〇) 〇se mechanical bond) between the semiconductor wafer 11 () and the solder mask 156. The semiconductor wafer 110 and the metal substrate 120 are placed in opposite positions such that the semiconductor wafer 110 is placed in the edge of the adhesive 164, and the metal wall 132, the solder layer 142, the winding 150, and the electrical joint Point 162 is placed outside the edge of the semiconductor wafer. The semiconductor wafer 110 and the metal substrate 12 are arranged by an automatic pattern recognition system. The whole structure is placed in an oven, and the adhesive 164 is completely hardened at a relatively low temperature. The relatively low temperature range is between .200 degrees and 250 degrees, and forms an adhesive insulative thermosetting polyimide 44 1292195 layer, which is in contact with the semiconductor wafer 110 and the solder mask 156. And being sandwiched between the semiconductor wafer 11 and the solder mask 156, and mechanically connecting the semiconductor wafer 11 and the fresh mask L to the thickness of the adhesive 164 between the semiconductor wafer 11 and the solder mask 156. 35 microns. In the attack phase, the metal substrate 120 covers the semiconductor wafer 110, the winding 150, the solder mask 156, the plating contact 162, and the adhesion d 164 'and the semiconductor wafer 11 is wound, wound, The solder mask 156, the plating contact 162 and the adhesive 164 extend downwardly. The metal wall 132 is disposed outside the edge of the semiconductor wafer and is from the semiconductor. The sheet 110, the winding 150, the solder mask 156, the plating contact (6) and the adhesive 丨 164 extend downward, and the solder layer 142 is disposed outside the edge of the semiconductor crystal; j 11G, and from the semiconductor wafer U 〇 The metal wall 132, the winding 150, the solder mask 156, the electric ore code (4), and the adhesive 164 extend downward, and the winding 15 is placed in the downward direction of the semiconductor wafer 11G and is on the semiconductor wafer. And outside the edge of the metal wall 32 and the solder layer 142, the semiconductor wafer m is extended toward the semiconductor wafer m, and the adhesive 164 extends downward from the semiconductor wafer 11 。 and the semiconductor wafer ιι〇 It is still electrically isolated from the metal substrate 丨2〇, the metal wall 132, the solder layer 142, the winding 150, and the plating contact 62. 曰Please refer to the “Figure 20, 208, and 2〇c diagrams” , is a structural section of the connecting portion of the invention attached to the conductive pin and the plated joint 45 1292195

The schematic view of the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact is a schematic view of the structure when the connecting portion of the present invention is attached to the conductive pin and the electric ore joint. As shown in the figure, the connecting portion 166 is a metal gold wire which is ball-bonded to the conductive pin 116 and wedge-shapedly bonded to the plating contact 162. The metal wire is connected to a spherical defect and a wedge contact, and the thickness of the wire is 25 meters. Therefore, the connection portion 166 is in contact with the conductive pin 116 and the plated contact 162, and the conductive pin 116 and the plated contact 162 are electrically connected to each other. Therefore, the conductive pin 116 can also have the conductive pin 116. Electrically connected to the metal substrate 〇2〇, the metal wall 132, the solder layer 142, and the winding 150. The connecting portion 166 extends inside and outside the edge of the semiconductor wafer, and extends 100 U meters upward from the semiconductor crystal #10, and is connected to the metal substrate 12, the metal wall (7), and the winding 142. 150 and welded mask 丨 56 isolated. J ^. The structure of the sealing layer of the crucible shown in Fig. 1 and Fig. 1 is a schematic view of the structure of the present invention. As shown in the figure: the _:68,:==^^ (4) nsfer mo丨cnng) is deposited, _...彡&amp; ^ ^ The structure of the conductor crystals is used for the purpose of the transfer molding method Including the components in - poor,, Lu ^ ### (m〇lding c〇mp〇und), under the pressure of heat and plastic state, the injection molding material is in the name, 攸1P heart storage phase 46 1292195 ( The central reservoir is also delivered to the sealed cavity by a transfer pot through the tree array of runners and gates. Preferably, the transfer molding system comprises a preheater, a mold, a press, and a cure oven. The mold system includes an upper mold portion and a lower mold portion, which may also be referred to as (platens) or halves to define the mold size. The mold system also includes the chamber, runner wash, and vents. The cavity accommodates the injection molding material. The runner and gate provide access from the chamber to the cavity. The gate is placed near the entrance of the cavity and is compressed to control the flow rate and injection speed of the injection molding material when entering the cavity and to facilitate the movement of the solidified injection molding material during the formation of the transfer . The vent allows the restricted air to be vented, but the vent is small enough to allow very small amounts of injection molding material to pass. The injection molding material is in the form of a flat sheet at the beginning. The preheater uses a high frequency energy source to preheat the injection molding material to a temperature ranging from 50 degrees to 100 degrees. The preheating temperature is lower than the temperature of the transfer, so the preheated injection molding material is not in a fluid state. In addition, the unitary structure is placed in one of the cavities, and the molding machine operates hydraulically to close the mold and position the mold cavity by positioning the upper mold and the lower module. The leader pins ensure that the upper mold portion and the lower mold portion are just in close contact with the parting line. In addition, the mold is heated to a transfer temperature, and the transfer temperature ranges from 150 degrees to 250 degrees by electronically heating the upper mold portion and the lower mold portion by inserting 47 1292195. After the male mold is sealed, the preheated injection molding material is placed in the cavity in the form of a flat plate. A transfer plunger is then applied to the injection molding material in the chamber. This pressure range is from 10 to 100 kgf/cm2 and can be set as high as possible without reliability. The processing of heating and applying pressure to the mold to the transfer needle causes the injection molding material in the chamber to be switched to a fluid state. Moreover, the pressure from the transfer pin forces the transfer pin of the fluid to enter the cavity through the channel and the wash. The closing force is maintained at the optimum time for fixing to ensure that the injection molding material fills the lower module and is in contact with the metal substrate 120, and can be combined with the metal substrate 120, and the metal substrate (4) = even (four) 丨 66 distance 12_. Because ^ = material = material (four) wafer UG, winding i5Q, fresh contact with the contact compensation ^ 162, adhesive 164 and the connection portion 166 exposure "妾 核 nuclear hole. After the transfer temperature has passed 1 to 3 minutes Thereafter, the injection molding material (4) is polymerized and partially hardened in the elastic Si portion of the mold: after the material is hardened, the system has sufficient and permanent (four): the strength of the extrusion is such that it cannot be taken in a significant mold: The mold is opened by the rolling machine. The mold release rod is attached to the scaled structure, and the injection molding material attached to the X is cured on the runner and the gate of the 48 1292195. The structure is finished and removed. The cast structure is loaded into a magazine and placed in the hardening oven for 4 to 16 hours' and at a temperature slightly lower than the transfer temperature but The high indoor temperature makes the injection molding material completely hardened. The injection molding material is a multi-component sealing resin added with various external force σ agents. The additive of the main wife includes a hardener, an accelerated lean filler, Bonding agent, flame retardant, stress relief agent, colorant and mold release agent. (4) Sealing resin A bmder, the curing agent provides a straight line/crosshair, cooperative (iinear/cross_polymerizati〇n), the accelerator increases the gas polymerization rate, and the inert filler increases thermal conductivity. , thermal shock resistance and reduction of thermal expansion coefficient, resin loss, shrinkage and residual pressure'. The bonding agent increases the adhesion to the overall structure, and the flame retardant reduces flammability. The stress relieving agent reduces crack growth. The coloring reduces the photon activity and device visibility, and the release agent is easily removed from the mold. The sealing layer 168 and the semiconductor wafer 110, the winding 150, the solder (four) cover 156' plating contacts 162, the adhesive The sealing layer 168 is in contact with the first surface 1丨2 of the semiconductor wafer and its outer edge, but is isolated from the first plane 1 14 of the semiconductor wafer 110. The layer 1 68 is overlaid on the metal plate 1 and the soldered end 42 but is isolated from the metal substrate 120, the metal nib 2 and the soldered end 142. 49 1292195 The sealing layer 168 is - it can provide an environment Protection, such as protection of 11 billion resistant particles of a solid adhesive as the wire protective layer of a compressible, such as resistance; ^ crystal 44, W β # 4 *; if ... *

The semiconductor wafer is subtracted from the sealing layer 168. The sealing layer 168 is from the semiconductor wafer 110, the metal substrate, the 'genus wall 132, the solder layer 142, the winding 15 〇, the solder mask 156, the plating contact 162, the adhesive 164, and the connecting portion 166. The extension is extended to a thickness of 400 microns and is 120 microns upward from the joint 166. Please refer to the "22nd, 22nd, 22th and 22th" diagrams, which are schematic cross-sectional views showing the structure of the metal pillar of the present invention formed on the metal substrate, and the structure of the metal pillar of the present invention formed on the metal substrate. A schematic view of the structure of the metal pillar of the present invention formed on a metal substrate. As shown in the figure, the metal post 17 is an unetched portion of the metal substrate 120, which is in contact with the metal wall 132 and the winding 15 and is sandwiched between the metal wall 132 and the winding 150. The metal wall 132 is electrically connected to the winding 150, but is not integrated with the metal wall 132 and the winding 150. The metal pillar 17 is made of copper. The metal pillar Π0 is formed by etching the metal substrate 120 by a wet chemical etch, and etching the mask by the metal wall 132 and the solder layer 142, and selectively protecting the metal substrate 12 〇. Therefore, the metal post 170 is formed by the metal wall 132 to define that the metal 50 1292195 substrate 12G is not (four). A backside wet chemical etch is used for the metal substrate 120, which is a primary plane 124, a metal wall 132, and a soldered end 142. The bottom 卩 nozzle can spray the wet chemical surname solution on the metal substrate 120. When the top nozzle system is not used or the entire structure is immersed in the wet chemical etching solution, the sealing layer 168 can provide Front side protection. When copper is used for nickel, tin, epoxy, and injection molding materials, the wet chemical etching is applied, so when the metal substrate 120 is on the metal wall 132, the solder layer 142, and the nickel layer of the winding 15 The wet chemical etching is applied when soldering the mask 156 and the sealing layer 168. The wet chemical etching completely passes through the metal substrate 120, thereby affecting the transfer of the pattern of the metal wall 132 onto the metal substrate 120. The wire 150 and the solder mask 156 are exposed to reduce, but not remove, the contact area of the metal substrate 120 with the metal wall 132, the wire 15 and the solder mask 156. However, the metal wall 132, the solder layer μ, the nickel layer of the winding 150, the solder mask 156 or the sealing layer 168 are not removed, and the nickel layer of the winding 150 protects the winding 15 during chemical etching. The copper layer. Therefore, the winding 150 is not removed. The wet chemical etching system also laterally cuts the metal substrate 12 to the metal wall 132 and causes the metal post 17 to tilt toward the inside and increase the height. A suitable angle of inclination is between 45 degrees and less than 90 degrees, such as about 75 degrees. The metal post 170 is in contact with the winding 150 at a relatively large circular portion 154 51 1292195, but is isolated from the elongated winding portion 152 and extends downwardly from the winding 15〇. Therefore, the metal post and the winding 15 are turned downward. The heavy dragon, however, the metal column] 70 series does not cover the winding ^ in the downward direction. ^ A suitable wet chemical etching solution can be provided by alkaline ammonia. The metal substrate 12 is exposed to the chemical etching solution. The time of the etching must be repeated several times. A money penetrates the metal substrate 120 and forms a metal pillar 17 of a desired size, but The 4 metal walls 132 f are not allowed to smear or the m5 避免 is prevented from being exposed to the chemical etching solution. The first metal plane 170 includes a corresponding first plane 172, a second plane Π4, and a tapered side 174 (tapered sidewaHs), wherein the first plane 丨 72 of the metal pillar 170 is constructed on the metal substrate 120 The second plane 174 of the metal post 170 on the unetched portion of the first major plane 122 of the first major plane is an unetched portion of the recess 130 formed in the metal substrate 120. Therefore, the second plane 174 is oriented downward. The first plane 接触 is in contact with the imaginary winding, the line 150 and faces the winding "5" and is isolated from the metal 32" and the second plane 174 is connected to the metal wall 132 facing the metal wall 132, but isolated from the winding 15〇. In addition, the Diping® 172 is flat and parallel to the semiconductor wafer ιι〇=一: face η2 and second plane 114 and winding 15〇, and the 4 second plane 174 is along the wheel of the metal wall 132 temple. The surface 52 1292195 176 is adjacent to the first plane 172 and the second plane Π4 and is inclined toward the second plane 174. The metal post 170 is a conical shape, and the height between the first plane Η and the second plane 174 is 7 〇 micrometers. When the first plane 172 extends downward (from the first plane 172) The second plane 174) is gradually reduced in diameter. The first plane 172 is circular and has a diameter of 250 microns, while the second plane 174 is also circular and has a diameter of 200 microns. The first plane 172 and the second plane 174 are arranged perpendicular to the metal wall 132, the solder layer 142, and the larger circular portion 154. Therefore, the second plane 174 is placed in the surface area of the metal wall 132, the solder layer 丨钧, the larger circular portion 154, and the first plane 172. Moreover, the surface area of the first plane 172 is at least 1% larger than the surface area of the second plane 174. The metal post 170 is placed outside the edge of the semiconductor wafer 11 and placed on the semiconductor wafer n, the winding 15 , the solder mask 156 'adhesive 164 , the connecting portion 166 and the sealing layer ι 68 . The lower direction extends upward from the metal wall 132 and the solder layer 142. The semiconductor wafer 110 extends upward from the winding 15 , the solder mask 56 , the adhesive 164 , and the metal post 170 , and the winding is placed on the metal wall 132 , the solder layer 142 , and the metal pillar 17 . The semiconductor layer 110, the metal wall 132, the solder layer 142, and the winding are covered by the metal layer 132, the solder layer 142, and the metal pillars 170 extending laterally toward the semiconductor wafer 110. 150, 53 1292195 fresh mask 156, adhesive 164, connecting portion 166 and metal post 17A, and from semiconductor wafer 110, metal wall 132, solder layer 142, winding 150, solder mask 156, adhesive 164 The connecting portion 16 is extending upward from the column 170. The sealing layer 168 is provided with a mechanical support for the winding 15〇 and the metal post 17〇 to reduce the mechanical tension on the adhesive 1.64. After the metal substrate 12G is formed by the (4) gold vein 17G, it works. The sealing layer 168 protects the winding, the wire 150 and the metal column. Chemical (4) and mechanical damage during steam cleaning. For example, when the .S Hai seals 68 are absorbed in chemical remnants and steamed mineral water, the physical force' may be separated from the winding 150 by the chemical #刻 and steaming water cleaning. Therefore, the sealing layer 68 can increase the structural integrity, and can be solidified by chemical etching and steam washing, thereby improving productivity. 'Xuan Conductive Trace 1 8〇 includes metal niche 32, welded layer 142, winding 15G, electric ore joint (6) and metal column 17G. The conductive trace 180 is adapted to provide a horizontal and vertical path between the conductive pin (1) and the next level. Please read the "23rd, 23rd, and 23C" drawings of the present invention, which is a schematic cross-sectional view of the insulating seal of the present invention, the knot after the formation of the insulating sealant of the present invention, and the insulating seal of the present invention. The structure after the formation of the glue is a bottom view. As shown in the figure: the insulating encapsulant 182 is initially a -τ-like epoxy resin comprising an epoxy tree 54 1292195 grease, a hardener, an accelerator, and a filler, wherein the filler is an inert Materials such as silica are powder-dissolved quartz, which improves the thermal conductivity, thermal shock resistance and thermal expansion coefficient. The epoxy paste can be deposited on the metal nib 32, the solder layer 142, the winding 150, the solder mask 15 6 and the metal post 17 , and then the epoxy paste is at a relatively low temperature. Hardening to form a solid adhesive insulator, the relative low temperature range is from 100 degrees to 250 degrees, and can provide a winding 1 and a metal post 1 - a protective seal ° The insulating seal 182 Contacting the metal niche 32, the solder layer 142, the winding 150, the solder mask 156, and the metal post 170, and covering the metal wall 132, the solder layer 142, the winding 150, the solder mask 156, and the metal post 170, and The metal wall 132, the solder layer 142, the winding 15 〇, the surface mask 156 and the metal post 170 extend downward to cover the semiconductor wafer U0, the plating contact 162, the connecting portion 166 and the sealing layer 168. However, it is isolated from the semiconductor wafer 110, the plating contact 162, the connection portion 166, and the sealing layer 168. The insulating encapsulant 182 has a thickness of 2 μm. Therefore, the insulating encapsulant 182 extends downward from the metal wall 132, the solder layer 142, the winding 丨5〇, and the metal post 170, and the metal wall 132, the solder layer 142, the winding 丨50, and the metal post 〇7 Exposed. Please refer to FIG. 24A, FIG. 24B and FIG. 24C for a schematic cross-sectional view of the insulating encapsulant after the removal of the insulating sealant of the present invention, and a schematic top view of the structure of the present invention after removal of the insulating encapsulant 55 and the insulation of the present invention. The structure after the sealant is removed is shown in a bottom view. As shown, the lower portion of the insulating encapsulant 182 is removed by a grinding process. Specifically, a rotating diamond wheel and a distilled water system are used for the back surface of the insulating sealant 82. Initially, the diamond grinding wheel only grinds the insulating encapsulation crucible 82, and § holds, and the bead is polished, so that the insulating encapsulant 182 is thinned when the surface to be polished migrates upward. The diamond wheel train is then in contact with the weld layer 142 so that the weld layer 142 is ground. When the grinding is continued, the insulating sealant 182 and the solder layer 142 are simultaneously thinned as they migrate upwardly from the surface to be polished. However, the diamond wheel contacts the metal wall 132, thereby opening the metal wall 132. When the grinding is continued, the side metal wall 132, the solder layer M2, and the insulating encapsulant 182 are thinned when the surface to be polished migrates upward. Continuously grinding until the metal wall 132, the solder layer 142 and the insulating encapsulant 182 reach the required thickness and contact with the germanium semiconductor wafer, the winding 15 〇, the fresh mask φ 156, the electric ore joint 1 62, and the adhesion The agent 164, the joint portion 16A, the sealing layer 168, or the genus column 7 7, for example, stops grinding, after which the entire structure is washed with distilled water and the contaminants are removed. After the grinding process is completed, the metal wall 132, the solder layer 142, and the insulating encapsulant 182 extend downward from the metal post 7〇 by 7 μm. Thus, the grinding process removes the lower portion of the 10 micron thick metal wall 132, removes the lower portion of the 40 micron thick solder layer 142, and removes the lower portion of the insulating encapsulant 1 82 from the 6 micron thickness. 56 1292195 After the above process, the semiconductor wafer 110 is still embedded in the sealing layer 16 8 , and the metal pillar 17 is embedded in the insulating sealing material 18 2 , and the winding 150 and the metal pillar 170 are still not Being exposed, and the gold

The genus wall 132 and the weld layer are exposed. The insulating encapsulant 182 covers the semiconductor wafer 110, the plating contact 162, the adhesive 164, and the connection portion 166, and the semiconductor wafer 110, the plating contact 162, the adhesive 164, and the connection portion 166, and from the semiconductor wafer 11 The crucible, the electric ore joint 162, the adhesive 164 and the connecting portion 166 extend downward, but are isolated from the semiconductor solar wafer 110, the electric ore joint 162, the adhesive 164 and the connecting portion 166; and the winding 150, The solder mask 156 is in contact with the metal post 17 and extends downward from the winding 150, the solder mask 156 and the metal post 17, in contact with the metal wall 132 but with the solder layer! 42 R away. The insulating encapsulant 1 82 is partially overlapped with the winding 15 , the solder mask i % sealing layer 168 and the metal post 170 in a downward direction, and the insulating encapsulant 82 no longer covers the winding. 150, the welding ς ^ 156 ' sealing layer ι68 or metal column 丨 7 〇 in the downward direction. Moreover, the shot = bismuth I solder layer 142 and the insulating encapsulant 182 are laterally mutually oriented: on the plane facing downward. Therefore, the metal wall layer (4) and the insulating turn 182 are exposed to face down.卞向, ^千珣 Refer to "25th Α zdo 25Γ m ^ The structure of the invention after the formation of the solder ball is shown in Figure 4": shows a schematic view of the structure after the formation of the structure and the schematic view of the 57 1292195 structure of the present invention. As shown in the figure: the solder ball 184 is initially a lead-free ball and has a spherical shape with a diameter of 300 μm. The lead-free ball system is immersed in a flux and the solder ball 184 is provided with a flow surface coating. It surrounds the lead-free ball. The overall structure is then inverted such that the solder layer 142 is oriented upward and the solder balls 184 are deposited on the solder layer 142. The solder ball 184 is attached to the solder layer 142 and is not solidified because of the flow surface coating of the solder ball 184. For ease of illustration and description, the solder ball 184 is drawn under the solder layer 142 'maintained in the same direction as the previous figure for comparison. Although the overall structure is reversed, the solder ball 184 is adhered to the solder layer by gravity. . Please refer to the drawings of FIGS. 26A, 26B and 26C, which are schematic cross-sectional views of the structure after the formation of the welded end of the present invention, a schematic plan view of the structure after the formation of the zinc joint of the present invention, and the structure after the formation of the welded end of the present invention. Looking up at the schematic. As shown, the solder joint 186 includes the solder layer 142 and the solder balls 184 and is formed by the solder layer 142 and the solder balls 184. First, the solder ball 184 is placed on the solder layer 142. The overall structure is then heated to a temperature of about 260 degrees. Heating is performed to cause a fluxing reaction on the solder ball 84 to remove oxides from the solder layer 142 and to melt the solder layer 14 2 and the solder balls 128. Therefore, the solder layer 142 and the solder balls 184 are reflowed into a molten tin mixture and a tin reflow is generated. The insulating encapsulant 182 does not provide a wet surface that allows the tin to reflow easily. Therefore, the tin reflow is limited by the metal wall 132. Thereafter, the heating is stopped to cool and solidify the melted tin to form the welded end 186. In this method, the fresh layer 142 and the solder balls 184 are converted into soldered ends 186. Therefore, the solder layer 142 and the soldering end 186 are formed in order. The metal wall 132 is plated on the metal substrate 120, and then the tin-depleted 140 is deposited on the metal wall 132 and forms the solder layer 142 upon reflow. Then the solder ball 184 is deposited on the solder layer 142. The solder layer 142 and the solder balls 184 are then reflowed together to form the solder end 186. The soldering end 186 has a diameter of 400 micrometers, and has a thickness of 5 micrometers in a downward direction with respect to the metal wall 132 and the insulating encapsulant 182, and fills the hole 134, and the metal wall 132 and the larger circular portion. Parts 15 4 and metal columns 17 are arranged vertically. The soldering end 186 is in contact with and electrically connected to the metal wall 132, but is not integrated with the metal wall 132, and is only in contact with the metal wall 132 and the metal wall 132 in the hole 134. The soldering end 186 is isolated from the semiconductor wafer 11 , the winding 15 , the zinc mask 156 , the plating contact 162 , the adhesive 164 , the connecting portion 166 , the sealing layer 168 , the metal post 17 , and the insulating encapsulant 182 . And extending downward from the semiconductor wafer 110, the winding 15 〇, the solder mask 156, the electric ore joint 162, the adhesive 164, the connecting portion 166, the sealing layer 168, the metal post 170, and the insulating seal 82. Moreover, the soldering end 丨86 59 1292195 is extended to the inside of the U4, and the metal wall: 32 and the metal post 17 are folded in the downward direction, but are not covered by any material of the semiconductor chip package structure. Down direction. Similarly, the integral portion of the fresh terminal 186 extending toward the insulating sealant 182 is only in contact with the metal wall 132 and is covered by the metal wall upwardly and within the hole 134. The splicing terminal 186 provides - (iv) a power contact to the metal, 132, and the contact end to an external circuit. The soldering end 186 is extended to the metal wall 132 in the insulating encapsulant 182 and avoids contact with the high-voltage boundary of the opening 136 in a lateral plane. The opening 136 is mainly attached to the insulating encapsulant 182. Exposure to the surface and downwards thus reducing solder separation and increasing reliability. Throughout the above, the conductive traces 180 include metal walls 132, , , &gt; turns 15 , electrical ore junctions 162 , metal posts 170 , and solder ends 186 . For the sake of convenience of illustration, the soldering end 186 is drawn below the semiconductor sheet and maintains the same direction as the previous figure for convenience. Although the overall structure is reversed, when the soldering end 186 is formed, by gravity Help tin reflow. Referring to the "27A, 27B, and 27C", which is a schematic cross-sectional view of a semiconductor wafer package structure of the present invention, a schematic view of a half-battery sealing structure of the present invention, and a semiconductor wafer sealing structure of the present invention. Looking up at the schematic. As shown in the figure, the semiconductor package structure 198 includes a semiconductor wafer no, a metal wall 132, a winding 15 〇, a solder mask 156, a plating contact i62, an adhesive 164, and a connection portion ι66. The sealing layer 168, the metal post 17〇, the insulating sealant 182 and the welded end 186 are formed. The semiconductor wafer extends upward from the conductive trace 18' and partially overlaps the insulating seal 182 in the upward direction, but does not overlap the conductive trace 18 in the upward direction. Thus, the conductive traces 180 are placed outside the edge of the semiconductor wafer 11 turns. The Meng dynasty wall 132 extends upwardly from the weld end 186 and has a fixed thickness and is only in contact with the metal post 170, the insulating sealant 182, and the weld end I%. The hole 134 is placed in the insulating encapsulant 182 and filled by the solder end 186. The winding 15〇 is mechanically coupled to the semiconductor wafer by an adhesive 164 and electrically connected to the semiconductor wafer by the connecting portion 166, and from the metal wall 132 and the metal pillar The 17" and the fresh terminals 186 extend laterally toward the semiconductor wafer U0, which is flat and parallel to the first plane 112 and the second plane U4 of the body sheet U:. The sealing layer 16 is coated with the semiconductor wafer 11G, the solder mask 156, the adhesive (6), the connecting portion 166, the conductive traces 180, and the insulating encapsulant 182. The metal post 170 is covered by the winding 15〇 and covered upward by the welding end 186 of the metal wall (10) in the downward direction: although the metal post 17G is not exposed, and the metal wall 1 is sealed 182 and the welded end The 186 has a partial overlap in the downward direction, and the ^1292195 sub-column m is not covered by the sealing layer 168, the insulating encapsulant i82 or any insulating substrate in the semiconductor chip package structure in the downward direction. The insulating encapsulant 182 and the metal wall 132, the winding 132 and the soldering end are extended upwards, and the k semiconductor wafer i! Q, the winding, the soldering mask 156, the connecting portion 166, the sealing layer 168 and the metal post 17 Extend downwards. The metal wall 132, the metal post 17〇 and the welded end 186 extend downward from the winding wire 150, but do not cover the winding 15 in a downward direction γ. The metal wall 132 extends laterally around the fresh terminal 186. The peripheral portion of the insulating encapsulant 182 is rotated around the periphery, and the insulating encapsulant 182 is rotated laterally around the periphery of the metal wall 132. The sealing layer 168 and the insulating encapsulant 182 provide mechanical support and environmental protection to the semiconductor wafer package structure 198. The connecting portion 166 provides horizontal winding and vertical winding between the conductive pin 116 and an external circuit, and provides horizontal output winding.

(hor丨z〇nta丨fan_out r〇uUng) The winding 15 is tied between the conductive pin 116 and the external circuit 'but no vertical winding is provided, and the metal post (7) and the recording end 186 provide vertical winding The conductive pin 116 is connected to the external circuit, but the horizontal output winding is not provided, and the metal wall U2 i the electric ore contact 162 is not provided with the horizontal winding 51 directly between the conductive pin 116 and the external circuit. Similarly, the metal wall 132 is not wound between the solder end 186 and any of the conductors. The semiconductor chip package structure is a first level of a single wafer. Therefore, the semiconductor wafer #110 is a germanium wafer of the semiconductor chip package junction 62 1292195, which is embedded in the sealing layer 168. , &quot;: body chip package structure contains other conductive traces, and 匕: ί cover 156, sealing layer 168 and insulating sealant 182 'in the figure only I will make - guide lightning worry ^ conductive trace I80 Make the illustration and description convenient. The mother-and-electric traces are isolated from each other and electrically. Each of the itch lines comprises a respective metal wall, a winding, an electric ore joint, a metal post and a soldering end' and electrically connected between the conductive pin of the semiconductor wafer 110 and the conductive trace by respective connecting portions. The connections are provided with horizontal output windings and vertical windings to the respective conductive pins. Moreover, each of the conductive traces has a downwardly projecting solder end that provides a ball format array configuration. The semiconductor wafer 110 includes a conductive pin, but the component is isolated. However, the corresponding winding is initially plated with a substrate, and the metal substrate is electrically connected to the other component. connection. Moreover, the connection portion electrically connects the winding and the corresponding conductive pins, so that the conductive pins can be electrically connected to other components. Then, once the metal substrate is etched to form a metal post that is isolated from other parts, the conductive leg is isolated from the other parts. Therefore, after the metal substrate 120 is etched to form a metal pillar, the electroless ore busbar or associated circuitry can be connected to the conductive trace. The 28th to 54Cth drawings are a second embodiment of the process of manufacturing the semiconductor wafer package structure. In the second embodiment, the solder layer 63 1292195 is formed after the sealing layer is formed. For the sake of simplicity, the same description as the first embodiment does not need to be repeated. Similarly, the elements of the second embodiment have similar reference numerals to the first embodiment, but the number of elements in the second embodiment is represented by "2," and the number of elements in the first embodiment is " That is, it means that, as the semiconductor wafer 2H) coincides with the semiconductor wafer 11 〇, the winding 25 〇 corresponds to the winding 150... and the like. Referring to Figures 28A, 28B and 28C, there are shown schematic cross-sectional views of a semiconductor wafer structure of the present invention, a top view of the semiconductor wafer structure of the present invention, and a bottom view of the semiconductor wafer structure of the present invention. As shown, the semiconductor wafer 21 includes a first planar surface 212 and a second planar surface 214. The first plane 212 includes a conductive pin 216 and a passivation layer 218. Referring to the drawings of Figs. 29A, 29B and 29C, which are schematic cross-sectional views of the metal substrate structure of the present invention, a plan view of the metal substrate structure of the present invention, and a bottom view of the metal substrate structure of the present invention. As shown in the figure, the metal substrate 220 includes a first plane 22 to 2 and a second plane 224. Referring to FIG. 30A, FIG. 30B and FIG. 30C, FIG. 30 is a schematic cross-sectional view showing the structure of the photoresist layer and the metal substrate of the present invention, a top view of the structure of the photoresist layer and the metal substrate of the present invention, and a photoresist layer of the present invention. A schematic view of the structure of the metal substrate. As shown, the first photoresist layer 226 and the second photoresist layer 228 are formed on the metal substrate 64 1292195 220. The second photoresist layer 228 includes an opening and partially exposes the second plane 224. The first photoresist layer 226 is unpatterned. Referring to Figures 31A, 31B and 31C, there are shown schematic views of a notched structure of the present invention, a top plan view of a notched structure of the present invention, and a bottom view of the notched structure of the present invention. As shown, the recess 230 is formed in the metal substrate 220. • Please refer to the “32A, MB and 32C diagrams” for a schematic view of the metal substrate structure of the present invention, a schematic view of the metal substrate structure of the present invention, and a metal wall 232 of the present invention. It is formed on the metal substrate 220. Please refer to FIG. 33A, 33B and 33C for a schematic cross-sectional view of the first photoresist layer and the second photoresist layer after stripping, the first photoresist layer and the second photoresist of the present invention. A schematic top view of the structure of the layer after peeling and a schematic view of the structure of the first photoresist layer and the second photoresist layer of the present invention. As shown in the figure, the structure of the metal substrate 220 and the metal wall 232 is stripped after the first photoresist layer 226 and the second photoresist layer 228 are stripped. Please refer to FIG. 34A, FIG. 34B and FIG. 34C for a schematic cross-sectional view of the third photoresist layer and the fourth photoresist layer formed on the metal substrate of the present invention, and the third photoresist layer and the third layer of the present invention. The schematic view of the structure in which the four photoresist layers are formed on the metal substrate and the structure in which the third photoresist layer and the fourth photoresist layer of the present invention are formed on the metal substrate are shown in the bottom view 65 1292195. As shown in the figure, the third photoresist layer 244 and the fourth photoresist layer 246 are formed on the metal substrate 220. The third photoresist layer 244 includes an opening and a partially exposed portion of the first plane 222 of the metal substrate 220. The fourth photoresist layer 246 has no pattern. Please refer to FIG. 35A, FIG. 35B and FIG. 35C for a schematic cross-sectional view of the structure of the present invention when the winding is attached to the metal substrate, and a schematic plan view of the structure of the present invention when the winding is attached to the metal substrate and the winding of the present invention. A schematic view of the connection when the wire is attached to the metal substrate. As shown, the winding 250 is plated on the metal substrate 220 by electroplating. Please refer to the "36A, 36B and 36C" diagrams, which are schematic structural cross-sections of the third photoresist layer and the fourth photoresist layer of the present invention, the third photoresist layer and the fourth photoresist of the present invention. A schematic top view of the structure after stripping and a bottom view of the structure of the third photoresist layer and the fourth photoresist layer of the present invention. As shown in the figure, the structure of the metal substrate 220, the metal wall 232 and the winding 250 is stripped after the third photoresist layer 244 and the fourth photoresist layer 246 are stripped. Please refer to FIG. 37A, FIG. 37B and FIG. 37C for a schematic cross-sectional view of the welding mask of the present invention on a metal substrate and a winding, and a structural plan view of the welding mask of the present invention on a metal substrate and a winding. A schematic view of the structure and the structure of the solder mask of the present invention on a metal substrate and a winding. As shown, the solder mask 256 is formed on the metal substrate 220 and the winding 250. 66 1292195 Please refer to the "38A, 38B and 38C" diagram, which is a schematic cross-sectional view of the fifth photoresist layer and the sixth photoresist layer after the formation of the fifth photoresist layer and the sixth photoresist layer of the present invention. A schematic top view of the structure after the formation of the photoresist layer and a schematic bottom view of the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are formed. As shown, the fifth photoresist layer 258 and the sixth photoresist layer 260 are formed on the structure. The fifth photoresist layer 258 is formed on the winding 250 and the solder mask 256. The sixth photoresist layer 260 is formed on the metal substrate 220 and the metal wall 232. The fifth photoresist layer 258 and the sixth photoresist layer 260 are respectively embossed on corresponding planes by a dry film lamination technique. The fifth photoresist layer 258 includes an opening and a partially exposed portion of the winding 250. The sixth photoresist layer has no pattern. Please refer to FIG. 39A, 39B and 39C for a schematic cross-sectional view of the structure in which the electroplated contacts of the present invention are formed after winding, and a schematic plan view of the structure in which the electroplated contacts of the present invention are formed after winding and the present invention. The electroplated contacts are formed in a bottom view of the structure after winding. As shown in the figure, the plating contact 262 is plated on the winding 250 by electroplating. Please refer to "Fig. 40A, 40B and 40C" for the fifth photoresist layer and the sixth invention. Schematic diagram of the structure of the photoresist layer after stripping, the top view of the fifth photoresist layer and the sixth photoresist layer after stripping, and the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention After the 260 stripping, the structure of the metal substrate 220, the gold 67 1292195 is the wall 232, the winding 250 and the plating contact 262. Please refer to FIG. 41A, FIG. 41B and FIG. 41C for a schematic cross-sectional view showing the structure of the adhesive of the present invention after the solder mask is formed, and the structure of the present invention after the adhesive is formed on the solder mask. The structure of the adhesive formed on the welded mask is a bottom view. As shown, the adhesive 264 is formed on the solder mask 256. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ As shown, the semiconductor wafer 210 is attached to the structure by the adhesive 264. The structure includes a metal substrate 220, a metal wall 232, a winding 250, a solder mask 256, and a clock contact 262. Please refer to FIG. 43A, FIG. 43B and FIG. 43C for a schematic cross-sectional view of the connection portion of the present invention attached to the conductive pin and the plated contact. The connection portion of the present invention is attached to the conductive pin and electroplating. A schematic top view of the structure at the time of the contact and a schematic view of the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact. As shown, the connecting portion 266 is formed on the conductive pin 216 and the plating contact 262. Please refer to FIG. 44A, FIG. 44B and FIG. 44C for a schematic sectional view of the structure of the sealing layer of the present invention, a schematic top view of the structure of the sealing layer of the present invention, and a structure of the sealing layer of the present invention, looking up 68 1292195 210 The winding 250, the solder mask 256 plating contacts 262, the adhesive 264 and the connecting portion 266. Please refer to FIG. 45A, FIG. 45B and FIG. 45C for a schematic cross-sectional view of a template covering the metal substrate of the present invention, a schematic plan view of the structure of the present invention covering the metal substrate, and a template cover 238 of the present invention. On the metal substrate 220. Please refer to FIG. 46A, 46B and 46C for a schematic cross-sectional view showing the structure of the solder paste deposited on the metal wall of the present invention, a top view of the structure in which the solder paste of the present invention is deposited on the metal wall, and the solder paste deposition of the present invention. A schematic view of the structure of the metal wall. As shown, the solder paste 240 is deposited on the metal wall 232. Please refer to FIG. 47A, FIG. 47B and FIG. 47C for a schematic cross-sectional view of the structure after removing the template of the present invention, a top view of the structure after removing the template of the present invention, and a structure of the present invention after removing the template. schematic diagram. As shown, the template 238 is removed from the metal substrate 220. Please refer to FIG. 48A, FIG. 48B and FIG. 48C for a schematic cross-sectional view of the solder paste of the present invention after forming a solder layer, a schematic top view of the solder paste of the present invention after forming a solder layer, and a solder paste formation of the present invention. A schematic view of the structure behind the solder layer. As shown, the solder layer 242 is formed from the solder paste 240. The metal wall 232 provides a wet surface to allow the solder to flow easily, however the metal substrate 220 is not provided. Therefore, the tin material can only flow in the metal wall 232. 69 1292195 Please refer to FIG. 49A, FIG. 49B and FIG. 49C for a schematic cross-sectional view of a metal post of the present invention formed on a metal substrate, and a schematic plan view of the structure of the metal post of the present invention formed on the metal substrate. A schematic view of the structure of the metal pillar of the present invention formed on a metal substrate. As shown, the metal post 270 is formed from the metal substrate 220. Please refer to FIG. 50A, FIG. 50B and FIG. 50C for a schematic cross-sectional view of the insulating encapsulant of the present invention, a schematic top view of the insulating encapsulant of the present invention, and an insulating encapsulant of the present invention. The structure is viewed from the bottom. As shown, the insulating encapsulant 282 is formed on the metal wall 232, the solder layer 242, the winding 250, the solder mask 256, and the metal post 270. Please refer to FIG. 51A, 51B and 51C for a schematic cross-sectional view of a portion of the insulating encapsulant after removal of the present invention, a top view of the structure after removing the insulating encapsulant of the present invention, and the present invention. A schematic view of the structure after the partial insulation seal is removed. As shown in the figure, the structure is shown after the partial insulating sealant 282 is removed. Please refer to FIG. 52A, 52B and 52C for a schematic cross-sectional view of the structure of the solder ball of the present invention, a schematic top view of the structure after the solder ball of the present invention is formed, and a structure of the structure after the solder ball of the present invention is formed. schematic diagram. As shown, the solder ball 284 is formed on the solder layer 242. Please refer to the "Fig. 53A, 53B and 53C" diagrams, which is a schematic cross-sectional view of the structure after the formation of the welding end, a schematic top view of the structure of the present invention, and a schematic view of the welded end of the present invention. As shown in the figure, the zinc terminal is formed by the solder layer 242 and the solder ball 284. Μ 第 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54 54

Towel, picture. As shown in the figure, the use of a blade, a solder mask, a cover 56, a sealing layer 268, and an insulating encapsulant 282 are shown in the form of a chip package structure. The semiconductor chip package structure 29 2 includes a + conductor wafer 2i 〇, a metal wall 232, a winding 25 〇, a solder 256 electric ore joint 262, an adhesive 264, a connecting portion 266, a sealing layer 268, a metal post 27, The insulating sealant (10) and the solder end tear ▲ are the third embodiment of the present invention from the 55A to 81C, which is the manufacturing process of the half, the body crystal &gt; Compared with the previous embodiment, the third embodiment is formed after the metal wall and the solder layer are sealed, and the metal pillar is removed. Referring to Figures 55A, 55B and 55C, there is shown a schematic cross-sectional view of a semiconductor wafer structure of the present invention, a schematic plan view of the semiconductor wafer structure of the present invention, and a semiconductor wafer structure of the present invention. As shown, the semiconductor wafer 310 includes a first planar surface 3U and a second planar surface 314. The first plane 312 includes a conductive pin 3 16 and a protective layer 3 1 8 〇 1292195. Please refer to FIG. 56A, 56B and 56C for a cross-sectional view of the metal substrate structure of the present invention, and the metal substrate of the present invention. A schematic top view of the structure and a schematic view of the metal substrate structure of the present invention. As shown, the metal substrate 320 includes a first plane 322 and a second plane 324. Please refer to FIG. 57A, 57B and 57C for a schematic cross-sectional view of the photoresist layer and the metal substrate of the present invention, a top view of the structure of the photoresist layer and the metal substrate of the present invention, and a photoresist layer of the present invention. A schematic view of the structure of the metal substrate. As shown in the figure, the third photoresist layer 344 and the fourth photoresist layer 346 are formed on the metal substrate 320. The fourth photoresist layer 346 includes an opening and a partial exposure of the first plane 322. The third photoresist layer 344 is not printed with a pattern. Please refer to FIG. 58A, FIG. 58B and FIG. 58C for a schematic cross-sectional view of the winding of the present invention attached to a metal substrate, a schematic plan view of the structure of the winding of the present invention attached to the metal substrate, and a winding of the present invention. A schematic view of the structure when the wire is attached to the metal substrate. As shown, the winding 350 is plated on the metal substrate 320 by electroplating. Please refer to FIG. 59A, 59B and 59C for a schematic cross-sectional view of the third photoresist layer and the fourth photoresist layer after stripping, the third photoresist layer and the fourth photoresist of the present invention. A schematic top view of the structure after stripping and a bottom view of the structure of the third photoresist layer and the fourth photoresist layer of the present invention. As shown in the figure, the third photoresist 72 1292195 layer 344 and the fourth photoresist layer 346 are stripped, and the metal substrate 320 and the winding 350 are structurally schematic. Please refer to FIG. 60A, FIG. 60B and FIG. 60C for a cross-sectional view showing the structure of the welding mask of the present invention on a metal substrate and a winding, and the structure of the welding mask of the present invention when viewed on a metal substrate and a winding. A schematic view of the structure and the structure of the solder mask of the present invention on a metal substrate and a winding. As shown, the solder mask 356 is formed on the metal substrate 320 and the winding 350. Please refer to FIG. 61A, FIG. 61B and FIG. 61C for a schematic cross-sectional view of the fifth photoresist layer and the sixth photoresist layer of the present invention, the fifth photoresist layer and the sixth photoresist of the present invention. A schematic plan view of the structure after the layer is formed and a schematic view of the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are formed. As shown in the figure, the fifth photoresist layer 358 and the sixth photoresist layer 360 are formed on the structure. The fifth photoresist layer 358 is formed on the winding 350 and the solder mask 356. The sixth photoresist layer 360 is formed on the metal substrate 320. The fifth photoresist layer 358 includes an opening and a partially exposed portion of the winding 350. The sixth photoresist layer is not printed with a pattern. Please refer to the "62A, 62B and 62C" diagrams, which are schematic cross-sectional views of the structure in which the electroplated contacts of the present invention are formed after winding, and the structure of the present invention is formed after winding. The electroplated joint of the invention is formed in a bottom view of the structure after winding. As shown in the figure: the plating defect 362 is plated on the winding 350 73 1292195 by electroplating. Please refer to "Fig. 63A, 63B and 63C" as the fifth photoresist layer of the present invention. A schematic cross-sectional view of the sixth photoresist layer after stripping, the fifth photoresist layer and the sixth photoresist layer stripped structure of the present invention, and a fifth schematic view of the fifth photoresist layer and the sixth photoresist layer of the present invention The structure is viewed from the bottom. As shown in the figure, after the fifth photoresist layer 358 and the sixth photoresist layer 360 are stripped, the metal substrate 320, the winding 350 and the electrical contact 362 are schematicly constructed. Please refer to FIG. 64A, 64B and 64C for a schematic cross-sectional view showing the structure of the adhesive of the present invention after the solder mask is formed, and the structure of the present invention after the adhesive is formed on the solder mask and the present invention. The structure of the adhesive formed on the welded mask is a bottom view. As shown, the adhesive 364 is formed on the solder mask 356. Referring to the drawings of Figs. 65A, 65B and 65C, which are schematic cross-sectional views of a semiconductor wafer of the present invention, a schematic plan view of a semiconductor wafer of the present invention, and a bottom view of the structure of the semiconductor wafer of the present invention. As shown, the semiconductor wafer 310 is attached to the structure by the adhesive 364. The structure includes a metal substrate 320, a wire 350, a solder mask 356, and a plating contact 362. Please refer to FIG. 66A, 66B and 66C for a schematic cross-sectional view of the connecting portion of the present invention attached to the conductive pin and the plated contact. The connecting portion of the present invention is attached to the conductive pin and the plated contact. FIG. 74 is a top view of the structure of the structure and the structure of the connecting portion of the present invention attached to the conductive pin and the plated joint. As shown in the figure, the connecting portion 366 is formed on the conductive pin 316 and the plating contact 362. Referring to the drawings of Figs. 67A, 67B and 67C, which are schematic cross-sectional views of the structure of the sealing layer of the present invention, a schematic plan view of the structure of the sealing layer of the present invention, and a bottom view of the structure of the sealing layer of the present invention. As shown, the sealing layer 368 is formed on the semiconductor wafer 310, the winding 350, the solder mask 356, the electrical joint 362, the adhesive 364, and the connecting portion 366. Referring to FIG. 68A, FIG. 68B and FIG. 68C, a schematic cross-sectional view showing a structure in which a second photoresist layer of the present invention is formed on a metal substrate, and a top view of a structure in which a second photoresist layer of the present invention is formed on a metal substrate; A schematic diagram of a structure in which a second photoresist layer of the present invention is formed on a metal substrate. As shown, the second photoresist layer 328 is formed on the metal substrate 320. The second photoresist layer 328 includes an opening having an opening diameter of 200 microns and partially exposing the second plane 324. Referring to the drawings of Figs. 69A, 69B and 69C, there are shown schematic views of a notched structure of the present invention, a plan view of a notched structure of the present invention, and a bottom view of the structure of the present invention having a notch. As shown, the perforation 330 is passed through the metal substrate 320. The via 330 is etched from the partially exposed portion of the second major plane 324 of the metal substrate 320 by a chemical etching solution, and the second photoresist layer 328 is used to etch the mask. The bottom nozzle sprays a chemically etched 75 1292195 solution onto the metal substrate 320. When the top nozzle is not used or the entire structure is immersed in the chemical etching solution, the sealing layer 368 can protect the front side, and the chemical etching solution is highly selective. The copper is etched through the metal substrate 320. Therefore, the through hole 330 penetrates the metal substrate 320 between the first plane 322 and the second plane 324 of the metal substrate 320 and exposes the winding 350. The perforations 330 have a diameter of 300 microns on the first plane 3 2 2 and a depth of 150 microns. Therefore, the through hole 330 is formed in the same manner as the notch 130 of the first embodiment except that the chemical etching is applied for a long time to etch the metal substrate 320. One suitable chemical etching solution is alkaline ammonia. The desired etching time for immersing the metal substrate 320 in the chemical etching solution is a repeated test in order to form the perforations 330 of appropriate diameter. Referring to the drawings of Figures 70A, 70B and 70C, there are shown a schematic cross-sectional view of a metal wall structure of the present invention, a top view of the structure of the metal wall of the present invention, and a bottom view of the structure of the metal wall of the present invention. As shown, the metal wall 332 is formed on the metal substrate 320 and the winding 350. The metal wall 332 is electrically connected to the metal substrate 320 and the winding 350 in the recess 330, but is not integrally joined to the metal substrate 320 and the winding 350. Please refer to FIG. 71A, 71B and 71C for a schematic cross-sectional view of the structure of the second photoresist layer covering the second photoresist layer of the present invention, and a schematic plan view of the structure of the present invention covering the second photoresist layer. 76 1292195 A schematic view of the structure of the invention covering the second photoresist layer. As shown in the figure, the template 338 is overlaid on the second photoresist layer 328. Please refer to FIG. 72A, 72B and 72C for a schematic cross-sectional view showing the structure of the solder paste deposited on the metal wall of the present invention, a schematic view of the structure of the solder paste deposited on the metal wall of the present invention, and the solder paste deposition of the present invention. A schematic view of the structure of the metal wall. As shown, the solder paste 340 is deposited on the metal wall 332. Please refer to FIG. 73A, 73B and 73C for a schematic cross-sectional view of the structure after removing the template of the present invention, a schematic top view of the structure after removing the template of the present invention, and a structure of the present invention after removing the template. schematic diagram. As shown, the template 338 is removed from the second photoresist layer 3 28 . Please refer to FIG. 74A, 74B and 74C for a schematic cross-sectional view of the solder paste of the present invention after forming a solder layer, a schematic top view of the solder paste of the present invention after forming a solder layer, and a solder paste formation of the present invention. A schematic view of the structure behind the solder layer. As shown, the solder layer 342 is formed of the solder paste 340. Please refer to FIG. 75A, 75B and 75C for a schematic cross-sectional view of the second photoresist layer after stripping, a top view of the structure of the second photoresist layer of the present invention, and a first embodiment of the present invention. A schematic diagram of the structure of the two photoresist layers after peeling off. As shown in the figure, after the second photoresist layer 328 is peeled off, the semiconductor wafer 310, the metal substrate 320, the metal wall 332, the solder layer 342, the winding 350, the plating interface 77 1292195 point 362, the adhesive 364, the connecting portion 366 and the structure of the sealing layer 368. Please refer to FIG. 76A, 76B and 76C for a schematic cross-sectional view of the metal substrate after the removal of the metal substrate of the present invention, a schematic top view of the metal substrate after removal of the present invention, and a metal substrate of the present invention. The structure is viewed from the bottom. As shown, the metal substrate 320 is etched from the second major plane 324, the metal wall 332, and the solder layer 342 by a backside wet chemical etching solution. If the bottom nozzle sprays a chemical etching solution onto the metal substrate 320, when the top nozzle is not used or the entire structure is immersed in the chemical etching solution, the sealing layer 368 can protect the front side, when copper is opposed to nickel, tin, In the epoxy resin and the injection molding material, the wet chemical etching is applied. Therefore, the metal substrate 320 is used for the metal wall 332, the solder layer 342, the nickel layer of the winding 350, the solder mask 356, and the sealing layer 368. Use this wet chemical name. &gt; The wet chemical etching etches and removes the metal substrate. Therefore, the wet chemical etching system can remove the metal wall 332, the winding 350, and the area where the solder mask 356 contacts the metal substrate 320. Therefore, the metal substrate 320 is removed in the same manner as the metal substrate 120 of the first embodiment is etched to form the metal pillars 170, except that the chemical etching is applied for a long time to etch the metal substrate 320. A suitable chemical solution is alkaline ammonia. The desired etching of the metal substrate 320 in a chemical etching solution 78 1292195 is time tested in order to remove the metal substrate 320 without exposing the metal wall 332 and the winding 350 to the chemical etching solution. Please refer to FIG. 77A, 77B and 77C for a schematic cross-sectional view of the insulating encapsulant of the present invention, a schematic top view of the insulating encapsulant of the present invention, and an insulating encapsulant of the present invention. The structure is viewed from the bottom. As shown, the insulating encapsulant 382 is formed on the metal wall 332, the solder layer 342, the winding 350, and the solder mask 356. Please refer to FIG. 78A, 78B and 78C for a schematic cross-sectional view of a portion of the insulating encapsulant after removal of the present invention, a schematic top view of the structure after removing the insulating encapsulant of the present invention, and the present invention. A schematic view of the structure after the partial insulation seal is removed. As shown in the figure, the structure is shown after the partial insulating sealant 382 is removed. Please refer to FIG. 79A, 79B and 79C for a schematic cross-sectional view of the structure after the formation of the solder ball of the present invention, a schematic plan view of the structure after the solder ball of the present invention is formed, and a structure of the structure after the solder ball of the present invention is formed. schematic diagram. As shown, the solder ball 384 is formed on the solder layer 342. Please refer to FIG. 80A, FIG. 80B and FIG. 80C for a schematic cross-sectional view of the structure after the formation of the welded end of the present invention, a schematic plan view of the structure after the formation of the welded end of the present invention, and a structure of the structure after the formation of the welded end of the present invention. schematic diagram. As shown, the solder end 386 is formed by a solder layer 342 and a solder ball 384. 79 1292195 ^ Please refer to FIG. 81A, 81B and 81C for a schematic cross-sectional view of a semiconductor wafer package structure, a top view of a semiconductor wafer package structure of the present invention, and a bottom view of the semiconductor wafer package structure of the present invention. As shown, the metal wall 332 is bonded only to the winding 350' insulating sealant 382 and the solder layer 386, which has no metal posts. The semiconductor chip package structure 398 includes a semiconductor wafer 31, a metal wall 332, a wire 350, a solder mask 356, a plating contact 362, an adhesive 364, a connecting portion 366, a sealing layer 368, an insulating seal 382, and a soldering end. 386. FIG. 28 is a cross-sectional view showing a semiconductor chip package structure according to a fourth embodiment of the present invention. FIG. 2 is a plan view of a semiconductor chip package structure according to a fourth embodiment of the present invention. The semiconductor chip package structure of the fourth embodiment is not intended to be viewed. As shown in the fourth embodiment, the semiconductor chip package and the germanium structure 498 are flip chip bonded. First, the connection portion 々a is deposited on the conductive pin 416 by a solder bump, and the solder bump is a half sphere having a diameter of 1 μm. For the sake of brevity, the same description as the first embodiment is not repeated. Similarly, the elements of the fourth embodiment have similar reference numerals as the first embodiment, such as the semiconductor wafer 41 〇 conforming to the semiconductor wafer 110, the winding 450 conforming to the winding 150, and the like. The winding 450 extends over the periphery of the semiconductor wafer 41. Therefore, the elongated winding portion (relative to the component number 1292195 No. 152 in the first embodiment) is lengthened. Further tuned to the windings 150 formed by electroplating in the first embodiment. In particular, a second pre-resist layer of the flute (relative to the third photoresist layer 144 of the first embodiment) is patterned back and/or patterned to re-form an opening on ^(4): The winding 450 is longer than the winding 15 of the first embodiment. The electric ore joint (relative to the electric clock contact 162 of the first embodiment) is omitted. 1. The first plane 412 of the semiconductor wafer 41 faces downward, and the first plane 414 faces upward. The winding 45 〇 extends laterally through the conductive pin 416 &quot;A connection portion 466 is connected to the conductive pin The windings 450 are in contact with and in contact with each other 'and then heated to cause the connecting portion to generate a flow. 'Stop heating to cool the connecting portion 466 to form a hard'. The contact points can be attached to the conductive pins 416 and the windings 45〇. The electrical connection between the conductive pin 416 and the winding 45G is electrically connected. The connection portion 466 is partially wetted but not collapsed, and the semiconductor wafer 410 is isolated from the winding 450. Thereafter, the adhesive 464 is filled between the semiconductor wafer 41 and the solder mask 456, and then the adhesive is hardened. Therefore, the adhesive 464 is sandwiched between the semiconductor wafer 41 and the bump mask 456, and is bonded to the semiconductor wafer 41G and the recording mask 456, and is also bonded to the connecting portion 466 and is not in contact with the conductive pin 416. . Therefore, the adhesive 464 is thicker than the adhesive 164 of the first embodiment. A suitable adhesive is the Namics U8443. The sealant layer 468, the metal post 470, the insulating sealant 482, and the welded 1292195 end 486 are formed. The semiconductor chip package structure 498 includes a half, a first-410, a metal wall 432, a wire 45, a solder mask wafer 464, a connection portion 466, a sealing layer 468, a metal post, an adhesive 482, and a solder end 486. For the insulating package, please refer to the "Sections 83A, 83B, and 83C". The semiconductor wafer package structure of the fifth embodiment of the invention is a cross-section of the semiconductor wafer package structure of the fifth embodiment of the present invention: The semiconductor wafer package of the fifth embodiment of the present invention is intended to be a bottom view. As shown in the figure: in the fifth embodiment: formed by an electric mine. For the sake of brevity, the same description as the first implementation = does not need to be repeated. Similarly, the elements of the first example have similar reference numerals as the first embodiment, such as: ί = sheet 510 coincides with semiconductor wafer no, winding two coincides with winding 150, and the like. The conductive pin 516 can accommodate the connection of the electroplated copper by forming a recording surface layer on the substrate. For example, the semiconductor wafer 51 is sub-packaged in a -zinc bath to deposit a layer on the substrate. This side is zincated. The zinc solution contains 15 g/L of hydrogen, sodium, 25 g/L of zinc oxide, and g/L of sulphate is like a stone, which reduces the decomposition rate of the substrate. The recorded surface layer is then electrolessly deposited on the zincated substrate. - A suitable non-electric recording clock solution is in degrees Celsius - 82 1292195

Enplate NI-424. The winding 550 is extended within and outside the edge of the semiconductor wafer 51. Therefore, the elongated winding portion (relative to the elongated winding portion 152 in the first embodiment) becomes longer by slightly treating the winding formed by the plating in the first embodiment. Ground adjustment. The second photoresist layer (printed with respect to the third photoresist layer 14 in the first embodiment) and re-formed an opening to the winding 55〇, so that the winding φ 550 is larger than in the first embodiment. The wire 150 becomes longer. The metal substrate (relative to the metal substrate 12A in the first embodiment) is etched to form a second back side notch (not shown), the plated joint (relatively The plating contact 162) in the first embodiment is deleted, and the adhesive 564 is deposited on the winding 55〇 and the soldering mask 556. The half-V body day 510 is inverted, wherein The first plane 512 is directed downward and the second plane 514 is oriented upward. The adhesive 564 is in contact with the conductive pin 516 and the winding 550, and is sandwiched between the conductive pin 510 and the winding 55. The conductive pin 516 and the wire 550 are in contact with each other. The thickness between the conductive pin 516 and the winding 55 is 5 micrometers. The winding 55 〇 and the conductive pin 516 are partially rich. Then, the sealing layer 568 is formed, and then the metal substrate is further converted into a slot by the residual (sl〇t) (not shown) The slot extends and penetrates the metal substrate to expose the solder mask 556 and is vertically aligned with the conductive pin 516. Then, the through-hole 565 is formed in the solder 83 1292195 The mask 556 and the adhesive 564 θ are exposed, and the conductive pin 516 is exposed. When the solder mask 556 and the adhesive 564 are used for the conductive pin 516 and the winding 550, a suitable method for forming a perforation can be used. In this embodiment, a &amp; ΤΕΑ (: 雷 2 laser surname method is selected. The laser is directed to the conductive pin 516, and is vertically aligned at the conductive pin 516 and concentrated on the conductive pin. 516. The laser system has a light spot having a size of 70 micrometers, and the conductive pin 516 has a length and a width of 1 micron. The laser system hits the conductive pin 516 and a portion of the winding 550. The solder mask 556 and the adhesive state extend in the edge of the conductive pin 516 and melt the solder mask 556 and the adhesive (four) 564. The laser drill (four) portion of the solder mask 556 and the adhesive 564 'And remove some of the solder mask 5 brothers and adhesive 564. However, some of the fresh mask 556 and The primer (10) extends past the edge of the conductive pin 516, but outside the consumption of the laser energy contact. Similarly, the winding 55 is protected from a laser etch to protect a portion of the adhesive 564. The portion of the adhesive (10) is sandwiched between the conductive pin 516 and the winding 55G and joined to each other. The money is anisotropic, so a small portion of the adhesive (10) is: The conductive pin 516 and the winding 550 are removed or cut away. The opening 565 may be slightly cut off between the conductive pin 516 and the winding ο, because of the angle of the laser beam, The temperature of the laser and the isotropic or chemical cleaning of the plasma oxygen make the mouth-feeding milk 2 slightly larger than 7G micron. For the convenience of explanation, the cutting and expansion of the shape are omitted. The formation of the recess 565 then does not damage the semiconductor 84 1292195: sheet 510 or winding 55, nor does it extend into the interior of the semiconductor wafer 51. The conductive pads 516 and portions of the wires 550 are then exposed to remove oxides and debris using a short cleaning step. For example, a short electro-hydraulic oxygen-washing method is applied to the structure, or a short chemical cleaning method using a potassium permanganate solution is applied to the structure. The above-mentioned cleaning method can clean the conductive pin 516 and the winding. The exposed portion of 550 does not damage the overall structure. The connecting portion 566 is formed by electroplating. First, the metal substrate is connected to an electroplating bus bar (not shown). The electroplating bus bar uses an external power source, and the whole structure is immersed in an electrolytic copper plating solution. The solution is as Sel_Rex CUBATH 室温 at room temperature. Therefore, the connecting portion 566 is plated on the exposed portion of the metal substrate. In addition, current is supplied from the plating busbar to the metal substrate, so that the metal substrate will supply current to the winding 550, which is plated in the portion of the perforation 565 where the wire 550 is exposed. At the beginning of this phase, the adhesive 564 is an insulator, and the conductive pin 516 is not connected to the electric clock bus. The connecting portion 566 is not plated on the conductive pin 516 and is electrically connected to the conductive pin. Bit 516 is isolated. However, when copper plating is continued, the connecting portion 566 is continuously plated on the winding 550 and penetrates through the adhesive 564, and finally contacts the conductive pin 516. The conductive pin 516 is connected to the plating bus by the metal substrate, the winding 550 and the connecting portion 566, so the connecting portion 566 can be plated on the 85 1292195 conductive pin 516. Copper plating is continued until the joint 566 reaches the desired thickness. The bulk structure is then removed from the electrolytic copper plating solution and washed with distilled water to remove contaminants. The insulating plug 569 is then formed on the solder mask 556 and the connecting portion 566 and deposited in the slot, and then the metal wall 570, the insulating encapsulant 582 and the solder end 586 are formed.

The semiconductor chip package structure 598 includes a semiconductor wafer 51 , a metal wall 532 , a winding 550 , a solder mask 556 , an adhesive 564 , a connecting portion 566 , a sealing layer 568 , an insulating plug 569 , a metal post 570 , and an insulating seal 582 . And welding end 586. FIG. 84 is a schematic cross-sectional view showing a semiconductor chip package structure according to a sixth embodiment of the present invention, and a plan view of a semiconductor chip package structure according to a sixth embodiment of the present invention and the present invention. A schematic view of a semiconductor wafer package structure of a sixth embodiment. As shown in the figure: in the sixth embodiment, the connecting portion is electroless plating. For the sake of brevity (d), the same description as the first embodiment does not need to be repeated. Similarly, the member of the sixth embodiment has a similar reference number as the first embodiment, such as the body wafer 610 conforming to the semiconductor wafer no, the winding 650 conforming to the winding 150, and the like. In the fifth embodiment, the winding 650 is the same as the fifth embodiment. The adhesive 664 is deposited. The conductive pin 616 includes a conductive pin 516. The winding method is the same as the winding 550 in the same embodiment. The forming method phase 86 1292195 is the same as the method in which the winding 650 and the solder mask 656 are deposited on the winding 550 and the solder mask 556 in the fifth embodiment, the plating contact (relative to the first embodiment) The plating contact 162) is omitted. The semiconductor wafer 610 is flipped, wherein the first plane 612 is below and the second plane 614 is above, and the adhesive 664 is interposed between the conductive pin 616 and the winding 650, and the conductive pin The 516 is in contact with the winding 550 with a thickness of 5 microns therebetween, and the winding 650 partially overlaps the conductive pin 616. Next, the sealing layer 668 is formed, and then the metal substrate is etched to form a metal pillar 670. Next, the via 665 is formed in the solder mask 656 and the adhesive 664 and exposes the conductive pin 616. This perforation 665 is formed in the same manner as the perforation 565 in the fifth embodiment. Next, the connecting portion 666 is formed by electroplating. The monolithic structure is immersed in an electrolytic nickel plating solution such as Enthone Enplate NI-424 at 85 degrees Celsius. A preferred electrolytic nickel ore solution comprises nickel-sulfate and nickel-chloride, and the solution has a pH of between about 9.5 and 10.5. A high concentration electrolytic nickel plating solution accelerates the plating rate but reduces the stability of the solution. A certain amount of chelating agents or ligands in the solution are based on the concentration of nickel and their chemical structure, functionality and equivalent weight. Most of the chelating agents are used in electroless nickel electricity money solution system 87 1292195

Organic hydroxy organic acids form one or more water soluble nickel ring complexes. The above complex reduces the concentration of free radical nickel ions, thereby increasing the stability of the solution and maintaining a rapid plating rate. Generally, the composite has a high concentration and reduces the plating rate. In addition, when electroless plating is continued, the pH and plating rate of the solution continue to decrease due to the injection of hydroxide ions into the solution as a by-product of nickel reduction. The solution is then buffered and compensated for by the influence of «Hai hydrogen oxide ions. Suitable buffering agents include monoatomic (sodium) or potassium salts and dibasic organic acids. Finally, from the above process, it is known that the electroless nickel plating solution does not deposit pure elemental nickel, and a reducing agent such as HJO2 will naturally be decomposed into the electroless plating process. Therefore, in the above process, it is known that the nickel compound is almost nickel but not pure elemental nickel. The conductive pin 616 includes an exposed nickel surface layer, and the conductive pin 616 is in contact with the non-following contact. Moreover, the radiation mask 656, the adhesive 664, and the seal layer are not in contact with the μ. Therefore, it is not necessary to use a plating mask. The connecting portion 66 is electrically connected to the conductive pin 616 and is in contact with the conductive pin 616 and the hole 650 in the hole 665 and electrically connected between the conductive pin 616 and the winding (4) in the hole 665. Connection. When the (4) electroplating coffee is continued until the thickness of the connecting portion 666 is about 1 〇, then the overall structure is removed from the electroless plating solution and washed with the base crane water 1292195. Next, the insulating encapsulant 682 and the solder end 686 are formed. The semiconductor wafer package structure 698 includes a semiconductor crystal 61, a metal wall 632, a winding 65, a solder mask 656, a bonding 664 connection 666, a sealing layer 668, a metal pillar go, an insulating adhesive 682, and a soldering end 686. ^ 凊 "85A, 85B, and 85C", which is a sectional view of a semiconductor wafer package structure according to a seventh embodiment of the present invention: the semiconductor wafer sealing structure of the seventh embodiment of the present invention is intended to be And a bottom view of the semiconductor wafer package structure of the seventh embodiment of the present invention. As shown in the figure: in the seventh embodiment, the fresh sound is provided to the welded end. For the sake of brevity, the description of the first embodiment is not necessarily repeated. Similarly, the member of the seventh embodiment has a reference number similar to that of the first embodiment. For example, the semiconductor wafer 71G conforms to the semiconductor wafer UG, and the winding 75 〇 corresponds to the winding 150. The solder ball (the 18th sentence of the solder ball in the first embodiment is omitted) so the solder layer (relative to the solder layer 142 in the first embodiment) provides the solder end 786. The solder end 786 is placed The hole 734 =, the metal wall 732, the insulating sealant 782 and the welded end 786 are laterally arranged on each other in a downwardly facing plane. Since &amp; an exposed horizontal plane is facing downward, and comprises a metal wall 732, an insulating sealant 782 and the splicing end 786. Each of the conductive traces comprises a laterally aligned 89 1292195. The soldered end provides a planar grid array assembly. The semiconductor wafer package structure 798 includes a semiconductor wafer 710 and a metal wall 732. , winding 750, solder mask 756, plating contact 762, adhesive 764, connecting portion 766, sealing layer 768, metal post 770, insulating encapsulant 782 and soldering end 786. Please refer to "86A, 86B and 86C" The semiconductor chip package structure of the eighth embodiment of the present invention is not intended to be a semiconductor chip package structure of the eighth embodiment of the present invention, and the semiconductor chip package of the eighth embodiment of the present invention is not shown. A bottom view is shown. As shown in the figure: in the eighth embodiment, the insulating sealant portion is removed by laser ablation. For the sake of brevity, the same description as the first embodiment is used. Similarly, the elements of the sixth embodiment have similar reference numerals as the first embodiment, such as the semiconductor wafer 610 conforming to the semiconductor wafer 110, the winding 650 conforming to the winding 150, etc. The insulating encapsulant 882 is formed without the use of a filler. Therefore, the insulating encapsulant 882 is more sensitive to laser encapsulation than the insulating encapsulant 182 of the first embodiment, and the polishing process is removed to The selective TEA C02 laser etch replaces and utilizes a composite laser direct write head that is directed at the solder layer (relative to the solder layer 142 of the first embodiment). The spot size of the laser is 100. Micron. And the laser direct writes are offset from each other so that the central portion of the laser scanning solder layer has a scan diameter of 1292195 150 microns. In this method, the laser is straight. Write head (la The ser direct writes are arranged vertically and concentrated on the metal wall 832, the metal post 870 and the solder layer. Therefore, the laser light hits the solder layer and etches the portion of the insulating encapsulant 882 overlapping the solder layer. The insulating encapsulant 882 is melted. The laser drills through and removes part of the insulating encapsulant 882. Then a portion of the insulating encapsulant 882 extends and passes through the edge of the solder layer, φ but is shot by the thunder Therefore, the insulating encapsulant 882 still contacts and overlaps with the solder layer, but no longer covers the solder layer. The exposed portions of the solder layer are then removed using a short cleaning step to remove oxides and debris. For example, a short plasma oxygen cleaning method is applied to the structure, or a short chemical cleaning method using a potassium permanganate solution is applied to the structure. The above cleaning method can clean the exposed portion of the solder layer without damaging the overall structure. • The opening 883 is formed on the insulating encapsulant 882 and extends vertically to the insulating encapsulant 882 but does not penetrate the insulating encapsulant 882 and is placed on the edge of the semiconductor wafer 81 and with metal The wall 832, the metal post 87〇 and the solder layer are vertically arranged, the opening μ) exposing the solder layer and separating from the metal wall 832, the winding 85〇, the solder mask 856 and the metal post 870, the opening 883 The diameter is 15 inches. The opening 883 is formed without causing damage to or extending into the solder layer. The diameter of the opening 883 may be slightly larger than 15 μm, due to the angle of the 1292195 beam at 5 Hz, the temperature of the laser and the isotropic nature of the plasma oxygen. For the convenience of explanation, there is a slightly expanded part of the bird. ▲ Then the fresh joint 886 is formed. The soldering end 886 extends inside and outside the opening 883 and fills the opening 883 and extends downward from the insulating encapsulant 882. Moreover, although (4) the entire portion of the solder joint 886 extending into the insulating encapsulant 882 is within the surface area of the hole (4). The semiconductor chip package structure 898 includes a semiconductor wafer 810, a metal wall 832, a wire 85 〇, a solder mask 8S6, a plating contact 862, an adhesive 864, a connecting portion 866, a sealing layer 868, a metal post 870, and an insulating sealant. 882 and welded end 886. FIG. 87 is a cross-sectional view showing a semiconductor wafer package structure according to a ninth embodiment of the present invention, and a plan view showing a semiconductor chip package structure according to a ninth embodiment of the present invention and the present invention. A schematic view of a semiconductor wafer package structure of a ninth embodiment. As shown in the ninth embodiment, the insulating encapsulant portion is removed by plasma engraving. For the sake of brevity, the same description as the first embodiment is not required to be repeated. Similarly, the elements of the ninth embodiment have a similar spring number as the first embodiment, such as the semiconductor wafer 910 conforming to the semiconductor wafer 11A, the winding 950 conforming to the winding 150, and the like. The insulating encapsulant 982 is shaped as 92 1292195 without the use of a filler (fiUer). Therefore, the insulating encapsulant 982 is more sensitive to laser encapsulation than the insulating encapsulant 182 of the first embodiment, and the grinding process is omitted, and is further replaced by a blanket backside plasma and applied to the structure. When the epoxy resin is used for plasma etching of nickel and tin, plasma etching may be employed when the insulating encapsulant 982 is applied to the metal wall 932 and the soldered end 986. The plasma etch can remove a thickness of 80 microns from the lower portion of the insulating encapsulant 982. Therefore, the metal wall 932 and the soldering end 986 extend downward from the insulating encapsulant 982, and the insulating encapsulant 982 is recessed in a downward direction with respect to the metal wall 932 and the soldering end 986. Moreover, the insulating encapsulant 982 extends downwardly from the metal post 970, which is unexposed. The semiconductor chip package structure 998 includes a semiconductor wafer 91, a metal wall 932, a wire 950, a solder mask 956, an electrical contact 962, an adhesive 964, a connection portion 966, a sealing layer 968, a metal post 970, and an insulating cover. Win 982 and fresh pick up 986.

〇〇8, "" and 88C diagram" - w 』 』 factory / | small, the semiconductor chip package structure of the tenth embodiment of the invention is shown in the tenth embodiment of the semiconductor wafer package (10) π 图;, the semiconductor wafer package of the tenth embodiment of the invention _ looking up is not as good as the ten hehe sealant. For the sake of briefness, the 盥笫 ^ ^ , , , , , , , , , , , , , , , , , , , , , , , , , Similarly, the tenth embodiment (10) similarly has a matching reference number, such as the semiconductor wafer 93 1292195 in the semiconductor wafer 110, the winding 1G5G conforms to the winding, the insulating seal (relative to the first implementation) In the example, the insulating encapsulant 18 is removed, so no polishing is required in this embodiment. The semiconductor chip package structure 1098 includes a semiconductor wafer 1010, a metal wall 1032, a winding 1050, a solder mask 1〇56, and a plating contact 1062. , the adhesive 1〇64, the connection part 1〇66, the metal column chatter and the soldering end. 1068, please refer to the “Analysis of the 89th, 89B and 89C”, which is the semiconductor of the eleventh embodiment of the present invention. Schematic diagram of chip package structure ^ A plan view of a semiconductor wafer package structure according to a tenth embodiment of the present invention and a semiconductor chip package structure according to an eleventh embodiment of the present invention are shown in a bottom view. As shown in the eleventh embodiment, the metal wall and the winding are simultaneously It is formed for the sake of brevity, and has the same description as the second embodiment, and need not be repeated. Similarly, the elements of the eleventh embodiment have similar reference numerals as the first embodiment. For example, the semiconductor wafer 111 〇 conforms to the semiconductor wafer winding 1150 conforms to the winding 15 〇, etc. The metal wall 1132 and the winding 1150 are simultaneously formed in the plating process, and the metal wall 132 is formed in the first embodiment. The plating process is slightly adjusted. Specifically, the first photoresist layer (relative to the first photoresist layer 126 in the first embodiment) is connected to the third photoresist layer (relative to the third resistor in the first embodiment). The layer 144) is printed with the pattern forming winding 94 1292195 1150 as well, and the notch (relative to the notch 13 第一 in the first embodiment) is formed by a backside wet chemical etching, without using the front side Wet a front-side wet chemical etch, such that the first photoresist layer (relative to the first photoresist layer 126 in the first embodiment) selectively elects the metal substrate (relative to the first embodiment) The first plane of the metal substrate 120) is exposed. For example, the bottom nozzle can spray a wet chemical etching solution on the metal substrate (relative to the metal substrate 120 in the first embodiment) when the top nozzle is not used. Then, the metal wall 1132 and the winding 1150 are simultaneously plated on the metal substrate. Therefore, the metal wall 1132 and the winding 115 are both made of a nickel layer plated on the metal substrate and a gold layer plated with a nickel layer. Composed of. And the thickness of the nickel layer is 3 〇 micron. In both the metal wall 1132 and the winding 115 ,, the nickel layer is sandwiched between the metal substrate and the gold layer, and covered by a gold layer, and the thickness of the nickel layer is 3 〇 micrometer, and the gold layer The nickel layer is bonded, but is isolated from the metal substrate, and the surface of the gold layer is violently exposed to a thickness of 〇·1 μm. In addition, the third photoresist layer and the fourth photoresist layer (relative to the third photoresist layer 144 and the fourth photoresist layer 146 in the first embodiment) are removed by forming a winding 115 during the electroplating process. The solder layer (relative to the solder layer 142 in the first embodiment), the solder mask 1156, the plating contacts 1162 and the adhesive n64, the formation and the semiconductor wafer H10 are mounted on the adhesive 1164, and then the connection portion A crucible 66, a sealing layer 1168, a metal post 1170, an insulating encapsulant 1182, and a soldered end 1186 are formed. 95 1292195 The semiconductor chip package structure 1198 includes a semiconductor wafer 1110, a metal wall 1132, a winding 1150, a solder mask 1156, a plating contact 1162, an adhesive 1164, a connection portion 1166, a sealing layer 1168, a metal pillar 1170, and an insulating seal. Glue 1182 and welded end U86. FIG. 90 is a schematic cross-sectional view showing a semiconductor chip package structure according to a twelfth embodiment of the present invention, and a schematic view of a semiconductor chip package structure according to a twelfth embodiment of the present invention. A schematic view of a semiconductor wafer package structure of a twelfth embodiment of the present invention. As shown in the figure: In the twelfth embodiment, the metal wall and the plating contact are simultaneously formed. For the sake of brevity, the same description as the first embodiment does not need to be repeated. Similarly, the elements of the twelfth embodiment have similar reference numerals as the first embodiment, such as the semiconductor wafer 1210 conforming to the semiconductor wafer 110' winding 1250 conforming to the winding 15... and the like. The «Metal metal wall 1232 and the electric ore joint 1262 are simultaneously formed during the electric ore process, and the electroplating process for forming the metal wall 132 in the first embodiment is slightly adjusted. In particular, after the winding 1250 and the solder mask 12/6 are formed, the first photoresist layer (relative to the first photoresist layer 126 in the first embodiment) is opposite to the fifth photoresist layer (relative to It has the same pattern as the fifth photoresist layer 158) in the first embodiment. Then, the notch (relative to the recess 13 第 in the first embodiment) is formed by a backside wet chemical chemistry, and does not use the front side wet chemical etch, so the first photoresist The layer (relative to the first light 96 1292195 resist layer 126 in the first embodiment) is configured to selectively expose the copper layer of the winding 1250. For example, the bottom nozzle can eject a wet chemical etching solution onto a metal substrate (relative to the metal substrate 120 in the first embodiment) when the top nozzle is not in use. Then, the metal wall 1232 and the plating contact 1262 are simultaneously plated on the metal substrate and the winding 1250, respectively. Therefore, the metal wall 1232 and the plating contact 1262 are composed of a 10 micron thick nickel layer and a 0.1 micron thick gold layer. In addition, the fifth photoresist layer and the sixth photoresist layer (relative to the fifth photoresist layer 158 and the sixth photoresist layer 160 in the first embodiment) are formed by forming the plating contacts 1162 during the electroplating process. Next, the solder layer (relative to the solder layer 142 in the first embodiment) and the adhesive 1264 are formed, the semiconductor wafer 1210 is mounted on the adhesive 1264, and then the connecting portion 1266, the sealing layer 1268, the metal pillar 1270, an insulating sealant 1282 and a soldered end 1286 are formed. The semiconductor chip package structure 1298 includes a semiconductor wafer 1210, a metal wall 1232, a winding 1250, a solder mask 1256, a plating contact 1262, an adhesive 1264, a connection portion 1266, a sealing layer 1268, a metal pillar 1270, and an insulating sealant 1282. And welding end 1286. And a semiconductor chip package structure according to a thirteenth embodiment of the present invention, a top view of a package structure, and a semiconductor wafer according to a thirteenth embodiment of the present invention. The package structure is not intended to look up. In the thirteenth embodiment, the metal wall, the metal post and the solder end are disposed within the edge of the semiconductor wafer. For the sake of brevity, the same description as the first embodiment does not need to be repeated. Similarly, the elements of the thirteenth embodiment have similar reference numerals as the first embodiment, such as the semiconductor wafer 1310 conforming to the semiconductor wafer, the winding 1350 conforming to the winding 150, and the like. The winding 1350 is disposed in the edge of the semiconductor wafer and the edge/extends the metal wall 1332, the metal pillar 137, and the soldering end 1386 are disposed in the periphery of the semiconductor wafer 131, by - The plating process of the notch 130 and the winding 15 in the embodiment is slightly adjusted. In particular, the second photoresist layer (relative to the second photoresist layer 128 in the first embodiment) is patterned and changed transversely to the recess (relative to the recess 13 in the first embodiment) The opening, so the recess has been altered relative to the recess 130. The third photoresist layer (relative to the third photoresist layer 144 in the first embodiment) is then patterned to reform the opening forming the striking line 1350. Therefore, the metal wall 1332, the metal pillar 1370, and the soldering end 1386 are disposed in the periphery of the semiconductor wafer 131A. The semiconductor wafer package structure 1398 includes a semiconductor wafer 131, a metal wall 1332, a winding 1350, a solder mask 1356, an electroplated contact 1362, an adhesive 1364, a connecting portion 1366, a dense insulating cap (10), and a soldering end 1386. 9 368 ′′, as shown in the “92A, 92B, and 92C diagrams”, is a semiconductor wafer package structure of the fourteenth embodiment of the semiconductor chip package structure of the fourteenth embodiment of the present invention: The semiconductor wafer C and the nose and mouth of the fourteenth embodiment are not tolerated. As shown in the figure: In the fourteenth embodiment, the metal column is turned upside down. For the sake of the short head #, the same description of the second money, there is no need to be repeated. Similarly, the elements of the first embodiment have a reference fiducial pattern 45' similar to that of the first embodiment, = the conductor wafer conforms to the semiconductor wafer &quot;, the winding 1450 corresponds to the winding 150, and the like. - The metal substrate (relative to the metal substrate in the first embodiment has a thickness of 5 μm. The recess (relative to the recess 130 in the first embodiment) and the metal wall 1432 are formed on the metal substrate. The first major plane (relative to the first-first plane 122) is formed on the metal wall 1432 by the solder joint 142 in the first embodiment, and the winding 145 is A second plane (relative to the second major plane 124 in the first embodiment) formed on the metal substrate is removed (relative to the solder mask 15 2 in the first embodiment). Next, the insulation The encapsulant 1482 is placed on the winding 1450 and the metal substrate, and then the portion of the insulating encapsulant is polymerizable and forms a gel. Next, the overall structure is placed in a metal of the first embodiment. The substrate 120 is similar to the support. When the insulating sealant 1482 is a gel, the insulating sealant 1482 is in contact with the support and is sandwiched between the metal substrate and the support and the winding 1450 and the support, and then The insulating sealant 1482 is hardened. Then the metal pillar 1470 Formed, then the plating contact 1462 is formed. Then, the adhesive 1464 is placed on the insulating encapsulant 1482, and then the semiconductor wafer 1410 is placed on the adhesive ι464, and then the adhesive 1464 is hardened. The metal post 147 is not disposed below the half V body fin 1410, but expands upward and exceeds the thickness of the semiconductor wafer 1410. The metal post 147 is 42 μm thick.

Next, the connecting portion 1466 is formed, and the sealing layer 1468 is subsequently formed. The sealing layer 1468 is similar to the insulating encapsulant 182 of the first embodiment and has a thickness of 6 μm. Therefore, the sealing layer is placed on the δ 半导体 semiconductor wafer 丨 4 丨〇, the winding 丨 45 〇, the adhesive 1464, the connection portion Μ 66, the metal pillar 1470, and the insulating sealant 1482, and the sealing layer 1468 is Harden. The post-u-sea sealing layer 1468 is ground and the metal wall 1432 and the splicing layer are exposed, and then the soldering end 1486 is formed. The semiconductor chip package structure 1498 includes a semiconductor wafer L410, a metal wall 1432, a winding 1450, a plating contact 1462, an adhesive 4 1464, a connection portion 1466, a sealing layer 1468, a metal pillar 1470, a 100 1292195 insulating sealant 1482, and a soldering process. End i486. Please refer to the figure "93A, 93B and 93C".

The semiconductor chip package of the fifteenth embodiment of the invention; the vertical view, the semiconductor chip package structure of the fifteenth embodiment of the invention, and the semiconductor chip package structure of the fifteenth embodiment of the invention are not looked up intention. As shown in the fifteenth embodiment, the semiconductor chip package structure is a multi-wafer package. For the purpose of simplicity, the same description as the first embodiment is not required to be repeated. Similarly, the elements of the fifteenth embodiment have similar reference numerals, such as semiconductor wafers, to the first embodiment. (7) Corresponding to the semiconductor wafer 110, the winding 1550 corresponds to the winding 15... and the like.

The plated contact 1562 is extended to slightly adjust the electrical process (four) of the electric ore junction 162 in the first embodiment. In particular, the fifth photoresist layer (relative to the fifth photoresist layer 158 in the first embodiment) has a pattern and extends the opening forming the plated contact 1562, so the plated contact 1562 is relative to the first The plated contacts 162 of the embodiment become longer. The semiconductor wafer 1510 is mechanically coupled to the solder mask 1556 by the first adhesive 1564, and is electrically connected to the winding ι 55 by the first connecting portion 1566. Then, the second adhesive 1565 is disposed on the first semiconductor die 1510, which is a silicone separated from the first semiconductor wafer 1510 and the second semiconductor wafer 1511, and then the second semiconductor wafer 101 1292195 1511 ( The conductive pin 1517 is disposed on the second adhesive 1565, and the second adhesive 1565 is sandwiched between the first semiconductor wafer 151 and the conductive material 1515. Between the second semiconductor wafers 1511, the overall structure is placed in an oven, so that the second adhesive 1565 is hardened at a relatively low temperature to form a solid adhesive insulative layer, so that the first semiconductor wafer 1510 Physically connected to the second semiconductor wafer 1511, the relative low temperature range is between 15 degrees and 2 degrees, and the second adhesive 1565 is interposed between the first semiconductor wafer 151 and the second semiconductor The thickness of the wafer 1511 is 1 μm, and the first semiconductor wafer 1510 and the second semiconductor wafer 1511 are separated and arranged perpendicular to each other. A suitable sp acer paste is Hysol QMI 500. Then, the second semiconductor wafer 1511 is electrically connected to the winding _155 by the second connecting portion 1567, and the first semiconductor wafer 1510 and the winding 155 are connected by the second connecting portion 1566. The same method with electrical connections. Thereafter, the sealing layer 1568 is formed to have a thickness of 7 μm, and the f sealing layer 1568 is bonded to the first semiconductor wafer 151, the second semiconductor wafer 1511, the winding 155, the solder mask 1556, and the plating contact. 1562, the first adhesive 1564, the second adhesive 1565, the first connecting portion 1566, and the second connecting portion 1567 are in contact with and covered thereon. The metal post 1570, the insulating seal 1582, and the solder end 1586 are then formed by 102 l292l95. The semiconductor chip package structure 1598 is a multi-chip first-level package. The first semiconductor wafer 1510 and the second semiconductor wafer j 5 i j are embedded in the sealing layer 1568. Moreover, the first conductive pin 1516 and the soldering end 1586 not only comprise and require the metal wall 1532, the winding 1550, the electric ore joint 1567 and the metal post 1570 to form a conductive path, and the second conductive pin position I517 and the soldering The end 1586 includes and requires a metal wall 1532, a winding 1550, a plated joint 1567, and a metal post 1570 to form a conductive path. Therefore, the first semiconductor wafer 151 and the second semiconductor wafer 1511 are embedded in the sealing layer 1568, and the conductive path formed by the metal wall 1532, the winding 1550, the plating contact 1567 and the metal pillar 1570 The soldered end 1568 is electrically connected. The semiconductor chip package structure 1598 includes a first semiconductor wafer 1510, a second semiconductor wafer 1511, a metal wall 1532, a winding 1550, a solder mask 1556, a plating contact 1562, a first adhesive 1564, and a second adhesive 1565. The first connecting portion 1566, the second connecting portion 1567, the sealing layer 1568, the metal post 157 〇, the insulating sealant 1582, and the soldering end] [586. Referring to the drawings of Figures 94, 95, 96, 97 and 98, a cross-sectional view of a metal post structure of the sixteenth to twentyth embodiments of the present invention is shown. As shown in the figure, when wet chemical etching is performed, the metal pillars 1670, 1770, 1870, 1970, and 103 1292195 in the sixteenth to twentyth embodiments are narrow and cut the metal wall, for example, by adding Erosion / Chen time or money engraved time. Yanhai metal column touch, 1770, job, and 0 are also tapered. When the metal column extends downward, its diameter will hold: n::)r Each metal column contains an upper plane (relative to the first pass) In the example, the first plane 172) of the metal post 17G, the lower plane (relative to the second plane of the metal post 170 in the first embodiment) and a cone surface (relative to the metal post (7) in the first embodiment) The cone surface Π6), between these, the τ square plane is concentrated in the surface area of the upper plane, and the surface area of the lower plane is at least 2% larger than the surface area of the upper plane. The semiconductor wafer package I structure in the embodiment is only an example of the target. There are many embodiments which are conceivable, for example, the solder mask, the plating contact, the metal pillar and the insulating substrate are deleted. The embodiments can be used in combination with each other, for example, forming a solder layer after the sealant of the second embodiment, and forming a metal wall and a solder layer after the sealant of the third embodiment can be applied to other embodiments. Ground' 5H in the fourth embodiment of the flip chip The plated connections of the fifth and sixth embodiments can be used in other embodiments, except for the multi-wafer semiconductor chip package structure of the fifteenth embodiment, since the semiconductor wafer cannot be flipped. Similarly, the seventh embodiment can be used in other embodiments. The insulating substrate of the eighth and ninth embodiments and the insulating substrate removed in the tenth embodiment can be similarly used for other implementations. In the eleventh embodiment, the metal wall and the winding formed by the shape 104 1292195 can be used in other embodiments as well as the metal wall and the plating contact system simultaneously formed in the twelfth embodiment. The metal walls, the metal posts and the soldered ends of the thirteenth and fourteenth embodiments can be similarly used in other embodiments. The multi-wafer semiconductor chip package structure of the fifteenth embodiment can be similarly used for other In the embodiment, except for the fourth to sixth embodiments, the semiconductor wafer system cannot be flipped. The metal pillars of the sixth, seventh, eighth, ninth and twelfth embodiments are similarly used. First second And the fourth to fifteenth embodiments, but not for the third embodiment, because the metal posts are deleted. The above embodiments can be mixed with each other to form other embodiments, which can be designed and reliability. The metal substrate does not need to be removed within the boundary of the semiconductor wafer, for example, the metal substrate extends within the boundary of the semiconductor wafer and is separated by the metal wall, and the system remains intact. A heat sink is also provided.

The metal wall system can be made of various materials, including copper, nickel, nickel, solder, and a combination of the above materials. The metal coil can be formed in various ways, including electricity, flow, and In combination with the above manner, the metal wall is stored in an early layer or a layer and has different shapes and sizes. For example, the soil can be produced by a single-mode such as electro-mine or solder paste deposition*, such as deposition with solder paste. Conducting electricity during reverse flow: and. The soil system includes a hole, the hole is a single metal surface, and the single metal surface 105 1292195 can be different wettable metals, including gold, titanium and tin, especially in the reflow of the tin or When different non-wettable metals are used, in particular, the tin has been refluxed or not. Further, the hole has an opening, and the shape of the opening may be circular, rectangular or square. ^ The metal wall may be deposited on the metal substrate before the wire is deposited between the metal substrate or after the wire is deposited on the metal substrate, and is deposited on the remote plating contact before the winding After the plating contact is deposited between the windings or after the plating contacts are deposited on the wire; before the semiconductor wafer is connected to the winding or after the semiconductor wafer is connected to the winding; Before being formed or after the sealing layer is formed, and before the connection portion is formed, between the connection portions, or after the connection portion is formed, it is deposited on the metal substrate. For example, the plated metal wall can be formed simultaneously with the winding, the plated joint or the joint, thus improving the manufacturing yield. The solder layer is deposited on the metal wall by a reflow of a tin material (e.g., a non-solid material containing tin material), and then an external force is applied to reflow the solder material to form a hardened solder layer. Suitable materials comprising tin include solder paste, liquid tin and tin particles. The tin material can be a tin-lead alloy (tin-Iead an〇y), although lead-free composites such as tin-bismuth and tin-silver-copper will be environmentally related to excessive use of lead in the electronics industry, making lead-free compounds Will become very popular. Suitable deposition processes include grid printing (sreen ρη·ηη·ηβ), stencil printing (price 106 1292195 printing) 'semicircular coating (menisc concave s coating), liquid tin material spraying (liq concave id solder jetting) And solder particle placement. It can be heated by a two-flow oven, although other techniques such as infrared continuation of the belt (infrared continent s belt reflow), hot nitrogen gas, laser beam and vapor phase reflow (vapor-phase re flow) can be used. The soldering layer is before or after the wire is deposited on the metal wall, before or after the plating contact is deposited on the winding wire, before or after the semiconductor wafer is connected to the winding, before the sealing The layer can be formed before or after the layer is formed, before or after the connection portion is formed, before or after the metal pillar is formed, and before or after the insulating sealant is formed. The solder layer can be formed on the metal wall before or after the photoresist layer (the second photoresist layer 128) defining the metal wall is removed. For example, the photoresist layer used to define the metal walls is deposited and reflowed to help confine the solder layer to remain intact between the metal walls. The winding system can be a different conductive metal comprising copper, gold, nickel, silver, palladium, titanium, a combination of the above metals, and an alloy of the above metals. The preferred combination of the windings will depend on the nature of the connection as a matter of design and reliability. Moreover, as can be seen from the above, the copper material is a typical copper alloy, and most of the components are copper but not pure copper, such as copper beryllium alloy (99.9% copper), copper-silver-phosphorus-magnesium 107 1292195 (copper- Silver-phosphorus-magnesium) (99.7% copper) or copper _ titanium-iron-phosphorus (99.7 〇 / 〇 copper) 5 Hai winding can be input (fan-in) such as output (fan_out) -kind. The winding is formed on a metal substrate by a variety of deposition techniques, including electroplating and electroless plating. Alternatively, the winding can be deposited on a metal substrate, which may be a single layer or multiple layers. For example, the winding system can be a gold layer of 1 μm thick, or a nickel layer of _ 9.5 μm thick can be plated in a 0.5 μm thick gold layer and mined on a copper substrate to reduce the cost. Or a 9-micron-thick nickel layer is plated on a 5 μm gold layer and then plated on a 5 μm titanium layer and plated on a copper substrate to reduce cost and avoid etching of the copper plating layer. Gold and copper alloys that are difficult to remove. In another example, the winding system can be formed by plating a non-copper layer (n〇n-Copper iayer) on a copper substrate and a copper layer on the non-copper layer. Suitable non-copper layers include nickel, gold, palladium, and silver. When the wire is formed, the copper is applied to the non-copper layer for wet chemical etching to etch the copper substrate and expose the wire, but the copper layer and the non-copper layer are not removed. The non-copper layer provides an etch st etch to prevent the wet chemical etch from removing the copper plated layer. In the above description, the winding and the metal substrate are different metals (or metal materials), although the winding system having a plurality of layers includes a single layer which is similar to the metal substrate or a single layer of a multilayer metal substrate ( Single layer 〇f江 multi-layer metal base) 〇 This winding system can be formed by engraving a metal layer attached to a metal substrate 108 1292195. For example, a photoresist layer can be formed on the metal layer, and the photoresist layer is etched by the photoresist layer, and then the photoresist layer is peeled off; or a photoresist layer is formed. On the metal layer, an electroplated metal can be selectively immersed in the metal layer and coated with a photoresist layer, and then the photoresist layer can be peeled off, and the metal layer can be etched and The electroplated metal is used as an etch mask, in which the winding system can be formed comprising an unetched portion of the metal layer and an electroplated metal. The winding is formed by a metal layer to which the plated metal can adhere regardless of whether the plated metal is an etch mask. The wire can be spot plated (Sp〇t plated) near the conductive pin and the connection portion can be phased out. In the case of h, the winding system can be plated with the recording point, and then the silver is made compatible with the joint of a metal gold ball to avoid a mixture of brittle silver and copper. The metal wall can be electroplated to make it compatible with the soldered end. For example, a metal wall of nickel can be plated with gold to promote reflow of tin. The metal column can have a variety of shapes and sizes. For example, the upper plane and the lower plane (relative to the first plane 172 and the second plane 174 of the metal post of the first embodiment) may be circular, rectangular or square. Additionally, the diameter of the plane above the metal post is less than, equal to, or greater than the diameter of the lower plane of the metal post. If the lower plane of the metal post and the larger circular portion of the winding are over the upper plane of the metal crucible and covered, the diameter is at least 109 1292195 100 micrometers smaller than the outer boundary of the metal crucible and makes it easy Form a high density circuit. The details of the bismuth metal column are the formation of the metal substrate and the connection to the winding. U.S. Patent Application Serial No. 10/714,794, issued on December 17, 2003, by Chuen R.ng Leu et al. "Semiconductor chip package structure with embedded metal posts", U.S. Patent Application Serial No. 10/994,604, filed on December 2, 2004 by Charles W. CLin et al., entitled "Blocked Metal Columns" "Semiconductor chip package structure" and the US special (10) were issued by Chades^=^ on the 22nd of the month, and the patent name was "Semiconductor chip package structure with carved block contact end", so the metal column was revealed. The details are known from this reference. ,

The underside of the soldered end cannot be covered by the encapsulant, insulating substrate or other insulating material of the semiconductor chip package structure. For example, the cough can be exposed under the soldering end, or the underside of the soldering end can be covered by the insulating material outside the semiconductor chip package structure, such as a plurality of semiconductor layers. In each semiconductor wafer package structure, the underside of the solder bump is not covered by the male, sealant, insulating substrate or other insulating material of the semiconductor wafer package structure. The source or ground plane function is based on the 5th conductive trace capability of the signal 'electricity, ', and 5 semiconductor wafer pins. / the semiconductor wafer system can be perpendicular to the main plane, the semiconductor wafer system is included in the upward direction of the conductive pin and away from the winding, or ^ 110 1292195 朝心曰 &amp; flipped 'the main plane is tied to the The lower direction and the second direction H are, for example, the semiconductor wafer system can be bonded to the main plane located in the upward direction by wire bonding, or the semiconductor wafer can be bonded to the main plane standing in the downward direction by flip chip bonding. Moreover, the semiconductor wafer can be electrically connected to the winding by a variety of different connections and the semiconductor wafer is upright or flipped. For example, the connection between the semiconductor wafer and a tin or a gold connection is overlapped by B. For example, a fresh tin bump can be formed on the conductive pin. The semiconductor wafer can be flipped or configured by a pick-up head. The head is attached to the conductive bump. The oven between the pin and the winding 'heats the convection oven so that the solder bumps to the tin connection portion' the tin connection portion and the conductive pin are bonded to the winding. Other examples, such as a gold bump, can be formed on the conductive pin, the wire is formed with a gold layer that can be flipped or configured by a couching head, the picking head being the The gold bump is sandwiched between the conductive pin and the winding, and can apply thermal energy and pressure and is transmitted through the semiconductor wafer to the gold bump, and the combination of heat, pressure and ultrasonic can form a gold-to-gold A connection (g〇ld g〇id interconnect, GGI) is interposed between the gold bump and the gold layer of the winding, so that a gold connection portion is bonded to the conductive pin and the wire. The power-off pin has several shapes, and its shape includes a flat rectangular convex shape. The conductive pin is compatible with the connection. Several adhesives can connect the semiconductor wafer to the winding. For example, 111 1292195 The adhesive, such as paste, interlayer or liquid, is applied to screen-printing, spin-on or spray-on. The adhesive is applied as a single layer to a metal substrate or a solder mask, and is in contact with the semiconductor wafer, or a single layer is applied to the semiconductor wafer and is in contact with the metal substrate or the solder mask. Similarly, the adhesive is a composite layer having a first layer for use with a metal substrate or a solder mask, a second layer for the semiconductor wafer, and then the first layer and the second layer are in contact with each other. The thermosetting adhesive forms a liquid and a paste, such as a resin. Similarly, thermoplastic adhesives such as an insulating thermoplastic polyimide film having a 4 degree glass transition temperature are suitable. A gelatinous adhesive system is also suitable. The sealant is formed using a variety of different techniques, including techniques for printing and transfer molding. For example, the encapsulant, such as a resin, can be printed on a semiconductor wafer and then cured to form a solid adhesive protective layer. The sealant can be of the type of the above adhesive. Further, the sealant φ is not in contact with the δ ray semiconductor wafer. For example, a glue coating can be placed on the semiconductor wafer after the semiconductor wafer is attached to the winding, and then the sealant can be formed on the sealant. The insulating substrate may be rigid or elastic, and can form several organic or inorganic insulators such as a tape, a polyamide, a resin, a silicone rubber from various insulating films or glass fibers. , glass, aromatic aramid and ceramic. The organic insulating system has low cost and high insulation, however, the inorganic insulator is important in the high thermal power consumption of 112 1292195 and a considerable coefficient of thermal expansion. For example, the insulating substrate is initially an epoxy resin comprising an epoxy resin, a hardener, an accelerator, and a filler which are simultaneously hardened to form a solid adhesive insulating layer. The filler can be an inert material such as silica (powder-dissolved quartz) which improves thermal conductivity, thermal shock resistance and thermal expansion coefficient. The organic reinforcing fiber system may be used in resins such as epoxy resins, cyanate resins, polyamidones, Teflon, and combinations thereof. The fibers include aromatic polyamines, polyesters, p〇ly-ether "ether-ketone", poly-anisamines, thermoformable polyetherimides, and polysulfones. The reinforcing fiber system may be a woven fabric, a woven glass, a random microfiber glass, a woven quartz, a woven, an aramid, or a non-woven fabric ( Non-woven fabric, non-woven aramid fiber or paper. Commercially available insulating materials such as SPEEDBOARD C prepreg manufactured by WL Gore &amp; Associates of Eau Claire The insulating substrate can be formed in several ways, including printing and transfer forming, and the insulating substrate can be before the semiconductor wafer is connected to the winding or after the semiconductor wafer is connected to the winding. The insulating substrate is removed by a variety of different techniques. The technology includes grinding (including mechanical grinding and chemical mechanical grinding 113 1292195 grinding), blanket-type lightning Ablation and blanket plasma etching. Similarly, the insulating substrate is selectively removed from the metal wall, the metal post and the solder layer using various techniques, wherein the technology includes selective lightning Ejection melting, selective plasma etching, and photo etching. The insulating substrate can be aligned with the metal wall along its downward plane, and extends downward from the winding and the metal pillar, and the insulating substrate is polished but not ground. The soldering layer, the metal post or the winding, and then grinding the Lu insulating substrate and the metal wall without grinding the metal post or winding, and then stopping the grinding after reaching the metal post and the winding system. The insulating substrate is transverse to the soldering layer Arranged in a downward plane, the insulating substrate extends downward from the winding and the metal pillar, and the insulating substrate is polished but the soldering layer, the metal pillar or the winding is not polished, and then the insulating substrate and the soldering plate are polished but The metal post or winding is not ground, and then the grinding is stopped before reaching the metal post or winding. Similarly, the insulating substrate can be aligned with the metal wall and the #层层, facing the lower plane, and The winding and the gold-like pillars extend downward, and the insulating substrate is polished but the metal wall, the soldering layer, the metal pillar or the winding, the wire is not ground, and then the insulating substrate, the metal wall and the soldering layer are polished but the metal is not ground. Column or winding, followed by stopping the grinding before reaching the metal column or winding. The connection can be made of various materials, including copper, gold, nickel, palladium, titanium, alloys and combinations thereof. And formed by various processes, including electroplating, electroless ore, ball bonding, wire bonding, studumping, tin reflow 114 1292195 welding, conductive adhesive hardening and welding, the connection can be Available in a variety of shapes and sizes. Depending on the design and reliability considerations, the shape and composition of the connection is based on the composition of the winding. The details of the connection between the ear and the ear are made by Charles WC Lin on May 24, 2002, and the patent name is "the contact end with the simultaneous formation of electric ore and The semiconductor chip package structure of the connection portion has been disclosed. And the details of the electroless plating connection are proposed by Charles Wc Lin on May 24, 2002. The patent name is "the contact end formed by simultaneous electroless plating and A semiconductor chip package structure of a connection portion has been disclosed. The joint formed by ball bonding is disclosed in U.S. Patent Application Serial No. 09/864,773, on May 24, 2001.

Charles W. C. Lin proposed that the patent name "semiconductor wafer with a joint formed by a ball" was revealed. The connection formed by the bright tin or the conductive adhesive is proposed by Charles Wc in the US Patent Application No. 9/927,216 on 2 (10) 1 August ίο, and is a "semiconductor wafer with a hardened joint" Was revealed. The spliced connection is proposed by Cheng-Lien Chiang et al. on November 23, 2002, and the f patent name is the method of using the plasma money to connect the conductive traces to the semiconductor wafer. Was revealed. ▲ After the connection portion is formed, the connection portion is not connected to the conductive trace if the electrowinning bus bar is present. The electric current manifold is borrowed from the 1292195 pile machine: ί: knife cutting, laser cutting, chemical etching and merging are not connected. 2. The plating bus is placed on the semiconductor chip package 2 = integrated into the a semiconductor chip package structure, and then the busbar package structure is separated from other semiconductor chip package structures, and the bus bar system is not connected. However, if the electrode bank sink 2 has been: to the semiconductor chip package structure, or Is independently ί ί Ίί (10). Can- kiss step system, can selectively: force two = semiconductor chip package structure circuit cutting, and the semi-conductive chip package structure is equipped with an electric mine to shorten the conductive trace When the wire is used, the other metal plate is not connected to the coffee bus. By shutting down the tin material or __ by (4) being placed on the soldering layer, who is required to 耔T a W4

Mm# ^ a hierarchical structure. The next step is to install a semiconductor wafer package containing tin material, such as: in a planar grid array, and the material is supplied by the panel &amp; The contact end of the wafer material structure. Various cleaning methods such as a short electric polyoxygen cleaning method, or a short wet chemical cleaning using a (four) potassium solution is applied to a variety of different processes in the gentleman's place, the main part, in the formation of the joint The predecessor immediately cleans the conductive trace and the conductive pin. According to the specification of the present invention, in the encapsulant, the semiconductor wafers of the electric power are connected by electric power, and the conductive path of the electric power of the (2) path connection terminal includes the winding 116. 1292195 and metal wall means that the winding and metal wall connection are embedded in the electrically conductive conductive path between the soldering end of the encapsulant and any semiconductor wafer. Whether a single wafer is embedded in the encapsulant (the semiconductor wafer is embedded in the encapsulant by a power conductive path and a connection between the solder ends, the electrically conductive path includes winding And a metal wall) or a multi-wafer is embedded in the encapsulant. A semiconductor wafer is embedded in the encapsulant. The electric path is electrically connected to the soldering end by an electrical path of the electric power. Whether the system includes winding and metal walls). Regardless of whether the power path includes or requires - the connection and/or the electrical ore junction between the f, ~ line and the semiconductor wafer. Whether or not the electrically conductive path includes or requires a metal post between the winding and the metal wall. Regardless of the conductive path of the power system, it contains or needs to be a passive component such as a capacitor. Also, regardless of whether or not the multi-chip system is electrically connected to the bobbin by a number: the solid connection portion, the plurality of connection windings are electrically connected to each other. Regardless of whether the multi-chip system is a different electrically conductive path and has a power=connection (as in the case of the plurality of connections described above), as long as each power ν electrical path includes the winding and the metal wall . It is known from the description of the invention of the second invention that the metal pillar is formed by the wet mU but does not form the metal pillar once. For example, the second wet chemical system is formed to form the recess and can form the metal post, the surface, and the second wet chemical etching system can form the metal pillar 117 1292195 iS:: and its tapered surface. In this example, the second Tan-type silver engraving system completely formed the metal pillar. Lt of the surface: Ming: It can be seen in the specification that the metal column is a cone-shaped surface, and the surface of the cone is adjacent to and extends over the metal column. • f is changed _, and the inter-sub-direction is inclined internally, even if the internal slope It can be: the surface of the cone can be tilted to the inside, even if - part =: tilted to the outside, only the metal column

= 7 The diameter of the square plane and the surface of the cone are inclined almost inward. The plane above the metal column is inclined to the lower plane. The instructions for the sound connection indicate that the fresh joint includes the welding

The gold μ contact of ^ = 1 regardless of the fresh end of the package 2 and other fresh tin material, or the zinc joint consists of the fresh joint. It is not the case that the welded end extends inside the hole and expands externally or is placed in the hole. Regardless of whether the weld layer is in contact with the metal wall outside the hole. Regardless of whether the solder layer is in contact with the metal wall. It can be understood in the specification of the present invention that the soldering end includes the soldering layer, even if the material layer may be changed. For example, the shape of the solder layer may be chemically formed (4) to form a metal pillar, and to form an insulating substrate. When the exposed portion of the solder layer is polished and the solder reflows to form the soldered end, it is changed. _ ground, material (10) (4) welding end may change the shape and combination of the welding layer, and may be mixed with the solder ball and the welding layer, so that they are no longer clearly definable. In each embodiment the weld end includes the weld layer. 118 1292195 The "upward" and "downward" vertical directions are not determined by the orientation of the semiconductor wafer package structure' and will be expressly expressed herein. For example, the encapsulant extends from the winding, extending vertically in an upward direction, the gold wall extends from the semiconductor wafer, and extends vertically downwardly, and the insulating substrate passes from the encapsulant. The downward direction extends vertically, regardless of whether the semiconductor wafer structure is difficult or covered on the printed circuit board. Similarly, the winding extends from the metal (four) to the ground, regardless of whether the semiconductor package structure is inverted Mounting, rotating, or splitting. Therefore, the up, and, and down, directions are relative and orthogonal in a lateral direction, the "horizontal arrangement" of the surface is only in the same lateral plane or upward And the downward direction. The semiconductor wafer is drawn on the winding, the metal wall, the metal pillar, the soldering end and the insulating substrate: and the sealing agent is drawn on the semiconductor wafer, the winding, the metal wall, the metal pillar, the soldering end and the insulating substrate The top has a single position on the map for comparison between the figure and the figure, although the semiconductor chip package structure and its components may be flipped in various different manufacturing processes. The semiconductor chip package structure can be operated in a single wafer configuration or a multi wafer structure based on the manufacturing design. For example, the single wafer package comprises a single wafer that can be fabricated independently. Or a plurality of conductor wafers can be simultaneously fabricated on a metal substrate having a single solder mask, a sealant, and a slab edge substrate, and then isolated from each other, such as a notch system in a multi-slice assembly. Simultaneously forming the metal substrate, 119 1292195 and then the metal wall can be simultaneously plated on the recess of the metal substrate, and then the separation solder paste can be simultaneously placed in the corresponding metal wall by using a single template system. The solder paste can then be simultaneously reflowed to form a solder layer' and the winding system can be simultaneously plated on the metal substrate, and then the

The electroplated contacts can be simultaneously plated on the matching windings, and the adhesives of the separately separated semiconductor chip package structures can be simultaneously placed on the solder masks, and the semiconductor wafers can be simultaneously placed in conformity On the adhesive, the adhesive can be simultaneously hardened, and then the joint can be formed on the corresponding plating contacts and the conductive pins, and then the sealant can be formed, and the gold substrate can be formed. The metal pillar is etched and simultaneously formed, and then the insulating substrate is formed, and the insulating substrate metal wall and the soldering layer can be simultaneously ground, and then the space in which the solder paste is separated can be simultaneously placed in the matching soldering layer. The solder layer and the solder ball layer can be reflowed to form a soldering end, and the solder mask, the (4) agent, and the insulating substrate are cut, and are thus divided into semiconductor wafer package structures having independent single-wafer substrates. , Yu Jin: The lithography package structure can have different configurations. When I Tianyi is installed, for example, the conductive trace system can be formed because of the semiconductor wafer sealing dream ~ ball format The array and column format arrays are as flat as the columns. J 千 袼 袼 array or pin format array The semiconductor chip package structure structure can be a single γ a structure, which is consistently applied to the fourteenth embodiment 120 1292195 夕 曰 构 构 ( ( Five embodiments). Moreover, the multi-wafer layer, the human package can comprise semiconductor wafers stacked and vertically aligned, or semi-conductive, laterally aligned. The white sheets are the same-plane and are reliable with each other. The manufacturing method of the semiconductor chip package structure is provided with the half; the sealant and the insulating substrate can protect the crucible; the process is damaged, and the line is provided. The shield of the source is sealed by the moon-to-shoulder* electric knife and the semiconductor chip package structure is not = the music and the unnecessary tin material are reflowed in the lower-level structure. This (4) agent can provide the conductive material - mechanical support ^ = into, when removed, 1 metal wall can be limited; = 曰 4 in the order of the tin reflow operation. In addition, the soldering end can extend-extension to the metal wall of the insulating pure, without the high-voltage boundary contact of the lateral plane,

= Money good reliability. The joining method can be changed from mechanical J# to "golden type", ensuring that the metallurgical joint has a sufficiently strong trace to mechanically and metallurgically on the semiconductor sheet without using wire bonding, automatic tape winding. Bonding tin or conductive adhesive, although the process is adjustable, the required technology can be adjusted. The process is versatile and permits a variety of different bonding techniques to be applied to the individual and (four) cover And the metal column is particularly suitable for the position of the lower layer due to the temperature of 121 1292195 degrees = symmetry, the force of the lower layer and the material yield and the reliability of the lower layer combination. The ball format structure of the present invention can improve the throughput, performance and the like compared with the conventional package technology. Moreover, the semiconductor chip package structure of the present invention can be compatible with copper metal. The present invention is only an embodiment of the present invention, and the scope of the present invention is limited by the following: 9. The simpleness of the application according to the present invention is as follows. The effect change and the decoration should still fall within the scope of the present invention. 1292195 [Simplified Schematic] FIG. 1A is a schematic cross-sectional view showing the structure of the semiconductor wafer of the present invention. FIG. 1B is a plan view of the semiconductor wafer structure of the present invention. 1C is a schematic cross-sectional view of a semiconductor wafer structure of the present invention. FIG. 2A is a schematic cross-sectional view showing a metal substrate structure of the present invention. FIG. 2B is a schematic plan view of a metal substrate structure of the present invention. FIG. 2C is a view of the present invention. FIG. 3A is a schematic plan view showing the structure of the photoresist layer and the metal substrate of the present invention. FIG. 3C is a top view of the structure of the photoresist layer and the metal substrate of the present invention. 4A is a schematic cross-sectional view of a metal substrate having a notch according to the present invention. FIG. 4B is a plan view of a metal substrate having a notch according to the present invention. Figure 4C is a bottom view of the metal substrate structure of the present invention having a notch. Figure 5A is a metal wall of the present invention formed on a metal base. Figure 5B is a top view of the metal substrate of the present invention formed on the metal substrate structure. 123 1292195 Figure 5C is a bottom view of the metal wall of the present invention formed on the metal substrate structure. Figure 6A is a view of the present invention FIG. 6B is a top plan view showing a structure in which the template of the present invention covers the second photoresist layer. FIG. 6C is a plan view of the present invention covering the second photoresist layer. FIG. 7A is a schematic cross-sectional view showing a structure in which a solder paste of the present invention is deposited on a metal wall. FIG. 7B is a top plan view showing a structure in which a solder paste of the present invention is deposited on a metal wall. FIG. 7C is a view of the present invention. A schematic view of the structure in which the solder paste is deposited on the metal wall. FIG. 8A is a schematic cross-sectional view of the structure of the present invention after the template is removed. Fig. 8B is a top plan view showing the structure of the present invention after the template is removed. Fig. 8C is a bottom view showing the structure of the present invention after the template is removed. Fig. 9A is a schematic cross-sectional view showing the structure of the solder paste of the present invention after forming a solder layer. Fig. 9B is a plan view showing the structure of the solder paste of the present invention after forming a solder layer. Fig. 9C is a bottom view showing the structure of the solder paste of the present invention after forming a solder layer. Figure 10A is a cross-sectional view showing the structure of the first photoresist layer and the second photoresist layer of the present invention after peeling off 124 1292195. Fig. 10B is a top plan view showing the structure of the first photoresist layer and the second photoresist layer of the present invention after peeling off. Fig. 10C is a bottom view showing the structure of the first photoresist layer and the second photoresist layer of the present invention after peeling off. Figure 11A is a cross-sectional view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention formed on the metal substrate. Fig. 11B is a top plan view showing the structure in which the third photoresist layer and the fourth photoresist layer of the present invention are formed on the metal substrate. Figure 11C is a bottom plan view showing the structure in which the third photoresist layer and the fourth photoresist layer of the present invention are formed on a metal substrate. Fig. 12A is a schematic cross-sectional view showing the winding of the present invention attached to a metal substrate. Fig. 12B is a view showing a structure in which the winding of the present invention is attached to a metal substrate. I Fig. 12C is a schematic elevational view showing the structure of the winding of the present invention attached to a metal substrate. Figure 13A is a cross-sectional view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention after peeling off. Fig. 13B is a top plan view showing the structure after the third photoresist layer and the fourth photoresist layer of the present invention are peeled off. Fig. 13C is a bottom view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention after peeling off. Fig. 14A is a schematic cross-sectional view showing the structure of the welding mask of the present invention on the metal substrate and the winding 125 1292195. Fig. 14B is a top plan view showing the structure of the welding mask of the present invention on a metal substrate and a winding. Fig. 14C is a bottom plan view showing the structure of the welding mask of the present invention on a metal substrate and winding. Fig. 15A is a schematic cross-sectional view showing the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 15B is a top plan view showing the structure after forming the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 15C is a bottom plan view showing the structure after forming the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 16A is a schematic cross-sectional view showing the structure of the electroplated joint of the present invention formed after winding. Fig. 16B is a top plan view showing the structure in which the plating contact of the present invention is formed after winding. Fig. 16C is a bottom view showing the structure in which the electroplated contacts of the present invention are formed after winding. Figure 17A is a cross-sectional view showing the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention after peeling off. Figure 17B is a top plan view showing the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are peeled off. Fig. 17C is a bottom view showing the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are peeled off. Fig. 18A is a schematic cross-sectional view showing the structure of the adhesive of the present invention formed after the solder mask 126 1292195. Fig. 18B is a schematic plan view showing the structure of the adhesive of the present invention formed after the solder mask. Fig. 18C is a bottom plan view showing the structure of the adhesive of the present invention formed after the solder mask. Figure 19A is a schematic cross-sectional view showing the structure of a semiconductor wafer of the present invention. Figure 19B is a top plan view showing the structure of the semiconductor wafer of the present invention. Figure 19C is a bottom plan view showing the structure of a semiconductor wafer of the present invention. Fig. 20A is a schematic cross-sectional view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact. Fig. 20B is a top plan view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact. Fig. 20C is a bottom plan view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact. Figure 21A is a schematic cross-sectional view showing the structure of the sealing layer of the present invention. Figure 21B is a top plan view showing the structure of the sealing layer of the present invention. Figure 21C is a bottom plan view showing the structure of the sealing layer of the present invention. Fig. 22A is a schematic cross-sectional view showing the structure of the metal post of the present invention formed on a metal substrate. Fig. 22B is a top plan view showing the structure of the metal post of the present invention formed on a metal substrate. Fig. 22C is a bottom plan view showing the structure of the metal post of the present invention formed on a metal substrate. Fig. 23A is a structural cross-sectional view showing the formation of the insulating encapsulant of the present invention 127 1292195. Fig. 23B is a plan view showing the structure after the formation of the insulating sealant of the present invention. Fig. 23C is a schematic view showing the structure after the formation of the insulating sealant of the present invention. Figure 24A is a schematic cross-sectional view of the insulating encapsulant of the present invention after removal. Fig. 24B is a plan view showing the structure of the insulating encapsulant of the present invention after removal. Fig. 24C is a schematic view showing the structure after the insulating encapsulant of the present invention is removed. Fig. 25A is a schematic cross-sectional view showing the structure of the solder ball of the present invention. Figure 25B is a top plan view showing the structure of the solder ball of the present invention. Fig. 25C is a bottom view showing the structure of the solder ball of the present invention. Figure 26A is a schematic cross-sectional view showing the structure of the welded end of the present invention. Figure 26B is a top plan view showing the structure of the welded end of the present invention. Figure 26C is a bottom view of the structure after the formation of the welded end of the present invention. Fig. 27A is a schematic cross-sectional view showing the structure of a semiconductor wafer package structure of the present invention. Fig. 27B is a plan view showing the structure of the semiconductor wafer package structure of the present invention. Fig. 27C is a view showing the structure of the semiconductor wafer package structure of the present invention. Figure 28A is a schematic cross-sectional view showing the structure of a semiconductor wafer of the present invention. 1292195 Figure 28B is a top plan view of the semiconductor wafer structure of the present invention. Figure 28C is a bottom plan view of the semiconductor wafer structure of the present invention. Figure 29A is a schematic cross-sectional view showing the structure of the metal substrate of the present invention. Figure 29B is a top plan view showing the structure of the metal substrate of the present invention. Figure 29C is a bottom plan view showing the structure of the metal substrate of the present invention. Fig. 30A is a cross-sectional view showing the structure of the photoresist layer and the metal substrate of the present invention. Fig. 30B is a plan view showing the structure of the photoresist layer and the metal substrate of the present invention. Fig. 30C is a schematic view showing the structure of the photoresist layer and the metal substrate of the present invention. Figure 31A is a cross-sectional view showing the structure of a notched metal substrate of the present invention. Fig. 31B is a plan view showing the structure of the notched metal substrate of the present invention. $31C is a schematic view of a notched metal substrate structure of the present invention. Figure 32A is a schematic cross-sectional view showing the structure of a metal substrate having a metal wall according to the present invention. Figure 32B is a top plan view showing the metal substrate structure of the present invention. Figure 32C is a bottom plan view showing the metal substrate structure of the present invention. Figure 33A is a cross-sectional view showing the structure of the first photoresist layer and the second photoresist layer of the present invention after peeling off 129 1292195. Figure 33B is a top plan view showing the structure of the first photoresist layer and the second photoresist layer of the present invention after peeling off. Figure 33C is a bottom view showing the structure of the first photoresist layer and the second photoresist layer of the present invention after peeling off. Figure 34A is a cross-sectional view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention formed on the metal substrate. Figure 34B is a top plan view showing the structure in which the third photoresist layer and the fourth photoresist layer of the present invention are formed on the metal substrate. Figure 34C is a bottom plan view showing the structure in which the third photoresist layer and the fourth photoresist layer of the present invention are formed on a metal substrate. Fig. 35A is a schematic cross-sectional view showing the winding of the present invention attached to a metal substrate. Fig. 35B is a view showing a structure in which the winding of the present invention is attached to a metal substrate. ^ Figure 35C is a schematic elevational view showing the structure of the winding of the present invention attached to a metal substrate. Figure 36A is a cross-sectional view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention after peeling off. Figure 36B is a top plan view showing the structure after the third photoresist layer and the fourth photoresist layer of the present invention are peeled off. Figure 36C is a bottom view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention after peeling off. Figure 37A is a cross-sectional view showing the structure of the welding mask of the present invention on a metal substrate and winding 130 1292195. Figure 37B is a top plan view showing the structure of the welding mask of the present invention on a metal substrate and winding. Figure 37C is a bottom plan view showing the structure of the welding mask of the present invention on a metal substrate and winding. Fig. 38A is a schematic cross-sectional view showing the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 38B is a top plan view showing the structure after forming the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 38C is a bottom plan view showing the structure after forming the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 39A is a schematic cross-sectional view showing the structure of the electroplated joint of the present invention formed after winding. Fig. 39B is a top plan view showing the structure in which the electroplated contacts of the present invention are formed after winding. Fig. 39C is a bottom view showing the structure in which the electroplated contacts of the present invention are formed after winding. Fig. 40A is a cross-sectional view showing the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention after peeling off. Fig. 40B is a top plan view showing the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are peeled off. Fig. 40C is a view showing the structure after peeling off the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 41A is a view showing the formation of the adhesive of the present invention after welding the mask 131 1292195. Fig. 41B is a top plan view showing the structure of the adhesive of the present invention formed after the solder mask. Fig. 41C is a view showing the structure of the adhesive of the present invention formed after the welding mask is viewed. Figure 42A is a schematic cross-sectional view showing the structure of a semiconductor wafer of the present invention. Figure 42B is a top plan view showing the structure of the semiconductor wafer of the present invention. Figure 42C is a bottom plan view showing the structure of a semiconductor wafer of the present invention. Figure 43A is a cross-sectional view showing the structure of the connecting portion of the present invention attached to a conductive pin and a plated joint. Fig. 43B is a top plan view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact. Fig. 43C is a bottom plan view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact. Figure 44A is a schematic cross-sectional view showing the structure of the sealing layer of the present invention. Figure 44B is a top plan view showing the structure of the sealing layer of the present invention. Figure 44C is a bottom plan view showing the structure of the sealing layer of the present invention. Fig. 45A is a schematic cross-sectional view showing the structure of the present invention overlying the metal substrate. Fig. 45B is a schematic plan view showing the structure of the template of the present invention overlying the metal substrate. Fig. 45C is a schematic elevational view showing the structure of the template of the present invention overlying the metal substrate. Figure 46A is a schematic view of a structural section of the present invention deposited on a metal wall 132 1292195. Fig. 46B is a plan view showing the structure in which the solder paste of the present invention is deposited on a metal wall. Fig. 46C is a view showing the structure in which the solder paste of the present invention is deposited on a metal wall. Figure 47A is a schematic cross-sectional view showing the structure of the present invention after removal of the template. Figure 47B is a top plan view showing the structure of the present invention after the template is removed. Fig. 47C is a bottom view showing the structure of the present invention after the template is removed. Fig. 48A is a schematic cross-sectional view showing the structure of the solder paste of the present invention after forming a solder layer. Fig. 48B is a plan view showing the structure of the solder paste of the present invention after forming a solder layer. Fig. 48C is a bottom view showing the structure of the solder paste of the present invention after forming a solder layer. Fig. 49A is a schematic cross-sectional view showing the structure of the metal post of the present invention formed on a metal substrate. Fig. 49B is a plan view showing the structure in which the metal post of the present invention is formed on a metal substrate. Figure 49C is a bottom plan view showing the structure of the metal post of the present invention formed on a metal substrate. Fig. 50A is a schematic cross-sectional view showing the formation of the insulating sealant of the present invention. Fig. 50B is a plan view showing the structure after the formation of the insulating sealant of the present invention. 133 1292195 Fig. 50C is a schematic view showing the structure after the formation of the insulating sealant of the present invention. Figure 51A is a schematic cross-sectional view showing a portion of the insulating encapsulant of the present invention after removal. - Figure 51B is a schematic top view of the structure after removal of a portion of the insulating encapsulant of the present invention. Figure 51C is a schematic elevational view of the structure after removal of a portion of the insulating encapsulant of the present invention. Figure 52A is a schematic cross-sectional view showing the structure of the solder ball of the present invention. Figure 52B is a top plan view showing the structure of the solder ball of the present invention. Fig. 52C is a bottom view showing the structure of the solder ball of the present invention. Figure 53A is a schematic cross-sectional view showing the structure of the welded end of the present invention. Figure 53B is a top plan view showing the structure of the welded end of the present invention. Figure 53C is a bottom plan view showing the structure after the formation of the welded end of the present invention. Fig. 54A is a structural cross-sectional view showing a semiconductor chip package structure of the present invention. Fig. 54B is a plan view showing the structure of the semiconductor wafer package structure of the present invention. Fig. 54C is a schematic elevational view showing the structure of the semiconductor chip package structure of the present invention. Figure 5 5 A is a cross-sectional view of the semiconductor wafer structure of the present invention. Figure 55B is a top plan view showing the structure of the semiconductor wafer of the present invention. The fifth 5 C diagram is a schematic view of the semiconductor wafer structure of the present invention. Figure 56A is a schematic cross-sectional view showing the structure of the metal substrate of the present invention. 134 1292195 Figure 56B is a top plan view showing the structure of the metal substrate of the present invention. Figure 56C is a bottom plan view showing the structure of the metal substrate of the present invention. Figure 57A is a cross-sectional view showing the structure of the photoresist layer and the metal substrate of the present invention. Fig. 57B is a plan view showing the structure of the photoresist layer and the metal substrate of the present invention. Fig. 57C is a schematic view showing the structure of the photoresist layer and the metal substrate of the present invention. Fig. 58A is a schematic cross-sectional view showing the winding of the present invention attached to a metal substrate. Fig. 58B is a schematic plan view showing the structure of the winding of the present invention attached to a metal substrate. Fig. 58C is a schematic elevational view showing the structure of the winding of the present invention attached to a metal substrate. Figure 59A is a cross-sectional view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention. Fig. 59B is a top plan view showing the structure after the third photoresist layer and the fourth photoresist layer of the present invention are peeled off. Figure 59C is a bottom view showing the structure of the third photoresist layer and the fourth photoresist layer of the present invention after peeling off. Fig. 60A is a schematic cross-sectional view showing the structure of the welding mask of the present invention on a metal substrate and a winding. Fig. 60B is a top plan view showing the structure of the welding mask of the present invention on the metal substrate and the winding. 135 1292195 Figure 60C is a bottom plan view showing the structure of the welding mask of the present invention on a metal substrate and winding. Fig. 61A is a schematic cross-sectional view showing the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 61B is a top plan view showing the structure after forming the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 61C is a bottom plan view showing the structure after forming the fifth photoresist layer and the sixth photoresist layer of the present invention. Fig. 62A is a schematic cross-sectional view showing the structure of the electroplated joint of the present invention formed after winding. Figure 62B is a top plan view showing the structure in which the electroplated contacts of the present invention are formed after winding. Fig. 62C is a bottom view showing the structure in which the electroplated contacts of the present invention are formed after winding. Figure 63A is a cross-sectional view showing the structure of the fifth photoresist layer and the sixth photoresist layer of the present invention after peeling off. Fig. 63B is a top plan view showing the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are peeled off. Fig. 63C is a bottom view showing the structure after the fifth photoresist layer and the sixth photoresist layer of the present invention are peeled off. Fig. 64A is a schematic cross-sectional view showing that the adhesive of the present invention is formed after the solder mask. Fig. 64B is a top plan view showing the structure of the adhesive of the present invention formed after the solder mask. 136 1292195 Figure 64C is a schematic bottom view of the structure of the adhesive of the present invention formed after the solder mask. Figure 65A is a schematic cross-sectional view showing the structure of a semiconductor wafer of the present invention. Figure 65B is a top plan view showing the structure of the semiconductor wafer of the present invention. Figure 65C is a bottom plan view showing the structure of the semiconductor wafer of the present invention. Fig. 66A is a schematic cross-sectional view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plated contact. Fig. 66B is a top plan view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plating point. Fig. 66C is a bottom plan view showing the structure of the connecting portion of the present invention attached to the conductive pin and the plated joint. Figure 67A is a schematic cross-sectional view showing the structure of the sealing layer of the present invention. Figure 67B is a top plan view showing the structure of the sealing layer of the present invention. Figure 67C is a bottom plan view showing the structure of the sealing layer of the present invention. Figure 68A is a schematic cross-sectional view showing the structure of the second photoresist layer of the present invention formed on a metal substrate. Fig. 68B is a top plan view showing the structure in which the second photoresist layer of the present invention is formed on a metal substrate. Fig. 68C is a bottom plan view showing the structure in which the second photoresist layer of the present invention is formed on a metal substrate. Figure 69A is a schematic cross-sectional view showing the structure of the notch of the present invention. Figure 69B is a top plan view of the recessed structure of the present invention. Figure 69C is a bottom plan view of the notched structure of the present invention. Figure 70A is a schematic cross-sectional view showing the structure of the metal wall of the present invention. 137 1292195 Figure 70B is a top plan view of the structure of the metal wall of the present invention. Figure 70C is a bottom plan view showing the structure of the metal wall of the present invention. Figure 71A is a schematic cross-sectional view showing the structure of the present invention overlying the second photoresist layer. Figure 71B is a top plan view showing the structure of the template of the present invention overlying the second photoresist layer. Figure 71C is a bottom view showing the structure of the template of the present invention overlying the second photoresist layer. _ Figure 72A is a schematic cross-sectional view showing the structure of the solder paste of the present invention deposited on a metal wall. Figure 72B is a top plan view showing the structure in which the solder paste of the present invention is deposited on a metal wall. Figure 72C is a bottom plan view showing the structure in which the solder paste of the present invention is deposited on a metal wall. Figure 73A is a schematic cross-sectional view showing the structure of the present invention after removal of the template. _ 73B is a top plan view of the structure after removing the template of the present invention. Figure 73C is a bottom view of the structure of the present invention after removal of the template. Fig. 74A is a schematic cross-sectional view showing the structure of the solder paste of the present invention after forming a solder layer. Fig. 74B is a plan view showing the structure in which the solder paste of the present invention is formed into a solder layer. Fig. 74C is a bottom view showing the structure of the solder paste of the present invention after forming a solder layer. Figure 75A is a schematic view of a structural cross section of the second photoresist layer of the present invention 138 1292195. Figure 75B is a top plan view showing the structure of the second photoresist layer stripped after the invention. Fig. 75C is a bottom view showing the structure of the second photoresist layer of the present invention. Figure 76A is a schematic cross-sectional view showing the metal substrate of the present invention after removal. Fig. 76B is a plan view showing the structure of the metal substrate of the present invention after removal. Fig. 76C is a schematic view showing the structure after removal of the metal substrate of the present invention. Fig. 77A is a schematic cross-sectional view showing the formation of the insulating sealant of the present invention. Fig. 77B is a plan view showing the structure after the formation of the insulating sealant of the present invention. Fig. 77C is a schematic view showing the structure after the formation of the insulating sealant of the present invention. Figure 78A is a schematic cross-sectional view showing a portion of the insulating encapsulant of the present invention after removal. Figure 78B is a schematic plan view showing the structure of a portion of the insulating encapsulant of the present invention after removal. In the case of Fig. 78C, the structure after the partial insulation seal of the present invention is removed is not intended. Figure 79A is a schematic cross-sectional view showing the structure of the solder ball of the present invention. 139 1292195 Figure 79B is a top plan view showing the structure of the solder ball of the present invention. Figure 79C is a bottom view showing the structure of the solder ball of the present invention. Figure 80A is a schematic cross-sectional view showing the structure of the welded end of the present invention. Figure 80B is a top plan view showing the structure of the welded end of the present invention. Fig. 80C is a bottom view showing the structure after the formation of the welded end of the present invention. Fig. 81A is a schematic cross-sectional view showing the structure of a semiconductor wafer package structure of the present invention. Fig. 81B is a schematic view showing the structure of the semiconductor wafer package structure of the present invention. Fig. 81C is a schematic elevational view showing the structure of the semiconductor wafer package structure of the present invention. Figure 82A is a cross-sectional view showing the structure of a semiconductor wafer package of a fourth embodiment of the present invention. Figure 82B is a top plan view showing a semiconductor chip package structure of a fourth embodiment of the present invention. Figure 82C is a bottom plan view showing a semiconductor wafer package structure of a fourth embodiment of the present invention. Figure 83A is a cross-sectional view showing the structure of a semiconductor wafer package of a fifth embodiment of the present invention. Figure 83B is a top plan view showing a semiconductor chip package structure of a fifth embodiment of the present invention. Figure 83C is a bottom plan view showing a semiconductor wafer package structure of a fifth embodiment of the present invention. Figure 84A is a cross-sectional view showing the structure of a semiconductor wafer package 140 1292195 according to a sixth embodiment of the present invention. Figure 84B is a top plan view showing a semiconductor chip package structure of a sixth embodiment of the present invention. Figure 84C is a bottom plan view showing a semiconductor wafer package structure of a sixth embodiment of the present invention. Figure 85A is a cross-sectional view showing the structure of a semiconductor wafer package of a seventh embodiment of the present invention. Figure 85B is a semiconductor chip package of a seventh embodiment of the present invention. Fig. 85C is a bottom plan view showing the semiconductor chip package structure of the seventh embodiment of the present invention. Figure 86A is a cross-sectional view showing the structure of a semiconductor wafer package of an eighth embodiment of the present invention. Figure 86B is a top plan view showing a semiconductor chip package structure of an eighth embodiment of the present invention. I. Fig. 86C is a bottom plan view showing a semiconductor wafer package structure of an eighth embodiment of the present invention. Figure 87A is a cross-sectional view showing the structure of a semiconductor wafer package of a ninth embodiment of the present invention. Figure 87B is a top plan view showing a semiconductor chip package structure of a ninth embodiment of the present invention. Figure 87C is a bottom plan view showing a semiconductor chip package structure of a ninth embodiment of the present invention. Figure 88A is a cross-sectional view showing the structure of a semiconductor wafer package 141 1292195 of a tenth embodiment of the present invention. Fig. 88B is a top plan view showing the semiconductor wafer sealing structure of the tenth embodiment of the present invention. Figure 88c is a bottom plan view showing a semiconductor wafer package structure of a tenth embodiment of the present invention. Figure 89A is a cross-sectional view showing the semiconductor wafer package structure of the eleventh embodiment of the present invention.

Figure 89B is a top plan view showing a semiconductor wafer package structure of an eleventh embodiment of the present invention. Figure 89C is a bottom plan view showing the semiconductor wafer package structure of the eleventh embodiment of the present invention. Fig. 9A is a schematic cross-sectional view showing a semiconductor wafer package structure of a twelfth embodiment of the present invention. Fig. 90B is a top plan view showing the semiconductor wafer sealing structure of the twelfth embodiment of the present invention.

Fig. 90C is a bottom plan view showing the semiconductor wafer package package structure of the twelfth embodiment of the present invention. Figure 91A is a cross-sectional view showing the semiconductor wafer package structure of the thirteenth embodiment of the present invention. Figure 91B is a top plan view showing a semiconductor wafer package structure of a thirteenth embodiment of the present invention. Figure 91C is a bottom plan view showing the semiconductor wafer sealing structure of the thirteenth embodiment of the present invention. Figure 92A is a cross-sectional view showing the structure of a semiconductor wafer package 142 1292195 according to a fourteenth embodiment of the present invention. Figure 92B is a top plan view showing the semiconductor wafer package structure of the fourteenth embodiment of the present invention. Figure 92C is a bottom plan view showing the semiconductor wafer package structure of the fourteenth embodiment of the present invention. Figure 93A is a cross-sectional view showing the semiconductor wafer package structure of the fifteenth embodiment of the present invention. Figure 93B is a top plan view showing a semiconductor wafer package structure of a fifteenth embodiment of the present invention. Figure 93C is a bottom plan view showing the semiconductor wafer package structure of the fifteenth embodiment of the present invention. Fig. 94 is a view showing the structure of a metal post of a sixteenth embodiment of the present invention. Fig. 95 is a view showing the structure of a metal post of the seventeenth embodiment of the present invention. Fig. 96 is a view showing the structure of a metal post of the eighteenth embodiment of the present invention. Fig. 97 is a view showing the structure of a metal post of the nineteenth embodiment of the present invention. Fig. 98 is a view showing the structure of a metal post of the twentieth embodiment of the present invention. 143 1292195 [Description of main component symbols] semiconductor wafers 110, 210, 310, 410, 510, 610, 710, 810, 910, 1010, 1110, 1210, 1310, 1410 first planes 112, 212, 312, 412, 512, 612 second plane 114, 214, 314, 414, 514, 614 conductive pins 116, 216, 316, 416, 516, 616 protective layer 118, 218, 318 ® metal substrate 120, 220, 320 first main plane 122, 222, 322 second main plane 124, 224, 324 first photoresist layer 126, 226 second photoresist layer 128, 228, 328 notch 130, 230 perforations 330, 565, 665 • metal walls 132, 232, 332, 432, 532, 632, 732, 832, 932, 1032, 1132, 1232, 1332, 1432, 1532 holes 134, 734, 834 openings 136, 883 templates 138, 238, 338 solder paste 140, 240, 340 solder layer 142, 242, 342 third photoresist layer 144, 244, 344 fourth photoresist layer 146, 246, 346 144 1292195 winding 150, 250, 350, 450, 550, 650, 750, 850, 950, 1050, 1150, 1250 , 1350, 1450, 1550 elongated winding portion 152 larger circular portion 154 welding mask 156, 256 , 356, 456, 556, 656, 756, 856, • 956, 1056, 1156, 1256, 1356, 1556 fifth photoresist layer 158, 258, 358 sixth photoresist layer 160, 260, 360 _ plating contact 162 , 262, 362, 762, 862, 1062, 1162, 1262, 1362, 1462, 1562 Adhesives 164, 264, 364, 464, 564, 664, 764, 864, 964, 1064, 1164, 1264, 1364, 1464 166, 266, 366, 466, 566, 666, 766, 866, 966, 1066 ' 1166 , 1266 , 1366 , 1466 sealing layers 168 , 268 , 368 , 468 , 568 , 668 , 768 , 868 , 968 , 1068 , 1168, 1268, 1368, 1468, 1568

I metal column 170, 270, 470, 570, 670, 770 ' 870, 970, 1070, 1170, 1270, 1370, 1470, 1570, 1670, 1770, 1870, 1970, 2070 first plane 172 second plane 174 cone 170 conductive traces 180 insulating sealants 182, 282, 382, 482, 582, 682, 782, 882, 145 1292195 982, 1182, 1282, 1382, 1482, 1582 solder balls 184, 284, 384 solder joints 186, 286, 386, 486, 586, 686, 786, 886, 986, 1086, 1186, 1286, 1386, 1486, 1586 semiconductor chip package structures 198, 298, 398, 498, 598 v698, 798, 898, 998, 1098, 1198, 1298 , 1398 ' 1498 , 1598 insulating plug 569 first semiconductor wafer 1510 second semiconductor wafer 1511 conductive pin 1510 conductive pin 1517 first adhesive 1564 second adhesive 1565 second connecting portion 1560 second connecting portion 1567 146

Claims (1)

1292195 X. Patent application scope: 1. A semiconductor wafer package bonding method for soldering a metal wall, comprising at least: a. providing a metal substrate, a winding, a metal wall and a soldering layer, wherein the metal substrate The first plane and the second plane are included, the first plane of the metal substrate is oriented in a first direction, the second plane of the metal substrate is oriented in a second direction, and the second direction is opposite to the first direction Conversely, the metal wall extends from the second plane of the metal substrate to the first plane into the metal substrate, and the gold &gt; 1 wall comprises a hole, the hole being formed by the second plane of the metal substrate a first plane extending to the metal substrate p and including an opening facing the second direction, the zinc bonding layer being in contact with the metal wall in the hole; b, mechanically connecting the semiconductor wafer to the winding, wherein the semiconductor The chip system includes a conductive pin; C, forming a connecting portion, the connecting portion is electrically connectable to the winding and the conductive pin; the chemical (4) etching the metal substrate, / Winding and between the metal substrate and the metal substrate and the metal walls of the contact region; and E, providing - welding end, the end system and the weld metal within the metal wall contact hole, and comprising the solder layer. 147 1292195 2. The method for manufacturing a soldering metal wall of a soldering end according to the application of the patent semi-conductive (4)/the first item, wherein the winding method deposits the winding on the metal substrate. on. The manufacturing method of the two-piece wafer sealing structure of the welding end metal wall according to the second aspect of the invention, wherein the winding method comprises forming a plating mask on the metal substrate The plated mask includes - opening σ, the opening exposing a portion of the metal substrate; and plating the wire onto the exposed portion of the metal substrate and through the opening of the plating mask. 4. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim i, wherein the metal wall is formed by depositing the metal wall on the metal substrate. 5. The method of fabricating a semiconductor chip package structure for soldering end metal walls according to claim 4, wherein the metal wall is formed by forming a plating mask on the metal substrate. The mineral mask includes an opening that exposes a portion of the metal substrate, and the metal wall is plated to the exposed portion of the metal substrate and through the opening of the plating mask. The method for manufacturing a semiconductor chip package structure according to the first aspect of the invention, wherein the metal wall is formed by silver engraving the metal substrate to form a via hole, the via hole system Extending from the second direction of the metal substrate to the first direction into the metal substrate; and depositing the metal wall in the via 148 1292195. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 6, wherein the via hole is a through hole extending into the metal substrate and penetrating to make the winding The wire is exposed; and the metal wall extends into and penetrates the metal substrate and is in contact with the wire. 8. The method of manufacturing a soldering end metal walled rib+conductor chip package structure according to claim 7, wherein the metal substrate is etched through the metal substrate and the winding and the metal substrate The area of contact with the metal wall is removed. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 6, wherein the via hole is a notch, and the notch extends into the metal substrate but is not worn. And permeable to the first plane and the winding of the metal substrate; and the metal wall extends into the metal substrate but does not penetrate and is isolated from the first plane and the winding of the metal substrate. 10. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 9, wherein the metal substrate is formed by a metal pillar from an unetched portion of the metal substrate. The unetched portion of the metal substrate is defined by the metal wall that is in contact with the winding and the metal wall. 11. The method of fabricating a semiconductor wafer package structure according to the invention of claim 1, wherein the recording layer is formed by depositing the solder layer on the metal wall. 12. The method for manufacturing a semiconductor Ba package structure having a metal wall according to the above-mentioned item, wherein the formation of the fresh layer comprises contacting the solder layer only with the metal wall. 13. The method for manufacturing a body wafer package structure according to the fourth aspect of the present invention, wherein the method of forming the fresh layer is to deposit a solder paste on the metal wall. And returning the solder paste. 14. The method of manufacturing a semiconductor chip package structure having a metal terminal of a fresh terminal according to the patent specification (4) 1J; M, wherein the soldering end is the solder layer. 15. The method of manufacturing a semiconductor wafer package structure for soldering a metal wall according to the invention, wherein the method of forming the solder joint comprises depositing a solder material on the solder layer. And returning the solder material together with the solder layer. 16. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to the above-mentioned claim, wherein the soldering end forming method comprises at least the following steps and in accordance with the order: a. making the solder paste Deposited on the metal wall; b, reflowing the solder paste, thereby forming the soldering end; c, depositing a solder material on the solder layer; and 150 1292195 d. The solder material and the solder layer are reflowed together, thus forming the soldered end. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to the above item, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in accordance with the order: The metal substrate forms a via hole; b, depositing the metal wall on the metal substrate and entering the via hole; and c, depositing the solder layer on the metal wall. The method for manufacturing a semiconductor chip package structure according to the first aspect of the invention, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in the following order: ..., a. etching the metal substrate and passing through an opening of the etch mask, thereby forming a via hole; b, plating the metal wall on the exposed portion of the metal substrate, and entering the opening through a plating mask Inside the via hole; c depositing a solder paste on the metal wall; and d reflowing the solder paste, thereby forming the solder layer. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 1, wherein the method for forming the metal wall and the fresh layer comprises at least the following steps and is in accordance with the sequence of 151 1292195. · a, money engraved on the metal substrate to form a via; b, the metal wall is plated on the exposed portion of the metal substrate, and through a plating mask opening into the via hole; c, make a tin A paste is deposited on the metal wall; and d, the solder paste is reflowed, thereby forming the solder layer. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 1, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in accordance with the sequence. Forming a mask on the metal substrate, wherein the mask includes an opening to expose a portion of the metal substrate; b, leaving the metal substrate and passing through the opening of the mask, thereby forming a via hole; c. plating the metal wall on the exposed portion of the metal substrate, and entering the via hole through the opening of the mask; d, depositing a solder paste on the metal wall; and e, making the solder paste Reflow, thus forming the solder layer. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to the above-mentioned patent application scope, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in accordance with the sequence: , &amp; Forming an etch mask on the metal substrate, wherein the etch 152 1292195 mask includes an opening to expose a portion of the metal substrate; b, etching the metal substrate and passing through the opening of the etch mask, thereby forming a a via hole; c, forming a plating mask on the metal substrate, wherein the plating mask includes an opening to expose a portion of the metal substrate and the via hole; d, plating the metal wall on the metal substrate The exposed portion enters the via hole through the opening of the plating mask; e. depositing a solder paste on the metal wall; and f, reflowing the solder paste, thereby forming the solder layer. 22. The method of fabricating a semiconductor chip package structure having a solder end metal wall according to the scope of the claims, wherein the semiconductor: the die and the % wire are connected in a manner comprising placing an adhesive on the - Between the semiconductor wafer and the metal substrate, the adhesive is then hardened. • The manufacturing method of the 2-piece wafer sealing structure of the welding end metal wall according to the scope of the patent application scope, wherein the connecting portion can include the feeding portion to the winding and the guiding range* The welding end metal wall 3 = the manufacturing method of the two-package structure, wherein the winding and the::::: using the electric-free forging to connect the connection gamma according to the i-th item of the patent scope The soldering end has a metal (4) 153 l292l95 semiconductor wafer package structure manufacturing method, wherein the connecting portion is formed by depositing a non-solid material (n〇ns〇lidified material) on the winding and the conductive leg Between the bits, and harden the non-solid material. 6. According to the scope of patent application! The method of fabricating a semiconductor chip package structure having a solder end metal wall, wherein the connection portion is formed by providing a W bond between the winding and the conductive pin. The manufacturing method of the semiconductor chip package structure of the soldering end metal wall according to the first aspect of the invention, wherein the gold plate system uses the wet chemical money to engrave the residual, so that the winding exposes the soil . :::The welding end of the metal wall according to the first aspect of the patent:: The manufacturing method of the body S-chip package structure, wherein the metal base is engraved with the wet chemical money to remove most of the The manufacturing method of the metal wall of the fresh terminal according to the first item of the rm circumference is: the structure of the structure, wherein the metal substrate is carved into the metal substrate in the edge of the foot by using the wet chemical name. (4)# The method for manufacturing a structure of a metal wall of a soldering end according to the item of the present invention, wherein the metal-based phase chemical is removed from the metal substrate in the edge of the semiconductor wafer of the semiconductor 154 1292195. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 1, wherein the metal substrate is etched by the wet chemical etching to make the metal substrate and the winding and the The method of manufacturing a semiconductor chip package structure for soldering an end metal wall according to the above-mentioned claim, wherein the gold lip substrate is utilized, and the contact area between the metal substrate and the metal wall is reduced. The wet chemical etching is performed to form a metal pillar from a portion of the metal substrate, and an unmarked portion of the metal substrate is defined by the metal wall, the metal pillar is used to make the winding and the metal The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to the above-mentioned patent scope, wherein the metal base plate system is made of the wet chemical a method for manufacturing a +4 body 4 package structure in which the metal substrate and the metal (4) are in contact with each other and the metal substrate and the metal (4) are completely 34.=1. =__式化学(四)Into the pure engraving, and removing the metal soil 3 5 ·The welding end metal wall according to the scope of claim 1 155 1292195 =; manufacturing method of the package structure, wherein the metal base , '&quot; Wet chemical etching to etch, and to electrically connect the other windings of the reel to the metal substrate, and to weld the metal wall of the welding end as described in the first item Method of manufacturing a seismic structure, wherein Metal Base = The wet chemistry is used to engrave the last name so that the conductive pin is electrically isolated from the conductive pins on the semiconductor wafer. 37. A method of fabricating a semiconductor wafer package structure for soldering end metal walls according to the above-mentioned patent application, wherein the metal wall can be formed prior to formation of the solder layer. The method of manufacturing a semiconductor wafer package structure for soldering end metal walls according to claim 37, wherein the metal wall is formed to form the winding. 39. A method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 37, wherein the metal wall is formed to form the winding. 4. A method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 37, wherein the metal wall is formed simultaneously with the winding. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 37, wherein the metal wall is connectable to the metal substrate and the winding front shape 156 1292195 . 42. The method of fabricating a semiconductor chip package structure for soldering end metal walls according to claim 37, wherein the metal wall is formed after connecting the semiconductor wafer to the metal substrate and winding. 43. A method of manufacturing a semiconductor wafer package structure for soldering end metal walls according to claim 37, wherein the solder layer The system can be formed by connecting the semiconductor wafer to the metal substrate and winding. The method of manufacturing a semiconductor chip package structure for soldering a metal wall according to claim 37, wherein the solder layer is formed by connecting the semiconductor wafer to the metal substrate and winding 45. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 37, wherein the solder layer is formed before the solder end is formed. 46. A method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 37, wherein the solder layer directly forms the solder end. The method for manufacturing a semiconductor chip package structure according to the first aspect of the invention, wherein the connection portion is etched by wet chemical etching on the metal substrate to form a front shape 157 1292195. . 48. The method according to claim 1, wherein the bonding portion is formed by etching the metal substrate by wet chemical etching. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 1, wherein the soldering end is formed before the semiconductor wafer is connected to the metal substrate and the winding. ^ According to ΐ 4 patent scope! The method of fabricating a Y-conductor chip package structure having a metal end of a soldering end, wherein the soldering end is formed after connecting the semiconductor wafer to the metal substrate and winding. The method of manufacturing a conductor chip package structure for soldering a metal wall according to the invention of claim 2, wherein the fresh terminal is formed before the connection portion is formed. The method of manufacturing a conductor chip package structure for soldering a metal wall according to claim 1, wherein the soldering end can be formed after the connecting portion is formed. The method for manufacturing a soldering end metal wall according to the first aspect of the invention, wherein the fresh joint* can be subjected to wet chemical (four) on the metal substrate (four) front shape 158 1292195. The manufacturing method of the semiconductor chip package structure with a metal wall according to the invention of claim 1, wherein the soldering end is capable of performing the last name on the metal substrate by using a wet chemical residue. Formed after engraving. 5. The method of fabricating a semiconductor chip package structure for soldering end metal walls according to the above clause, wherein the package further comprises forming the metal wall, and then forming the "layer, and then connecting the semiconductor aa"; J_ the metal substrate, the winding, the metal wall and the recording layer, and the metal substrate is etched by using a wet chemical residue. 56. _ Patent application: a method of manufacturing a chip package structure, further comprising: forming the metal wall ′ and then connecting the semiconductor day and day sheet to the metal substrate, the wire and the metal wall, and then forming the solder layer, and using a wet chemical etching pair The metal substrate is etched. 57. According to the manufacturing method of the semiconductor chip package structure of the soldering end metal wall according to the above-mentioned item, wherein the package 3 is further connected to the metal substrate and the winding a wire, then forming a metal wall' and then forming the solder layer, and etching the metal substrate by wet chemical etching. The manufacturing method of the semiconductor chip package structure of the soldering end metal wall according to Item 1, wherein the further package 159 1292195 includes forming a sealant for covering the semiconductor wafer after connecting the semiconductor wafer to the winding. The method of manufacturing a semiconductor chip package structure for soldering a metal wall according to claim 58 of the invention, wherein the sealant is formed to further form an insulating substrate wall and The splicing layer is in the second direction, and then removing a substrate so that the insulating substrate cannot cover the soldering layer on the second. ～ 半导体 The semiconductor wafer with the metal end of the soldering end according to the scope of the patent application The manufacturing method of the package structure, wherein the semiconductor chip package structure is a first level package. 61. A method for manufacturing a semiconductor chip package structure with a solder end metal wall, at least comprising: a, providing a corresponding a metal substrate of the first plane and the second plane, wherein the first plane of the metal substrate faces the first direction, The second plane of the substrate is oriented toward the second direction, and the second direction is opposite to the first direction; b, forming a winding on the first plane of the metal substrate, wherein the winding is first with the metal substrate Contacting the plane and isolating from the second plane of the metal substrate; c. etching the metal substrate by using the first wet chemical etching, thereby forming a via hole in the metal substrate, the via hole is formed by the metal substrate The second plane extends into the first plane to the 160 1292195 metal substrate; d, forming a metal wall on the metal substrate, so that the metal wall is in contact with the metal substrate in the via hole, Metal wall system: the second plane of the metal substrate extends toward the first plane to the metal. The hole is: the hole extends from the second plane of the metal substrate to the first plane to the metal earth plate and is The metal wall covers the first direction and includes an opening facing the second direction; the 匕3 belongs to the second soldering layer 'the soldering layer is in contact with the metal soil in the hole and is isolated from the winding; Green, 1, = mechanical $ connected to a semiconductor wafer to the metal substrate and winding, the semiconductor chip system includes a conductive pin; g forms a connection portion, the connection portion can be electrically connected to the winding and the conductive pin Connecting; h9 connecting the semiconductor wafer to the metal substrate and the winding and the constitutive wall and the soldering layer, and using the second wet chemical to engrave the substrate, thereby reducing the i-metal β substrate and the metal wall between the metal substrate and the winding a contact area; and a weir, providing a solder end that is in contact with the metal wall in the hole and includes the solder layer. 62. The method according to claim 61, wherein the method of manufacturing the semiconductor chip package structure of the metal strip is as follows: wherein the method of forming the wire can comprise forming an electric ore mask on the metal substrate. 161 1292195, wherein the plating mask includes an opening that exposes a portion of the metal substrate; and the opening is plated through the opening of the plating mask to the exposed portion of the metal substrate. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 61, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in accordance with the order: φ a, wear Opening a metal wall on the metal substrate and entering the via hole; b, depositing a solder paste on the metal wall; and c, reflowing the paste, thereby forming the solder Floor. 64. A method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 61, wherein the soldering end is the solder joint. The manufacturing method of the semiconductor chip package structure of the soldering end metal wall according to claim 61, wherein the soldering end is formed by using the second wet chemical etching to the metal substrate After the etching, a solder material is deposited on the soldering pad and the fresh tin material and the fresh layer are reflowed together to form the soldering end. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 61, wherein the semiconductor chip and the metal substrate and the winding are connected to each other. 1292195 A reagent is placed between the semiconductor wafer and the metal substrate, and then the adhesive is hardened. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 61, wherein the connecting portion I is formed to provide a wire bunding to the winding Between the line and the conductive pin. 68. A method of fabricating a semiconductor wafer package structure according to claim 61, wherein the metal substrate is etched by the second wet chemical etch to expose the wire. 69. The method of fabricating a semiconductor wafer package structure of a soldering end metal wall according to claim 68, wherein the metal substrate is etched by the first wet chemical etching to form the via hole, the conducting The hole is a perforation and extends through the metal substrate to expose the winding; and the metal substrate is etched by the second wet chemical etching to remove the metal substrate and the winding and the metal substrate and the metal wall Contact area between. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 61, wherein the metal substrate is etched by the second wet chemical etching to remove the metal substrate. 71. The method of manufacturing a 316 1292195 semiconductor wafer package structure according to claim 68, wherein the metal plate is etched by the first wet chemical etching to form the via hole. The via hole is a recess and extends the metal substrate but does not penetrate; and the metal substrate is etched by the second wet chemical etching, and a metal pillar is formed from the unetched portion of the metal substrate, and the metal substrate is formed. The ungraved portion is defined by the metal wall that is in contact with the winding and the metal wall and electrically connects the winding to the metal wall. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 71, wherein the metal substrate is etched by the second wet chemical etching to remove most of the Metal substrate. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 71, wherein the metal substrate is etched by the second wet chemical etch and removed from the conductive leg A metal substrate within the edge of the bit. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 71, wherein the metal substrate is etched by the second wet chemical residue and removed from the semiconductor A metal substrate within the edge of the wafer. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 68, wherein the metal substrate is etched by a second wet chemical etching, and the winding 164 1292195 is Other windings in contact with the metal substrate are electrically isolated. 76. The method of manufacturing a semiconductor chip package structure for soldering a metal wall according to claim 68, wherein the metal substrate is subjected to a first wet chemical chemistry to make the conductive pin and the conductive pin Other conductive pins on the semiconductor wafer are electrically isolated. 77. A method of fabricating a semiconductor wafer package structure according to claim 61, wherein the metal wall is formed prior to connecting the semiconductor wafer to the metal substrate and winding. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 61, wherein the metal wall is formed after connecting the semiconductor wafer to the metal substrate and winding. 79. The method of fabricating a semiconductor wafer package structure according to claim 61, wherein the solder layer is formed before connecting the semiconductor wafer to the metal substrate and winding. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 61, wherein the solder layer i can be connected to the metal wafer to the metal substrate and after winding 165 1292195 The method of manufacturing a semiconductor chip package structure for soldering a metal wall according to claim 61, wherein the connection portion is formed before the metal substrate is etched by the second wet chemical etching. The method of manufacturing a semiconductor chip package structure for soldering a metal wall according to claim 61, wherein the connecting portion is formed after the metal substrate is etched by the second wet chemical etching. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 61, further comprising forming a sealant for connecting the semiconductor wafer to the metal substrate and winding The wire is then overlaid on the semiconductor wafer in a first direction. 84. The soldering end according to claim 83 A manufacturing method of a semiconductor chip package structure having a metal wall, wherein the sealant is formed to further form an insulating substrate, the insulating substrate is in contact with the winding, the metal wall and the solder layer, and covers the metal wall and is known The bonding layer is in the second direction, and then removing a portion of the insulating substrate so that the insulating substrate cannot cover the soldering layer in the second direction. 85. The soldering end metal wall according to claim 84 of the patent application scope A method of fabricating a semiconductor chip package structure, wherein the removing of a portion of the insulating substrate exposes the metal wall and the solder layer in a second direction, but does not expose the winding. 166 1292195 86. The method for manufacturing a semiconductor chip package structure of a metal end wall according to claim 85, wherein the insulating substrate is removed by grinding, and the insulating substrate is ground by grinding. 87. According to claim 86 The method for manufacturing a conductor chip package structure with a metal end of a soldering end, wherein the part of the insulating substrate is removed by grinding Grinding the insulating substrate 10, but not grinding the metal wall and the soldering layer, and then grinding the insulating substrate, the metal wall and the soldering layer, and then arranging the insulating substrate, the metal wall and the fused layer laterally in a direction toward the second direction The method of manufacturing the semiconductor wafer package structure of the soldering end metal wall according to claim 87, wherein the solder layer is directly formed into the soldering. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 88, wherein the soldering end is formed on the insulating substrate, the metal wall, and the soldering method. After the end is ground, a solder material is deposited on the solder layer, and then the solder material is reflowed together with the solder layer to form the solder end. According to the method of claim 61, the soldering end has a metal wall, such as a manufacturing method of a solar package structure, wherein the semiconductor chip package structure is a first level package. 167 1292195 91. The method for producing a semiconductor chip package structure for soldering end metal walls comprises at least: ka, providing a first planar and second planar metal substrate, wherein the first planar system of the metal substrate Oriented to the first direction, the second plane of the metal substrate is oriented toward the second direction, the first direction is opposite to the first direction; b, forming a winding on the first plane of the metal substrate, the winding system Contacting the first plane of the metal substrate and isolating from the second plane of the metal substrate; one μ C, using the first wet chemical _ to re-etch the metal substrate 'so forming a via hole on the metal substrate, the The via hole extends from the second plane of the metal substrate to the first plane thereof to the metal substrate; d. a metal wall is formed on the metal substrate, and the metal layer is formed in the crucible and the via hole Contacted by the metal substrate, the second plane of the metal two-t metal substrate extends into the first plane of the metal to the gold plate, and the metal wall comprises a hole, the hole is: the second flat of the metal substrate The surface extends into the first plane to the metal substrate, and is covered by the metal wall in the first direction, and includes an opening facing the second direction; e, forming a layer of the layer and the hole The metal wall is in contact with and separated from the winding; mechanically connecting a semiconductor wafer to the metal substrate and winding, wherein the semiconductor wafer system comprises a conductive pin, 168 I292l95 g, forming a connecting portion, the connecting portion is Electrically connecting with the winding and the conductive pin; forming a sealant after connecting the semiconductor wafer to the metal substrate and winding, wherein the sealant is in contact with the semiconductor wafer and from the semiconductor wafer, metal The substrate and the winding extend perpendicularly to the first direction, and the metal substrate extends perpendicularly from the semiconductor wafer and the winding to the second direction; %1, after forming the metal wall, the solder layer and the sealing agent, The second wet chemical etching etches the metal substrate, thereby reducing the contact area between the metal substrate and the winding and between the metal substrate and the metal wall; j. utilizing the metal substrate After etching by the wet chemical etching, an insulating substrate is formed, the insulating substrate is in contact with the winding, the metal soil and the fresh layer, and covers the winding, the metal wall and the soldering layer in the second direction; Removing a portion of the insulating substrate such that the insulating substrate cannot cover the solder layer in the second direction; and providing a soldering end, the soldering end is in contact with the gold wall in the hole, and includes the soldering Floor. The method of manufacturing a soldering end metal wall=conductor crystal&gt;1 package structure according to claim 91, wherein the method of forming the winding may include forming a plating mask on The metal substrate has an opening, the opening is exposed to a metal substrate of a portion of 169 1292195; and the winding is plated through the opening of the plating mask to the exposed portion of the metal substrate . The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 91, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and following the order: a. a plating mask opening, the metal wall is plated on the metal substrate, and enters the via hole; b, depositing a solder paste on the metal wall; and e, reflowing the solder paste, thereby forming the solder Floor. 94. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 91, wherein the soldering end is the solder joint layer. 95. The method of manufacturing a semiconductor wafer package structure according to claim 91, wherein the soldering end is formed by using the second wet chemical etching to the metal substrate. After etching, a solder material is deposited on the solder bump and the solder material and the bump layer are reflowed together to form the solder joint. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 91, wherein the semiconductor chip is connected to the metal substrate and the winding may comprise an adhesive. The semiconductor wafer is placed between the semiconductor wafer and the metal substrate, and then the 170 1292195 adhesive is hardened. 97. The method of fabricating a semiconductor chip package structure of a soldered end true metal wall according to claim 91, wherein the connecting portion is formed by providing a wire bond to the wire and the conductive wire. Between the feet. 98. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 91, wherein the metal substrate is etched by the second wet chemical etching to expose the winding. The method of manufacturing a semiconductor chip package structure for soldering a metal wall according to claim 98, wherein the metal substrate is formed by the first wet chemical (four) (4) forming the via hole By perforating and extending through the metal substrate to expose the winding; and the metal substrate is utilizing the second wetting Dry etching is performed to remove the contact area between the metal substrate and the winding and between the metal substrate and the metal wall. 100. The method for manufacturing a glazing end metal-clad package structure according to the above-mentioned patent specification (4), wherein the second wet 171 1292195 substrate is subjected to the first wet chemical _ (4) (4) The via hole 'the via hole is 1 σ and extends the metal substrate but is not penetrated, and the metal substrate is subjected to a second wet chemical etching to form a 'detailed portion from the metal substrate—the metal pillar The unfinished portion of the metal substrate is defined by the metal wall as the metal (four) and the service line and the metal wall, and the winding is electrically connected to the metal wall. 1〇2. The manufacturing method of the metal body 'package structure of the welded end according to the patent shaft 1〇1, wherein the gold ruthenium is re-etched using the mouth-wet chemical remnant Except for most metal substrates. 103. According to the scope of the patent application scope y rhyme, the welding end of the metal _ _ _ 裴 裴 之 之 , , , , , , , : : : : : : : : : : : : : : : : : : : : : : : ¥ The metal substrate inside the edge of the electric pin. 104. The manufacturing method according to the patent application scope of the package structure wherein the substrate is closed by the n-, and the metal substrate in the edge of the bobbin is removed. 105. A method for manufacturing a (4) chest structure of a welded end metal wall according to the patented semiconductor wafer (4), the towel 'the metal wire and the other with gold; engraved (four) engraved' and the surrounding earth plate The winding of the contact is electrically isolated. 172 1292195 106. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to item 5% of claim 1 , wherein the metal earth plate is subjected to a first wet chemical residue to make a The conductive pin position ', the conductive pin on the semiconductor wafer has a power gap 〇7·, the welding end metal wall according to the ninth patent scope of the patent, the manufacturing method of the semiconductor chip package structure, Wherein, the metal: is formed before connecting the semiconductor wafer to the metal substrate and winding. 108t=!: The manufacturing method of the welding end metal wall wall assembly according to Item 91, wherein the metal:: the semiconductor wafer to the metal substrate and the +conductor b-chip package structure of the winding The fabrication method layer can be formed prior to joining the semiconductor bismuth. The manufacturing method of the + conductor wafer package structure of the metal end wall of the welding end, wherein the fresh layer is connectable The semiconductor crystal is formed entirely/after. The method for manufacturing a semiconductor wafer package I structure of the metal substrate 173 1292195 according to the 91st item of the patent scope, wherein the connection portion is: the metal substrate The formation of the rhyme is performed using the second wet chemistry (4). A method of manufacturing a semiconductor chip package structure for soldering a metal wall according to the invention of claim 91, wherein the solder material is formed by etching the second wet chemical (10) of the metal substrate.制造 A method of manufacturing a semiconductor wafer package structure for soldering end metal walls according to claim 91, wherein the sealant is formed by transfer molding. The method for manufacturing a structure of a metal core 3 conductor wafer (4) according to claim 91, wherein the insulating substrate is removed to expose the metal wall and the solder layer in a second direction. But the winding is not exposed. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; An insulating substrate in the second direction. The manufacturing method of the semiconductor chip package structure of the metal terminal of the present invention according to claim 115, wherein the insulating substrate of the removed portion can be ground by polishing. 174 1292195 U7. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 116, wherein the insulating substrate is removed by grinding, and the insulating substrate is ground by grinding, but The metal wall and the solder layer are not polished, and then the insulating substrate, the metal wall, and the solder layer are polished, and then the polishing is stopped until the insulating substrate, the metal wall, and the solder layer are laterally arranged in a plane facing the second direction. The metal wall and the solder layer are exposed. 118. A method of fabricating a semiconductor wafer package structure for soldering and walling according to claim 1-4 of the patent, wherein the second layer is formed directly as the soldering end. According to the manufacturing method of the semiconductor chip package structure of the 118 item wall, the method of forming the terminal may be performed after the insulating base and the = end are ground, and the fresh tin material is deposited on the fresh layer I After Lu, the tin-tin material is reflowed together with the fresh joint layer to form the fresh joint. The fresh terminal metal wall package structure described in item 91 is a first layer cut. The oblique guide 121:=the second semi-guided wall (4) the package structure of the 'plate plane and the second plane 175 1292195 and the second direction is opposite to the first direction; b, forming a winding on the metal substrate a plane in which the winding is in contact with the first plane of the metal substrate and is isolated from the second plane of the metal substrate; C. etching the metal substrate by the first wet chemical etching, thereby the metal Forming a via hole in the substrate, the conducting The hole extends from the second plane of the metal substrate to the first plane to the metal substrate; d, forming a metal wall on the metal substrate, wherein the continuous metal wall is in contact with the metal substrate in the via hole, The metal wall extends from the second plane of the metal substrate to the first plane thereof into the metal substrate, and the metal crane includes a hole extending from the second plane of the metal substrate to the first plane thereof Into the metal substrate, covered by the metal wall in the first direction, and comprising an opening facing the second direction; Metal: two: the layer is connected with the winding in the hole, mechanically connecting a wire, the metal wall and the conductive layer of the soldering layer; the semiconductor wafer to the metal substrate, wherein the semiconductor chip comprises a 〇 team, Shao, conductive The foot is electrically connected; h, after connecting the metal wall of the semiconductor wafer and the soldering end, the shape of the metal substrate, the winding, and the sealing of the metal substrate, and the sealing of the semiconductor wafer Contacting and extending perpendicularly from the semiconductor wafer, the metal substrate, the winding, the metal wall, and the soldering layer to the first direction, and the metal substrate extends perpendicularly from the semiconductor wafer and the winding to the second direction; After the sealing agent is formed, the metal substrate is etched by the second wet chemical etching, thereby reducing the contact area between the metal substrate and the winding and between the metal substrate and the metal wall, and exposing the two windings; The metal substrate is subjected to a second wet chemical etching to form an insulating substrate, and the insulating substrate is in contact with the winding, the metal wall and the solder layer, and is covered. The winding 'metal wall and the soldering layer are in the second direction, · k, removing a part of the insulating substrate, so that the insulating substrate cannot cover the soldering layer in the second direction; and providing a soldering end, The solder end is in contact with the # metal wall in the hole and contains the solder layer. The manufacturing method of the semiconductor chip package structure of the soldering end metal wall according to the above-mentioned patent, wherein the winding and the wire are formed by forming a plating mask on the metal substrate, wherein The plating mask includes an opening that exposes the metal substrate of the file, and an opening through the electrode mask to electrically wire the exposed portion of the metal substrate. Π3. According to (4) the manufacturing method of the semiconductor chip package structure of the 177 1292195 wall of the splicing end of the invention, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in accordance with the order: a Passing a metal wall onto the metal substrate through the opening of a plating mask and entering the via hole; b, depositing a solder paste on the metal wall; and c, reflowing the solder paste, thereby forming The solder layer. #124. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 121, wherein the solder joint is the fresh joint layer. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 121, wherein the soldering end is formed by using the second wet chemical etching to perform the metal substrate After etching, a solder material is deposited on the solder layer, and then the solder material and the solder layer are returned together to form the solder end. 126. The method of fabricating a semiconductor chip package structure for soldering end metal walls according to claim 121, wherein the metal substrate is etched by the first wet chemical etching to form the via hole, the via hole Is a perforation and extending through the metal substrate to expose the winding; and the metal substrate is subjected to a second wet chemical surname to remove the metal substrate and the winding and the metal substrate and the metal wall Contact area between. 178 1292195 127. The method of fabricating a semiconductor wafer package structure having a metal wall according to claim 126, wherein the metal substrate is etched by the second wet chemical etching to remove the metal Substrate. 128. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to the invention, wherein the metal substrate is formed by using the first wet chemical residue; 'The via hole is a notch and extends the metal substrate but penetrates in winter; and the metal substrate is subjected to a second wet chemical residue for the remainder' to form a metal pillar from the unetched portion of the metal substrate The unetched portion of the metal substrate is defined by the metal wall as the metal pillar is in contact with the winding and the metal wall, and the winding is electrically connected to the metal wall. 129. According to the application for full-time (4) 128, the welding end of the metal-walled "body" 4 package structure manufacturing branch, wherein the metal substrate uses the second wet chemical _ to carry out the engraving, remove most of the The metal substrate is 130. According to the method of manufacturing the semiconductor chip package structure of the soldering end metal f according to the scope of the invention, wherein the gold earth plate is a C-wet-wet chemical remnant And the method of manufacturing the +-conductor chip package structure of the metal material of the soldering end according to claim 121, wherein The gold 179 1292195: the substrate is separated from the other semiconductors by the second wet chemical electric pin. The conductive pin on the conductor has a power of 132.=C21 The manufacturing method of the metal=+conductor chip package structure can be formed before the metal substrate/plate is etched. The plate is fabricated by using the first-wet chemical residue into the #121+V body wafer sealing structure. Method, wherein the company #4 can The metal substrate is formed by etching after the second wet chemical catalog. 134. According to the method for manufacturing a semiconductor wafer package having a metal wall according to the application of the above-mentioned item 121, wherein the removal method is The insulating substrate is such that the metal wall and the solder layer are exposed in the second direction, but the winding is not exposed. 135. The semiconductor chip package structure of the solder end metal wall according to claim 134 The manufacturing method, wherein the removing the insulating substrate is to remove the insulating substrate covering the metal wall and the soldering layer in the second direction. 136. The soldering end metal wall according to claim 135 A method of fabricating a semiconductor chip package structure, wherein the insulating substrate of the portion is polished to polish the 180 1292195 edge substrate by a polishing method. 137. According to the method of manufacturing the semiconductor chip package structure of the soldering end metal wall according to the item, wherein the part of the unrecorded substrate can be ground by grinding. But the metal wall and the solder layer are not polished, and then the insulating substrate, the metal wall, and the solder layer are polished, and then the polishing is stopped until the insulating substrate, the metal wall, and the solder layer are laterally arranged in a plane facing the second direction, and The metal wall and the solder layer are exposed. 138. A method of fabricating a semiconductor wafer package structure having a solder end metal wall according to the scope of the invention, wherein the fresh layer is directly formed as the solder end. 139. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 138, wherein the soldering end formation method is included in the insulating substrate, the metal wall, and the known end. After being ground, the solder material is deposited on the solder layer, and the solder material is reflowed with the solder layer 1 to form the fresh joint: •, / the semiconductor end of the welding end with the gold shoulder wall The manufacturing method of the chip package structure, wherein the 4 ¥ body day package structure is a first-level package. 141. The method for assembling a semiconductor chip package structure having a metal wall is at least included to provide a metal substrate including a corresponding first plane and a second flat lens 181 1292195, wherein the metal substrate The first plane is oriented toward the first direction, the second plane of the metal substrate is oriented toward the second direction, and the second direction is opposite to the first direction; b, forming a winding on the first plane of the metal substrate, wherein the The winding system is in contact with the first plane of the metal substrate and is isolated from the second plane of the metal substrate; c. etching the metal substrate by using the first wet chemical etching, thereby forming a via hole in the metal substrate, the via hole extending from the second plane of the metal substrate to the first plane to the metal substrate d. forming a metal wall on the metal substrate, wherein the metal wall is in contact with the metal substrate in the via hole, the metal wall extending from the second plane of the metal substrate to the first plane to the metal In the substrate, the metal wall includes a hole extending from the second plane of the metal substrate to the first plane thereof into the metal substrate, and is covered by the metal wall in the first direction, and includes a hole Opening to the second direction; the bar is connected to the D-Shou wafer to the metal substrate, the winding and the metal wall, wherein the semiconductor chip includes a conductive pin; the "connecting portion" is connectable to the wire and the conductive portion The foot is electrically connected; the green and the semiconductor wafer are connected to the metal wall to form a sealant, one, the wire, the middle, the male, the sealant and the 182 1292195 The semiconductor wafer is in contact with and extends perpendicularly from the semiconductor wafer, the metal substrate, the winding, and the metal wall in a first direction, and the metal substrate extends perpendicularly from the semiconductor wafer and the winding to the second direction; After forming the sealant, forming a solder layer that is in contact with and is isolated from the metal wall in the hole; 1. After forming the solder layer, the metal is wetted by the second wet chemical etching The substrate is etched, thereby reducing the contact area between the metal substrate and the winding and the metal substrate and the metal wall, and exposing the winding; j, after the metal substrate is etched by the second wet chemical etching, forming a An insulating substrate contacting the winding, the metal wall and the soldering layer, and covering the winding, the metal wall and the soldering layer in the second direction; k, removing a portion of the insulating substrate to make the insulating The substrate is incapable of covering the s-welding layer in the second direction; and l is provided with a soldering end that is in contact with the metal wall in the hole and includes the soldering layer. The method for manufacturing a semiconductor chip package structure having a metal end of a soldering end according to the invention, wherein the winding is formed by forming a “plating mask” on the gold substrate. (4) the plating mask includes an opening, the opening is 83 1292195 exposing a portion of the metal substrate; and the opening is plated through the opening of the plating mask to the exposed portion of the metal substrate. The method for manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 141, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in accordance with the sequence: ▲ a, through an electroplating Opening a metal wall on the metal substrate of the mask and entering the via hole; b, depositing a solder paste on the metal wall; and c, reflowing the solder paste, thereby forming the solder layer . 144. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 141, wherein the terminal is the fresh joint layer. (4) The method for manufacturing a semiconductor chip package structure according to claim 141, wherein the connection is formed by using the second wet chemical substrate after the (four) engraving, A solder material is deposited on the S, and then the solder material and the solder layer are flowed together to form the soldered end. The welding end piece (4) of item 141 belongs to the substrate system ^ m _ the through hole, and the through hole 2 is formed into a hole and extends through the metal 184 1292195 substrate to expose the winding. And the metal substrate is etched by the second wet chemical etching to remove the contact area between the metal substrate and the winding and between the metal substrate and the metal wall. 147. A method of fabricating a semiconductor wafer package structure having a metal terminal of a spliced end according to claim 146, wherein the metal substrate is etched using a second wet chemical rhyme to remove the metal Substrate. 148. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 141, wherein the metal substrate is etched by the first wet chemical etching to form a via hole. The hole is a notch and extends the metal substrate but does not penetrate; and the metal substrate is etched by the second wet chemical etching, and a metal pillar is formed from the unetched portion of the metal substrate, and the metal substrate is not The etched portion is defined by the metal wall that is in contact with the winding and the metal wall and electrically connects the winding to the metal wall. 149. The method of fabricating a semiconductor wafer package structure having a solder end metal wall according to claim 148, wherein the metal substrate is etched by the second wet chemical etching to remove a majority of the metal. Substrate. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 141, wherein the metal substrate is etched by a second wet chemical etching, and the 185 1292195 is wound and Other windings in contact with the metal substrate are electrically isolated. 151. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 141, wherein the metal substrate is engraved with a second wet chemistry, so that the conductive pin is Other conductive pins on the semiconductor wafer are electrically isolated. 152. The method of fabricating a semiconductor wafer package structure of a solder termination metal wall according to claim 141, wherein the connection portion is formed before the metal substrate is etched by the second wet chemical etching. 153. A method of fabricating a semiconductor wafer package structure having a metal wall according to claim 141, wherein the tantalum is formed by etching a metal substrate using a second wet chemical etch. . #Η4, the manufacturing method of the semiconductor chip package structure of the soldering end metal wall according to claim 141, wherein the insulating substrate is removed to make the metal wall and the fresh layer in the second direction Exposed, but does not expose the winding. 155. According to the invention, the method for manufacturing a conductor chip package structure according to the welding end of the invention, wherein the insulating substrate is removed to cover the metal wall and the solder layer. An insulating substrate in the second direction. 186. The method of manufacturing a semiconductor wafer package structure for soldering end metal walls according to claim 155, wherein the insulating substrate on which a portion of the damage is removed is capable of polishing the insulating substrate by grinding. 157. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 156, wherein the removing the insulating substrate is performed by grinding the brilliant substrate, but The metal wall and the solder layer are not polished, and then the insulating substrate, the metal wall and the solder layer are polished, and then the insulating substrate, the metal wall and the solder layer are arranged to be laterally arranged in a plane facing the second direction, and the polishing is known. The metal wall and the solder layer are exposed. 158. The method of manufacturing a semiconductor wafer package structure for soldering end metal walls according to the above-mentioned application, wherein the soldering layer is directly formed as the soldering end. 259. The method according to claim 158, wherein the crimping end is formed on the insulating substrate and the metal wall. After the soldering end is ground, the solder material is deposited on the soldering layer, and the "Xuanxue tin material is reflowed together with the soldering layer to form the soldering terminal 160. The soldering according to the semiconductor article of the patent application The conductor chip package structure of the earthen cows and the Japanese package structure is the first level package. 187 1292195 161. A method of manufacturing a metal wall for a soldering end, comprising at least a semiconductor chip package structure Providing a corresponding first metal substrate, wherein: (4) the second direction of the metal substrate: the second plane of the metal substrate is toward: a surface t toward the side: the second direction is opposite to the first direction; ° ▲ b, forming a winding on the first plane of the metal substrate, 1: the winding is in contact with the first plane of the metal substrate, and is isolated from the second plane of the metal substrate; c, mechanically connected a semiconductor wafer to the metal substrate and the wire: wherein the semiconductor chip includes a conductive pin; d, forming a connecting portion, the connecting portion is electrically connectable to the winding and the conductive pin; e, Connecting the semiconductor wafer to the metal substrate and winding to form a sealant, wherein the sealant is in contact with the semiconductor wafer, and extends perpendicularly from the semiconductor wafer, the metal substrate and the winding in a first direction, and The metal substrate extends perpendicularly from the semiconductor wafer and the winding in a second direction; f. after forming the sealant, the metal substrate is touch-etched by the first wet chemical etching, and thus the metal substrate is Forming a via hole in the board, the via hole extending from the second plane of the metal substrate to the first plane into the metal substrate; g, forming a metal wall on the metal substrate, wherein the metal wall is Contacting the metal substrate in the via hole, the metal wall 1292195 extends from the second plane of the metal substrate to the first plane thereof into the metal substrate, and the metal wall includes a hole, and the hole is formed by the metal substrate The second plane extends into the first plane to the metal substrate, and is covered by the metal wall in the first direction and includes an opening facing the second direction; -h, forming a solder layer, the solder layer is The metal wall in the hole contacts and is isolated from the winding; 1. after the solder layer is formed, the metal substrate is etched by the second wet chemical etching, thereby reducing the metal substrate and the winding and the a contact area between the metal substrate and the metal wall, and exposing the winding; j, after the metal substrate is etched by the second wet chemical etching, forming an insulating substrate, and the insulating substrate is The winding, the metal wall and the soldering layer are in contact with each other, and cover the winding, the metal wall and the soldering layer in the second direction; • k, removing a part of the insulating substrate, so that the insulating substrate cannot cover the soldering layer And in the second direction; and 1, providing a soldering end, the soldering end is in contact with the metal wall in the hole, and comprises the soldering layer. 162. The method of fabricating a semiconductor wafer package structure according to claim 161, wherein the winding is formed by forming a plating mask on the metal substrate. The plating mask includes an opening 189 1292195 that exposes the scratched metal substrate; and the wire is plated through the opening of the plating mask to the exposed portion of the metal substrate. 163. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 161, wherein the method for forming the metal wall and the solder layer comprises at least the following steps and in accordance with the order: a. Opening a metal wall on the metal substrate and entering the via hole through a opening of the plating mask; b, depositing a solder paste on the metal wall; and c, reflowing the solder paste, thereby forming the Welding layer. 164. A method of fabricating a semiconductor wafer package structure having a solder end metal wall according to item 161 of the article of the invention, wherein the solder joint is the fresh joint layer. 165. The method of fabricating a semiconductor wafer package structure for soldering end metal according to claim 161, wherein the soldering end is formed by using a second wet chemical surname to the gold &gt; 1 Substrate It row (4) After the crucible is deposited on the solder layer 'then the solder material and the solder layer - reflow' to form the solder end. 166. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 161, wherein the metal substrate is subjected to the first wet chemistry (4) to form a etched through hole Θ ' The through hole is—perforated and extends through the metal 190 1292195 substrate to expose the winding; the metal substrate is fabricated by the second wet chemical (4), and the metal substrate and the winding are removed and the metal substrate is removed. Contact area between metal walls. 7. The method according to claim 166, wherein the gold f substrate is etched by the second wet chemical etching to remove the Metal substrate. 68. The method of manufacturing a semiconductor chip package structure having a metal terminal of a spliced end according to claim 161, wherein the metal substrate is etched by the first wet chemical to form the via hole. The via hole is a notch and extends the metal substrate without penetration 'and the metal substrate is formed by a second wet chemical name d into the lamp to form a metal pillar from the undefected portion of the base metal substrate The un-part of the metal substrate is defined by the metal wall, the metal (4) is in contact with the winding and the metal wall, and the winding is electrically connected to the metal wall. 16= The manufacturing method of the semiconductor wafer sealing structure of the welding end metal soil according to the patent scope 帛168, wherein the metal substrate is the second wet chemical (10)] Part of the metal substrate. The method for manufacturing a semiconductor wafer chipping structure for soldering end metal according to claim 161, wherein the metal substrate is subjected to a second wet chemical residue (4), and the 191 1292195 is wound. The wires are electrically isolated from other windings made of metal substrates. 171 161 The method of manufacturing a body-wound package structure, wherein the gold f-substrate is electrically isolated from other conductive pins on the semiconductor wafer by using a second wet chemical. According to the invention, the method for manufacturing a semiconductor chip package structure for soldering end metal according to claim 161, wherein the connection portion can be formed before the metal substrate is etched by using a second wet chemical . 173=There is a method for manufacturing a zinc-terminated metal-semiconductor chip package structure as described in item i6i, wherein the connection portion can be formed by etching the metal substrate with a second wet chemical residue. . According to the method of manufacturing a semiconductor chip package structure of a zinc-bonded metal wall according to the above-mentioned patent, wherein the insulating substrate is removed, and the metal wall and the solder layer are The second direction is exposed, but the winding is not exposed. 175. The method of fabricating a semiconductor chip package structure for soldering end metal walls according to claim 174, wherein removing a portion of the insulating substrate is to remove the metal wall and the solder layer An insulating substrate in the second direction. The method of manufacturing a semiconductor chip package structure for soldering a metal wall according to claim 175, wherein the insulating portion of the removed portion is ground by polishing. 177. The method of fabricating a semiconductor chip package structure having a metal terminal of a spliced end according to claim 176, wherein the insulating substrate that is removed and smashed can be ground by grinding, but The metal wall and the solder layer are not polished, and then the germanium substrate, the metal wall and the solder layer are polished, and then the insulating substrate, the metal i and the germanium layer are laterally arranged in a plane in the second direction toward the second direction. And exposing the metal wall and the solder layer. According to the manufacturing method of the semiconductor chip package structure of the metal terminal of the present invention, the zinc bonding layer is directly formed as the soldering end. The method for manufacturing a solder-terminated metal-sa-package structure according to the above-mentioned item 179, 178, wherein the soldering end I is formed in the manner that the insulating substrate, the metal wall and the solder material are deposited on the solder layer, The bucket is reflowed together with the solder layer to form the solder end. 180. According to the scope of the patent application, the semi-conductor ^ meal _ end metal: the manufacturing method of the body 封装 chip package structure, wherein the 哕 conductor chip package structure is the first level package. The method for manufacturing a semiconductor chip package structure for soldering end metal walls includes at least: a. providing a metal substrate including a corresponding first plane and a second plane, wherein the metal substrate The first plane is oriented toward the first direction, the second plane of the metal substrate is oriented toward the second direction, and the second direction is opposite to the first direction; b, forming a winding on the first plane of the metal substrate, i The winding system is in contact with the first plane of the metal substrate and is isolated from the second plane of the metal substrate; c. the metal substrate is etched by the first wet chemical etch, and thus formed in the metal substrate a perforation, the perforation is passed between the first and second planes of the metal substrate to expose the winding; d, forming a metal wall on the metal substrate and the winding, wherein the metal wall and the perforation a metal substrate and a winding contact, the metal wall extending through the first and second planes of the metal substrate, and the metal wall includes a hole, the hole is formed by the metal base The first plane extends into the first plane to the metal substrate, and is covered by the metal wall in the first direction, and includes an opening facing the second direction; e, forming a solder layer, the solder layer is The metal wall in the hole contacts and is isolated from the winding; f. mechanically connects a semiconductor wafer to the metal substrate and the winding, wherein the semiconductor chip includes a conductive pin; 194 1292195 g, forming a connecting portion The connecting portion is electrically connected to the winding and the conductive pin; h, forming a sealing agent after connecting the semiconductor wafer to the metal substrate and the winding, wherein the sealing agent is in contact with the semiconductor wafer And extending perpendicularly from the semiconductor wafer, the metal substrate and the winding to the first direction, wherein the metal substrate extends perpendicularly from the semiconductor wafer and the winding to the second direction; 1. forming the metal wall and the solder layer After the sealant, the metal substrate is etched by the second wet chemical etching, thereby removing the contact area between the metal substrate and the winding and between the metal substrate and the metal wall. And exposing the winding; j, forming an insulating substrate by using the second wet chemical etching to form an insulating substrate, the insulating substrate contacting the winding, the metal wall and the soldering layer, and covering the Wrapping, metal wall and solder layer in a second direction; k, removing a portion of the insulating substrate such that the insulating substrate cannot cover the solder layer in the second direction; and l providing a soldering end, the soldering The end system is in contact with the metal wall in the hole and includes the solder layer. 182. The method of fabricating a semiconductor wafer package structure for soldering end metal walls according to claim 181, wherein the winding, the metal wall, and the soldering end are formed by plating the winding on the wire On the metal substrate, the metal wall is electroplated on the metal 195 1292195 substrate and the winding, and then a solder paste is deposited on the metal wall, and finally the solder paste is reflowed, thereby forming the solder layer. According to the manufacturing method of the semiconductor chip package structure with the metal end of the material described in the application (4), the solder joint is the fresh joint layer. 184. The method of fabricating a semiconductor chip package structure having a metal terminal of a spliced end according to claim s, wherein the soldering end is formed by using a second wet etching = the metal substrate Miscellaneous, a solder-on-four (4) material is deposited on the solder layer, and then the solder material and the solder layer are reflowed together to form the zinc joint. 185. The method of fabricating a semiconductor wafer package structure having a solder end metal wall according to claim 181, wherein the metal substrate is etched to remove the metal substrate by the second wet chemical etching. The method for manufacturing a semiconductor chip package structure of a solder end metal wall according to the above-mentioned item 181, wherein the metal substrate is etched by using a second wet chemical etching, and the winding and the other metal are The substrate contact windings are electrically isolated and electrically isolated from other conductive pins on the semiconductor wafer. 187. A method of fabricating a semiconductor wafer package structure having a metal 196 1292195 wall according to claim 181, further comprising forming the metal wall, then forming the solder layer, and then connecting the semiconductor wafer The metal substrate, the winding, the metal wall, and the solder layer are formed, and the sealant is formed. 188. The method of fabricating a semiconductor chip package structure for soldering end metal walls according to claim 8 wherein the method further comprises forming the metal wall, and then connecting the semiconductor metal substrate, the winding, and the metal wall, and then The encapsulant is formed and the solder layer is formed. 189. According to the method for manufacturing a semiconductor chip package structure of a soldering end metal wall according to Item 181, wherein a semiconductor package is connected to the metal substrate and the winding, and then the sealing is formed. And then forming the metal wall and forming the solder layer. The manufacturing method of the semiconductor chip package structure of the soldering end metal wall described in Item 181 of the application (4), wherein the insulating substrate for removing the β-brain can be ground by grinding, but not Polishing the metal wall and the solder layer, then grinding the insulating substrate, the metal wall and the solder layer, and then stopping the grinding until the insulating substrate, the metal wall and the solder layer are laterally arranged in a plane facing the second direction, and the metal is stopped The walls and solder layers are exposed. 191. A method of fabricating a semiconductor chip package structure having a metal end of a soldering end, comprising at least 197 1292195 a, providing a metal substrate including a corresponding first plane and a second plane, wherein the metal substrate is first The plane of the plane is oriented toward the first direction, the second plane of the metal substrate is oriented toward the second direction, and the second direction is opposite to the first direction; b, forming a winding on the first plane of the metal substrate, wherein the winding Contacting the first plane of the metal substrate and isolating from the second plane of the metal substrate; Lu C, using the first wet chemical name to etch the metal substrate, thereby forming a concave in the metal substrate a recess extending from the second plane of the metal substrate to the first plane into the metal substrate but not penetrating and isolated from the second plane of the metal substrate; d opening &gt; forming a metal wall a metal substrate and a winding, wherein the metal wall is in contact with the metal substrate in the recess, the metal wall extending from the second plane of the metal substrate to the first plane thereof The base (4) but not penetrating, and the metal wall is closed to the first plane of the metal substrate and includes a hole extending from the second plane of the metal substrate to the first plane thereof into the metal substrate, And being covered by the metal wall in a first direction, and comprising an opening facing the second direction; y into a layer, the fresh layer is in contact with the metal wall in the hole and is isolated from the winding; The second machine mechanically connects a semiconductor chip to the metal substrate and the core semiconductor chip comprises a conductive pin; 198 1292195 g, forming a connecting portion, the connecting portion is capable of being electrically connected to the winding and the conductive pin Connecting, forming a sealant after connecting the semiconductor wafer to the metal substrate and winding, wherein the sealant is in contact with the semiconductor wafer, and from the semiconductor wafer, the metal substrate and the winding to the first direction Extending vertically, the metal substrate extends perpendicularly from the semiconductor wafer and the winding to the second direction; φ 1, after forming the metal wall, the solder layer and the sealant, using the second wet chemical etch Etching the metal substrate, thereby reducing the contact area between the metal substrate and the winding and the metal substrate and the metal wall, but not removing the metal substrate from the unetched portion of the metal substrate. The etched portion is defined by the metal wall, the metal pillar is in contact with the winding and the metal wall, and the winding is electrically connected to the metal wall and is isolated from the soldering layer to make the winding After being etched by the second wet chemical residue, the insulating substrate is in contact with the winding, the metal wall, the metal pillar and the soldering layer, and covers the winding. The metal wall, the metal post and the solder layer are in the second direction; k. removing a portion of the insulating substrate such that the insulating substrate cannot cover the solder layer in the second direction; and providing a soldering end, The solder end is in contact with the metal wall in the hole and includes the solder layer. 199 1292195. The method of manufacturing a semiconductor wafer package structure for soldering end metal walls according to item 191, wherein the method of forming the soldering end of the turns of the tantalum metal may include: winding: metal: metal On the substrate, the metal wall is electroplated on the metal substrate and the winding wire, and the solder paste is deposited on the metal wall, and finally the solder paste is reflowed, thereby forming the solder layer. 193. The method of fabricating a semiconductor wafer package of a solder end metal according to claim 191, wherein the soldering end is the solder layer. 194. The method of fabricating a semiconductor chip package structure having a fused end metal wall according to the ninth patent application, wherein the splicing end is formed by using the second wet etch to the metal substrate. After etching, a solder material is deposited on the solder layer 1 to cause the soldering material and the solder layer to reflow together to form the solder end. 195=Manufacturing method of a soldering end metal=+conductor chip package structure according to the scope of application patent 帛(9), wherein the gold plate is subjected to 4 second wet chemical shots to remove most of the Parts of the metal substrate. 196. ^ 据 请 专 ( 四 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i The winding of the &quot;° line in contact with the other slanted metal substrate is electrically separated from each other by 200 1292195, and electrically isolates the conductive pin from other conductive pins on the semiconductor wafer. 197 φ 198. 199. The method of manufacturing a semiconductor chip package structure for soldering end metal walls according to claim 191, further comprising forming a metal wall, then forming the solder layer, and then connecting The semiconductor wafer is bonded to the metal substrate, the wire, the metal wall, and the solder layer, and the sealant is formed. The method for fabricating a semiconductor chip package structure for soldering end metal walls according to claim 191, further comprising forming the metal wall, and then connecting the semiconductor wafer to the metal substrate, the winding and the metal wall, and then The encapsulant is formed and the clathrate layer is formed. A method of fabricating a semiconductor chip package structure for soldering end metal walls according to claim 191, further comprising connecting the semiconductor wafer to the metal substrate and winding, forming the encapsulant, and then forming the metal a wall, and forming the solder layer. The method for manufacturing a semiconductor chip package structure of a soldering end gold wall according to claim 191, wherein the removing the insulating substrate is performed by grinding the insulating substrate, but the metal wall is not ground. And soldering the layer, then grinding the insulating substrate, the metal wall and the solder layer, and then stopping the grinding until the web, the metal wall and the solder layer are laterally arranged on a plane facing the second side 201 1292195, and the metal wall is closed And the solder layer is exposed. 202