TWI279831B - Transistor, memory cell array and method of manufacturing a transistor - Google Patents

Abstract

A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically insulated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

Description

1279831

V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a transistor, which is related to a memory cell array of the gamma number memory cell of the transistor, and the same method of integrating a complex transistor related. A manufacturing method of the prior art for storing and storing the address of the intermediate substrate between the storage region and the region of the first pole region has a lower limit in the lower edge state. The channel-type 直-type capacitor controls a current to form a crystal boundary by a memory cell integrated in a random access memory (DRAM) representing a conduction channel of the storage capacitor, and the edge has an integrated crystal surface crystal domain A junction of a crystal. The storage is read in the cell when the underlying cell area of the substrate is not accessed, and is a storage capacitor for the body cell to contact the surface of the information charge, and the access transistor. The access transistor package uses a β i region, a first and a first one, and a first and a second, a source I field, a pole/;: and a flowing gate pole. The transistor is usually at - and the information in the storage capacitor is: half, or write. The channel of the access transistor is below the boundary of the channel, and the access transistor is at a position other than 2 degrees. The effective channel length Lef is the lower boundary, and the planar transistor cell size of the body is formed horizontally on the surface of the plate. There is provided a possibility to enhance the length of the channel while maintaining the memory cells. The source/drain regions of the access transistor are aligned with the direction perpendicular to the surface of the substrate. The problem involved is that it is difficult to provide a stack. According to this, such a vertical transistor cell is difficult to container.

Page 7 1279831 V. Description of the Invention (2) A method of enhancing the effective channel length L eff , referred to as a recessed channel transistor, is like in US patent No. • 5, 9 4 5, 7 Known in 0 7 . In such a transistor, the first and second source/drain regions are disposed in a horizontal plane - parallel to the surface of the substrate. The gate is disposed in a recessed trench disposed in the semiconductor substrate between the two source/drain regions of the transistor. Accordingly, the effective channel length is equal to the sum of the distance between the two source/drain regions and the two undulations of the deep trench. The effective channel width W efM is related to the minimum structure size F. φ Another known concept of a transistor is to refer to a fin field effect transistor \ FinFET). The active region of a fin field effect transistor typically has a fin or ridge shape formed by a semiconductor substrate interposed between the two source/drain regions. A gate surrounds the sides or sides of the fin. The memory device typically includes an array of memory cells and a peripheral portion. The surrounding portion includes circuitry for operating the array of memory cells. According to the shrinking ground rule, there is a problem for the memory cell, that is, the surrounding portion consumes more space, and in addition, it is generated due to the bit line voltage and the word line voltage ruler. The reliability problem that arises. Accordingly, there is a need for a transistor that can solve the above mentioned problems, and can also be used in a peripheral portion of a memory device. SUMMARY OF THE INVENTION Embodiments of the present invention provide a transistor, a memory cell array

Page 8 1279831 V. INSTRUCTIONS (3) Columns, and a method of making a transistor. In one embodiment, the present invention provides a transistor at least partially formed in a semiconductor substrate, including: a first and a second source/drain region connecting the first and second source/drain electrodes a channel region of the region, the channel region is disposed in the semiconductor substrate, and a gate is disposed along the channel region and electrically insulated from the channel region for controlling between the first and second sources Current flow between the pole/drain regions, wherein the channel region includes a fin region, wherein the channel has a shape of a ridge that is perpendicular to the first connection In the cross section of the second source/drain region connection, the package I# has a top side and a side side, wherein the top side is disposed under the surface of the semiconductor substrate, and the gate is along the top The side is configured with the sides to the sides. The present invention is described with reference to the accompanying drawings in which the description of FIG. In this regard, directional terms such as π top π, π bottom 11, "front", "rear", "guide", "spread", etc., are used in reference to the orientations illustrated. Since the elements of the embodiments of the present invention can be positioned in many different orientations, the directional terminology is used for the purpose of illustration only and is not intended to be limiting. It is understood that other embodiments may be used without departing from the scope of the invention. The embodiment may also be changed structurally or logically. Therefore, the description of the subsequent details is not intended to be limiting, and the viewpoint of the present invention is defined by the scope of the appended patent application.

Page 9 1279831 V. INSTRUCTION DESCRIPTION (4) The present invention provides a transistor that eliminates the problems involved with conventional transistors. The invention also provides a memory cell array and method of making a transistor. These and other needs are achieved by a transistor that is a transistor that is at least partially formed in a semiconductor substrate, including a first source/drain region, suitably connected by a storage capacitor electrode. a first contact window region of the first source/drain region, a second source/drain region, and a second contact window region of the second source/drain region, suitably connected by a one-dimensional line Connecting the first and second source/drain regions-channel regions, the channel regions are disposed in the semiconductor substrate, and a gate disposed along the channel region, using a gate insulating layer and the channel Electrically insulating the region, the gate controlling current flow between the first and second source/drain regions, wherein the channel region includes a fin-region, wherein the channel region has a fin shape a shape, and wherein the gate is disposed at three sides of the channel region, wherein a current path connecting the first and second source contact regions includes a first vertical region, wherein the direction of the current has a One a vertical direction component 'a horizontal region, wherein the direction of the current has a horizontal component, and a second vertical direction, wherein the direction of the current has a second vertical direction component, 4, the first vertical direction and the second The vertical direction is opposite. Accordingly, the transistor of the present invention is implemented as a fin field effect transistor having an active region with a ridge or fin shape. Thereby, the conduction path connecting the first and second source/drain regions can be used completely, thereby reducing the off current (〇 f f - c u r r e n t) of the transistor.

1279831 V. INSTRUCTIONS (5) Furthermore, since the current path additionally includes a vertical component, the off current can be further reduced. The present invention additionally provides a transistor which is an at least one portion of a transistor formed in a semiconductor substrate, including a first source/germanium, a polar region, and a second source/drain region. Disposed in the semiconductor substrate, connecting a channel region of the first and second source/drain regions, and defining a first direction by a connection connecting the first and second source/drain regions, and a gate disposed along the channel region electrically insulated from the channel region by a gate insulating layer, the gate controlling current flow between the first and first source/drain regions, wherein The channel region includes a fin-region, wherein the channel region has a bounding shape, and the fin includes a top side and two side sides in a cross section perpendicular to the first direction, wherein the channel shape The top side is disposed under one surface of the semiconductor substrate, and the gate is disposed along the top side and the side portions. According to a preferred embodiment, the distance between the top side and the surface of the substrate measured in a direction perpendicular to the semiconductor of the substrate is from 1 2 to 200 nm. If the distance between the top side and the surface of the substrate is less than 10 nm, the advantageous effects of the present invention are greatly reduced. On the other hand, if the distance between the top side and the substrate surface is greater than 200 nm, the on-resistance will increase significantly. Furthermore, the present invention provides a memory cell array including a plurality of memory cells, a complex bit line disposed in a first direction, and a complex digital line disposed in a second direction crossing the first direction a memory cell comprising a storage capacitor, at least partially formed in a semiconductor substrate

Page 11 179831 5. A transistor of the invention (6), the transistor comprising a first source/drain region, a second source/drain region, and the first and second doped regions a channel region disposed in the semiconductor substrate, and a gate disposed along the channel region and electrically insulated from the channel region by a gate insulating layer, the gate control being between the first Current flow with the second source/drain region, wherein the channel region includes a fin region, wherein the channel region has a fin shape that is perpendicular to connecting the first and second sources/ The cross section of the drain region includes a top side and a side side, wherein the top side is disposed under a surface of the semiconductor substrate, and the gate is disposed along the top side and the side sides Each of the word lines is electrically connected to the plurality of gates, and wherein the second source/drain region of each of the transistors is connected to one of the bit lines through a one-dimensional line contact window. In addition, the present invention provides a method of fabricating a transistor in a semiconductor substrate, comprising the steps of providing a semiconductor substrate, defining two insulating trenches in a surface of the semiconductor substrate for laterally confining the transistor to be formed An active region is laterally confined by two insulating trenches, filling the insulating trench with an insulating material, providing a gate insulated from the active region by a gate insulating material, providing a first and second source a pole/drain region in which a conductive path is formed between the first and second source/drain regions, and a first direction is defined by a connection connecting the first and second source/drain regions, The step of providing a gate includes the steps of defining a trench in the active region, the trench extending from the surface of the semiconductor substrate to a first depth in a direction perpendicular to the surface

1279831 V. Description of the invention (7), after which a groove is defined in each of the insulating trenches adjacent to the groove, so that the two grooves will be connected to the groove, and the groove is Between the two grooves, the two grooves extend to a second depth greater than the first depth, provide a gate insulating material between the active region and the trench, and Depositing a gate material between the active region and the trench, depositing a gate material to fill the trench and the two recesses, partially removing the gate material, and thus the gate material is from the trench The groove is removed from the outer portions of the two grooves. According to the present invention, since the step of providing a gate includes forming a groove in the main p region, thereby defining the step of the recessed passage portion, it is possible to align the recessed passage with the gate. According to a preferred embodiment, the method further includes the step of thinning the active region portion between the first and second depths in a direction parallel to the substrate surface and perpendicular to the first direction. Thereby, it is possible to locally thin the active area at the channel area 'which will then be surrounded by the gate while maintaining the active area range outside the gate area. In particular, the width of the source/drain region can be maintained. Therefore, the confluent contact window area will not be thinned, thereby reducing a contact window impedance. • According to another embodiment, the two grooves are defined by wet etching. Accordingly, the two grooves can be formed in a self-aligning manner so that they will be formed only at the groove portions adjacent to the gate. Moreover, in the case where the trench portion is also defined using a wet residual, it is possible to perform a method in which the pass word line of the memory cell array will be located close to the

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1279831 V. DESCRIPTION OF THE INVENTION (8) The position of the surface of the semiconductor substrate at the surface is thus reduced by the influence of the word line on the adjacent active area. According to another embodiment of the present invention, the step of providing a gate includes the steps of defining a groove in each of the insulating trenches, the two grooves extending to a second depth, and then adjacent to the groove Positioning a location in the active region defining a trench, such that the trench is disposed between the two recesses and electrically connected to the two recesses, the trench being perpendicular to the semiconductor substrate a surface of the surface of the semiconductor substrate extending to a first depth, wherein the second depth is greater than the first depth, providing a gate material between the active region and the trench, and Positioning a gate between the active region and the recess, depositing a gate material to fill the trench and the two recesses, partially removing the gate material, and thus the gate material is The groove is removed from the outer portions of the two false grooves. In this case, the grooves are particularly preferably formed in parallel with each other to more simply produce alignment of the grooves with the gate groove portions. The transistor of the present invention can be used, inter alia, in a dynamic random access memory (DRAM) memory cell comprising a capacitor and an access transistor. However, the transistor of the present invention can also be used in the core circuit of a memory device. In particular, the transistor of the present invention can be a part of a word line driver. Moreover, the transistor of the present invention can be used in any form of circuit or application. Figure 1A depicts a cross-sectional view of the transistor 16 along a direction connecting the first and second source/drain regions 1 2 1 , 1 2 2 .

Page 14 179831 V. Description of the Invention (9) The transistor 16 includes a first and a second source/drain region 1 2 1 , i22, and connects the first and second source/drain electrodes The passages of the regions 121, 12 2 are 1 . The conductivity of the channel is controlled by the gate 85. The active zone - domain 1 2 has a shape of a profile or ridge, and the three sides of the fin are surrounded by the gate. The first and second source/drain regions 1 2 1 and 1 22 are disposed in the surface region of the half of the conductor substrate 1. The gate 85 includes a trench region 852 and two plate-like portions 851. The trench region of the gate 85 is disposed in a trench etched in the surface 1 of the substrate. The top side of the active region is disposed at a deeper depth position than the surface of the semiconductor substrate. This type of flat portion extends before and after the depicted section and is thus described by the broken line. The lower portion of the trench portion 825 is electrically insulated from the stone material by the gate oxide layer 80. The first and second source/drain regions 1 2 1 and 1 2 2 are electrically insulated from the trench portion 852 by the tantalum nitride spacer 86. Further, the sacrificial yttrium oxide layer 181 is disposed between the tantalum nitride spacers 86 and the first and second source/drain regions 1 2 1 2 2 . The first contact f region 93 is provided for electrically connecting the first source/drain region 1 21 to the storage capacitor, and a second contact window region 94 is provided for The second singular/polar region 1 2 2 is electrically connected to a bit line (not shown). The details of the contact window areas 93, 94 of the younger brother and the younger brother will be described next in the first to fourth embodiments of the present invention. Between the ΰ 间 极 极 极 极 极 极 极 极 极 极 极 极The first and second source/pole regions 1 2 1 and 1 2 2 are implemented as light η-doped germanium regions, and thus

1279831 V. INSTRUCTIONS (ίο) A good electrical conductivity is now available. Optionally, the first source/drain region 121 or the source/drain region 12 122 may additionally include a lightly doped region (not shown) disposed in the channel region. Between this height and the miscellaneous area. The channel 14 is lightly p_mutated and thus insulates the first source from the second source/drain region, and the depolarizer 52 applies an appropriate voltage. ^ A ray path between the first and the second contact window regions 93, 94 first extends in the -first-vertical direction, in other words, the delay:: two t-directions and then Opposite to the first-vertical direction

Uiba i fork extends in the middle. Differently stated, the current path includes the 忒 channel £ domain 14 and also the distance from the source/deuterium contact window regions 93, 94. % U boundary to telecontrol, ILfi: the current path to the second contact window area 93, 94, the vertical path of the current, the weak vertical path, followed by the - strong gate path, and the ii - strong The horizontal path, a strong gate vertical because of the weak vertical path of the current path. The same is true, the difference is between the weight; i includes the distance between the extensions 1 2 2 in the recess formed in the surface of the substrate & * the first and second source/drain regions 1 2 _, wherein the main 'in contrast to a fin field effect transistor is an increased flow path including only the domain is disposed along the surface of the substrate, and wherein the intersection of the channels is an electrocluster path. Therefore, a leakage current is reduced in the source/drain region - through the highly doped region' and thus. In addition, the poles 852 are separated, because \\21, I22 utilizes the partition wall portion 86, and the electric field of the gate is shaped by the electric field of the gate.

Page 16 8 1279831 V. Description of invention (11) ... · . Fig. 1B is a cross-sectional view showing the transistor in a direction perpendicular to the direction of Fig. 1A. In particular, it shows a cross-section of the fin-shaped region of the active region: 11 which is the portion of the active region having a narrow width, the fin-shaped region being surrounded by the gate on its three sides. In the dome-shaped region 11, the active region has a ridge or a fin shape. The active region has a top side 1 1 a and a side facing side 11 b, the length of the top side 11 a being less than the length of the lateral side 1 1 b. In Fig. 1B, the plate-like portion 851 of the gate 85 is disposed along the lateral side 11b of the fin, and the trench-like portion 852 of the gate is along the fin The top side 1 1 a configuration. The gate electrode 85 is insulated from the fin region 11 by the gate oxide 80. As can be seen from Figure 1B, the current path 15 is in a direction perpendicular to the plane depicted in Figure 1B. Due to the narrow fin-shaped region, the transistor body can be completely used, so that the closing current of the transistor can be reduced. In accordance with a preferred embodiment of the present invention, the fin region can be locally thinned such that the width of the channel region is less than the width of the first and second source/drain regions. Therefore, the off current of the currently known transistor can be further improved without reducing the contact window area of the source/drain region. Therefore, the conduction impedance is not applied. In the structures described in Figures 1A and 1B, the length L eff of the channel is related to the distance between the first and second source/drain regions. Furthermore, the width of the channel is related to the width of the conductive region - controlled by the gate. According to this, the width of the channel and the fin height and the fin shape

1279831 V. INSTRUCTIONS (12) The sum of the widths, or alternatively, is related to the length of the top side of the ridge and the double length of the lateral side. In particular, the channel length -degree L eff can be from 30 to 150 nm. In addition, the height of the shape may be from 20 to 100 nm, and the width of the fin may be from 10 to 50 nm. Accordingly, the transistor of the present invention provides an improved on-current as compared to known transistors because the width of the channel increases and the impedance decreases. In addition, the transistor exhibits a large secondary threshold characteristic slope and a significant reduction in the subject effect. Therefore, the turn-on current is further increased. φ In contrast to known transistors, the transistor additionally provides an improved shutdown current due to its large pass %: length and its large secondary threshold slope. In summary, the transistor described in Figures 1A and 1 B integrates the improved turn-on current with the reduced turn-off current. Figure 1C depicts the transistor structure modification in Figure 1A. In Fig. 1C, the first source/drain region includes a heavily doped region 1 2 1 '' and a lightly doped region 1 2 1 '. The lightly doped region 1 2 Γ extends to the same depth as the second source/drain region 12 2 extends. The electric field can be reduced by providing a lightly doped region 1 2 1 ' between the heavily doped region 1 2 1 '' and the channel 14 . Accordingly, a confluent leakage current is reduced. In general, when the gate is not addressed, the leakage current is related to the current flowing from the storage capacitor to the second source/drain region or the body of the crucible. Therefore, the electric field at the junction of the first source/drain region-channel,

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5. The invention description (13) is particularly highly sensitive to the leakage of the chilled zone - the leakage of the channel junction, ^, at the first source/drain current, the retention time, in other words <" _ have ^ profit. By reducing the leakage by the identifiable storage time, information can be added in the memory cell, as in the symmetry of the second source/drain region of the present invention, a first and a Arranged, wherein the first source is as described in the ic diagram, and the lightly doped Qiu: f 121 includes a light and heavy/drain region 1 2 2 The extension of the same two 1 extends to the second source, however, the viewpoint of the present invention is highly advantageous. The bungee region includes a light and a heavy matrix including the second source/region being disposed in the heavily doped region, including the light and heavily doped regions of the jth! Between: Special polar regions, can be arranged in a symmetrical manner. μ /, brother - source / 汲 according to the lower side of the cautious right 丨 pole / bungee region i 2 1, described in Figure 1 C, θ配•, the effective wide yield of the lightly doped first source-source/drain region can be on the top side. The first width is determined by the opening width of the opening/width. The increase is because this |r is further improved. ", L The transistor's turn-on current characteristic is then connected to the storage capacitor: the confinement field connected to the storage load: =. According to this, the retention time will be further increased.

Page 19 1279831 V. INSTRUCTION DESCRIPTION (14) As already indicated above, the transistor described above can be used as a transistor forming portion of a memory cell. Additionally, the transistor can form part of a word line driver. In particular, the use of the electro-optic body in a peripheral portion of a memory device has a less severe limitation on the leakage current of the transistor. In accordance with the present invention, it is contemplated that the electro-optic body as defined in the scope of this patent application clearly includes all of the transistors comprising the features defined herein regardless of its leakage current characteristics. Figures 2A through 2W depict a first embodiment of the present invention in which a memory cell array comprising a transistor of the present invention and a trench capacitor is implemented. Fig. 2A depicts a plan view of the array of memory cells, the memory cell array comprising a plurality of memory cells 1 〇 , each cell comprising a trench capacitor 3 and a transistor 16. The complex digital line 8 is disposed in a first direction, and the plurality of bit lines are disposed in a direction perpendicular to the word line 8. Similarly, the positions I, I I, I I I and I V described in Fig. 2A describe the direction taken along the cross-sectional illustration depicted in Fig. 2B. More specifically, the cross-sectional illustration from I to II depicts a cross-section of the bit line perpendicular to between the adjacent word lines 8, and a cross-sectional view from II to III. Depicted a cross section perpendicular to the word line along a one-bit line 9, and a cross-sectional illustration from III to IV depicting a line 9 perpendicular to a line of characters 8 Cross section. Figure 2B depicts three of the memory cells used to define the capacitor trench from position I to I I , I I to I I I , and I I I to I V .

Page 20 1279831 V. INSTRUCTIONS (15) Cross-sectional illustration. The structure described in Fig. 2B can be obtained, for example, first by depositing a pad oxide layer (not shown) on a semiconductor substrate 1 by a generally known method, more often in this field. The use of a nitride layer 17 is used. Thereafter, the capacitor trench is defined by the known method of light-micro-shadow. In particular, the opening associated with opening in a trench mask is etched into a hard mask layer (not shown) deposited on the tantalum nitride layer 17. Thereafter, the opening is etched into the tantalum nitride layer 17, the pad oxide layer, and the germanium substrate 1. Furthermore, a first capacitor electrode, like the capacitor dielectric, is formed in a generally known manner. Thereafter, a plurality of stone fillings 31 are filled into the capacitor trench, the multi-turn filler is in-wall type, and an insulating collar 3 2 is formed in the upper portion of the trench capacitor to block A parasitic transistor is formed in this portion. The resulting structure is filled with a second multi-stone filler and planarized using known methods. The multi-filler fill is then recessed in the same manner as the etch step performed by the recess 3 when forming a buried strap. Specifically, the multi-ruthenium filler is etched by 30 nm below the surface of the substrate. A plan view of the capacitor trench arrangement is depicted in Figure 2C, in which the plurality of capacitor trenches 3 are arranged in a checkerboard manner. The different argument is that the ft capacitor trench is arranged in a column, where two adjacent trenches have the same distance, and the two adjacent columns of trenches are arranged in a staggered manner, so that one column of trenches is located in the adjacent column two adjacent The middle position between the trenches. The size of a memory cell 100 is 2F in a first direction and 4F in a - second direction, where F is the minimum available in the related art.

Page 21 1279831 V. Description of invention (16) Structure size. Then, the active region is defined by photolithography, and the insulating trench 2 is etched to expose the active region. The final width of the active area is expected to be specific to 0 · 8 F. For example, ρ can be 1 〇 〇, 80 or 50 nm' or assumed to be any desired value. Thereafter, the active region is oxidized by a heat treatment, and the trench between adjacent active regions is filled with a common STI filler. In the present example, the insulated trench is filled with a layer of dioxide dioxide that fills the upper portion of the capacitor trench 3 and forms the top oxide 34 of the trench. L. After defining the active area, the configuration as described in Fig. 2D is obtained, wherein the reference number 12 is indicated as the active area. It is to be noted that in the plan view of Fig. 2D, after etching the insulating trench, the upper portion and the lower portion of each of the capacitor trenches 3 are also etched. Thereafter, the semiconductor substrate 1 is briefly immersed in diluted hydrogen fluoride (HF), for example, to remove a surface oxide layer (oxide deg laze step). The final step height at the insulated trench is expected to be 0 nm. Thereafter, the tantalum nitride layer 7 and the pad oxide layer (not shown) are removed by known methods. Thereafter, the sacrificial oxide _ 181 is thermally grown and the implantation process generally used in the memory cell is performed to form the well region. At this point, a lightly covered source/drain implant that may be used for the drift region, in other words, the weak gate portion of the current path - (not shown) may be implemented. These processing steps result in the knot shown in Figure 2E.

1279831

With ρ ί : 士 矽 矽 ΐ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 。 。 。 。 。 Thereafter, the oxidation: 丄 83 having a thickness of about nanometer is deposited in a known manner. Finally, as a mask, the multi-layer 184 of the thickness of ? = :, , , 8 〇 nanometer is deposited in a known manner. The resulting structure is described in Figure 2F. A GC array mask having a spacing of 1.4 X 2 · 2 F (not shown to provide an opening portion of the interpole is made by a known method.) The multi-layer layer 8 is forged in the defined portion: and then the 'yttria layer 183 is also etched and centered on the liner layer 182. The tantalum nitride layer is removed 1 8 2 Thereafter, an etching step is performed to t 彳 彳 夕 # 氧化 氧化 氧化 氧化 氧化 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到 直到2 A diagram depicting a planar representation of the structure in which a gate 8 5 3 is disposed in a space between two adjacent trenches in an active region. Thereafter, an additional sacrificial oxide layer 181 is Heating a long length on the exposed portion, particularly at the bottom and bottom portions of the trench sidewall 2 defined for the gate 853. Thereafter, a tantalum nitride spacer layer 6' is deposited and etched. 2F. / The sacrificial oxide layer 181 is advantageous because it can be used as the final thickness at the sidewall of the opening of the Gc mask. At this later, an oxide interface is provided between the germanium portion of the source/drain region and the nitride spacer. Thus, in the formed transistor,

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V. DESCRIPTION OF THE INVENTION (18) A surface having a surface J is present and the leakage current of the source/drain region of the electrospray species directly adjacent to the tantalum nitride spacer is thereby invited. In contrast, in the comparison, the structure formed by the above description is formed, and in the Fig. 21, the gate region is further etched by τ. The bottom portion of the pad oxide layer 181. In addition, the second is particularly etched by etching the liner and tantalum nitride in comparison. Since the oxidized second layer 3 2 is in the cross-sectional area between the crucible and the crucible, a concave pattern is formed in the emulsified second layer 32 in the oxygen = 靥f between I 1 1 and IV _. The groove extends to a depth of 1 〇〇 or i 2 〇 nanometer below the surface of the substrate: φ, an isotropic etching is performed to remove the 矽 portion formed in the previous step adjacent to the groove . Thereby, the fin-shaped region forming the active region portion is thinned, for example, on each side from 丨〇 to 奈5 nm to achieve a final fin width of 30 nm. Therefore, the channel can be fully used by applying an appropriate voltage to the gate. However, since the fin shape is locally thinned only at a portion adjacent to the gate, the contact window region of the source/drain region is reduced, and thus the contact window impedance is not increased. In particular, due to the wave processing of the description, the thinned active region and the gate are formed in a self-aligned manner. The resulting structure is described in Figure 2J. As can be seen from the cross-sectional illustration of II and η I, the region 854 extends deeper than the depth at which the sidewall spacers 86 extend. Further, as can be seen between III and I ν As seen in the cross-sectional illustration, the defined GC region 8 54 includes a/central portion and two sidewall portions that extend deeper than the depth at which the central portion extends - 0

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V. Description of the Invention (19) After a sacrificial oxide layer (not shown) to reduce the effect of an ion transport is formed, and an ion implantation step is performed to pick up the channel region, if necessary, grow Gate oxide layer 8 〇. Subsequent to the deposition of a scaly junction in the original with a thickness of 40 nm; 185.曰 The resulting structure is described in Figure 2K. Thereafter, the multi-layer 185 is etched to 70 nm below the surface of the multi-turn described in Figure 2K to form the gate 85. Thereafter, a layer of tantalum nitride 186 is deposited to fill the region above the gate 85. The formed structure is depicted by W ^ ^ u T j as described in the 2L diagram, the gate 85 includes a trench portion 852 and two flat portions 851u to remove the tantalum nitride layer 18 from the surface. After 6th, layer U3 is removed, and the first and second source/no-polar regions are defined; Thereafter, the ruthenium oxide layer 183 is deposited again and an f GC connection line is provided. For this purpose, first remove the ί 186 that exposes the gate milk. Thereafter, an additional emulsified 矽SlsN冏 partition 87 having a thickness of 〇.2f was deposited. Accordingly, the opening is used for the opening of the 5H GC connecting line 83 than the partition wall. The structure formed is described in Figure 2M. In this case, the surface strip region will be derogated. In particular, the method of using the method of 壮r A 少 A 是 是 是 是 是 是 是 是 是 是 是 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 The stone layer 18 is a mask, the oxygen pair; the eve ♦ and the 1 fragmentation are selective moments. After that, Shiyiyi

1279831

The tantalum nitride liner penetrates the step, and finally the trench top oxide layer 34 is selectively etched for Doshi and Nibble. • The resulting structure is described in Figure 2N. Figure 20 depicts a planar representation on the array of formed memory cells. • The strip mask opening 34 is formed between a capacitor trench 3 and a defined Gc region. After that, the exposed tantalum nitride SiN spacer is removed, and a germanium telluride layer (not shown) is grown, and a nitrided partition wall 37 as a strip-shaped partition is deposited and etched. Thereafter, f is a selective step, 丨I* plant point implantation step to reduce the interface window resistance between the internal capacitor electrode and the surface. The structure formed by these steps is to form a strip connection connecting the internal capacitor electrode and the first source/drain region of the transistor, depositing a titanium nitride TiN pad and then forming a metal Layer deposition step. The deposited material is then etched to form the metal strip 38. Next, the multi-layer mask layer 187 is removed, and a tantalum nitride liner 188 having a thickness of 50 nm is deposited to fill the portion of the metal strip & Thereafter, the tantalum nitride liner is etched at 60 nm to provide a smooth surface. The resulting structure is described in the second Q diagram. The step of forming the word line 8 is then performed. First, the surface is planarized by performing a CMP (Chemo-mechanical P 〇 Li shing) step, and the ruthenium nitride is oxidized by an over-grinding agent. The object is polished. Thereafter, a layer 8 of tantalum and a layer of tantalum nitride cover 81 are deposited. Forming the sidewall spacer 8 1 and

Page 26

1279831 V. INSTRUCTIONS (21) After a space of quartz glass (the space is 2, the figure is described as a replacement of the buried contact 3 3 , the pole / drain region 1 2 1 . Compared with the same reference symbol Below, the depth of the 2S figure is deeper to provide a representation of the surface of the T substrate extending to the second TT. The word line is connected. BPSG) material 82 is filled between adjacent word lines to the The structure described in the 2R diagram. A similar illustration uses a surface strip 38 to connect the internal capacitor electrode 3 1 to the first source. In Figure 2, similar elements are indicated in Figure 2R. As can be seen from Fig. 2S, the δH gate trench in Fig. 2R must be engraved with the same length of current path as Fig. 2R. In particular, the surface of the gate 1 has a depth of at least 5 〇 nanometers below. A memory cell array of the structure described in Fig. 2R is provided to connect the gates 845 of a row. Next, a quartz glass day (BPSG) layer 92 is formed as a bit line insulating layer. Next, the opening for providing the bit line contact window 61 is lithographically defined and etched using known methods. Thereafter, an implantation step at the bottom of the bit line contact opening is performed to improve the contact window impedance. Finally, the bit line contact opening is filled and planarized. In addition, the M0 layer is deposited, lithographically patterned and etched in a known manner to provide the bit line 9. After that, a common execution step of providing the higher metallization layer is performed. A second figure depicts a plan view of the memory cell array after forming the bit line contact window 90. Further, the 'wth w diagram depicts a planar representation of the memory cell array after patterning the bit line 9. In the 2U diagram, in the cross section between 丨丨 and j丨丨, an electric

1279831 V. DESCRIPTION OF THE INVENTION (22) A crystal 16 is formed between the first and second source/drain regions 1 2 1 and 1 2 2 . The first source/drain region 1 2 1 is connected to the internal capacitor electrode of the trench transistor 3 through the surface strip 38 and the multi-turn 3 true charge 3 6 . The channel conductivity between the first and second source/drain regions 1 2 1 and 1 2 2 is controlled by the gate 85. a current path between the first and second source/drain regions 1 2 1 and 1 2 2 extending from a surface of the first source/drain region 121 to the second source/汲The surface of the pole region 122. In the upper portion of the current path, the potential of the gate 85 is isolated by the spacer 86, and in the lower portion of the current path, the conductivity is controlled by the gate. The information stored in the trench capacitor is read by the transistor and transmitted through the bit line contact window 90 to the bit line 〇 as can be traversed between III and IV. As can be seen, the active region surrounded by the gate 85 has a fin region, wherein the active region has the shape of a fin or a ridge. The gate is placed around the fin at three sides of the fin. More specifically, the gate 85 includes a trench region 825 as described between I I and I I I, and two types of flat portions 851 adjacent to the fin side. In the cross section between I I I and I V , the fin region is surrounded by the gate 8 3 and has a narrower width than the lower region. In the second S diagram, in the contact window between the first source/drain region 1 21 and the internal capacitor electrode, which is completed by a buried strap 3 3 , the current path is also a kind Vertical component, because in this case, the channel

Page 28

1279831 V. INSTRUCTIONS (23) In the case of the surface band, the description of the 3A to 3L figures depicts that the cell array includes a stack of the described transistor. Figure 3A depicts the memory as described in Figure 3A, with adjacent configurations between them, the homo-line contact window 90. Depending on the container 4, the broken line 4 is used between the insulating strips 2 3 at 3B, 3C, 3F and between points V and V. In order to provide an insulating trench 23 in the surface 10 of the light lithography according to the present invention. Charging, and then performing a multi-layer mask layer for providing a thickness of a layer of silicon dioxide having a thickness of about 10 nm at a sacrificial concentration of about 10 nm (in the next step, Used to define the multi-mask. The shape of the wire in the second embodiment is thus defined

Below, it is recessed to a deeper depth. A second embodiment of the present invention, wherein a memory capacitor and the configuration of the cell array active region 12 are referenced above with reference to the 1A and 1B cells. As in the formation of the two active regions 1 2 of the transistor, and sharing the stacking electricity indicated by the broken line, which is common to each of the memory cells 100. The sections of the active area 12 are separated from each other. The cross-sectional illustrations shown in the figures of 3 G and 3 J are the memory cell array definitions of the second embodiment and the last name is engraved on a semiconductor substrate 1. The insulating trench 2 is made of cerium oxide. A common planting step to fill the well area. After the thermal curing step with layer 181, a tantalum nitride layer 108 is deposited, and thereafter has 100 nm 183. After that, the deposition one has about 80 nm (not shown). The light lithography method defines the word line. First, the gate of the opening in the stone mask layer (not shown) includes the gate mask used for the opening, instead of the opening in the first embodiment,

Page 29 1279831 V. INSTRUCTIONS (24) Separated word lines. Thereafter, the patterned multi-mask mask is used as a mask, and the oxide is in the vicinity of the selective tantalum </ RTI> until reaching the tantalum nitride layer 182. After the tantalum nitride in the exposed area, the 矽 and = 夕 in the exposed area are the depth of about 4 〇 nanometers below the surface of the stone. Oh, the groove part of the gate. + 热 Thermal oxidation for growing a sacrificial oxide layer (not shown)

After H is at risk, L is deposited and a nitriding wall 86 is left, thus generating 0·2F. The steps are based on the reference to the first embodiment at 2F, 2G, 2J. : Execute in the same way. Thereafter, as described with reference to Fig. 2J, the +, bismuth layer is deposited, and the two-rolled ruthenium layer is for the nano. \ is selectively etched to the surface of the crucible 1 〇 to 1 0 〇 to 1 2 0 二 二 做 做 做 做 做 做 做 。 。 。 。 。 。 。 。 。 。 。 。 。 Thereafter, 15 is performed, i is engraved to thin the continuation, wherein the edge is engraved 10 on each side - thus becoming a fin shape that is eventually 30 nm wide. Deposition-ΪZ is used after the thermal oxidation step of the growth-depletion pole oxide 8G. 440 0米米厚度, a multi-layer layer doped with phosphorus in the original place (there is no obvious "Xi Shixi material fills the groove portion and the groove, so as to explain the two types of flat parts of the pole." The surface portion of the gate is removed from the multi-layer layer, and the yttria layer is removed from the region between the word line 852. Then, the implementation is performed. The implantation step of the drain 1 2 1 , 1 2 2 闵μμ is filled with a cerium oxide layer 183 and a planarization step is performed, and the structure described in the third drawing is applied.

Page 30 1279831 V. Description of Invention (25) After that, the tungsten layer is recessed in the multi-coffin = second material 852 and deposited and planarized and etched. Connected to a space above 852 and above the surface, wherein the poly-, bis-niobium nitride layer is filled in the tungsten line to the tantalum nitride layer 81_insulating/52 is the tungsten line 8 Coverage, which uses the 3D diagram to describe the formation of the cell to the word line 8 and is spoken by the master. A phantom plane diagram, as seen from this figure, in a subsequent step, the direction defined by area 12 is vertical. Defining the bit line and the stacking electrical = 1 吏 a strip mask 6 is formed for | ' as in Figure 3E; to the valley contact window area. The special portion of the yttrium oxide material, combined, and selectively etched in the photolithography. The different statement is that 誃^ is formed in the open position at the position marked by X, but does not form a talk word - in the area below the mask opening 6, however, it can be cleared d:: the: word mark only Formed along the 乂 to v to the relevant area.疋 After these openings are also on the outside of V to V, the implantation step is performed to deposit a layer of conductive material. Finally, the nitride is covered by 8 turns. &quot; The opening 6. The layer is planarized to form the structure in FIG. 3F. As seen from the 3F figure, the pass: the second assist structure, and the contact for the bit line contact 41 in the roll The assisted contact window of the stacked capacitor is in the next step, and the known method lithography defines the bit to start after the germanium layer 91' and utilizes the °, friend contact window opening. In the cerium oxide

Page 31 1279831 V. INSTRUCTION DESCRIPTION (26) After the associated opening is formed in layer 91, the opening is filled with a conductive material to the two-dimensional contact window 61. After a planarization step, a known crane layer 1 2 3 4 5 6 7 is used with a nitride layer &amp; Thereafter, the crane layer 7 is formed by a smear pattern to form a sidewall spacer after a strip extending in a direction parallel to the (four)v connecting line. 1 A sidewall spacer is formed by a generally known method (a structure not formed) In the line of Figure 3, the external contact is used. In the definition of the bit line contact window 61, the memory cell =: face diagram. As can be seen, the bit is visible. The line contact window 61 is at the left side of the vertical portion of the active region 12. One bit line is connected from 6 1 疋 for the formation of two adjacent memory cells. Figure 31 depicts the memory after defining the bit line 9 The cell array t-plane/n is not located at line 7 is formed perpendicular to the word line 8. The bit 9疋 is deposited over the bit line contact window 61, and in a planar illustration, they are formed between Adjacent to the space between the active areas 12. 1 ί : The team t rushes to the space between adjacent bit lines, which is filled with layers, and planarizes the formed structure. 2 The capacitor in the stack is connected to 3, and the opening, like a touch window, is filled with (4) a known ancient if material. In this step, the 4:: one: Γ the layered capacitor 4. In particular, the -5 sense:), and the - capacitor contact window is connected to the 6-pole. Finally, the internal power supply is provided, and the mouth structure is described in FIG. 3 j. As can be seen in the description of the invention (27), since the first and second source/drain regions are deposited adjacent to the surface of the substrate, an electrical contact window to the stacked capacitor can be easily completed. Figure 3K depicts a planar illustration of the array of hidden cells after formation of the capacitor contact window structure 42. In particular, the capacitor contact window mask 43 has a strip opening that is perpendicular to the bit line 9. Since the bit line material is selectively etched for filling the yttrium oxide between the bit lines, a hole-like opening is formed. The opening is opened below the strip 43 and formed above the active region 12 to contact the first source/drain region 112. Figure 3L depicts the memory cell_plane diagram after defining the stacked capacitor 4. The stacked capacitors 4 are arranged in a checkerboard pattern because the stacked capacitors of the two adjacent columns are arranged in an interleaved manner. Figures 4A through 4J disclose a third embodiment of the present invention in which a memory cell array includes the transistor of the present invention which has been described with reference to Figures 1 B and 1 C and forms a stacked capacitor. In particular, according to this third embodiment, the trench for the gate is formed in an earlier step. The upper portion of Fig. 4A depicts a plan view on the array, and the lower portion of Fig. 4A depicts a cross-sectional view. In particular, the left-hand side of the cross-sectional illustration is depicted as depicted in the upper portion of Figure 4A, with a cross-section between VI and VII, and the right-hand side of the lower portion is depicted between Lu and I. Cross section between VII. In order to perform the third embodiment of the present invention, first, a pad oxide layer (not shown) and a tantalum nitride layer 17 are deposited on the surface 10 of the semiconductor substrate 1 of the substrate 1, in particular. . Thereafter, the active region 12 of the memory cell is defined by a known method of photolithography, and the sweet insulating trench 2 3 is

Page 33 1279831 V. Description of the Invention (28) Etching in a conventional manner to expose the active region 12 . The sidewall of the active region is oxidized and the insulating trench 23 is filled with an insulating material, particularly a dioxide chopping layer. The formed surface is planarized. The structure formed is described in the lower portion of Fig. 4A, and the upper portion of Fig. 4A. A plan view on the array is described. As can be inferred from the upper portion of Figure 4A, the wiring connecting VI and VII intersects the active region 12, and the wiring connecting VI I and VI II intersects the insulating trench 23, also in the active region 1 2 The smaller side intersects it. In this second step, the tantalum nitride layer 17 and the lower if hafnium oxide layer are removed by etching. Thereafter, a thermal oxidation step is performed to grow a sacrificial oxide layer on the exposed germanium portion. Thereafter, a planting step is performed to extract the desired doping well region. As an alternative step, another implantation step can be performed to extract the lightly n-doped first source/drain region 1 2 1 '. Thereafter, a hard mask layer or layer stack is formed to define the gate trench. For example, the hard mask layer may comprise a first layer 71 of polysilicon or carbon and a second layer 72 such as a photo-resistive material or carbon. The hard mask layer stack is patterned using a strip mask having a strip width of less than 1 F. Finally, the mask layer stack is etched to expose the _-plate at the trench portion. As can be seen from Fig. 4, the insulating material of the insulating trench 23 protrudes from the surface of the crucible because the STI surface portion has been coplanar with the pad nitride layer 17 in the step of previously planarizing the surface. Therefore, after the pad nitride layer 17 is removed, the insulating material of the insulating trench 23 protrudes

Page 34 1279831 V. INSTRUCTIONS (29) or extending from the surface of the crucible 1 〇. During the discharge of the A &amp; layer, the insulating trench = 2: the spacer nitride and the spacer gas are the same as the material from the upper portion. The part of .• is speculated in a groove 7 area; it is in the area between ¥11 and VI11. —, for s, the trench has been etched in the trench 23 of the insulating material = ' to (d) in the insulating barrier layer 72, and another 1 = ^ is performed. Thereafter, the groove portion 7 in the second hard type i is removed. In particular, it is good to engrave the substrate material

Below the surface, about 40 to 15 〇 = = gh; the 疋 is etched to the substrate ^ 〇 7p 〇 waterless ice. The width of the groove 73 is 0. E 式 ί ί Ϊ = t to avoid the square ήΛ ^ ^ ^ ' of the sharp corner below the groove 73. It is particularly preferred that these corners are in Figure 4C

The position of the day of the day is rounded. As can be noted from the V I I and V I I I II in Fig. 4, the 杈 杈 , , , , , , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Then, an etching step of performing an isotropic etch is performed. The etched step sleeve can be a wet or dry etch step, such as a chemical downstream etch (CDE, chemical d (10) nsheam • fh). Thereby, the groove formed in the hard mask layer 71 is laterally stretched by the groove 7 3 which is also formed in the multi-turn material. In particular, the diameter of the trench is extended by 〇· 2 f and additionally as depicted in the cross section between VI丨 and VI丨丨 in Figure 4C, possibly, in a trench 7 3 and the residual 77 7 generated between the adjacent insulating trenches 2 3

1279831 V. Description of invention (30) Removal. The resulting structure is depicted in Figure 4D. As can be inferred from the upper part of the 4D figure, the width of the vertical strip has been widened. The final width of the trench (CD, critical dimension) is now 0·9F. In the next step, a wet type engraving of the sulphur dioxide is performed. The exposed oxide region can be etched by this isotropic etching. Therefore, the groove in the insulating trench described in the left-hand side of FIG. 4E is widened and deepened, and the portion between VII and VIII is formed in the insulating material of the insulating trench 23. Groove structure 74. The dimensions of these grooves 74 are the % of the stomach referred to by the fracture line surrounding the groove 73 in the cross-sectional illustration between VI V I I . In particular, the groove structure 74 is formed around the fin region 11. Since this step is carried out in a wet etching step, the formation of the groove structure is performed in alignment with the groove. Next, an anisotropic ? is performed to further etch the cerium oxide. In particular, approximately 25 nanometers of cerium oxide is etched, so the total depth of the grooves 7 4 amounts to 40 nanometers below the groove. Therefore, as can be seen from the cross section of the 4F between V I I and V I I I , the depth of the fin-shaped region 1 1 is approximately 40 nm. This is also depicted in the left hand side of the figure, between V I and V I I , as indicated by reference numeral 7 4 ''. The area previously etched by the isotropic step is indicated by reference numeral 7 4 '. The height of the oxide surface in the right hand side of the figure is indicated by the fracture line 75. As an optional step, another etch step can be performed to thin the fin region 11 . By this selective anisotropic etching step, the etching is partially deepened but not widened.

Page 36 1279831 V. INSTRUCTIONS (31) In the next step, a gate oxide 80 is thermally grown in a known manner. In the 4Gth diagram, the portion 80' indicated in the cross-sectional view between VI and VI I indicates the gate oxide portion grown above the region 7 4 ', which corresponds to A cross section taken from another plane before or after the described plane. In addition, a multi-layered layer 187 forming the gate is also deposited by known methods. In the next step, the gate material of the gate material 187 is isotropically etched to a depth of about 40 nm below the crucible surface 10 . Thereafter, as an optional step, an angled implant for providing a slight η-doped first source/drain g domain 1 2 可执行 can be performed, and the trench can be exposed by using this method. section. In the next step, a layer of nitride layer is deposited and inscribed to form a partition wall 86. The partition wall has a thickness of about 0.2 F. The step ’ also forms a partition wall portion 8 6 ' between V I I and V I I I. The resulting structure is described in Figure 4H. Thereafter, the exposed portion 801 of the ceria layer is etched. Next, a plurality of layers 81 1 are deposited to fill the space between the nitride spacers 86. Thereafter, a structure in which a tungsten layer 8 2 and another tantalum nitride layer 8 1 〇 φ are deposited in a generally known manner is described in Fig. 4I. In the next step, the character line is patterned. Before the patterning of the word line, a step of implanting to define the first and second source/drain regions may be performed to form the first and second source/drain regions 1 2 1 , 1 2 2. This implantation step is also performed after defining the word line.

Page 37

1279831 V. Inventive Description (32) In order to pattern the word line, the tantalum nitride layer is first etched to form a strip-like portion 81a, and then the tungsten layer 82 is etched to form 'the last name of the stone. The layer 811 thus forms a gate stack. When the multi-layer 8 1 1 is used, special treatment must be employed, that is, an over-etching step is usually performed, and does not extend to a deep depth because the formed transistor will be degraded. In particular, an excessive depth of the surface of the crucible of the crucible of 2 to 3 nanometers is often considered to be the maximum depth of 2 seconds. w excessive eclipse as another alternative 'The source has no polar domain can also be defined here. Processing Time The resulting structure is described in Figure 4J. After stepping, the processing of the processing of the memory cell, which is usually used to complete the memory cell array, will be performed similarly to that described in relation to the 3F to 3L diagrams. Figure 4 is inserted in the figure: 'very obvious in the 4th figure, the (2) element line = the depth of the pair of ... word lines in the composition; This = in the same manufacturing process. In particular, since it is not found, according to the third embodiment, first, the Z-groove portion '(4) is etched in an isotropic step to: those portions where the gate is not formed The: This STI is filled. / Re-wooding - To be more specific, according to the third embodiment, first, the tantalum/niobium nitride is selectively etched. Thereafter, an isotropic etch is applied to the ruthenium, and then the yttrium oxide is anisotropically etched. According to this, it may be defined close to

Page 38 1279831 V. INSTRUCTIONS (33) The pass surface of the substrate passes the word line 8 b. Therefore, the active area 12b' disposed near the pass word line is not affected by the pass word line. In a different manner, a parasitic transistor functioning as a charge pumping device is typically formed in the active region 12b disposed adjacent to the pass word line. In particular, a trap present at the interface between the single crystal germanium and the tantalum dioxide layer of the insulating trench 23 may cause a direct current that interferes with the memory. Therefore, as described in Fig. 4J, the pass word line 8b does not extend to such a deep depth, and this problem can be avoided. _ As described in Figure 4J, the first source/drain region includes a lightly doped portion 1 2 1 '. Of course, this slightly doped portion can be omitted. The fourth embodiment of the present invention is only a dynamic random access memory (DRAM) memory cell array including a capacitor implemented as a stacked capacitor, and the electric power described with reference to FIGS. 1A and 1B. Crystal. In the memory cell array of the fourth embodiment, since the pass word line is disposed on the surface of the semiconductor substrate 1, the influence of interference by the word line can be further reduced. To be more specific, according to the fourth embodiment, first, the groove is defined in the insulating trench, and the portion of the insulating trench where the groove is not shaped is masked. After that, the groove portion is defined. The pass word line may be disposed on the surface of the substrate by a continuous manufacturing step. The first step in this step is to refer to the description of Fig. 4A, so the description is omitted. After defining the active region 12 and the insulating trench 2 3, the nitrogen is removed

1279831 V. Description of invention (34) 矽 layer 1 7 A thermal oxidation step is then performed to grow a sacrificial dioxide layer 18.1 . The implantation step is then performed to provide the doped well portion that is typically present in a memory cell, and the most optional step is to perform a LDD implantation step to define the first and first source/no-polar regions Lightly doped part. Thereafter, a layer of nitride 188 is deposited in a generally known manner. In a single step, a multi-layer layer 51 is deposited in a generally known manner. On the surface of the multi-layer layer 51, an optical impedance extension 52 is deposited, and the photo-resistive layer 52 is photolithographically formed to form an opening 5 3 having a length 4F and a width 1 F. Thereafter, the multi-layer layer 5 1 is left, so that the opening 5 3 also penetrates the multi-layer layer 5 &gt; The formed structure is described in FIG. 5A, wherein the lower portion of the 5th AK describes a cross-sectional view The upper portion of Figure 5A depicts a planar representation of the array of memory cells. The complex active regions 1 2 are arranged in columns, while the adjacent columns are separated by insulating trenches 2 3 . The segment active area portion 丨2 of a particular column is also insulated from each other by the insulating trenches 2 3 . The complete memory cell array is covered by a layered stack comprising the multi-layer layer 51 and the optical impedance layer 52, except for the central portion of the active region 12. In the upper portion of the fifth figure, the points VI, VII, and VII I are irons taken along the cross-section of the image portion. The active region 12 and, in particular, the opening 5 3, traverse the direction from v丨 to. Thereafter, a similar step as described with reference to FIG. 4B is performed. Specifically, a carbon hard mask 7 1 is deposited, and then a photoresist layer 7 2 is deposited. Thereafter, the trenches for the gates 85 are defined by the lithography of the general use steps. In the picture

Page 40 1279831

After the photoresist layer 7 2 is formed, the carbon hard mask 71 is etched and the trench 7 is formed. V. DESCRIPTION OF THE INVENTION (35) As can be seen from Fig. 5B, above the active region 12, the trench 'slot 7 extends to the surface of the tantalum nitride layer ι88, and the trench is formed on the insulating trench The groove stops on the multi-turn hard mask portion 51. ^ In this first step, an etching step for selective ruthenium oxide and tantalum nitride etching of tantalum, niobium and carbon is performed. Therefore, the exposed portion of the SiO2 layer 1 8 1 and the tantalum nitride layer 184 will be etched. Accordingly, in the cross section between VI and VII, the surface of the crucible substrate will be exposed in the trench portion, and the cross-section portion between V丨I and V丨丨丨The recess 74 will be etched around the active region 丨2. The position of the groove between v and v is indicated by a broken line 7 4 '. The duration of the etching step will coincide with the desired depth of the gate-like plate portion. This is described in Figure 5C. In this second step, the trench portion of the gate 825 will be defined. A special 'system pair' is anisotropically selectively etched by the cerium oxide to define the trench 73. The depth is about 8 〇 nanometers below the surface of the raft. By this step, preferably, the remaining portion of the multi-turn hard mask layer 5 1 will be removed. As an optional step, an additional isotropic etching step can be performed: etching the germanium, thereby thinning the fin region u. The hard mask portion 71 is etched by selective etching or by a ashing (aShing) step in the oxygen plasma. The resulting structure is depicted in Figure 5D

Page 41 1279831 V. INSTRUCTION DESCRIPTION (36) As seen in the cross section between V I I I, the recess 74 is formed in the ceria layer. Between the grooves 74, there is a fin portion having a smaller width than the underlying crucible material. Above the fin portion 11, the crucible material is recessed to form the trench 73. According to a fourth embodiment of the invention, the trench 7 3 - can also be etched at a portion where the recess 74 has previously been defined. Accordingly, the components of the gate are formed in a self-aligned manner. In a single step, a sacrificial oxide layer is selectively thermally grown and then removed to fill the hole. Further, an implantation step is performed to form the first and second source/drain regions 1 2 1 , 1 2 2 . Thereafter, the gate oxide layer 80 is grown in a conventional manner. In one step, a multi-layer layer 187 is deposited. The resulting structure is described in Figure 5E. Thereafter, the multi-layer layer 187 is etched to form a recess extending to about 40 nm below the surface of the crucible. As an optional step, an angular array implantation step (LDD implantation) can be performed to form a slight n-doped source/drain region that is self-aligned with the spacer depth. The resulting structure is described in Figure 5F. In this second step, the inner partition wall 86 will be formed. The partition walls used in this processing step can be made of ruthenium dioxide as compared with the previously described embodiments. The use of cerium oxide is advantageous because dioxin has better screen properties than tantalum nitride (S i 3 Ν 。. Therefore, in the active region 12, the word line and other adjacent conductive portions The cross-talking can be reduced. Since tantalum nitride is easier to handle, tantalum nitride is generally used as the partition material. According to the fourth embodiment of the present invention,

Page 42 1798831 V. INSTRUCTIONS (37) A good manufacturing procedure, niobium oxide can be used instead of tantalum nitride (Si D. The partition 86 has a width of 〇·2F to 0·3F, which is the curtain The resulting transistor is related to the width of the transistor. After the structure is formed in FIG. 5G, another multi-layer 811 is deposited as described in FIG. 5H. Next, similar to that described in FIG. The method defines the word line. First, a heave layer 82 and a tantalum nitride cover i are deposited by known methods (see Fig. 51). Thereafter, the light lithography pattern is layered to form a top layer having The tantalum nitride covers a single word line 8 2 of 8 1 a. This is described in Fig. 5 j. In the next step, a tantalum nitride layer is deposited and etched to form a TO partition 81b. Thereafter, an HDD implantation step for forming the first and second source-level pole regions 1 2 1 , 1 2 2 may be performed. Thereafter, a step generally performed to complete the memory cell array is performed. a step of the first to the elaboration to provide the bit line, the bit line is in contact with the stacked capacitor Also in contact with the connector between the stacked capacitor and the first source/drain region, domain 1 2 1. When comparing the structure described in the 4th J with the structure described in FIG. 5K, It can be inferred that the pass word line is disposed on the surface of the substrate, and is separated from the adjacent active area 12 in one step. In particular, the pass line jb does not extend into the base substrate! In the structure and arrangement of the adjacent active region, the structure is made of sulphur dioxide, and in the 4th figure, it is made of chaotic stone eve. No. 35 ′ according to the fourth embodiment of the present invention, the partition wall

1279831 V. INSTRUCTIONS (38) 8 6 can also be made of tantalum nitride. Although the first source/drain region 1 2 1 is only described as a region in FIG. 5K, it is apparent that the first source/drain region 1 2 1 may also include the fourth J-map. The same lightly doped portion 1 2 Γ and a heavily erbium doped portion 1 2 are described. Further, as also described in FIG. 4J, the second source/drain region 1 2 2 can be extended to A deeper depth. Figure 6 shows a plan view of an exemplary memory device that can be fabricated using the method of the present invention. In the central portion of Fig. 6, the memory cell array including the memory cell 100 is displayed. As is well understood, the particular configuration of the memory cell array can be arbitrary. In particular, by way of example, the memory cell 100 can be configured as a checkerboard pattern or other suitable pattern. As shown in Fig. 6, a memory cell array is configured such that a single memory cell 10 has an area of 8F2 (4F X 2 F), so that it can be performed in a cross bit line configuration. The memory device of Fig. 6 further includes the peripheral portion 99. Typically, the peripheral portion 99 includes the core circuit 197. The core circuit 197 includes a word line driver 96 for addressing the word line 8 and an inductive amplifier for sensing the bit line 9 transmission signal. . The core circuit 97 typically includes other means for controlling and addressing the individual memory cell 100. The peripheral circuit 9 9 further includes a support portion 98 that is generally external to the #heart circuit 909. When the shrinking basis rule (shrinkinggr 〇un dru 1 e) of the dynamic random access memory (DRAM) memory cell is obtained to obtain a minimum structural feature size F of less than 100 nm, the word line voltage and the bit are The line voltage cannot be scaled to the same extent, especially because of traditional inductive amplifiers.

Page 44 1279831

However, in order to obtain a higher power', the core circuit is over, and the chip size of the core circuit is increased. In addition, the same spacing of the individual memory cells is generated to reduce the size of the word line driver. As the transistor of the inventor of the present invention is also provided in the peripheral portion core circuit 97, the reduction can be simultaneously satisfied. need. The pressure must increase the electric θ cloud storm, and the size of the wafer required for daily body length increases. Does not cause during the shrinking process = circuit 9 7 components need to be configured to pass. Accordingly, it is required, for example, to find that, in accordance with the present invention, in particular, the transistor length of a memory device increases with the wafer size if the transistor of the present invention is used as the dynamic random access memory. An array of access cells of memory cells and surrounding portions of the memory device can use the same processing flow to simultaneously form transistors in the memory cell array and the surrounding portion, except to form the The first is different from the source of the brother /> and the polar region 'and the implementation of the well planting and channel planting. Therefore, the general sister will not increase the complexity of the process. By using the transistor of the present invention in the surrounding portion, a high voltage device can be used in the core-heart circuit without sacrificing reliability limitation and consumption of crystal

1279831 V. Description of invention (40) Area of the film. While the specific embodiments have been described and described herein, it will be understood by those skilled in the art that a <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; In a particular embodiment. This application is intended to cover any adaptations and variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the scope of the application and the equivalent. Page 46 1279831 BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A through 1C depict an exemplary embodiment of a transistor of the present invention. Figures 2A through 2W depict an exemplary embodiment of a memory cell array of the present invention. 3A to 3L are diagrams depicting another exemplary embodiment of the memory cell array of the present invention&lt;4A to 4J depicting another exemplary embodiment of the memory cell array of the present invention (Fig. 5A to 5K) Another exemplary embodiment of an inventive memory cell array (Fig. 6 depicts a plan view of a memory device in which the transistor of the present invention is used. Main element symbolic description: I 0 substrate surface II a top side 12 active region of the ridge 1 semiconductor substrate" 1 fin region 1 b lateral side 12a of the ridge portion adjacent to the active region 1 1 1 through the word line, the first source/drain region 1 2 Γ lightly doped first source/drain Region 1 2 1 '' heavily doped first source/drain region 1 2 2 second source/drain region 1 2 5 narrowed fin region 1 4 channel 1 5 current path 15a, 15b, 15c current path Composition 1 6 transistor #8 1,1 8 1 'sacrificial oxide 1 8 3 cerium oxide layer 2 insulated trench 3 trench capacitor 3 2 insulated collar 17 pad nitride 1 8 2,1 8 6,1 8 8 tantalum nitride layer 184, 185, 187 multi-layered layer 2 3 insulated trench 3 1 internal electrode 33 buried

Page 47 1279831 Brief description of the diagram 3 4 Ditch top oxide 3 6 more stone eve filler 3 8 surface band 41 assist contact window 43 capacitor contact window mask 5 2 hard mask layer 6 1 bit line contact window 7 groove Slot mask opening 7 2 optical impedance layer 7 3 ' ί 夕 414 ' 'extending groove structure 8 word line 8 b through word line 8 1 a tantalum nitride covering 8 0 1 cerium oxide layer 8 2 crane layer 8 5 gate 8 5 2 trench region 8 54 defines GC region &amp; 7 internal partition wall 90 bit line contact window assist structure 9 2 bit line insulator 94 second contact window region 9 6 word line driver 3 5 strip mask opening 3 7 strip tantalum nitride partition wall 4 stacked capacitor 42 capacitor contact window 5 1 hard mask layer 6 contact window area mask opening 6 2 bit line insulation layer 7 1 multi-layer hard mask Layer 73矽 Trench 74, 74' Groove Structure 7 5 Oxide Surface 8 a Function Word Line 80 Insulator 8 1 b Tantalum Nitride Partition 8 1 1 Multilayer 8 3 GC Connection Line 851 Flat Area 8 5 3 GC mask opening 8 6 GC internal partition 9-bit line 9 1 bit line insulation layer 93 first contact window area 9 5 inductive amplifier 97 core circuit

Page 48 1279831 Brief description of the diagram 98 support circuit 1 0 0 memory cell 99 peripheral part Φ • 111111第49页

Claims (1)

1^79831 $, Patent Application No. 1 - A type of transistor, at least partially formed in a semiconductor substrate, comprising: - a first source/drain region; a * first contact window region For connecting the first source/drain region to the storage capacitor electrode; - the second source/drain region; - the second contact window region for connecting the second source/drain region and the - Yuan line a channel region connecting the first and second source/drain regions, the channel region being located in the semiconductor substrate and having a connection connecting the first and second source/drain regions Defining a first direction and a gate, the edge of the child is configured to be electrically insulated from the channel region by a gate insulating layer, the gate being controlled by the first I source/drain The current flowing between the regions is transmitted by -2 ^ A. The channel region is white, and the fin region (fin-regi〇n), where 兮9匕, and the gate is disposed in the region a ridge shape connecting the three sides of the first and second contact window region regions, wherein the vertical region, a horizontal region, and a first current path include/the first vertical region, the square-vertical region of the current a component in the direction having a first vertical-horizontal component in the horizontal region and a component having a second vertical direction in the direction of the current in the second vertical direction, the current being current The direction of the second vertical direction is opposite. The first vertical direction is an electro-optic crystal according to the first item of the patent application, and further includes a partition wall made of an insulating material of the patent application scope of 1,297,831, the partition wall being disposed at the gate and the current An interface between the first and second vertical regions of the path and having a thickness greater than the gate insulating layer. 3. The transistor of claim 1, wherein the first and second source/drain regions are disposed in the first and second vertical regions, respectively. 4. The transistor of claim 1, wherein the channel region has a width smaller than a width of the first and second source/drain regions, the width being perpendicular to the first direction and parallel to the semiconductor Measured in a surface direction of the substrate. 5. A transistor, at least partially formed in a semiconductor based plate, comprising: a first source/drain region connected to an electrode of a storage capacitor; a second source/ a drain region connected to a bit line; a channel region connecting the first and second source/drain regions, the channel region being located in the semiconductor substrate, and connecting the first and second sources The wiring of the pole/drain region defines a first direction; and a gate disposed along the channel region and electrically insulated from the channel region by a gate insulating layer, the gate being controlled by the first and the first a current flowing between the two source φ pole/drain regions, wherein the channel region includes a fin region, wherein the channel region has a ridge shape, the ridge portion being included in a cross section perpendicular to the first direction A top side and two side sides, wherein the top side is disposed under a surface of the semiconductor substrate, and the gate is disposed along the top side and the side portions. 1279831___ VI. Patent Application No. 6: The transistor of claim 5, wherein the distance between the top side and the surface of the substrate measured in a direction perpendicular to the surface of the substrate is 10 to 200. Nano. 7. The transistor of claim 5, further comprising a partition wall made of an insulating material, the partition wall being disposed between the gate and the first and second source/drain regions Interface. 8. The transistor of claim 5, wherein the first source/drain region comprises a heavily doped region and a lightly doped region, the lightly doped region being disposed in the heavily doped region Between the channel area and the channel. 9. The transistor of claim 8 wherein the lightly doped region @ extends to a depth below the top side of the fin region. 10. The transistor of claim 9, further comprising a partition wall made of an insulating material disposed between the gate and the first and second source/drain regions Between the interface. 1 1. The transistor of claim 10, wherein the heavily doped region is above the lightly doped region and the spacer extends to a depth corresponding to the depth of the heavily doped region. 1 2. The transistor of claim 5, wherein the first source/tin region extends to the same depth as the second source/drain region. The transistor of claim 7, wherein the insulating material of the partition is selected from the group consisting of cerium oxide and tantalum nitride. 1 4. The transistor of claim 5, wherein the width of the channel region is less than a width of the first or second source/drain region, wherein Page 52 1279831 _______ VI. Patent Application Scope The width is measured in a direction perpendicular to the first direction and parallel to the surface of the semiconductor substrate. , a memory cell array comprising a plurality of memory cells, a complex bit line disposed in a first direction, and a complex disposed in a second direction crossing the first direction &quot; a digital element line, each of the memory cells comprising: a storage capacitor; a transistor formed at least partially in a semiconductor substrate, the transistor comprising: a first source/drain region, and the storage An electrode of the capacitor is connected to a second source/drain region; a channel region connecting the first and second doped regions, the channel region being disposed in the semiconductor substrate; and a gate Arranging along the channel region and electrically insulated from the channel region, the gate controlling a current flowing between the first and second source/drain regions, wherein the channel region includes a fin region, wherein the channel region The channel region has a ridge shape including a top φ side and two side sides in a cross section perpendicular to the wires connecting the first and second source/drain regions, wherein the top side is configured On the semiconductor substrate Under a surface, and the gate is disposed along the top side and the side portions, wherein each of the word lines is electrically connected to a plurality of gates, and wherein the second source/汲 of each of the transistors The polar region is connected to one of the bit lines through a one-dimensional contact window. Page 53 1279831__ VI. Patent Application Range 16. The memory cell array of claim 15 of the patent application, wherein the storage capacitor is a trench capacitor. • 17. The memory cell array of claim 15 wherein the storage capacitor is a stacked capacitor. 18. The memory cell array of claim 15, wherein the memory cells are respectively disposed in a matrix, and the storage capacitor and the transistor are configured as a checkerboard pattern such that the transistor and the transistor A first location is associated with the storage capacitor and a second location, one of the first locations being disposed between the two of the second locations, and vice versa. 9. The memory cell array of claim 15, wherein the memory cells are respectively disposed in a matrix, and the storage capacitor and the transistor are arranged in pairs such that the two storage capacitors are in phase with each other In the adjacent configuration, the two transistors are arranged adjacent to each other, and the two adjacent memory cells share a common bit contact window. 20. The memory cell array of claim 15 wherein each of the word lines comprises a complex pass word line portion, wherein the word line is not connected to a gate, the pass word line portion is It is disposed at a depth of the substrate that is less than the depth of the gate. The memory cell array of claim 15, wherein each of the word lines includes a complex pass word line portion, wherein the word line is not connected to a gate, and the pass word line portion is disposed On the surface of the substrate. 22. A method of fabricating a transistor in a semiconductor substrate, comprising: Page 54 179831 6. The patent application scope provides the semiconductor substrate having a surface; defining an insulating trench in the surface of the semiconductor substrate to laterally confine an active region, wherein the transistor is in two insulated trenches The laterally confined active region is formed; 'filling the insulating trench with an insulating material; providing a gate insulated from the active region by a gate insulating material; providing a first and second source/drain a region, wherein a conductive path is formed between the first and second source/drain regions to define a first direction of wiring connecting the first and second source/drain regions; wherein a gate is provided The step of: defining a trench extending from the surface of the semiconductor substrate perpendicular to the surface of the semiconductor substrate to a first depth in the active region; and then adjacent to each of the insulating trenches a position of the groove defines a groove such that the two grooves are to be connected to the groove, and the groove is disposed between the two grooves, the two grooves extending to be greater than the first depth a second depth; a gate insulating material is provided between the active region and the interface between the active region and the interface; and a gate material is deposited to fill the trench a slot and the two recesses; the gate material is partially removed such that the gate material is removed from the trench and the outer portions of the recesses. 2 3 · If the method of applying for patent item 22 is further included, it will be parallel to 1279831 VI. Patent application scope The step of thinning the active region between the first and second depths of the substrate surface and the direction perpendicular to the first direction. The method of claim 2, further comprising the step of providing a partition wall laterally confining the groove in a direction parallel to the first direction, the partition wall being An insulating material is formed, and the step is performed after the step of defining the trench and before the step of defining the recess. The method of claim 2, wherein the two grooves are defined by an isotropic etching. The method of claim 2, wherein the gate electrode material is partially removed and the top portion of the gate material in the trench and the two recesses is removed, and further comprising a a step of partitioning the trench laterally confining the trench in a direction parallel to the first direction, the spacer being made of an insulating material and providing a spacer wall in the portion The step of removing the gate material is performed. 2 7. A method of fabricating a transistor in a semiconductor substrate, comprising: providing the semiconductor substrate having a surface; defining two insulating trenches in the surface of the semiconductor substrate to be laterally φ-limited to form therein An active region of the transistor, the active region is laterally limited by two insulated trenches; the insulating trench is filled with an insulating material; and a gate is provided, which is insulated from the active region by a gate insulating material. 1279831__ 6. The patent application scope provides a first and second source/drain regions, wherein a conductive path is formed between the first and second source/drain regions, and the first and second are connected The wiring of the source/drain region defines a 'first direction; ' wherein providing a gate includes: defining a groove in each of the insulating trenches, the two grooves extending to a second strike depth; and then, adjacent Forming a groove in the active region at a position of the groove portion, such that the groove is disposed between the two grooves and electrically connected to the two grooves, the groove being perpendicular to the surface Extending from the surface of the semiconductor substrate to a first depth, wherein the second depth is greater than the first depth; the interface between the active region and the trench and between the active region and the recess The interface provides a gate insulating material; depositing a gate material to fill the trench and the two recesses; partially removing the gate material such that the gate material is from the trench and the recess The outer portion of the slot is removed. The method of claim 27, further comprising thinning the active region portion of the portion between the first and second depths in a direction parallel to the surface of the substrate and perpendicular to the first direction A step of. The method of claim 27, wherein partially removing the gate material and removing the top portion of the gate material in the trench and the two recesses further comprises the step of providing a spacer wall, The partition wall laterally confining the groove in a direction parallel to the first direction, the partition wall being made of an insulating material, the step being partially shifted Page 57 1279831_ VI. Scope of application for patents Except for the steps of the gate material. « 111111第58页