TWI278984B - Electronic component and fabricating the same - Google Patents
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【發明所屬之技術領域】 本發明是有關於一種高效能之積體電路的製作,且特 別是有關於一種形成比如是電感元件之高效能的電子元脊 於晶片之表面上的方法,可以降低因為晶片所導致的電磘 才貝耗。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of a high-performance integrated circuit, and more particularly to a method for forming a high-performance electron ridge such as an inductor element on a surface of a wafer, which can be reduced. Because the electricity caused by the wafer is consumed. [Prior Art]
半導體技術持續所追求的目標係能夠在具競爭性的償 格下製造出高效能的半導體元件。隨著半導體製程及材料 的研發,再配合新型且精緻的元件設計,如此半導體元件 的^寸可以大幅縮小。大部分的半導體元件係用來處理數 位資料,然而也有部分之半導體元件整合有類比的功能, 如此半導體元件便可以同時處理數位資料及類比資料,或 者半導體元件亦可以僅具有類比的功能。製造類比電路的 主要困難點之一是在於許多用於類比電路的電子元件甚 大’難以與次微米極的電子元件整合,尤其是針對電容元 件及電感元件而言,此乃因為電容元件及電感元件的尺寸 過於魔大。 一般而言’電感元件係應用在移動通訊的領域中,比 |如疋應用在配置有射頻放大器(RF amplifier)之半導體元 件上’而射頻放大器主要包括有調整電路(tuned circuit) ’其中調整電路具有電感元件及電容元件。調整 電路之電感元件的電感值、電容元件之電容值及頻率均會 影響由調整電路所產生的阻抗,針對某一頻率的訊號,調 整電路可以是具有高阻抗的或是低阻抗的。調整電路可以 阻隔或導通訊號之傳導,並且依照元件的頻率,調整電路The goal pursued by semiconductor technology is to be able to manufacture high-performance semiconductor components under competitive compensation. With the development of semiconductor processes and materials, coupled with new and sophisticated component designs, the size of such semiconductor components can be significantly reduced. Most of the semiconductor components are used to process digital data. However, some semiconductor components have integrated analog functions, so that semiconductor components can simultaneously process digital data and analog data, or semiconductor components can have only analog functions. One of the main difficulties in manufacturing analog circuits is that many of the electronic components used in analog circuits are very large. It is difficult to integrate with sub-micron pole electronic components, especially for capacitive components and inductive components. This is because of capacitive components and inductive components. The size is too big. In general, 'inductive components are used in the field of mobile communications, such as 疋 applied to semiconductor components equipped with RF amplifiers' and RF amplifiers mainly include tuned circuits. It has an inductance element and a capacitance element. Adjusting the inductance of the inductive component of the circuit, the capacitance of the capacitor, and the frequency all affect the impedance generated by the trimming circuit. For a signal of a certain frequency, the trimming circuit can be either high impedance or low impedance. The adjustment circuit can block or conduct the conduction of the communication number, and adjust the circuit according to the frequency of the component.
第5頁 1278984 案號 93111830 五、發明說明(2) 還可以放大類比訊號。如此,調整電路可以作為濾波器之 用,藉以濾掉某一頻率之訊號或者是去掉由處理類比訊號 之電路所產生的雜訊。利用LC共振的原理,調整電路亦可 以產生高的電子阻抗,藉以抵消在部分線路中之寄生電容 效應、當電感元件形成於半導體基底之一表面上時,合產 生下述的問題,就是在螺旋狀之電感元件與位在下面^基 底之間所產生的寄生電容會有自我共振的效應,因此會限 制當在設計高頻電路時,電感元件的使用。另外,藉由電 感元件的設計,可以減少電感元件與位在下面之基底之 的電容耗合。 在高頻電路中,由電感元件所產生的電磁場會使得矽 土底内產生渦電流(eddy current)的現象。由於矽基底係 為-種電阻型導體’因此渴電流會損耗電磁能^,產生嚴 重的能量損耗’而形成一低品質參數之電感 ^共振頻率限制I頻率的上限。另外,由電感元件所產生 的满電流會干擾靠近電感元件之電路效能。金 性的原因,用來形成電感元件之細屬舍 吾,‘仏女各泌士、 ^ 也项深路亦會消耗能 量,如此亦會形成一低品質參數之電感元件。 ‘ 在製作高頻類比半導體元件時,必須要媒枇 元件,就是電感元件,#以形成LC妓接供-關鍵的 ^ ^ 兴振電路。在珣人主迷 會元件密度的趨勢發展,s此基底:面的 即使如此,電感元件還是形成在極小 情況下…般而言,形成在基底表 數的 + 1呈現螺&狀的樣式,此平面係平行於基麻夕| 1278984 案號 93111830 五、發明說明(3) 傳統製造電感元件於基底之表面上的方法有如下所述之限 制。大部分高品質係數的電感元件係配置在混合元件結構 (hybrid device configuration)中、單晶微波積體電路 (Monolithic Microwave Integrated Circuits ’MMICas)Page 5 1278984 Case No. 93111830 V. Description of the invention (2) The analog signal can also be amplified. Thus, the adjustment circuit can be used as a filter to filter out signals of a certain frequency or to remove noise generated by circuits that process analog signals. By using the principle of LC resonance, the adjustment circuit can also generate high electronic impedance, thereby canceling the parasitic capacitance effect in some lines, and when the inductance element is formed on one surface of the semiconductor substrate, the following problem occurs, that is, in the spiral The parasitic capacitance generated between the inductive component and the underlying substrate has a self-resonant effect, thus limiting the use of the inductive component when designing the high frequency circuit. In addition, by designing the inductive component, the capacitance of the inductive component to the underlying substrate can be reduced. In high-frequency circuits, the electromagnetic field generated by the inductive element causes an eddy current to occur in the bottom of the earth. Since the germanium substrate is a kind of resistive conductor, the thirst current will consume electromagnetic energy, resulting in a severe energy loss, and a low quality parameter is formed. The resonant frequency limits the upper limit of the I frequency. In addition, the full current generated by the inductive component can interfere with the performance of the circuit close to the inductive component. The reason for the gold is to form the details of the inductive components. ‘The prostitutes and the deeper circuits also consume energy, which also forms an inductive component with low quality parameters. ‘ When making high-frequency analog semiconductor components, it is necessary to use a dielectric component, that is, an inductor component, to form a LC 供 connection-critical ^ ^ 兴 电路 circuit. In the trend of the density of components of the main fans, this substrate: even if the surface is formed, the inductive component is formed in a very small case... In general, the + 1 formed on the number of bases exhibits a spiral & This plane is parallel to the base of the mat | 1278984 Case No. 93111830 V. Description of the invention (3) The conventional method of manufacturing the inductive component on the surface of the substrate has the following limitations. Most of the high quality coefficient inductive components are arranged in a hybrid device configuration, Monolithic Microwave Integrated Circuits 'MMICas
中或者疋由分開配置之元件所提供,然而上述電子元件之 製造係不易與積體電路製造之基本製程整合。若是將作為 類比資料控制及類比資料貯存之電路與作為數位資料控制 及數位資料貯存之電路整合並製造在半導體大型基底上, 則會達到許多顯著的優點,而整合的優點包括降低製造成 本及降低能量消耗。形成在半導體基底表面上之螺旋狀的 電感兀件由於受到實際尺寸的限制,會導致電感元件之線 路與下面基底之間產生寄生電容,並且受到位在下面之電 阻性矽基底的影響,電感元件會導致電磁能量損耗的發 生。當調整電路之共振頻率突然下降時,寄生電容會對LC 電路產生嚴重的負面效果。 值得注意的是,由電感元件所產生的電磁場會使得電 阻性之矽基底内產生渦電流的現象,而產生嚴重的能量損 耗,如此會形成一低品質參數之電感元件。 丨另外’可以藉由品質參數(Q)來代表電感之效能。品 質參數係定義為Q = Es/El ,其中Es係代表貯存在元件之 f應部分的能量,而E 1係代表在元件之反應部分所失去的 月b量。當元件的品質愈高時,元件之電阻值會愈趨近於 零,此時元件之品質參數係趨近於無限大。就形成在矽基 底上之電感元件而言,由於受到位在下面之電阻性之矽基 ^所影響及受到形成電感元件之金屬線路所影響,使得電 1278984 案號 93111830 曰 修正 五、發明說明(4) 磁能量會顯著地下降。就元件而言,品質參數係用來量测 元件之反應純度(purity)或敏感性(susceptance),然而 電阻性之矽基底、電阻性之金屬線路及介電耗損均會降低 品質參數。在實際上,電路總是配置有部分會浪費能量之 電阻元件’如此會減少能夠被補償(r e c 〇 v e r e d)之能量。 品質參數係為無單位的,就裝配在印刷電路板(PCB)上之 分開配置的電感元件而言,當品質參數大於丨00時,係認 定為具有甚高的品質參數;然而就形成在積體電路中之電 感元件而言,品質參數係大約介於3到1 〇之間。 電感元件可以利用傳統的半導體製程形成在具有半導 體元件之大型基底上,此時由電感元件所,產生之寄生電容 會限制截止頻率的上限,然而這個限制在許多應用上是不 能被接受的,因此必須設計具有較高品質參數之電感元 件,比如是50或更高,其中品質參數會受到1(:電路之共振 頻率所影響。在習知技術中,必須要配置彼此分離的元件 才能提供較高的品質參數,而這些分開的元件要與周圍元 件的功能整合。但是當要將電感元件及這些周圍的元件配 置於半導體基底上而欲形成大型電路結構時,便無法達 高品質參數的目的。若是採用非大型的電路結構^必須 配置,額外的線路藉以連接裝置之附屬元件,而此類似網 形式之用來連接的線路亦會產生額外的寄生電容及電阻 耗。在RF放大器之許多應用上,比如是可攜式電池充: 用品,此時電力的消耗是一項重要的考量點,並且是备 低愈好。藉由提咼電力的消耗,係可以部分地補償寄二 容效應及電阻能量損耗,但是這個方法還是有一些限制電The middle or the 疋 is provided by separately arranged components, however, the manufacture of the above electronic components is not easily integrated with the basic process of integrated circuit manufacturing. If the circuit for storing analog data and analog data is integrated with the circuit for digital data control and digital data storage and fabricated on a large semiconductor substrate, many significant advantages will be achieved, and the advantages of integration include reducing manufacturing costs and reducing energy consumption. The spiral inductor element formed on the surface of the semiconductor substrate is limited by actual size, which causes parasitic capacitance between the line of the inductor element and the underlying substrate, and is affected by the resistive germanium substrate underneath. Inductive component It will cause the loss of electromagnetic energy. When the resonant frequency of the trimming circuit suddenly drops, the parasitic capacitance can have a serious negative effect on the LC circuit. It is worth noting that the electromagnetic field generated by the inductive component causes eddy currents in the resistive substrate to cause severe energy loss, which results in a low quality parameter inductive component.丨In addition, the quality parameter (Q) can be used to represent the performance of the inductor. The quality parameter is defined as Q = Es/El, where Es represents the energy stored in the component of f, and E1 represents the amount of monthly b lost in the reaction portion of the component. When the quality of the component is higher, the resistance value of the component will become closer to zero, and the quality parameter of the component will be infinitely large. In the case of an inductive component formed on a germanium substrate, it is affected by the underlying resistive structure and is affected by the metal line forming the inductive component, so that the electric 1278984 is number 93111830. 4) The magnetic energy will drop significantly. In terms of components, the quality parameters are used to measure the purity or susceptance of the component. However, the resistive base, resistive metal circuitry, and dielectric loss all degrade the quality parameters. In practice, the circuit is always equipped with some resistive elements that waste energy. This reduces the energy that can be compensated (r e c 〇 v e r e d). The quality parameter is unitless. For a separately arranged inductive component mounted on a printed circuit board (PCB), when the quality parameter is greater than 丨00, it is considered to have a high quality parameter; however, it is formed in the product. In the case of an inductive component in a bulk circuit, the quality parameter is between approximately 3 and 1 〇. The inductive component can be formed on a large substrate having a semiconductor component by a conventional semiconductor process. At this time, the parasitic capacitance generated by the inductor component limits the upper limit of the cutoff frequency. However, this limitation is unacceptable in many applications. Inductive components with higher quality parameters must be designed, such as 50 or higher, where the quality parameters are affected by the resonant frequency of the circuit (1). In the prior art, components that are separated from each other must be configured to provide higher The quality parameters, and these separate components should be integrated with the functions of the surrounding components. However, when the inductor components and these surrounding components are to be placed on a semiconductor substrate to form a large circuit structure, high quality parameters cannot be achieved. If a non-large-scale circuit structure is used, additional lines must be used to connect the components of the device, and the network-like connection will also generate additional parasitic capacitance and resistance. In many applications of RF amplifiers. For example, portable battery charger: supplies, the power consumption is Important considerations entry point, and are better prepared low. 咼 by lifting power consumption can be partially compensated based send two resistive-capacitive effect and energy loss, but there are some limitations to this method of electrically
第8頁 1278984 案號 93111830 五、發明說明(5) 而上述的這些問題均發生在市場快速#張的無線通訊用品 上,比如是行動電話,其中RF積體電路之整合係為最重要 的挑戰之一。另外,藉由顯著地增加操作頻率,比如是增 加到lOG^Hz到100GHz之間,可以部分解決上述問題,然而3 在如此高的操作頻率之下,受到矽基底的影響,電感元件 的品質參數會顯著地下降。為了要使產品能夠在此頻率下 運作,研發出大型電感元件,其係利用除了矽以外的材賞 作為製作電感元件之基底,而這種大型電感元件比如可以 利用藍寶石(sapphire)或是砷化鎵(GaAs)^為基底。相較 於矽基底,這些形成在非矽材質之基底上的電感元件具有 較低的基底損耗,此乃因為不會形成渦電流(eddy current) ’因此便不會有電磁能量的損耗,如此可以製作 出具有高品質參數之電感元件。並且,利用上述方式所形 ,之電感元件會產生較少的寄生電容,因此可以允許在較 ,的頻率下操作。然而,若是需要更複雜的應用,還是必 須要利用石夕作為基底來形成電感元件,此乃因為若是要利 用除了矽以外的材質,比如是砷化鎵,作為基底係為甚為 麻f的’並且在形成半導體元件時,會遇到需多技術上的 丨·挑戰。由於砷化鎵在高頻下係為半絕緣的材質,因此可以 減少因為神化鎵基底所導致的電磁損耗,如此可以增加形 成在坤化鎵基底上之電感元件的品質參數。然而砷化鎵之 晶片係為非常昂貴的,若是能夠避免使用砷化鎵之RF晶 片’則在製程上具有較佳的成本優勢。 在不犧牲元件效能的情況下(比如是因為基底損耗而 f牲元件效能),有許多方法可以將電感元件與半導體環Page 8 1278984 Case No. 93111830 V. Invention Description (5) And all of the above problems occur in the fast-moving wireless communication products, such as mobile phones, where the integration of RF integrated circuits is the most important challenge. one. In addition, the above problem can be partially solved by significantly increasing the operating frequency, for example, increasing from 10 GHz to 100 GHz. However, under such a high operating frequency, the quality parameters of the inductive component are affected by the 矽 substrate. Will drop significantly. In order to enable the product to operate at this frequency, large-scale inductive components have been developed, which use materials other than germanium as the basis for making inductive components, such as sapphire or arsenic. Gallium (GaAs) is the substrate. Compared with the germanium substrate, these inductive elements formed on a non-antimony substrate have a low substrate loss because eddy current is not formed, so there is no loss of electromagnetic energy. Inductive components with high quality parameters are produced. Moreover, in the above manner, the inductance element generates less parasitic capacitance, and thus can operate at a relatively high frequency. However, if more complex applications are required, it is necessary to use Shi Xi as a substrate to form the inductive component. This is because if a material other than tantalum is used, such as gallium arsenide, it is used as a substrate. And when forming a semiconductor component, there are many technical challenges. Since gallium arsenide is a semi-insulating material at high frequencies, the electromagnetic loss caused by the deified gallium substrate can be reduced, which can increase the quality parameters of the inductive components formed on the gallium-arsenic substrate. However, gallium arsenide wafers are very expensive, and the use of RF wafers using gallium arsenide has a better cost advantage in the process. There are many ways to integrate an inductive component with a semiconductor ring without sacrificing component performance (for example, due to substrate loss).
mm 第9頁 1278984 ___案號 93111830 _年 月 日_修正 五、發明說明(6) 境整合。其中一種方法便是利用蝕刻或是微機械加工的方 式將位在電感元件底部之矽基底選擇性地去除,因此可以 減少基底之電阻能量耗損及寄生效應。另外一種方法便是 利用多層金屬層連線,其材質比如是鋁,或是利用陰刻法 (damascene)所形成之銅金屬層連線。 而另外一種方法,便是利用高電阻性之石夕基底,如此 可以減少由矽基底所產生的電阻耗損。而由基底所產生的 電阻損耗會顯著地影響以矽作為材質之電感元件的品質參 數。另外,偏壓井(biased we 11)可以配置在螺旋狀之電 感元件下,因此可以減少基底内之電感耗損。而另外一種 複雜的方法是形成主動性之電感元件,其可以利用主動電 路模擬電感元件之電子特性。然而模擬的電感元件會導致 高功率的消耗並且會有雜訊的產生,故此方法不能應用在 低功率及高頻率的產品上。所有的方法均有共同的目的, 就是要提咼電感元件之品質參數及降低電感元件在製造上 的表面積,而最重要的考量點就是關於電磁能量損耗的部 分,此乃因為電磁能量會使矽基底產生渦電流。 當積體電路之體積 低,並且會增進晶片某 線路或系統之金屬連線 逐漸縮小之際,這些金 面衝擊。由於金屬線路 導致晶片效能顯著地下 匯流排及接地匯流排之 遲緩(RC delay)效應。若是為了降低電阻而採用寬的金屬Mm Page 9 1278984 ___ Case No. 93111830 _ Year Month Day _ Amendment 5. Invention Description (6) Integration. One of the methods is to selectively remove the germanium substrate at the bottom of the inductor element by etching or micromachining, thereby reducing the resistance energy loss and parasitic effects of the substrate. Another method is to use a multi-layer metal layer connection, such as aluminum, or a copper metal layer connection formed by damascene. In another method, a high-resistance stone substrate is used, which can reduce the resistance loss caused by the substrate. The loss of resistance caused by the substrate significantly affects the quality parameters of the inductive component with germanium as the material. In addition, the biased well (biased we 11) can be placed under the spiral inductor element, thereby reducing the inductance loss in the substrate. Another complicating method is to form an active inductive component that can utilize the active circuitry to simulate the electronic characteristics of the inductive component. However, analog inductive components can cause high power consumption and noise, so this method cannot be applied to low power and high frequency products. All methods have a common purpose, which is to improve the quality parameters of the inductive component and reduce the surface area of the inductive component. The most important consideration is the part of the electromagnetic energy loss, because the electromagnetic energy will cause 矽The substrate generates eddy currents. These gold surfaces are impacted when the volume of the integrated circuit is low and the metal wiring of a certain line or system of the wafer is gradually reduced. Due to the metal wiring, the wafer performance is significantly RC delay effect of the underground bus and the ground bus. Use a wide metal to reduce the resistance
第10頁 縮小之際,每片晶 方面之效能。用來 變得較為重要,並 屬連線會對線路效 之寄生電容及電阻 降,其中最明顯的 電壓降及關鍵訊號 連接晶片與其他 且隨著積體電路 能產生嚴重地負 會增加,因此會 衝擊係在於電源、 電路之電阻電溶 1278984 __案號93111830_年月曰 铬,τ,__· 五、發明說明(7) 線路,則又會導致金屬線路具有較高的電容。 在現今的技術中,當電感元件欲形成在半導體基底上 時,可以利用細線路的技術,並且將電感元件形成在保護 層下。如此會使得電感元件很接近基底的表面,而電感元 件與基底之表面間的距離基本上是小於1 0微米,因此在石夕Page 10 The effectiveness of each piece of crystal is reduced. Used to become more important, and it is a parasitic capacitance and resistance drop that will be effective on the line. The most obvious voltage drop and key signal are connected to the chip and others, and the integrated circuit can generate a serious negative increase. The impact system is the resistance of the power supply, the circuit, the electric solution 1278984 __ case number 93111830_ 曰 曰 chrome, τ, __ · five, invention description (7) line, which will lead to a higher capacitance of the metal line. In today's technology, when an inductive component is to be formed on a semiconductor substrate, fine line technology can be utilized and the inductive component can be formed under the protective layer. This will make the inductive component very close to the surface of the substrate, and the distance between the inductive component and the surface of the substrate is substantially less than 10 microns, so in Shi Xi
基底内會導致高電磁損耗的產生,且會降低電阻元件之品 質參數。 M 美國專利公告第5, 21 2, 403號(Nakani Shi)揭露一種形 線路連線的方法’其中内部及外部之線路連線係形成在 於晶片上之線路基底内,並且邏輯線路的設計會取決於 線路連線的長度。 美國專利公告第5,50 1,006號(66[1111311,1厂^31·) 揭露一種積體電路與線路基底之間具有絕緣層之結構,而 藉由分散出去的引腳可以是晶片之接點與基板之接點電性 美國專利公告第5, 055, 907號(Jacobs)揭露一種整合 型半導體結構,可以允許製造商將一薄膜多層線路形成在 支樓基板上或晶片上,藉以整合位在晶片外之電路。 #美國專利公告第5,1〇6,461號(Volfson et al·)揭露 一種多層連線結構,其係藉由TAB結橼並利用聚醯亞胺 (polyimide)之介電層及金屬層交互疊合於晶片上而成。 美國專利公告第5,635,767號(Wenzel et al·)揭露— 種在PBGA結構中降低電阻電容遲緩效應之方法,其中多声 金屬層係分開配置。 美國專告第.5, 686, 764號(Fulcher)揭露一種覆晶The presence of high electromagnetic losses in the substrate can reduce the quality parameters of the resistive components. M. US Patent Publication No. 5, 21, 403 (Nakani Shi) discloses a method of connecting a line of wires in which internal and external line connections are formed in a circuit substrate on a wafer, and the design of the logic circuit depends on The length of the line connection. U.S. Patent Publication No. 5,50,006 (66 [1111311,1, ^31·) discloses a structure having an insulating layer between an integrated circuit and a circuit substrate, and the pin which is dispersed can be a contact of the wafer. Contact with a substrate. U.S. Patent No. 5,055,907 (Jacobs) discloses an integrated semiconductor structure that allows a manufacturer to form a thin film multilayer circuit on a support substrate or wafer for integration. Circuitry outside the chip. #US Patent Publication No. 5,1,6,461 (Volfson et al.) discloses a multilayer wiring structure that is bonded by a TAB junction and using a dielectric layer of a polyimide and a metal layer. Made on the wafer. U.S. Patent No. 5,635,767 (Wenzel et al.) discloses a method of reducing the resistance of a resistive capacitor in a PBGA structure in which multiple layers of metal are separately disposed. U.S. Patent No. 5,686,764 (Fulcher) discloses a flip chip
第11頁 1278984 J^J3H1830 五、發明說明(9) 護層上或是厚介電層上,其十電子元件比如是電感元 電容元件或電阻元件。另外,本發明還提供一種將已經製 作完成的被動元件接合到晶片之表面上的方法。 ” 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉較佳實施例,並配合所附圖式, 說明如下: 砰、、,田 【實施方式】 美國專利公告第6, 383, 9 1 6號係讓渡於與本發明相同Page 11 1278984 J^J3H1830 V. INSTRUCTIONS (9) On the protective layer or on the thick dielectric layer, the ten electronic components are, for example, inductive element capacitive elements or resistive elements. Additionally, the present invention provides a method of bonding a passive component that has been fabricated to the surface of a wafer. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Announcement No. 6, 383, 9 1 6 is the same as the present invention
•之讓渡人,其揭露一種晶片結構具有重配置線路層及金P 連線層,係配置在介電層上,其中介電層係位於傳統晶片 之保護層上。保護層係位於積體電路上,而厚的聚合2層 =擇性地配置在保護層上,寬的或厚的金屬連線係位在 保護層上。 美國專利公告第6,3〇3,423號係讓渡於與本發明相同 f讓渡人,其揭露一種形成具有高品質參數之電感元件於 曰曰片之保護層上的結構。此種具有高品質參數 ^應用在高頻電路中,並且可以減少電能的損:感:: 、,還揭露電容70件及電阻元件,可以形成在矽基底的 $面上,藉以減少位於⑨基底下之電子元件所引發出的寄 生效應。 榦=參照第1圖,其繪示依照美國專利公告第6, 383, 91 6 u =片結構的剖面示意圖。梦基底10的表面具有電晶體 有ii:元件(未繪示於第1圖)’石夕基底10的表面係覆蓋 電芦二介電層i2(ild) ’位於上述之電子元件上。金屬/介 —~位於内部介電層12上,金屬/介電層"由扛s小• The transferee, which discloses a wafer structure having a reconfigured wiring layer and a gold P wiring layer disposed on the dielectric layer, wherein the dielectric layer is on the protective layer of the conventional wafer. The protective layer is on the integrated circuit, while the thick polymeric layer 2 is selectively disposed on the protective layer, and the wide or thick metal wiring is on the protective layer. U.S. Patent Publication No. 6,3,3,423 is assigned to the same extent as the present invention. The assignee discloses a structure for forming an inductive component having a high quality parameter on a protective layer of a cymbal. This kind of high quality parameter is applied in the high frequency circuit, and can reduce the loss of electric energy: Sense::, also exposes 70 pieces of capacitor and resistive element, which can be formed on the $ surface of the 矽 substrate, thereby reducing the position on the 9 base The parasitic effects caused by the electronic components. Dry = Referring to Figure 1, there is shown a schematic cross-sectional view of a sheet structure in accordance with U.S. Patent Publication No. 6,383,91. The surface of the dream substrate 10 has a transistor. ii: an element (not shown in Fig. 1). The surface of the stone substrate 10 is covered with a dielectric layer i2 (ild) ’ on the electronic component. Metal / dielectric - ~ located on the internal dielectric layer 12, metal / dielectric layer " by 扛s small
第13頁 1278984 _93111830---壬-------:- 五、發明說明(8) 基板,藉由將電源線與輸入輸出引線分開配置’可以降低 電阻電容遲緩效應° 美國專利公含第6, 〇〇8, 102號(Alford et al·)揭露一 種利用兩層金屬層戶斤形成之螺旋狀電感元件’其中此兩層 金屬層可以利用導通孔連接。 美國專利公告第5,372,967號(Sundaram et a1·)揭露 一種螺旋狀電感元件0 美國專利公告第5, 576,680號(Ling)及第5, 884, 990號 (Burghartz et al.)揭露一種其他形式之螺旋狀電感元 ,件。 【發明内容】 因此本發明目的之一就是提供一種高效能之晶片結 構,尤其可以改善RF之效能。 本發明目的之二就是提供一種具有高品質係數之電感 元件的製造方法。 本發明目的之三就是可以利用矽晶片來代替砷化鎵晶 片’並且在石夕晶片上可以製作出高品質係數之電感元件。 本發明目的之四就是可以使形成在矽基底表面上之電 元件的頻率範圍延伸。 本發明目的之五就是可以使形成高品質之被動元件於 梦基底的表面上。 :關,在保護層上此厚介電層上製Page 13 1278984 _93111830---壬-------:- V. Invention Description (8) Substrate, by disposing the power supply line from the input and output leads, can reduce the resistance and capacitance delay effect. No. 6, 〇〇 8, 102 (Alford et al.) discloses a spiral inductor element formed by two layers of metal layers, wherein the two metal layers can be connected by via holes. US Patent Publication No. 5,372,967 (Sundaram et al.) discloses a spiral inductive component. U.S. Patent Nos. 5,576,680 (Ling) and 5,884,990 (Burghartz et al.) disclose another form. Spiral inductor element, piece. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a high performance wafer structure which, in particular, can improve the performance of RF. Another object of the present invention is to provide a method of manufacturing an inductor element having a high quality coefficient. The third object of the present invention is that a germanium wafer can be used instead of a gallium arsenide wafer and an inductive component of high quality coefficient can be fabricated on a stone wafer. The fourth object of the present invention is to extend the frequency range of the electrical components formed on the surface of the crucible substrate. The fifth object of the present invention is to enable the formation of high quality passive components on the surface of the dream substrate. : off, on the thick dielectric layer on the protective layer
第12頁 fi wVcnR缺 /線路之製程可以參照美國專利公告第 祙 * s * 士改货明係延伸自美國專利公告第6,383,91 6 --遷揭路可以形成高性能之電子元件於保 1278984 修正 MM 93insan 五、發明說明(10) 一層之介電層,而至少一金屬連線13係位在金屬/介電層 14中’金屬連線13係構成電子連接的網路,而最上層之金 屬層具有部分區域係定義為電子接點1 6,這些電子接點16 可以與位於矽基底1〇之表面上或表面内之電晶體n或其他 元件電丨生連接。保護層18係位於金屬/介電層1 4,藉以避 免移動離子(比如是鈉離子)、濕氣、過渡金屬(比如是 金、銀、銅)或其他污染物進入到晶片内,其中保護層i 8 比如是由氧石夕化合物或氮矽化合物所構成之複合層。保護 >層1 8係用來保護位在下面之比如是電晶體、多晶矽電阻元 件或多晶石夕-多晶矽電容元件之電子元件及細金屬線路。 美國專利公告第6, 383, 91 6號之關鍵步驟係起始於沈 積厚的聚合物層20開始,其中聚合物層2〇係沈積在保護層 18上。為了要與電子接點16連接,開口22、36、38會穿過 聚合物層20及保護層18,並且會對準於電子接點16。透過 位於聚醯亞胺(polyimide)層20内之開口 22、36、38,電 子接點1 6可以將電性延伸至聚合物層2 〇中。 在較佳的情況下,聚合物層20之材質比如是聚醯亞 胺’而聚合物層20比如是感光材料。而聚合物層2〇之材質 是苯基環 丁埽(benzocyclobutene,BCB)、聚亞芳 香基峻(parylene)或者是以環氧樹脂為基礎之材料,比如 疋SU-8 環氧樹脂(可以從s〇tec Microsystems, Renens, Switzerland 獲得)。 ’ 在形成開口22、36、38之後,可以進行一金屬化製 程,藉以形成圖案化寬金屬層26、28,並且可以連接電子 接點16。而線路26、28可以是任何設計形式之寬度及厚Page 12 fi wVcnR lack / line process can refer to the US Patent Bulletin 祙 * s * Shi change the goods are extended from the US Patent Notice No. 6,383,91 6 - Qian Jie Road can form high-performance electronic components in Bao 1278984 MM 93insan V. Invention Description (10) A dielectric layer of one layer, and at least one metal connection 13 is in the metal/dielectric layer 14 'Metal connection 13 constitutes an electronically connected network, and the uppermost metal The layer has a partial region defined as an electrical junction 16 which can be electrically connected to a transistor n or other component located on or in the surface of the substrate 1 . The protective layer 18 is located on the metal/dielectric layer 14 to prevent mobile ions (such as sodium ions), moisture, transition metals (such as gold, silver, copper) or other contaminants from entering the wafer, wherein the protective layer i 8 is, for example, a composite layer composed of an oxygen stone compound or a nitrogen compound. Protection > Layer 18 is used to protect electronic components such as transistors, polysilicon resistors or polycrystalline slab-polysilicon capacitors and fine metal traces underneath. The key step in U.S. Patent Publication No. 6,383,91 6 begins with the deposition of a thick polymer layer 20 in which a polymer layer 2 is deposited on a protective layer 18. In order to be connected to the electronic contacts 16, the openings 22, 36, 38 will pass through the polymer layer 20 and the protective layer 18 and will be aligned with the electronic contacts 16. Electrodes 16 can be electrically extended into the polymer layer 2 through openings 22, 36, 38 located in the polyimide layer 20. In the preferred case, the material of the polymer layer 20 is, for example, polyimide, and the polymer layer 20 is, for example, a photosensitive material. The polymer layer 2 is made of benzocyclobutene (BCB), polyarylene or (parylene) or epoxy-based materials such as 疋SU-8 epoxy resin. S〇tec Microsystems, Renens, Switzerland). After the openings 22, 36, 38 are formed, a metallization process can be performed whereby the patterned wide metal layers 26, 28 are formed and the electronic contacts 16 can be connected. The lines 26, 28 can be of any design in width and thickness
第14頁 1278984 __案號93111830_年月日 修正 五、發明說明(11) 度,以符合所需的電路設計,且線路26、28可以作為電源 匯流排、接地匯流排或訊號匯流排之用。經由打線導線或 凸塊可以使線路26、28連接於晶片外之電路。 電子接點1 6係位在薄介電層1 4 (如第1圖所示)的頂 部,並且電子接點1 6之尺寸可以縮小,藉以減少位於下面 之金屬層的電容值。若是電子接點16之尺寸過大時,會影 響金屬層之繞線。 ' 比如是聚醯亞胺之厚聚合物介電層2〇 在硬化之後 -------,识〜电甩“0 >厚度可以超過2微米,而聚合物介電層2〇之厚度比如是介 於2微米到1 5 0微米之間,視電子設計之需求而定。而就較 厚的聚醯亞胺層20而言,可以利用多次旋塗及硬化的方 式,形成聚醯亞胺薄膜。 美國專利公告第6, 383, 91 6號揭露利用厚或寬之金屬 28所形成如第1圖所示之具有不同方向的路徑3〇、32、 34,可以作為電路間的電性連接之用。相較於位在下声之 細線路金屬層14,寬金屬2 8具有較小的電阻值及電容值, 並且較容易製造,且成本較低。 蠢Ϊίϊ第2圖,其係修改自美國專利公告第6,383, 916 電ί元件於厚聚酿亞胺層20上。電感元線 多^12丨4乂式,並且可以平行於基底10的表面,而透過 多層12、14、18、20結構所槿点夕古命 处项 姝#齙其念^ 再所構烕之同度,可以使得電感元 件运離基底之表面。第2圖繪示係 作剖面所形成之電感元件罝於基底10之表面Page 14 1278984 __ Case No. 93111830_ Year of the Moon Amendment 5, invention description (11) degrees to meet the required circuit design, and lines 26, 28 can be used as power bus, ground bus or signal bus use. The wires 26, 28 can be connected to circuitry external to the wafer via wire bonds or bumps. The electronic contacts 16 are positioned at the top of the thin dielectric layer 14 (as shown in Figure 1), and the size of the electronic contacts 16 can be reduced to reduce the capacitance of the underlying metal layer. If the size of the electronic contact 16 is too large, the winding of the metal layer will be affected. ' For example, the thick polymer dielectric layer 2 of polyimine is after hardening -------, the thickness of the electrical layer "0 > can exceed 2 microns, and the polymer dielectric layer 2 The thickness is, for example, between 2 microns and 150 microns, depending on the needs of the electronic design. For thicker polyimide layers 20, multiple spin coatings and hardenings can be used to form the poly. U.S. Patent No. 6,383,91, the disclosure of which discloses the use of the thickness or width of the metal 28 to form paths 3, 32, 34 having different directions as shown in Fig. 1, which can be used as inter-circuit. For electrical connection, the wide metal 28 has a smaller resistance value and capacitance value than the fine line metal layer 14 located below, and is easier to manufacture and has a lower cost. It is modified from the US Patent Publication No. 6,383, 916 on the thick polyimide layer 20. The inductance element is more than 12 丨 4 ,, and can be parallel to the surface of the substrate 10, and through the layers 12, 14, 18, 20 structure of the point of the eve of the ancient life of the project 姝 龅 龅 念 念 再 再 再 再 再 再 再 再 再 再 再 再 再 再 再 再 再 再The surface of the substrate. Figure 2 shows the inductive component formed by the cross-section on the surface of the substrate 10.
第15頁 屬的权叶,可以減少電阻能量的指鉍“厚金 鍍的方式,形成比如是金:^耗。其中,可以利用電 一 二··一 ------- 銀或鋼之低電阻金屬,而其金The genus of the genus on page 15 can reduce the index of resistance energy. The way of thick gold plating is to form, for example, gold: ^. In which, you can use electricity one or two. Low resistance metal, while its gold
V 1278984 Λ 一月 曰 修正 案號 93111830 五、發明說明(12) ^ 屬厚度比如是大約20微米。 相較於將電感元件形成於保護層下之習知技術,藉由 增加電感兀件與矽基底之間的距離’彳以減少矽基底1〇所 產生的電磁場,並且電感元件之品質參數可以提高。電感 元件可以形成在保護層上,或者可以形成在位於保護層上 :厚介電層(比如是聚醯亞胺)上。另外,利用寬且厚的金 屬所形成之電感元件,具有較小的寄生電阻。 本發明之另-重點,就是保護層18之開口19的寬度可 鲁以小至0.1微米。因此,電子接點16可以是很小的,如此 可以提升位在頂層之細線路金屬層之繞線能力,並且具有 較低之電容值。 而本發明之另一重要特徵,就是聚合物層20之開口 22、36、38可以是大於保護層開口19,而聚合物層2〇之開 口 22、36、38係對準於保護層開口19。將聚合物層2〇設計 有較大的開口22、36、38係為一種選择性的設計,並且較 容易製作完成,且將聚合物層20設計有較大的開口 22、 、38可以配合厚金屬層的設計使用,藉以完成本發明在 ^成保護層後之金屬沈積製程。 第2圖繪示連線結構26及電感元件40,其中電感元件 40包括兩個接點41、43,透過聚合物層2〇可以與電子接點 1 6電性連接。 另外,請參照第2圖,依照本發明之另一觀點,還可 以形成另一聚合物層於如第2圖所示的結構上。 第24a圖及第2 4b圖繪示本發明之另一特徵,其中連接 $,J t $元件之接點的方式係不同於如第2圖所示之兩個向V 1278984 Λ January 曰 Amendment Case No. 93111830 V. Description of invention (12) ^ The thickness of the genus is, for example, approximately 20 microns. Compared with the conventional technique of forming an inductor element under a protective layer, the electromagnetic field generated by the 矽 substrate 1 矽 is reduced by increasing the distance 兀 between the inductor element and the 矽 substrate, and the quality parameter of the inductance element can be improved. . The inductive component can be formed on the protective layer or can be formed on the protective layer: a thick dielectric layer such as polyimide. In addition, an inductive component formed of a wide and thick metal has a small parasitic resistance. Another important point of the invention is that the width of the opening 19 of the protective layer 18 can be as small as 0.1 microns. Therefore, the electronic contacts 16 can be small, which can improve the winding capability of the thin metal layer of the top layer and have a lower capacitance value. Another important feature of the present invention is that the openings 22, 36, 38 of the polymer layer 20 can be larger than the protective layer opening 19, and the openings 22, 36, 38 of the polymer layer 2 are aligned with the protective layer opening 19. . Designing the polymer layer 2〇 with larger openings 22, 36, 38 is a selective design and is easier to fabricate, and the polymer layer 20 is designed with larger openings 22, 38 that can be matched. The design of the thick metal layer is used to complete the metal deposition process of the present invention after the protective layer. FIG. 2 illustrates the wiring structure 26 and the inductive component 40. The inductive component 40 includes two contacts 41 and 43 that are electrically connected to the electronic contacts 16 through the polymer layer 2 . Further, referring to Fig. 2, in accordance with another aspect of the present invention, another polymer layer may be formed on the structure as shown in Fig. 2. Figures 24a and 2b show another feature of the invention wherein the way of connecting the contacts of the $, J t $ elements is different from the two directions as shown in Figure 2
第16頁 1278984 案號 931Π83Π 五、發明說明(13) 下連接的接點。如第2 4a圖所示,其中介電層35係形成在 金屬連線26及電感元件4〇上,而介電層35之材質比如是聚 酿亞胺。開口36a會連通至電感元件4〇之一端,並且可以 將電感元件40之一端暴露於外。電感元件4〇具有一向上連 接之接點及一向下連接之接點39,其係為,,一上一下”的結 構。 、、口 第24b圖繪示另外一種結構,其中具有兩個朝上的接 點開口36a、38a ,係暴露出電感元件4〇,其係為,,均 上”的結構。 在第24a圖及第24b圖中,電感元件之朝上的接點可以 透過打線的方式或是形成凸塊的方式與外部元件電性連 接。就打線製程而言,電感元件40元件之上表面必須要形 成一可與打線導線接合的金屬,其材質比如是金或鋁。就 凸塊連接而言,凸塊底層金屬(UBM)可以形成在朝上的接 點開口中,藉以形成凸塊。 在第24a圖及第24b圖中,利用形成與結構26及電感元 件40相同之方法來形成連接線路,可以使電感元件經由接 ,開口36a、38a與晶片上之其他接點或如前所述之外 電性連接。 請參照第2 4 c圖,其繪示本發a月之另一特徵,其中一 延伸線路89會連接至電感元件4〇,而接點開口 361)會暴露 出延伸線路89,其中接點開口36b的位置比如是在晶片的 邊緣,而可以方便進行打線製程,如此電感元件4〇可以透 過延伸線路89改變對外連接的位置。接點開口38b的配置 前所述。延伸線路89、金屬結構26與電感元件40係同 ^Blll Mil k ^_ __ m 第17頁 1278984 案號 93111830 千 η 五、發明說明(14) 時製作完成。 延伸線路89可以連接至電感元件4〇,藉以改變電感元 件40對外連接的位置,其中延伸線路89可以具有向下連接 的接點(未繪示,但是此概念之前已敘述過),取代向上連 接的接點3 6 b。 當電感元件的接點係位在中間區域時,比如是第24c 圖之開口 38b所暴露之接點,此時位在電感元件之中間區 域的接點係無法藉由延伸線路而改變其對外連接的位置, 但是位在電感元件之中間區域的接點可以向上連接或是向 下連接。 第3圖繪不螺旋狀電感元件4〇之上視圖,其中電感元 件40係位在介電層2〇之表面上,第2圖所示的電感元件係 為第3圖中沿著剖面線2 — 2之剖面示意圖。 第4圖繪示電感元件4〇之剖面示意圖,藉由增加一導 電片44a可以隔絕電感元件4〇對基底1〇的影響,其中導電 糸雪大Λ上位在電感元件下,而導電片44a比如是 a雷成_ f料。導電片44a係在保護層18之表面上延伸, =几件4〇係對準於導電片—且位在導電片—上。導 件4。之電:響的此力’藉以避免基底10受到電感元 域電感元件40至少百分之五十以上的區 況下,電感元件40至少百八> I .在較佳的情 底10之間係存在有導;=之八十以上的區域與半導體基 二一一 —---—D44a ’如此更可以增進遮蔽基底 第18頁 1278984Page 16 1278984 Case No. 931Π83Π V. Inventions (13) Connected contacts. As shown in Fig. 24a, the dielectric layer 35 is formed on the metal wiring 26 and the inductance element 4, and the dielectric layer 35 is made of, for example, a polyimine. The opening 36a is connected to one end of the inductive element 4, and one end of the inductive element 40 can be exposed. The inductive component 4A has an upwardly connected contact and a downwardly connected contact 39, which is a top-to-bottom structure. The port 24b shows another structure in which two upwards are provided. The contact openings 36a, 38a expose the inductive component 4A, which is a "upper" structure. In Figures 24a and 24b, the upwardly facing contacts of the inductive component can be electrically connected to the external component by way of wire bonding or by forming bumps. In the case of the wire bonding process, the upper surface of the component of the inductive component 40 must form a metal that can be bonded to the wire bonding wire, such as gold or aluminum. In the case of a bump connection, a bump underlayer metal (UBM) may be formed in the upwardly facing contact opening to form a bump. In Figs. 24a and 24b, the connection lines are formed by the same method as the structure 26 and the inductance element 40, so that the inductance elements can be connected to the other contacts on the wafer via the openings 36a, 38a or as described above. Electrical connection. Please refer to FIG. 24C, which illustrates another feature of the present month, in which an extension line 89 is connected to the inductive component 4〇, and the contact opening 361) exposes the extension line 89, wherein the contact opening The position of 36b is, for example, at the edge of the wafer, and the wire bonding process can be facilitated, so that the inductance element 4 can change the position of the external connection through the extension line 89. The configuration of the contact opening 38b is as described above. The extension line 89 and the metal structure 26 are the same as the inductance element 40. ^Blll Mil k ^_ __ m Page 17 1278984 Case No. 93111830 Thousand η V. The invention description (14) is completed. The extension line 89 can be connected to the inductive component 4 to change the position of the inductive component 40 to the external connection, wherein the extension line 89 can have a connector that is connected downward (not shown, but this concept has been described previously) instead of the upward connection. The contact is 3 6 b. When the contact of the inductive component is in the middle region, such as the contact exposed by the opening 38b of the 24th figure, the contact located in the middle region of the inductive component cannot change its external connection by extending the line. The position, but the contacts located in the middle of the inductive component can be connected upwards or downwards. Figure 3 is a top view of the non-helical inductive component 4, wherein the inductive component 40 is on the surface of the dielectric layer 2, and the inductive component shown in Figure 2 is along the section line 2 in Figure 3. — 2 is a schematic view of the section. FIG. 4 is a schematic cross-sectional view of the inductor element 4 ,. By adding a conductive sheet 44a, the influence of the inductor element 4 〇 on the substrate 1 可以 can be insulated, wherein the conductive 糸 Λ Λ is placed under the inductor element, and the conductive sheet 44 a is like Is a Lei into _ f material. The conductive sheet 44a extends over the surface of the protective layer 18, and a number of pieces are aligned with the conductive sheet - and placed on the conductive sheet. Guide 4. The power of the ring: to avoid the substrate 10 being subjected to at least 50% of the inductance of the inductive element 40, the inductive element 40 is at least one hundred and eight > I. Between the better case 10 There are guides; = more than 80% of the area and the semiconductor base 2 - 1 - D44a 'so can enhance the shielding base page 18 1278984
1 〇的能力。 導電片44a可以電性連接於電感元件4〇之其中一電極 (如第4圖所示,導電片44a可以與電感元件4〇之最右端的 電極43電性連接),而導電片44a可以是處在浮動電壓之準 位’或者是可以與其他的電壓準位連接,取決於系統的電 子設計。 •製作導電片44a的方法及材質可以是利用如後所述之 製作金屬連接線路26及電感元件40的方法及材質。在製作 導電片44a時可以同時形成導體44,而藉由導體軻可以將 位在上層之厚金屬連接至電子接點16,如第4圖所示。 第一聚合物層47可以是選擇性地形成在電感元件4〇上 及金屬連接線路26上,可以對金屬結構提供額外的保護。 凊參照第1 2圖至第2 3圖,其緣示依照本發明保護層上 形成電感元件或其他被動元件之方法。如第丨2圖所示,基 底80係為位在下層之介電層,而金屬接點81的材質比如是 铭。藉由圖案化的步驟可以形成開口 82 ,貫穿保護層84 , 而開口82可以暴露出金屬接點81。比如是聚醯亞胺之聚合 物層86可以是形成在保護層84上及金屬接點81上,而比如 攀 聚醯亞胺之聚合物層86比如是利用旋塗的方式完成,或 者亦可以利用網板印刷的方式完成,或者亦可以是利用壓 合聚合物乾膜的方式完成。 第1 3圖係繪示形成聚合物層8 6之開口 8 7的,製程,其中 聚合物層86之開口87之最大寬度係大於保護層84之開口82 之最大寬度(請參見圖12 ),開口 8 7具有傾斜的側壁8 5。在 剛開始時,聚合物層86之開口 87具有垂直之側壁,然而在1 〇 ability. The conductive sheet 44a can be electrically connected to one of the electrodes of the inductor element 4 (as shown in FIG. 4, the conductive sheet 44a can be electrically connected to the rightmost electrode 43 of the inductor element 4), and the conductive sheet 44a can be It is at the level of the floating voltage' or it can be connected to other voltage levels, depending on the electronic design of the system. The method and material for producing the conductive sheet 44a may be a method and a material for forming the metal connecting line 26 and the inductance element 40 as will be described later. The conductor 44 can be formed at the same time when the conductive sheet 44a is formed, and the thick metal in the upper layer can be connected to the electronic contact 16 by the conductor ,, as shown in Fig. 4. The first polymer layer 47 can be selectively formed on the inductive component 4 and on the metal connection line 26 to provide additional protection to the metal structure. Referring to Figures 12-2 through 2, there is shown a method of forming an inductive component or other passive component on a protective layer in accordance with the present invention. As shown in Fig. 2, the substrate 80 is a dielectric layer located on the lower layer, and the material of the metal contact 81 is, for example, Ming. The opening 82 can be formed by a patterning step through the protective layer 84, and the opening 82 can expose the metal contacts 81. For example, the polymer layer 86 of the polyimide may be formed on the protective layer 84 and the metal contact 81. For example, the polymer layer 86 of the polyimide may be formed by spin coating, or may be This can be done by screen printing, or it can be done by pressing the polymer dry film. Figure 13 is a process for forming the opening 87 of the polymer layer 86, wherein the maximum width of the opening 87 of the polymer layer 86 is greater than the maximum width of the opening 82 of the protective layer 84 (see Figure 12). The opening 8 7 has an inclined side wall 85. At the beginning, the opening 87 of the polymer layer 86 has vertical sidewalls, however
第19頁 1278984Page 19 1278984
,過,化步驟之後’侧壁85會呈現傾斜的樣式,而開口 87 :以疋呈現半錐形的樣式,而側壁85的傾斜角度比如是45 又或疋更大,基本上大約是介於5〇度到6〇度之間。另外, 側壁85的傾斜角度亦可以是小至20度。 ,本實施例中’較大的導通孔線路(vias)可以是穿過 比如疋聚醯亞胺之聚合物層86,且對準於較小之位在下層 ^巧護層的開口,並且還連接位在下層之次微米金屬層。 酼者由次微米金屬層往寬金屬層級的方向,次微米金屬之 丨_導通孔線路之尺寸可以是逐漸加大。 请繼續參照第1 3圖,其繪示依照本發明形成保護層上 連接線路及電感元件之方法及金屬結構。首先可以利用濺 鍍的方式,形成一黏著/阻障層88,其材質包括鈦鎢合 金、鈦氮化合物、鈕或鈕氮化合物等,而黏著/阻障層88 ,厚度比如是介於5〇〇埃(angstr〇ffl)到5〇〇〇埃之間。接 ,,可以利用濺鍍的方式形成比如是金的種子層9〇於黏 著/阻障層88上,其中種子層9〇的厚度比如是介於3〇〇埃到 3 0 0 0埃之間。 請參照第1 4圖,接著可以利用電鍍的方式,形成一厚 •^層92 ’其材質比如是金,其中厚金屬層92的厚度比如 是介於1微米到20微米之間。而在進行電鍍製程之前,會 先形成厚光阻94,而光阻94的厚度大於或等於厚金屬層92 的厚度,透過微影步驟,光阻94會暴露出種子層9〇,接著 才以電鍍的方式形成厚金屬層92。 在電鑛製程之後,可以將光阻94去除,如第丨5圖所 示。利用厚金屬層92作為蝕刻罩蔽,,並藉由蝕刻製程可以After the step, the side wall 85 will assume a slanted pattern, and the opening 87 will have a semi-tapered shape with 疋, and the inclination angle of the side wall 85 is, for example, 45 or 疋, which is approximately 5 degrees to 6 degrees. In addition, the inclination angle of the side wall 85 may also be as small as 20 degrees. In the present embodiment, the larger vias may be through the polymer layer 86 such as yttrium polyimine, and aligned with the opening of the lower layer in the lower layer, and also The connection is in the sub-micron metal layer of the lower layer. The size of the sub-micron metal layer to the wide metal level, the size of the sub-micron metal 导-via line can be gradually increased. Please refer to FIG. 1 3, which illustrates a method and a metal structure for forming a connection line and an inductance element on a protective layer in accordance with the present invention. First, an adhesion/barrier layer 88 may be formed by sputtering, and the material thereof includes a titanium tungsten alloy, a titanium nitride compound, a button or a nitrogen compound, and the adhesion/barrier layer 88 has a thickness of, for example, 5〇. 〇 ang (angstr〇ffl) to 5 〇〇〇 between. Then, a seed layer 9 such as gold may be formed by sputtering to adhere to the adhesion/barrier layer 88, wherein the thickness of the seed layer 9〇 is, for example, between 3 〇〇 and 300 Å. . Referring to FIG. 14 , a thick layer of a material such as gold may be formed by electroplating, wherein the thickness of the thick metal layer 92 is, for example, between 1 micrometer and 20 micrometers. Before the electroplating process is performed, a thick photoresist 94 is formed, and the thickness of the photoresist 94 is greater than or equal to the thickness of the thick metal layer 92. Through the lithography step, the photoresist 94 exposes the seed layer 9〇, and then The thick metal layer 92 is formed by electroplating. After the electro-mine process, the photoresist 94 can be removed, as shown in Figure 5. The thick metal layer 92 is used as an etching mask, and can be processed by an etching process.
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如 1278984 _m 93111830___年月日 條正 五、發明說明(17) 去除黏著/阻障層88及種子層90,如第16圖所示。在圖示 中,僅繪示出電感元件4〇之其中一線圈,然而熟悉該項技 藝者應知’整個電感元件4 〇可以在此步驟完成。 如第17圖及第18圖所示,厚金屬層92亦可以是僅填入 於開口 8 7中之部分區域,如此可以設計出線路密度高且線 路甚細之電感元件。而在本實施例中,聚合物層開口 87之 尺寸D比如是約1 5微米,而電感元件之金屬線路之間距係 小至4微米。因此,將位於聚合物層開口 87内之金屬圖案 化亦是本發明的重要特徵。 如刖所述’可以利用錢鍵的方式’形成一黏著/阻障 層88及比如是金的種子層9〇,並且還形成一光阻95,如第 17圖所不。接著可以利用電鍍的方式形成比如是金的厚金 屬層92。之後,可以將光阻95去除,並且蝕刻掉先前位在 光阻9 5下方之黏著/阻障層88及種子層90,如第18圖所 示0 ^在本發明之另一實施例中,可以利用銅來作為位在保 護層上之金屬結構中之厚金屬層的材質。剛開始之結構係 ’第Ϊ 3圖所示,接著請參照第1 9圖,可以利用濺鍍的方式 成比如是鉻或鈦之黏著/阻障層1〇〇,其厚度比如是介於 2 〇 (^埃到2 0 〇 〇埃之間,接著,可以利用濺鍍的方式形成比 如疋銅之種子層102,其厚度比如是介於2〇〇〇埃到1〇〇〇〇埃 之間。接著,可以利用電鍍的方式形成比如是銅之厚金屬 層1、0 4 ’其厚度比如是介於3微米到2 〇微米之間,而可以利 ,光阻9 4a及傳統的微影製程定義出欲電鍍的區域。接For example, 1278984 _m 93111830___ year, month, and day, paragraph 5, invention description (17) remove the adhesion / barrier layer 88 and seed layer 90, as shown in Figure 16. In the illustration, only one of the inductive elements 4A is shown, but it will be appreciated by those skilled in the art that the entire inductive element 4 can be completed in this step. As shown in Figs. 17 and 18, the thick metal layer 92 may be filled only in a portion of the opening 87, so that an inductance element having a high line density and a fine line can be designed. In the present embodiment, the size D of the polymer layer opening 87 is, for example, about 15 μm, and the distance between the metal lines of the inductive element is as small as 4 μm. Therefore, patterning the metal located within the opening 87 of the polymer layer is also an important feature of the present invention. An adhesive/barrier layer 88 and a seed layer 9 of, for example, gold may be formed by the means of a money bond, and a photoresist 95 may be formed, as shown in Fig. 17. A thick metal layer 92, such as gold, can then be formed by electroplating. Thereafter, the photoresist 95 can be removed and the adhesion/barrier layer 88 and the seed layer 90 previously under the photoresist 95 can be etched away, as shown in FIG. 18, in another embodiment of the present invention, Copper can be utilized as the material of the thick metal layer in the metal structure on the protective layer. The structure at the beginning is shown in Figure 3, and then refer to Figure 19. It can be sputtered into an adhesion/barrier layer such as chrome or titanium. The thickness is, for example, 2 〇(^ Å to 2 〇〇 ,, then, a seed layer 102 such as beryllium copper may be formed by sputtering, the thickness of which is, for example, between 2 〇〇〇 and 1 〇〇〇〇 Then, a thick metal layer such as copper can be formed by electroplating, and the thickness of the metal layer 1, for example, is between 3 micrometers and 2 micrometers, and the thickness can be improved, the photoresist 9 4a and the conventional lithography process. Define the area to be plated.
麵 國Country
第21頁 1278984Page 21 1278984
層1 06,其中金屬頂層1 〇6的厚度比如是介於〇· i微米到3微 米之間。 請參照第20圖,接著可以將光阻94a去除並暴露出比 如疋銅的種子層102。接著,可以利用比如是銅的厚金屬 層1 04作為蝕刻罩蔽’並藉由蝕刻方式可以去除黏著/阻障 層100及比如是銅之種子層1〇2。 如果有形成比如是鎳的金屬頂層丨〇6 ,則在蝕刻黏著/ 阻障層100及種子層102的過程中,金屬頂層1〇6可以作為 蝕刻終止層,此時便可以使用對銅蝕刻速率較快的蝕刻劑 來蝕刻種子層102,如此可以減少厚金屬層1〇4之銅金屬的 消耗。 在圖示中’僅緣示出電感元件4〇之其中一線圈,然而 熟悉該項技藝者應知,整個電感元件4〇可以在此步驟完 成0Layer 106, wherein the thickness of the metal top layer 1 〇6 is, for example, between 〇·i micrometers to 3 micrometers. Referring to Figure 20, the photoresist 94a can then be removed and exposed to a seed layer 102 such as beryllium copper. Next, a thick metal layer 104 such as copper may be used as an etch mask' and the adhesion/barrier layer 100 and a seed layer 1〇 such as copper may be removed by etching. If a metal top layer 比如6 such as nickel is formed, the metal top layer 1 〇 6 can serve as an etch stop layer during the etching of the adhesion/barrier layer 100 and the seed layer 102, at which time the copper etch rate can be used. A faster etchant is used to etch the seed layer 102, which reduces the consumption of copper metal in the thick metal layer 1〇4. In the illustration, only one of the inductor elements 4A is shown, but it is known to those skilled in the art that the entire inductor element 4 can be completed in this step.
如第22圖及第23圖所不’厚金屬層1〇4亦可以是僅填 入於開口 87中之部分區域,如厚金屬層1〇4填入於開口中 的部分9 2所示。如前所述,可以利用濺鑛的方式,形成一 黏著/阻障層100及比如是銅的種子層102,並且還形成一 <瞻光阻95a ’如第22圖所示。接著可以利用電鍍的方式形成 比如是銅的厚金屬層104。之後,可以將光阻95a去除,並 且蝕刻掉黏著/阻障層100及種子層102,如第23圖所示。 清參照第5 a圖,其金屬結構係如前所述,值得注意的 是,在本實施例中並未形成比如是聚醯亞胺之聚合物層於 保護層上。電感元件1 9a係直接形成在保護層1 8上,其中 用來形成電感元件19a之金屬線路的電阻值要愈低愈好,As shown in Figs. 22 and 23, the thick metal layer 1〇4 may be a portion filled only in the opening 87, as shown by a portion 9 2 in which the thick metal layer 1〇4 is filled in the opening. As previously described, an adhesion/barrier layer 100 and a seed layer 102 such as copper may be formed by sputtering, and a <front photoresist 95a' is formed as shown in Fig. 22. A thick metal layer 104, such as copper, can then be formed by electroplating. Thereafter, the photoresist 95a can be removed, and the adhesion/barrier layer 100 and the seed layer 102 can be etched away, as shown in Fig. 23. Referring to Figure 5a, the metal structure is as described above, and it is noted that in this embodiment, a polymer layer such as polyimide is not formed on the protective layer. The inductive component 19a is formed directly on the protective layer 18, wherein the lower the resistance of the metal line used to form the inductive component 19a, the better.
第22頁 1278984 """ _ 案號 93111830 __年月日_修正 ___ 五、發明說明(19) 為了達到上述目的,當在製作電感元件19a時,可以形成 比如是金的厚金屬層。在上述之設計中,針對2· 4GHz的應 用’電感元件19a之品質參數可以從5提升至20。 如前所述’第5a圖之電感元件可以與其他的元件連 接’比如是與位在下層之接點連接,如第4圖所示,而電 感兀件之連接方向可以是,,一上一下,,的結構,如第24a圖 所示;或者電感元件之連接方向可以是"均為朝上"的結 構,如第24b圖所示。Page 22 1278984 """ _ Case No. 93118830 __年月月日_修正___ V. Invention Description (19) In order to achieve the above purpose, when the inductor element 19a is formed, a thick gold such as gold may be formed. Metal layer. In the above design, the quality parameter for the application 'inductive component 19a of 2·4 GHz can be increased from 5 to 20. As mentioned above, the inductive component of Figure 5a can be connected to other components, such as the contact at the lower layer, as shown in Figure 4, and the connection direction of the inductor component can be, , the structure of, as shown in Figure 24a; or the connection direction of the inductive component can be "all upwards" structure, as shown in Figure 24b.
聚合物層(未繪示)可以選擇性地形成於電感元件 1 9 a 上0 另外’聚合物可以是僅形成在電感元件下,而不形成 在保護層上之其他地方,如此相較於面積較大之聚合物 層’小面積之聚合物塊具有較低的内應力,如第5b圖或第 5c圖所示’其分別繪示依照本發明形成於聚合物塊上之電 感元件的剖面示意圖及上視圖。每一聚合物塊上具有至少 一電感元件,其中第5C圖繪示第一電感元件4〇a及第二電 感元件40b。 請參照第5 b圖’聚合物塊2 0 a之形成方式比如是先沈 積一聚合物層,然後再圖案化聚合物層,如此便形成聚合 物塊2 0a。而聚合物塊20a亦可以藉由網板印刷的方式所形 成,或是壓合乾膜而成。在形成聚合物塊2〇3之後,可以 形成電感元件40a、40b於聚合物塊2〇a上。 第5b圖之電感元件40a、40b之對外連接方法可以是如 前所述’其中電感元件40b比如具有兩個朝下的接點“a、 43a,其可以連接至電子接點16。而電感元件4〇3並不具有A polymer layer (not shown) may be selectively formed on the inductive element 19a. Further, the polymer may be formed only under the inductive element and not formed elsewhere on the protective layer, as compared to the area. Larger polymer layer 'small area of polymer block has lower internal stress, as shown in Figure 5b or Figure 5c', which respectively shows a schematic cross-sectional view of an inductive component formed on a polymer block in accordance with the present invention. And the top view. Each of the polymer blocks has at least one inductive component, wherein FIG. 5C illustrates the first inductive component 4a and the second inductive component 40b. Referring to Figure 5b, the polymer block 20a is formed by, for example, depositing a polymer layer and then patterning the polymer layer, thus forming a polymer block 20a. The polymer block 20a can also be formed by screen printing or by pressing a dry film. After the formation of the polymer block 2〇3, the inductance elements 40a, 40b may be formed on the polymer block 2A. The external connection method of the inductive elements 40a, 40b of FIG. 5b may be as described above, wherein the inductive element 40b has, for example, two downwardly facing contacts "a, 43a, which may be connected to the electronic contacts 16." 4〇3 does not have
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接點’但是卻可以向上連接至外界電路,如前所述。 第5c圖係繪示依照本發明之電感元件的上視圖,而第 5b圖係在第5c圖中沿著剖面線55_51)之剖面示意圖。如第 5c圖所不,聚合物塊2〇a之間係為相互隔離的,且聚合物 塊20a係僅形成在電感元件下 ',而其他未形成聚合物塊施 的區域,保護層1 8可以暴露於外。 而另外的一聚合物保護層(未繪示)可以選擇性地形成 在電感元件40a、40b上。 t而如第5b圖及第5c圖所示之聚合物塊亦可以形成在其 他的元件下,舉例而言,可以形成在比如是電阻元件及電 容元件之被動元件下。 第6 a圖及第6 b圖緣示依照本發明之另一較佳實施例。 如第6a圖所示,介電層47係位在底層線圏6〇與上層線圈62 之間,而聚合物層20、47、64可以是利用如前所述的材質 所製成。而開口66係位在最上層之聚合物層64中,可以暴 露出上層線圈62。 第6b圖繪示依照本發明另一較佳實施例之晶片結構的 剖面示意圖。其中底層線圈6 〇可以直接形成在保護層j 8 第6c圖繪示電感元件i9a係為螺線管(s〇len〇id)形式 之立體示意圖,其中電感元件19a係形成在保護層18上, 電感元件19a係包括導通孔金屬23、底層金屬結構25及頂 層金屬結構2 7 ’其中導通孔金屬2 3係位在厚聚合物層2 0 中’其係為垂直的金屬結構。透過導通孔金屬23可以使底 層金屬結構25及頂層金屬結構27電性連接。The contact 'but can be connected up to the external circuit as previously described. Figure 5c is a top view of the inductive component in accordance with the present invention, and Figure 5b is a cross-sectional view along section line 55-51) in Figure 5c. As shown in Fig. 5c, the polymer blocks 2〇a are isolated from each other, and the polymer block 20a is formed only under the inductive element, while other regions where the polymer block is not formed, the protective layer 18 Can be exposed to the outside. An additional polymer protective layer (not shown) may be selectively formed on the inductive elements 40a, 40b. The polymer blocks as shown in Figures 5b and 5c may also be formed under other components, for example, under passive components such as resistive and capacitive components. Figures 6a and 6b illustrate another preferred embodiment in accordance with the present invention. As shown in Fig. 6a, the dielectric layer 47 is positioned between the bottom layer 圏6〇 and the upper layer coil 62, and the polymer layers 20, 47, 64 may be made of the material described above. The opening 66 is positioned in the uppermost polymer layer 64 to expose the upper coil 62. Figure 6b is a cross-sectional view showing the structure of a wafer in accordance with another embodiment of the present invention. The bottom layer coil 6 〇 can be directly formed on the protective layer j 8 . FIG. 6 c is a perspective view showing the inductor element i9a in the form of a solenoid, wherein the inductor element 19 a is formed on the protective layer 18 . The inductive component 19a includes a via metal 23, an underlying metal structure 25, and a top metal structure 2 7 'where the via metal 2 3 is in the thick polymer layer 20 'which is a vertical metal structure. The underlying metal structure 25 and the top metal structure 27 can be electrically connected through the via metal 23.
1278984 案號 93111830 五、發明說明(21) 第6d圖繪示電感元件19a係為螺線管形式之立體示意 圖,其中電感元件19a係形成在第一聚合物層29上,而電 感元件19a具有導通孔金屬23,位在形成於第一聚合物層 29上之第二聚合物層中。 第6e圖係繪示第6 c圖及第6(1圖_螺線管形式之電感元 件的上視示意圖,其中透過導通孔金屬23可以使底層金屬 .結構2 5及頂層金屬結構2 7電性連接。 第6f圖繪不第6c圖到第6e圖中之電感元件的剖面示意 圖,其中第6 f圖係繪示第6 e圖中沿著剖面線6 f 6 f之剖面 示意圖。 請參照第6g圖及第6h圖,其繪示依照本發明之超環面 (toroidal)形式之電感元件的示意圖,其中電感元件係類 似環繞形狀之螺線圈。在第6g圖中,其繪示電感元件之立 體不意圖,其中電感元件68係包括導通孔金屬23a、底層 金屬結構25a及頂層金屬結構27a,而導通孔金屬23a係連 接底層金屬結構25a及頂層金屬結構27a。 第6h圖繪示第6g圖中環面(t〇r〇idal )形式之電感元件 的上視示意圖。而電感元件68之繞線特點已在之前的較 佳實施例中闡述,在此便不再贅述。 第7a圖繪示依照本發明之電容元件形成在基底1〇上的 剖面示意圖,其中絕緣層係位在保護層上。導電連接線 層1 4及接點1 6係位在基底1 〇上,且保護層丨8係形成在 連接線路層14上,而保護層18具有開口,可以暴露出接點 電 熟習該項技藝者應知,電容元件係由一下電極、 第25頁 16 1278984 _案號931 η肋η 五、發明說明(22) 谷介電層及一上電極所構成,而電容介電層係位在上電極 與下,極之間。第7a圖所示之電容元件具有一下電極42、 一電谷介電層46及一上電極45。上電極45及下電極42比如 是利用如前所述之電鍍方式形成金或銅之厚金屬層而完 成,=可以選擇性地形成比如是聚醯亞胺之聚合物保護層 於電容元件上。電容元件之接點對外連接方式比如是如前 所述’(電谷元件之接點比如是均朝下連接、一上一下的 連接或是均朝上連接)。 下電極42的厚度比如是介於〇·5微米到2〇微米之間, 介電層4 6的厚度比如是介於5 〇 〇埃到5 〇 〇 〇 〇埃之間,而上電 極45的厚度比如是介於〇· 5微米到2〇微米之間。 如第7a圖所示之在保護層上形成電容元件之結構,具 有下列優點: 、 1 ·可以減少電容元件與下層矽基底之間的寄生電容。 2 ·可以利用厚金屬層形成電容元件之電極,如此可以 減少電容元件之電阻值,特別是可以應用在無線的領域 中。 ;·可以形成高介電常數之材質在電容元件之上電極與 下電極之間,其材質比如是二氧化鈦(Ti〇2)、五氧化二鈕 (Ta205)、高分子聚合物、氮矽化合物(Si3N4)或氧矽化合 物(Si02)等’如此可以提高電容元件之電容值。 而如第7a圖所示之電容元件亦可以形成在位於保護層 18上之聚合物層上,其概念係類似如第*圖所述之將電感 元件形成在位於保護層上之聚合物層上的結構。 介電層46係為高介電常數之材質,比如是利用化學氣 1278984 --— 案號>_卿__车月日_修正___ 五、發明說明(23) 象沈積的方式沈積氮矽化合物(Si 3N4)、四乙烷基氧矽甲 烧(TEOS)、五氧化二鈕(Ta2〇5)、二氧化鈦(Ti〇2)、鈦酸 錄(SrTi03)或氮氧矽化合物(Si〇N)等。 第7b圖及第7c圖繪示電容元件之剖面示意圖。如第7b 圖所示,厚聚合物層20可以形成在保護層18上,並且透逷 圖案化製程’可以使厚聚合物層2〇暴露出接點Μ,而聚合 物層20之導通孔的直徑係小於保護層開口之直徑。然而, 在較佳的情況下,聚合物層2〇之導通孔係與保護層開口速 #通,而聚合物層20之導通孔的直徑係大於保護層開口之直 徑。藉由厚聚合物層20的配置,可以使下電極μ、上電極 45及介電層46之配置向上移動約等於聚合物層2〇之厚度的 距離,如此電容元件配置可以在更遠離基底的地方。如前 所述,比如是聚醯亞胺之聚合物層2〇的厚度可以·是介於2 微米到1 50微米之間。如此,電容元件與位在下層之金屬' 線路結構及矽基底之間的距離可以增加,故可以大幅 寄生電容的發生。 · 第7a圖及第7c圖均繪示電容元件之接點係向下連接, 而電容元件亦m上-下的連接方式,#第25圖所 •示’或是電容元件均是朝上連接,如第24b圖所示的概 Γ二戈 所示之電容元件之上電極45可以經 由位在上電極45上之聚合物層之開口,向上與一 連接,如第25圖之剖面結構所示。其中介電層35係形 電容元件之上電極45上,經由貫穿介電層以之開口以 暴露出電容元件之上電極45,藉以^^電極鈈命1278984 Case No. 93111830 V. Description of Invention (21) Figure 6d shows a schematic perspective view of the inductor element 19a in the form of a solenoid, wherein the inductor element 19a is formed on the first polymer layer 29, and the inductor element 19a is turned on. The hole metal 23 is located in the second polymer layer formed on the first polymer layer 29. Figure 6e is a top view of the inductor element in the form of Figure 6c and Figure 6 (1) in the form of a solenoid, wherein the through-hole metal 23 can make the underlying metal, the structure 25, and the top metal structure 27 Figure 6f is a schematic cross-sectional view of the inductive component in Figures 6c through 6e, wherein Figure 6f is a cross-sectional view taken along line 6 f 6 f in Figure 6 e. 6g and 6h, which show schematic diagrams of a toroidal form of an inductive component in accordance with the present invention, wherein the inductive component is a spiral coil of a surrounding shape. In the 6th diagram, the inductive component is illustrated. The three-dimensional arrangement is not intended, wherein the inductive component 68 includes a via metal 23a, an underlying metal structure 25a and a top metal structure 27a, and the via metal 23a is connected to the underlying metal structure 25a and the top metal structure 27a. Figure 6h shows the 6g The top view of the inductive component in the form of a torus (t〇r〇idal) is shown in the figure. The winding characteristics of the inductive component 68 have been described in the prior preferred embodiment and will not be described here. A capacitive element in accordance with the present invention is formed in A schematic cross-sectional view of the bottom layer, wherein the insulating layer is on the protective layer. The conductive connecting layer 14 and the contact 16 are located on the substrate 1 and the protective layer 8 is formed on the connecting layer 14. The protective layer 18 has an opening, which can expose the contact point. It is known to those skilled in the art that the capacitive element is from the lower electrode, page 25, 16 1278984 _ case number 931 η rib η five, invention description (22) The electrical layer and an upper electrode are formed, and the capacitor dielectric layer is located between the upper electrode and the lower electrode. The capacitive element shown in FIG. 7a has a lower electrode 42, a valley dielectric layer 46 and an upper electrode. 45. The upper electrode 45 and the lower electrode 42 are formed, for example, by forming a thick metal layer of gold or copper by electroplating as described above, and a polymer protective layer such as polyimine may be selectively formed on the capacitor element. The contact point of the capacitor element is connected to the external connection as described above, for example, (the contacts of the electric grid element are, for example, a downward connection, a top-to-bottom connection or an upward connection). The thickness of the lower electrode 42 is as described above. Between 5 μm and 2 μm, dielectric The thickness of 4 6 is, for example, between 5 〇〇 and 5 〇〇〇〇, and the thickness of the upper electrode 45 is, for example, between 〇 5 μm and 2 μm. As shown in Fig. 7a Forming the structure of the capacitor element on the protective layer has the following advantages: 1. The parasitic capacitance between the capacitor element and the underlying germanium substrate can be reduced. 2 • The electrode of the capacitor element can be formed by a thick metal layer, so that the capacitor element can be reduced. The resistance value can be applied especially in the field of wireless. The material can form a high dielectric constant between the upper electrode and the lower electrode of the capacitor element, such as titanium dioxide (Ti〇2) and pentoxide oxide. (Ta205), a high molecular polymer, a nitrogen ruthenium compound (Si3N4), or an oxonium compound (SiO2), etc., can increase the capacitance value of the capacitor element. The capacitive element as shown in Fig. 7a can also be formed on the polymer layer on the protective layer 18, the concept of which is similar to that described in Fig. 4, in which the inductive element is formed on the polymer layer on the protective layer. Structure. The dielectric layer 46 is made of a high dielectric constant material, for example, using chemical gas 1278984 --- case number > _ _ _ _ _ _ _ _ _ _ _ 5, invention description (23) deposition of nitrogen like deposition Antimony compound (Si 3N4), tetraethyl oxysulfonate (TEOS), pentoxide pentoxide (Ta 2 〇 5), titanium dioxide (Ti 〇 2 ), titanate (SrTiO 3 ) or oxynitride (Si 〇 ) N) and so on. 7b and 7c are schematic cross-sectional views showing the capacitor element. As shown in FIG. 7b, a thick polymer layer 20 can be formed on the protective layer 18, and the through-patterning process can cause the thick polymer layer 2 to expose the contact Μ, while the conductive layer 20 of the via hole The diameter is smaller than the diameter of the opening of the protective layer. However, in a preferred case, the via layer of the polymer layer 2 is connected to the opening speed of the protective layer, and the diameter of the via hole of the polymer layer 20 is larger than the diameter of the opening of the protective layer. By the configuration of the thick polymer layer 20, the arrangement of the lower electrode μ, the upper electrode 45 and the dielectric layer 46 can be moved upward by a distance equal to the thickness of the polymer layer 2〇, so that the capacitive element configuration can be further away from the substrate. local. As mentioned before, the thickness of the polymer layer 2, such as polyimine, can be between 2 microns and 150 microns. Thus, the distance between the capacitor element and the metal-line structure and the germanium substrate located in the lower layer can be increased, so that the parasitic capacitance can be greatly generated. · Figures 7a and 7c show that the contacts of the capacitive element are connected downwards, and the capacitive elements are also connected in an up-down manner, #第25图•示' or the capacitive elements are connected upwards. The upper electrode 45 of the capacitive element, as shown in Fig. 24b, can be connected upwards through a opening of the polymer layer on the upper electrode 45, as shown in the cross-sectional structure of Fig. 25. . The dielectric layer 35 is formed on the upper electrode 45 of the capacitive element, and is opened through the dielectric layer to expose the upper electrode 45 of the capacitive element, thereby
第27頁 1278984 __案號93111830 午月日 條正 五、發明說明(24) 路電性連接。 而一聚合物保護層(未繪示)可以選擇性地形成在如第 7a圖至第7c圖所示之電容元件上。 第8圖繪示基底1〇的剖面示意圖,基底上形成有一 保護層18,而電阻元件48係位在保護層18上。熟習該項技 藝者應知,電阻元件係由能夠提供電性阻值之材質所構 成’且電流能夠留經該材質。電阻元件4 8之材質比如是鈕 氮化合物(TaN)、鎳鉻合金(NiCr)、鎳錫合金(NiSn)、鎢 <|^w)、鈦鎢合金(Tiw)、鈦氮化合物(TiN)、鉻(Cr)、鈦 (Ti)、鎳(Ni)或鈕矽化合物(TaSi)#。在上述的這些材質 中,鎳鉻合金能夠提供最佳的電阻溫度係數(Temperature C一coefficient of Resistance),可則、至5 卿厂 c。電阻 兀件之長度、厚度及寬度可以依照不同的應用而設計。而 I以應用如第7a圖至第7c圖所示之配置電容元件的概念, 來酉己斤如第8圖所示之電阻元件,其中電阻元件係形成在 μ ,圖;第⑽圖繪示依照本發明形成在厚聚合物層20 •連接。藉由增加電阻元…以與接點16 丁一丞底之間的距離(所增加的 離係大致上等於聚合物層2〇的厚^ 與基底之間的寄生電容效應的=以可二低電阻元件Page 27 1278984 __ Case No. 93111830 Noon Day Article 5, invention description (24) Road connection. A polymer protective layer (not shown) can be selectively formed on the capacitor elements as shown in Figs. 7a to 7c. Figure 8 is a schematic cross-sectional view of the substrate 1 . A protective layer 18 is formed on the substrate, and the resistive element 48 is tied to the protective layer 18. As will be appreciated by those skilled in the art, the resistive element is constructed of a material that provides electrical resistance and current can be retained by the material. The material of the resistive element 48 is, for example, a nitrogen compound (TaN), a nickel-chromium alloy (NiCr), a nickel-tin alloy (NiSn), a tungsten alloy, a titanium-titanium alloy (Tiw), and a titanium-nitrogen compound (TiN). , chromium (Cr), titanium (Ti), nickel (Ni) or button compound (TaSi) #. Among the above materials, nickel-chromium alloys can provide the best temperature coefficient of resistance (Temperature C-coefficient of Resistance). The length, thickness and width of the resistor element can be designed for different applications. I use the concept of arranging capacitive elements as shown in Figures 7a to 7c to remedy the resistive elements as shown in Fig. 8, wherein the resistive elements are formed in μ, Fig. 10; Formed in a thick polymer layer 20 in accordance with the present invention. By adding a resistance element... to the distance between the junction 16 and the bottom of the junction 16 (the added separation is substantially equal to the thickness of the polymer layer 2〇 and the parasitic capacitance effect between the substrate = the second low resistance element)
作下的電性效能) 的知耗,故可以提升在高頻運 Β如第8圖、第9a圖及第9b圖所示之電阻元件 I^J T it # °然而電阻元件亦 0 ” ----可以疋一上一下的連接,The power consumption of the underlying electrical performance can be improved in the high frequency operation such as the resistive element I^JT it # ° shown in Fig. 8, Fig. 9a and Fig. 9b. However, the resistive element is also 0" -- -- You can pick up the connection,
1278984 案號93111830 _年月曰 五、發明說明(25) 如第2.6圖所示,或是電阻元件之接點均是朝上連接,其不 以參考如第24b圖中電感元件40均是朝上連接的概念。、 而另一聚合物層可以選擇性地形成在如第8圖了第9a 圖及第9 b圖所示之電阻元件上,藉以保護電阻元件。 请參照第1 0圖及第11圖,其繪示依照本發明在保護層 上之另一種製程。在本實施例中,可以藉由形成凸塊使接 點1 6與位在上面之電子元件電性連接,比如是與已製作完 成之電感元件、電容元件、電阻元件或是其他的被動元件 丨電性連接。而連接金屬50可以形成在聚合物層之開口内, 其中聚合物層之開口係對準於較小之保護層的開口,如此 連接金屬50可以與接點16連接,作為凸塊底層-金屬(ϋβΜ) 之用。利用傳統的電鍍製程、植球製程或網板印刷製程, 可以开> 成凸塊於凸塊底層金屬5 〇上,而在助銲劑形成於凸 塊上之後,可以進行回銲的步驟。接著,已製作完成的電 子元件54可以連接到凸塊52上,其中已製作完成的電子元 件54具有銲料53,如此可以提升接合性。 上述之製程係類似於常應用在電子元件與印刷電路板 接合的表面黏著技術。已製作完成的電子元件54比如是電 ’感元件、電容元件或是電阻元件。 第11圖繪示利用凸塊56及凸塊底層金屬5〇將已製作完 成的電子元件54直接形成於保護層18上的結構。 由於已製作完成的電子元件並不是如習知技術係形成 在印刷電路板上,因此如第10圖及第11圖所示之已製作完 成的電子元件具有較佳的效能,且成本並不高。 凸塊底層金屬50可以是如本發明之第12圖到第23圖所 I麵 Ιϋ·Ι 第29頁 1278984 I- 93UI830 -日- 膝丨不 ,一· 五、發明說明(26) 不之金屬結構,然而若是利用金作為厚金屬層時,凸塊底 層金屬50的厚度可以是介於0·1微米到2〇微米之間,在較 佳的情況下,凸塊底層金屬50係為較薄的尺寸,如此在製 作完成之後,可以避免在凸塊底層金屬5〇之介面附近的凸 塊材質具有高濃度的金。 上述之被動元件之配置方式至少具有下列的優點: 1.由於已製作元成的電子元件可以提供適當的參數’ 並且可以接合在靠近晶片中線路的位置,因此藉由本發明 <•之被動元件的設計概念可以達到真正的系統化晶片的表 現。 2·由於已製作完成的電子元件可以接合在靠近晶片中 線路的位置,因此能夠減少寄生現象的發生。 3·在本發明中’由於可以選擇具有適當設計參數之已 製作完成的電子元件裝配在保護層上,此種設計可以減少 已製作完成的電容元件及已製作完成的電感元件之電阻效 應’為了更清楚的說明,下面有針對習知技術與本發明作 比較說明: ^ 習知技術係利用細的金屬導線來製作電感元件,而若 疋為了要減少電阻效應,必須製作較寬的線圈,則會使得 電感元件之表面面積增加。另外,習知技術會具有較大之 電感元件之寄生電容的現象,並且在基底内會有嚴重的渦 電流損耗。1278984 Case No. 93111830 _ 曰 曰 、 、, invention description (25) As shown in Figure 2.6, or the contact of the resistive element is connected upwards, which is not referred to The concept of connection. And another polymer layer can be selectively formed on the resistive element as shown in Fig. 8 and Fig. 9a and Fig. 9b, thereby protecting the resistive element. Referring to Figures 10 and 11, there is shown another process on the protective layer in accordance with the present invention. In this embodiment, the contact 16 can be electrically connected to the electronic component located thereon by forming a bump, such as an inductive component, a capacitive component, a resistive component, or other passive component. Electrical connection. The connecting metal 50 may be formed in the opening of the polymer layer, wherein the opening of the polymer layer is aligned with the opening of the smaller protective layer, so that the connecting metal 50 may be connected to the joint 16 as a bump underlayer-metal ( ϋβΜ). Using a conventional electroplating process, a ball-planting process, or a screen printing process, a bump can be formed on the under bump metal 5 ,, and after the flux is formed on the bump, a reflow step can be performed. Next, the fabricated electronic component 54 can be attached to the bump 52, wherein the finished electronic component 54 has solder 53 so that the bondability can be improved. The above process is similar to the surface adhesion technique commonly used in the bonding of electronic components to printed circuit boards. The finished electronic component 54 is, for example, an electrical sensing component, a capacitive component or a resistive component. Fig. 11 is a view showing the structure in which the completed electronic component 54 is directly formed on the protective layer 18 by using the bump 56 and the bump underlayer metal 5?. Since the completed electronic components are not formed on the printed circuit board as in the prior art, the completed electronic components as shown in FIGS. 10 and 11 have better performance and are not costly. . The bump underlayer metal 50 may be as shown in Fig. 12 to Fig. 23 of the present invention. 29·Ι Page 29 1278984 I-93UI830 - Day - knee 丨 not, 1-5, invention description (26) Metal of no Structure, however, if gold is used as the thick metal layer, the thickness of the under bump metal 50 may be between 0.1 micrometer and 2 micrometers. In the preferred case, the bump metal 50 is thinner. The size of the bump material in the vicinity of the interface of the under bump metal 5 具有 can be prevented from having a high concentration of gold. The above-described configuration of the passive components has at least the following advantages: 1. Passive components of the present invention by virtue of the fact that the fabricated electronic components can provide appropriate parameters 'and can be bonded to locations near the lines in the wafer. The design concept can achieve the performance of a truly systematic wafer. 2. Since the fabricated electronic component can be bonded to a position close to the line in the wafer, the occurrence of parasitic phenomena can be reduced. 3. In the present invention, 'the design can reduce the resistance effect of the fabricated capacitor element and the completed inductor element because the fabricated electronic component with appropriate design parameters can be selected to be mounted on the protective layer. More clearly, the following is a description of the prior art and the present invention: ^ The prior art uses a thin metal wire to make an inductive component, and if it is necessary to make a wider coil in order to reduce the resistance effect, This will increase the surface area of the inductive component. In addition, conventional techniques have a large parasitic capacitance of the inductive component and severe eddy current losses in the substrate.
然而本發明,係採用厚金屬層作為線路,因此可以減 ^電阻效應。另外’聚合物還可以塾在被動元件與下層結 構之間’ #必匕1以減少寄生效應,由於寄生效應的減少,However, in the present invention, a thick metal layer is used as the wiring, so that the resistance effect can be reduced. In addition, the polymer can also be trapped between the passive component and the underlying structure to reduce parasitic effects due to parasitic effects.
Η 第30頁 1278984 _案號93111830_ 年月日 修正_ 五、發明說明(27) 會使得共振頻率提高,故適合高頻電路的操作。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作各種之更動與潤飾,因此本發明之隔離 範圍當視後附之申請專利範圍所界定者為準。‘Η Page 30 1278984 _ Case No. 93118830_ Year Month Day Correction _ V. Invention Description (27) The resonance frequency is increased, so it is suitable for the operation of high frequency circuits. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of isolation is subject to the definition of the scope of the patent application. ‘
第31頁 1278984Page 31 1278984
【圖式簡單說明】 383, 916號之連接線 形成在厚聚醯亞胺 第1圖繪示依照美國專利公告第6, 路結構的剖面示意圖。 第2圖繪示依照本發明之電感元件 層上之剖面示意圖。 之上視示意圖。 的剖面示意圖,其 並且藉由一導電材 矽基底。 形成在保護層上之[Simple description of the drawing] The connecting line of No. 383, No. 916 is formed on the thick polyimine. Fig. 1 is a schematic cross-sectional view showing the structure of the road according to the sixth paragraph of the U.S. Patent Publication. Fig. 2 is a schematic cross-sectional view showing the layer of the inductor element in accordance with the present invention. The top view is schematic. A schematic cross-sectional view of the substrate by a conductive material. Formed on the protective layer
第3圖繪示依照本發明之電感元件 第4圖繪示依照本發明之晶片結構 中電感元件係形成在厚聚醯亞胺層上, 質可以避免電感元件影響到位在下層的 第5 a圖繪示依照本發明之電感元件 剖面示意圖。 第5b圖㈣依照本發明之多個電感元件形成在比如是 高分子聚合物之絕緣層上的剖面示意圖。 第5c圖繪示依照本發明之多個電感元件形成在比如是 高分子聚合物之絕緣層上的上視圖。 第6a圖繪示依照本發明之變壓器形成在比如是高分子 聚合物之絕緣層上的剖面示意圖,其中絕緣層係位在保護 層上。 # 第6b圖繪示依照本發明之變壓器的剖面示意圖,其中 位在下方的線圈係位在保護層上。 第6c圖繪示依照本發明另一較佳實施例之螺線管形狀 的電感元件之立體示意圖,其中電感元件係位在保護層 上0FIG. 3 is a view showing a fourth embodiment of the inductive component in accordance with the present invention, wherein the inductive component is formed on the thick polyimide layer in order to prevent the inductive component from being affected in the lower layer. A schematic cross-sectional view of an inductive component in accordance with the present invention is shown. Fig. 5b (d) is a schematic cross-sectional view showing a plurality of inductance elements according to the present invention formed on an insulating layer such as a polymer. Figure 5c is a top view showing the formation of a plurality of inductive elements in accordance with the present invention on an insulating layer such as a high molecular polymer. Fig. 6a is a schematic cross-sectional view showing the formation of a transformer according to the present invention on an insulating layer such as a polymer, wherein the insulating layer is tied to the protective layer. #图图bb is a cross-sectional view of a transformer in accordance with the present invention, wherein the coils located below are tied to the protective layer. FIG. 6c is a perspective view of a solenoid-shaped inductor element according to another preferred embodiment of the present invention, wherein the inductor element is tied to the protective layer.
I 第6d圖繪示依照本發明另一較佳實施例之螺線管形狀Figure 6d is a diagram showing the shape of a solenoid according to another preferred embodiment of the present invention.
第32頁 1278984Page 32 1278984
93111830 JE_L· 曰 修正 的 電 感元 件 之 分 子 聚合 物 之 第6e 圖 係 圖 0 第6f 圖 係 圖 〇 第6g 圖 繪 立 體 示意 圖 〇 第6h 圖 繪 示 意 圖。 第6 ^圖係為第6 e圖中沿著剖面線6 f - 6 f之剖面示意 高八^7a — 7C圖繪示依照本發明之電容元件形成在比如是 I^1 ί合物之絕緣層上的剖面示意圖,其中絕緣層係位 % Ί木邊層上。 剖面繪示依照本發明之電阻元件形成在保護層上的 忍圓。 如是Ϊ父圖及第9Β圖繪示依照本發明之電阻元件形成在比 为子聚合物之厚絕緣層上的剖面其 緣層係位在保護層上。 〜圃其中厚絕 中已圖纷示依照本發明之晶片結構的剖面示意圖,其 ^作完成的電子元件係利用表面黏著技術黏著於比如 W分子聚合物之厚絕緣層上。 、 第1 1圖繪示依照本發明之晶片結構Μ Μ & + i m 中已制A , Λ 傅的剖面不意圖,i b匕製作完成的電子元件係利用表面黏荃杜& & _ _其 層上。 仏田點者技術黏著於保護93111830 JE_L· 第 Modified 6th figure of the molecular polymer of the inductive element Fig. 0 6f drawing system 〇 6g drawing vertical figure 〇 Fig. 6h Fig. Fig. 6 is a cross-sectional view taken along line 6 f - 6 f in Fig. 6 e. The height is shown in Fig. 8 - 7a - 7C. The capacitor element according to the present invention is formed in an insulation such as I^1. A schematic cross-sectional view of the layer in which the insulating layer is at the % eucalyptus edge layer. The cross-section shows a forbearing circle formed on the protective layer by the resistive element according to the present invention. The figure of the parent and the figure 9 show that the resistive element according to the present invention is formed on the thick insulating layer of the sub-polymer, and the edge layer is on the protective layer. 〜 圃 圃 圃 纷 纷 纷 纷 纷 纷 纷 纷 纷 纷 纷 纷 纷 纷 纷 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 剖面 晶片 晶片 晶片 晶片 晶片 晶片 。 FIG. 1 is a cross-sectional view showing the structure of the wafer structure Μ Μ & + im in accordance with the present invention. The electronic component produced by the ib is made of surface adhesive Du && _ _ On its layer. Putian point technology is attached to protection
1278984 案號 93111830 a_a. 曰 修正 圖式簡單說明 第1 2圖至第1 8圖繪示依照本發明以金為材質之金屬結 構的剖面示意圖,其中金屬結構係穿過比如是高分子聚合 物之絕緣層。 第1 9圖至第2 3圖繪示依照本發明以銅為材質之金屬結 構的剖面示意圖,其中金屬結構係穿過比如是高分子聚合 物之絕緣層。 第24a圖至第24c圖繪示依照本發明另一種連接電感元 件的方法。 第25圖及第26圖分別繪示依照本發明另一種連接電容 元件及電阻元件的方法。 12 14 18 19a 20a 23a 25a 27a 主要元件符號說明】 10 :矽基底 11 内部介電層 金屬/介電層 保護層 19 :電感元件 聚合物塊 導通孔金屬 底層金屬結構 :電晶體 1 3 :金屬連線 16 :電子接點 :開口 20 :聚合物層 2 3 :導通孔金屬 25 :底層金屬結構 27 :頂層金屬結構 2 6 :線路 頂層金屬結構 28 線 路 29 :第一聚合物層 22 開 π 30 :路徑 32 路 徑 34 :路徑 第34頁1278984 Case No. 93111830 a_a. 曰Revision Diagram Simple Description FIGS. 1 2 to 18 show schematic cross-sectional views of a metal structure made of gold in accordance with the present invention, wherein the metal structure is passed through, for example, a polymer. Insulation. Figs. 19 to 2 are schematic cross-sectional views showing a metal structure made of copper in accordance with the present invention, wherein the metal structure is passed through an insulating layer such as a polymer. Figures 24a through 24c illustrate another method of connecting an inductive component in accordance with the present invention. 25 and 26 respectively illustrate another method of connecting a capacitive element and a resistive element in accordance with the present invention. 12 14 18 19a 20a 23a 25a 27a Main component symbol description] 10: germanium substrate 11 inner dielectric layer metal/dielectric layer protective layer 19: inductive component polymer block via hole metal underlayer metal structure: transistor 13: metal Line 16: Electronic Contact: Opening 20: Polymer Layer 2 3: Via Metal 25: Underlying Metal Structure 27: Top Metal Structure 2 6: Line Top Metal Structure 28 Line 29: First Polymer Layer 22 Open π 30 : Path 32 Path 34: Path第34页
1278984 案號 93111830 曰 修正 圖式簡單說明 35 : 36a 38 : 3 9 ·· 40a 41 : 42 ·· 43a 44a 46 : 48 : 52 ·· 54 : 56 : 62 : 66 : 80 ·· 82 : 85 : 87 : 90 : 94 : 100 104 接點 下電極 :接點 :導電片 介電層 電阻元件 凸塊 介電層 3 6 :開口 :開口 37 :開口 開口 38a :開口 接點 4 0 ·電感兀件 :第一電感元件 40b :第二電感元件 41 a ·接點 4 3 :接點 44 :導體 4 5 :上電極 4 7 :第二聚合物層 50 :連接金屬 53 :銲料 已製作完成的電子元件 凸塊 6 0 :底層線圈 上層線圈 64:聚合物層 開口 6 8 :電感元件 基底 8 1 :金屬接點 開口 8 4 :保護層 側壁 8 6 :聚合物層 開口 88 :黏著/阻障層 種子層 92:厚金屬層 光阻 95a :光阻 黏著/阻障層 1 0 2 :種子層 厚金屬層 106 :金屬頂層1278984 Case No. 93111830 曰Revision diagram simple explanation 35 : 36a 38 : 3 9 ·· 40a 41 : 42 ·· 43a 44a 46 : 48 : 52 ·· 54 : 56 : 62 : 66 : 80 ·· 82 : 85 : 87 : 90 : 94 : 100 104 Contact lower electrode : Contact : Conductive sheet Dielectric layer resistor element bump dielectric layer 3 6 : Opening : Opening 37 : Opening opening 38a : Opening contact 4 0 · Inductive component: An inductance element 40b: a second inductance element 41a, a contact 43: a junction 44: a conductor 4 5: an upper electrode 4 7 : a second polymer layer 50: a connection metal 53: a solder bump having been fabricated 6 0 : bottom layer coil upper layer coil 64: polymer layer opening 6 8 : inductance element substrate 8 1 : metal contact opening 8 4 : protective layer side wall 8 6 : polymer layer opening 88 : adhesion/barrier layer seed layer 92: Thick metal layer photoresist 95a: photoresist adhesion/barrier layer 1 0 2 : seed layer thick metal layer 106: metal top layer
第35頁Page 35
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