1273684 九、發明說明： 【發明所屬之技術領域】 本發明係有關—種料半導體封裝構造之測試裝置，更 特別有關一種氣壓式半導體測試裝置。 【先前技術】 隨著微小化以及高運作速度需求的增加，多晶片封裝構 造在許多電子裝置越來越吸引人。多晶片封裝構造可藉由 將兩個或兩個以上之晶片組合在單一封裝構造中，來使整 個系統之體積最小化，而具有較高的運作速度。此外，多 晶片封裝構造可減少晶片間連接線路之長度而降低訊號延 遲以及存取時間。 不論係單晶片或多晶片封裝構造完成封裝後，均須經過 一封裝測試，用以測試其電氣特性。習知之封裝測試用於 具有陣列式錫球之半導體封裝構造，已揭示於中華民國專 利公告第122371 1號，在此併入本文參考。 第la與lb圖為習知之封裝測試用於具有陣列式錫球之 半導體封裝構造之示意圖。該封裝測試裝置丨〇〇包含一壓 貨頭130以及一測試座（socket)12〇。該壓貨頭13〇具有一 壓板134，於該壓板134下方有一塊軟墊136 ;該測試座 120上則具有複數個探針（pr〇be)122。測試時，先將待測之 球格陣列封裝構造丨丨〇置於該測試座丨2〇上，並使該待測 之封裝構造110之基板114下方的錫球116與該等探針122 接觸。而該待測封裝構造丨丨〇之基板i i 4上方，有複數個 晶片112a及112b，該等晶片U2a、112b可具有不同的大 1273684 小與厚度，藉由例如打線或覆晶等方式（圖未示），與該等 錫球11 6包性連接，使能夠做訊號的輸出入。進行測試時， 將省壓貝碩13〇壓在該封裝構造11〇上，使該等錫球US 與該：探# 1 22能更緊密的接觸，以得到良好的電性連接 ^見第ib圖）。接著藉由該等探針122輸入電訊號至該等 曰曰片112a、11 2b上，以量測該封裝構造i丨〇的電氣特性。1273684 IX. Description of the Invention: [Technical Field] The present invention relates to a test device for a seed semiconductor package structure, and more particularly to a gas pressure semiconductor test device. [Prior Art] As the demand for miniaturization and high operational speed increases, multi-chip package construction is becoming more and more attractive in many electronic devices. The multi-chip package construction can minimize the volume of the entire system by combining two or more wafers in a single package configuration, while having a higher operating speed. In addition, the multi-chip package construction reduces the length of the connection between the wafers and reduces signal delay and access time. Whether packaged in a single-wafer or multi-wafer package, a package test is required to test its electrical characteristics. A conventional package test for a semiconductor package structure having an array of solder balls is disclosed in the Republic of China Patent Publication No. 122371 1 which is incorporated herein by reference. The first and lb diagrams are schematic diagrams of conventional package testing for semiconductor package construction with array solder balls. The package test device 丨〇〇 includes a press head 130 and a test socket 12 〇. The press head 13 has a pressure plate 134, and a pressure pad 136 is disposed below the pressure plate 134; the test socket 120 has a plurality of probes 122. In the test, the ball grid array package structure to be tested is first placed on the test socket 2, and the solder balls 116 under the substrate 114 of the package structure 110 to be tested are brought into contact with the probes 122. . Above the substrate ii 4 of the package structure to be tested, there are a plurality of wafers 112a and 112b, and the wafers U2a, 112b may have different diameters of 1273684 and a thickness, for example, by wire bonding or flip chip. Not shown), it is connected to the solder balls 11 6 to enable the input and output of signals. During the test, the pressure-relief Besuo 13 is pressed onto the package structure 11〇, so that the solder balls US can be in closer contact with the probe #1 22 to obtain a good electrical connection. Figure). Electrical signals are then input to the dies 112a, 11bb by the probes 122 to measure the electrical characteristics of the package structure.
上述習知之封裝測試裝置1〇〇於測試過程中，其壓板 134下方的軟塾136係緊屢在該等晶片仙、⑽上，备 ^應力集中而破壞產品之虞；再者，料等晶片ii2a、im :有無法對其施壓之晶片，例如被動元件，此—習知之封 裟測试裝置1〇〇，即無法用以測試。 有鑑於此’便有須蔣羽JLi 上述之問題。 “的封裝測試裝置改良，以解決 【發明内容】 種測試半導體裝置之氣壓裝 氣特性，可避免破壞基板上 本發明之目的在於提供一 置，用以測試半導體裝置之電 的元件。 為達上述目的，本發 導體裝置的測試座上， 該氣密的内部空間注入 力’均勻地作用在待測 接點能與測試座的探針 明以_^ 客 * I盍氣密蓋於容承有待測半 / v、内部空間達成氣密狀態。於 ".....~ ' ’使該氣體所產生的氣體壓 、半&體裝置上，讓其下方的訊號 条β地電性接觸。 此外’本發明的另—實施態樣係於壓貨頭上裝設可產生 1273684 正氣壓與負氣壓的氣壓裝置，並於該測貨頭上設置一罩 蓋’使因負氣壓而被該壓貨頭所吸附的待測半導體裝置置 於測試座後，該氣壓裝置可於該罩蓋所罩蓋的空間内產生 正氣壓’以使該半導體裝置下方的訊號接點能與測試座的 探針緊密地電性接觸。 為了讓本發明之上述和其他目的、特徵、和優點能更明 φ 顯’下文特舉本發明實施例，並配合所附圖示，作詳細說 明如下。 【實施方式】 現請參考第2圖，其顯示根據本發明第一實施例之測試 裝置200,用於測試一半導體封裝構造21〇，該半導體封裝 構造210具有至少一個晶片212以及複數個位於下表面218 的接點216。該測試裝置200包含一測試座22〇，該測試座 220具有複數個探針222,其一端可電性連接於一外部電氣 • 特性測試裝置（圖未示）。 私才、 當對該半導體封裝構造210進行測試時，先將其置於該 測試座220上，使其複數個接點216與該等探針222接觸: 而該半導體封袭構造210的下表面218周緣則與該測試座 220接觸。罩蓋23〇氣密蓋於該測試座22〇上，於其間界 定出一罩蓋空間260。以一氣壓裝置24〇於該罩蓋空間26〇 内產生正氣壓，該半導體封裝構造21〇會因該氣壓而使得 該等接點216與該特針222更緊密的電性㈣。對該等 探針222的其中-些施予電信號，該電信號經由該等接點 1273684 * ^而込至該包含晶片212之半導體封裝構造21〇中，再 =由/、他如針222量測由該半導體封裝構造21〇送出的電 仏號即可測得該半導體封裝構造〇之電氣特性。 二為了彳于到更佳的氣密效果，可於該半導體封裝構造 式座220㈣的位置之間，設一具彈性之氣密塾 匕外亦可於該罩盍230與該測試座220接觸的位置 之:’設另—具彈性之氣密塾226。上述氣密墊224、226 的叹置，可增加氣密效果，使得該等接點於測試時更 易與，等探針222錢密的電性接觸。此外，施予該半導 體ί衣構k 210的氣體壓力，係依該半導體封裝構造21〇 之接卿數概算出’平均每接腳至少需3G克之壓力計算，故 氣體壓力係依各種半導體封裝構造21〇尺寸而異，例如 BGA40X4G之產品可施予每平方公分2 5公斤之氣㈣ 力，以得到較佳的電性接觸。為了避免測試過程中因壓力 造成該等接點216或探針222的損壞，該等探針222可設 計成具有彈性的結構，而該等接點216可為锡球（例如嶋 結構）、針腳或其他結構。 根據本發明第一實施例之測試裝置，其所施加的氣體磨 力係均勻地作用在待測半導體裝置的上表面，降低應力集 中而破壞產品的可能性。 、 現明蒼考第3a與3b圖，其顯示根據本發明第二實施例 之測試裝置300,用於測試一半導體封裝構造31〇，該半導 體封裝構造310具有至少一個晶# 312以及複數個位於下 表面318的接點316,該測試裝置3〇〇包含一測試座32〇， 1273684 該測試座320具有複數個探針322，其_端可電性連接於 -外邛電乳特性測試裝置（圖未示）。該測試裝置3〇〇還包 '、測知頭350，其具有一可產生正氣壓以及_氣壓的氣 壓裝置340，其中該測貨頭35〇可藉所產生的負氣壓吸附 忒待測之半導體封裝構造3丨〇，使其置於該測試座3別内； 此外，於該測貨頭350上設有一罩蓋33〇。 當對該半導體封裝構造310進行測試時，以測貨頭35〇 吸附（見第3a圖）並將其置於該測試座32〇後，該罩蓋 330會與該測試座32〇氣密接觸（見第3b圖），同時該封 裝構造310的複數個接點316與該等探針322接觸，而該 半導體封裝構造31〇的下表面318周緣則與該測試座32〇 接觸。罩蓋330氣密蓋於該測試座32〇上，於其間界定出 一罩蓋空間360。以該氣壓裝置34〇於該罩蓋空間36〇内 產生正氣壓，該半導體封裝構造31〇會因該氣壓而使得該 等接點316與該等探針322更緊密的電性接觸。 為了得到更佳的氣密效果，可於該半導體封裝構造31〇 與該測試座320接觸的位置之間，設一具彈性之氣密墊 324;此外，亦可於該罩蓋33〇與該測試座32〇接觸的位置 之間，設另一具彈性之氣密墊326。上述氣密墊324、 的作用，類同於第一實施例之氣密墊224、226的作用，於 此不再贅述。此外，可施予該半導體封裝構造3 1〇約每平 方么刀2 · 5公斤的氣體壓力，以得到較佳的電性接觸。為 了避免測試過程中因壓力造成該等接點3 16或探針P 2的 損壞，該等探針322可設計成具有彈性的結構，而該等接 點3 16可為錫球（例如bgA結構）、針腳或其他結構。 1273684 根據本發明第二實施例之測試裝置，其所具有的效用類 同於第一實施例的測試裝置，於此不再賢述。 雖然前述的描述及圖示已揭示太恭日日 词不丰發明之較佳實施例，必 須瞭解到各種增添、修改和取代可妒你 〆 %代』此使用於本發明較佳實 施例，而不會脫離如所附申請糞剎鉻 Τ明寻利辄圍所界定的本發明原 理之精神及範圍。熟悉該技藝者將 仪π百騎可體會本發明可能使用 於很多形式'結構、佈i、比例、材料、元件和組件的修The above-mentioned conventional package testing device 1 is in the process of testing, and the soft 塾 136 under the pressing plate 134 is fastened on the wafers, (10), and the stress is concentrated to destroy the product; Ii2a, im: There are wafers that cannot be pressed, such as passive components. This is a conventional sealing test device that cannot be used for testing. In view of this, there is a problem with Jiang Yu JLi mentioned above. "The package test device is modified to solve the problem of the present invention. It is possible to avoid damage to the substrate. The object of the present invention is to provide a device for testing the electrical components of the semiconductor device. OBJECTIVE: In the test socket of the present conductor assembly, the airtight internal space injection force acts uniformly on the probe to be tested and the probe of the test socket is clearly sealed by the airtight cover. Half / v, the internal space is to be airtight. On the gas pressure, semi- & body device generated by the gas, let the signal strip below it be electrically In addition, in another embodiment of the present invention, a pneumatic device capable of generating a positive pressure of 1273684 and a negative air pressure is disposed on the pressure head, and a cover is disposed on the measuring head to be pressed by the negative air pressure. After the semiconductor device to be tested adsorbed by the cargo head is placed in the test socket, the air pressure device can generate positive air pressure in the space covered by the cover to enable the signal contact under the semiconductor device and the probe of the test socket. Tight electrical connection The above and other objects, features, and advantages of the present invention will be made apparent by the description of the embodiments of the invention and The figure shows a test apparatus 200 according to a first embodiment of the present invention for testing a semiconductor package structure 21 having at least one wafer 212 and a plurality of contacts 216 on the lower surface 218. The test The device 200 includes a test socket 22 having a plurality of probes 222, one end of which is electrically connected to an external electrical characteristic test device (not shown). When the test is performed, it is first placed on the test socket 220 with its plurality of contacts 216 in contact with the probes 222: and the periphery of the lower surface 218 of the semiconductor seal structure 210 is in contact with the test socket 220. The cover 23 is hermetically sealed on the test seat 22, and defines a cover space 260 therebetween. The positive air pressure is generated by the air pressure device 24 in the cover space 26, and the semiconductor package structure 21〇 Due to the air pressure, the contacts 216 are more closely related to the special pins 222. The electrical signals are applied to the probes 222 via the contacts 1273684*^. In the semiconductor package structure 21 including the wafer 212, the electrical characteristics of the semiconductor package structure can be measured by measuring the electric signal transmitted from the semiconductor package structure 21 by the needle 222. In order to achieve a better airtight effect, an elastic airtightness may be provided between the positions of the semiconductor package structure base 220 (4), and the cover 230 may be in contact with the test socket 220. Position: 'Set another - flexible airtight 塾 226. The sigh of the airtight pads 224, 226 can increase the airtight effect, making the contacts easier to test during the test, and the probe 222 is in close electrical contact. In addition, the gas pressure applied to the semiconductor device k 210 is calculated based on the number of contacts of the semiconductor package structure 21 'average pressure of at least 3 G per pin, so the gas pressure is based on various semiconductor package structures. 21〇 varies in size. For example, the product of BGA40X4G can be applied with a force of 25 kilograms per square centimeter (4) for better electrical contact. In order to avoid damage to the contacts 216 or probes 222 due to pressure during the test, the probes 222 may be designed to have a resilient structure, and the contacts 216 may be solder balls (eg, 嶋 structures), pins. Or other structure. According to the testing apparatus of the first embodiment of the present invention, the applied gas friction uniformly acts on the upper surface of the semiconductor device to be tested, reducing the possibility of stress concentration and destruction of the product. 3a and 3b, which show a test apparatus 300 according to a second embodiment of the present invention for testing a semiconductor package structure 31 having at least one crystal #312 and a plurality of The contact point 316 of the lower surface 318, the test device 3A includes a test socket 32〇, 1273684. The test socket 320 has a plurality of probes 322, and the _ terminal thereof is electrically connected to the external 邛 electric milk characteristic test device ( The figure is not shown). The test device 3 further includes a sensing head 350 having a pneumatic device 340 capable of generating a positive air pressure and a pressure, wherein the measuring head 35 is capable of adsorbing the semiconductor to be tested by the generated negative air pressure. The package structure is placed in the test stand 3; in addition, a cover 33 is provided on the test head 350. When the semiconductor package structure 310 is tested, after the probe head 35 is adsorbed (see FIG. 3a) and placed in the test socket 32, the cover 330 is in airtight contact with the test socket 32. (See FIG. 3b), while a plurality of contacts 316 of the package structure 310 are in contact with the probes 322, and the periphery of the lower surface 318 of the semiconductor package structure 31 is in contact with the test block 32. A cover 330 is hermetically sealed over the test block 32, defining a cover space 360 therebetween. The positive air pressure is generated by the air pressure device 34 in the cover space 36, and the semiconductor package structure 31 causes the contacts 316 to be in closer electrical contact with the probes 322 due to the air pressure. In order to obtain a better airtight effect, an elastic airtight pad 324 may be disposed between the semiconductor package structure 31 and a position in contact with the test socket 320. Further, the cover 33 may be Between the positions where the test socket 32 is in contact, another elastic airtight cushion 326 is provided. The function of the airtight gasket 324 described above is similar to that of the airtight gaskets 224, 226 of the first embodiment, and will not be described again. In addition, the semiconductor package structure can be applied with a gas pressure of about 2.5 kilograms per square knife to obtain a preferred electrical contact. In order to avoid damage to the contacts 3 16 or probes P 2 due to pressure during the test, the probes 322 may be designed to have a resilient structure, and the contacts 3 16 may be solder balls (eg, bgA structures). ), pins or other structures. 1273684 A test apparatus according to a second embodiment of the present invention has a utility similar to that of the first embodiment, and is not described herein. While the foregoing description and drawings have shown the preferred embodiments of the present invention, it is understood that various additions, modifications and substitutions may be used in the preferred embodiments of the invention. The spirit and scope of the principles of the invention as defined by the appended claims. Those skilled in the art will appreciate that the invention may be used in many forms of construction, fabric, proportions, materials, components and components.
改口此本文於此所揭π的實施例於所有觀點，應被視 為用以說明本發明，而非用职庄τ 阳非用以限制本發明。本發明的範圍 應由後附申請專利籍If!所哭a 、， 軛固所界疋，亚涵蓋其合法均等物，並 不限於先前的描述。 10 1273684 【圖式簡單說明】 第1a與lb圖·’為習用的封裝測試用於具有陣列式錫球 之半導體封裝構造之剖面示意圖。 第2圖：為根據本發明第一實施例之用於半導體封裝構 造之測滅裝置之剖面示意圖。 第3a與3b圖··為根據本發明第二實施例之用於半導體 封裝構造之測試裝置之剖面示意圖。 【圖號說明】 100 封裝測試裝置 110 封裝構造 112a 晶片 112b 晶片 114 基板 116 錫球 120 測試座 122 探針 130 壓貨頭 134 壓板 136 軟墊 200 測試裝置 210 封裝構造 212 晶片 216 接點 218 下表面 220 測試座 222 探針 224 氣密墊 226 氣密墊 230 罩蓋 240 氣壓裝置 260 罩蓋空間 300 測試裝置 1273684 Μ * 310 封裝構造 312 晶片 316 接點 318 下表面 320 測試座 322 探針 324 氣密塾 326 氣密墊 330 罩蓋 340 氣壓裝置 350 測貨頭 360 罩蓋空間The examples of the invention disclosed herein are to be considered as illustrative of the invention and are not intended to limit the invention. The scope of the present invention should be covered by the appended patent application If!, yoke, and its legal equivalents, and is not limited to the previous description. 10 1273684 [Simplified Schematic Description] The first and lb diagrams are schematic cross-sectional views of conventional semiconductor package structures having array solder balls. Fig. 2 is a schematic cross-sectional view showing a detecting device for a semiconductor package structure according to a first embodiment of the present invention. 3a and 3b are schematic cross-sectional views of a test apparatus for a semiconductor package structure according to a second embodiment of the present invention. [Description of the number] 100 package test device 110 package structure 112a wafer 112b wafer 114 substrate 116 solder ball 120 test socket 122 probe 130 pressure head 134 pressure plate 136 pad 200 test device 210 package structure 212 wafer 216 contact 218 lower surface 220 Test Stand 222 Probe 224 Airtight Pad 226 Airtight Pad 230 Cover 240 Air Pressure Device 260 Cover Space 300 Test Set 1273684 Μ * 310 Package Construction 312 Wafer 316 Contact 318 Lower Surface 320 Test Seat 322 Probe 324 Airtight塾326 airtight pad 330 cover 340 air pressure device 350 measuring head 360 cover space
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