1271880 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種發光二極體封裝之製造方 法，特別係有關於一種晶圓級發光二極體封裝之製造 方法。 【先前技術】 半導體發光元件是一種將電能轉換成光能的半導 體元件，由於其耗電量少、體積小、使用壽命長，已 廣泛地運用於家電音響的指示燈、彩色螢幕行動電話 的被光光源、發光二極體看板、交通號誌與汽車第三 煞車燈等等。 一種習知之發光二極體封裝，如我國專利公告第 5 62 244號「一種發光二極體之覆晶晶片結構」，其係 包括一矽基板及複數個晶片，該矽基板之一面係等距 離設置有複數個導電部，且該些導電部間係形成有一 斷路區，每一晶片之同一面上係分別具有一正電極及 一負電極，且該些晶片係以覆晶之方式將其位於同一 面上之正、負電極對應設置於上述基板之導電部上形 成一導通之狀態，且使該些導電部二端藉由該些晶片 而被定義為正、負電極，而該未與晶片連接之導電部 係可供連接外部電源使用，使得單一發光二極體形成 單色與多色之光源，且使其具有高電壓低電流之特 性，並可有效將晶片所發出的熱量導出之功效，然而 該發光二極體在封裝過程中，需——將該些晶片覆晶 5 1271880 接合於該梦基板之導電部’且必須調整該些晶片覆晶 之間距，以配合該矽基板之導電部，製程較為繁複。 【發明内容】 本發明之主要目的係在於提供一種晶圓級發光二 極體封裝之製造方法，利用切割一具有複數個發光二 極體晶粒之晶圓，分離成複數個相鄰接之發光二極體 晶粒，將該些相鄰接之發光二極體晶粒接合於一底座 基板，使得該晶圓級發光二極體封裝係包含有複數個 相鄰接之發光二極體晶粒，以增加該發光二極體封裝 結構之亮度。 本發明之次一目的係在於提供一種晶圓級發光二 極體封裝結構，利用一發光二極體晶粒與相鄰接且未 切割開之至少一另一發光二極體晶粒係同時封裝於該 發光二極體封裝結構中，以增加該發光二極體封裝結 構之亮度。 本發明之再一目的係在於提供一種晶圓級發光二 極體封裝結構，利用一形成有複數個導電線路怎透光 基板覆蓋一發光二極體晶粒，該些線路係連接該發光 二極體晶粒與一底座基板，以同時導通並保護該發光 二極體晶粒。 依本發明之晶圓級發光二極體封裝之製造方法，首 先，提供一發光二極體晶圓，該發光二極體晶圓係包 含複數個發光二極體晶粒，每一發光二極體晶粒係具 有一第一電極及一第二電極；接著切割該發光二極體 6 1271880 晶圓’以分離成複數個發光二極體晶粒組’每一發光 二極體晶粒組係包含複數個相鄰接之發光二極體晶 粒；接著將該些相鄰接之發光二極體晶粒接合於一底 座基板，該底座基板係具有一接合表面，該接合表面 係形成有複數個第一接塾及複數個第二接塾，該底座 基板之第一接塾係接合於該些發光二極體晶粒之第一 電極；接著貼合複數個圍堤於該底座基板；接著接合 一透光基板，該透光基板係形成有複數個導電線路， 該些導電線路之一端係電性連接該些發光二極體晶粒 之第二電極，該些導電線路之另一端係電性連接該底 座基板之第二接墊。 【實施方式】 參閱所附圖式，本創作將列舉以下之實施例說明。 依本發明之一具體實施例，一種晶圓級發光二極體封裝 之製造方法如下所述，請參閱第1A及2圖，首先，提供一 發光二極體晶圓100，該發光二極體晶圓1 〇〇係選自於氮化 鎵半導體、砷化鎵半導體、磷化鎵砷半導體、磷化鋁鎵銦半 導體、氮化鋁鎵銦半導體與氮化銦鎵半導體之其中之一，該 發光二極體晶圓1 〇〇係包含複數個發光二極體晶粒丨i 〇，每 發光一極體晶粒110之結構’如第2圖所示，本實施例係 以氮化鎵半導體為例，其係具有一藍寶石基板1 i i〔 sapphire substrate〕，該藍寶石基板ill之下表面係形成有一第一電 極112 ’該藍寶石基板111之上表面係形成有一 η型氮化鎵 化合物113〔 n-GaN〕，該η型氮化鎵化合物113上係形成 1271880 有一發光層114，該發光層114上係形成有一 p型氮化鎵化 合物11 5〔 p-GaN〕，該p型氮化鎵化合物丨丨5上係形成有 一包覆層116,該包覆層116上係形成有一第二電極117; 再请參閱第1B圖，切割該發光二極體晶圓i 〇〇，以分離成 複數個發光二極體晶粒組，每一發光二極體晶粒組係可包含 複數個相鄰接之發光二極體晶粒11〇或僅為單一之發光二極 體曰Θ粒11 0，本實施例中係以複數個相鄰接之發光二極體晶 粒11 0為例，請參閱第3圖，在另一具體實施例中，該些發 光二極體晶粒11 〇之間的切割線係形成有一狹長缺口丨丨8， 其係至少貫穿該些發光二極體晶粒110之發光層114、p型 氮化鍊化合物11 5與該包覆層11 6，以利光線在個別發光二 極體晶粒110產生全反射，而該些第一電極112係可為單一 金屬層即可；然後將該些相鄰接之發光二極體晶粒丨丨〇接合 於一底座基板200’該底座基板200係具有一接合表面210, 該接合表面210係形成有複數個第一接塾211及複數個第二 接墊212，該底座基板200之第一接墊2 11係接合於該些發 光二極體晶粒110之第一電極112;再請參閱笫ic圖，貼 合複數個圍堤300於該底座基板200之接合表面210上，該 些圍堤300係具有導通其上、下表面之線路31〇，且該些線 路3 10係連接該底座基板200之第二接墊212,該些圍堤300 係圍繞該些發光二極體晶粒11 0，較佳地，該些圍堤300之 内側壁與該底座基板200之接合表面2 10係經過鏡面處理， 具有光反射之效果；再請參閱第1D圖，接著接合一透光基 板400於該圍堤300，以覆蓋該些相鄰接之發光二極體晶粒 1271880 110,該透光基板400係具有一上表面410及一下表面42〇， 該透光基板400之下表面42〇形成有複數個導電線路43〇， 必要時，該透光基板4〇〇可形成有複數個貫穿該上表面4 i 〇 與該下表面420之導通孔〔圖未繪出〕，該些導通孔係連接 該些導電線路430，該些導電線路43〇之一端係翹離該透光 基板400之下表面42〇，或者接合有銲線與凸塊之其中之一 〔圖未繪出〕，以電性連接該些發光二極體晶粒11〇之第二 電極117,而該些導電線路43〇之另一端係連接該些圍堤3〇〇 之線路310，以電性連接該底座基板2〇〇之第二接墊212。 上述之晶圓級發光二極體封裝之製造方法，可視實際需 要’例如亮度需求或該底座基板200之尺寸，切割該發光二 極體晶圓1 00以得到複數個相鄰接之發光二極體晶粒丨丨〇或 單一之發光二極體晶粒110，將該些相鄰接之發光二極體晶 粒11 〇或單一之發光二極體晶粒i i 〇接合於該底座基板 200，再以形成有導電線路430之透光基板400覆蓋該些相 鄰接之發光二極體晶粒11 〇或單一之發光二極體晶粒丨丨〇， 使得該晶圓級發光二極體封裝可依需求同時封裝有複數個 相鄰接之發光二極體晶粒110或單一之發光二極體晶粒 11〇，此外，該晶圓級發光二極體封裝接構之透光基板4〇〇 可同時具有電性導通該（些）發光二極體晶粒110與保護該 (些）發光二極體晶粒110之功效。 本發明之保護範圍當視後附之申請專利範圍所界定者為 準，任何熟知此項技藝者，在不脫離本發明之精神和範圍内 所作之任何變化與修改，均屬於本發明之保護範圍。 1271880 【圖式簡單說明】 第1 A至1 D圖：依據本發明之一具體實施例，一種晶 圓級發光二極體封裝之製造方法，一發光二 極體晶粒在製造過程中之截面示意圖； 第2圖：依據本發明之一具體實施例，一發光二極體 晶粒之截面不意圖；及 第3圖··依據本發明之另一具體實施例，複數個發光 二極體晶粒之截面示意圖。 【主要元件符號說明】 100 發光二極體晶 圓 110 發光二極體晶粒 111 藍寶石基板 112 第一電極 113 η型氮化鎵化合物 114 發光層 11 5 p型氮化鎵化合物 116 包覆層 117 第二電極 118 缺口 200 底座基板 210 接合表面 211 第一接墊 212 第二接墊 300 圍堤 310 線路 400 透光基板 410 上表面 420 下表面 430 導電線路BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a light emitting diode package, and more particularly to a method of fabricating a wafer level light emitting diode package. [Prior Art] A semiconductor light-emitting element is a semiconductor element that converts electrical energy into light energy. Because of its low power consumption, small size, and long service life, the semiconductor light-emitting element has been widely used for the indicator light of a home electric appliance and a color screen mobile phone. Light source, LED signage, traffic signs and the third car lights. A conventional light-emitting diode package, such as the above-mentioned Patent Publication No. 5 62 244, "A flip-chip structure of a light-emitting diode", which comprises a substrate and a plurality of wafers, one side of which is equidistant a plurality of conductive portions are disposed, and a circuit breaker region is formed between the conductive portions, and each of the wafers has a positive electrode and a negative electrode on the same surface, and the wafers are placed in a flip chip manner. The positive and negative electrodes on the same surface are disposed on the conductive portion of the substrate to form a conductive state, and the two ends of the conductive portions are defined as positive and negative electrodes by the wafers, and the unconnected electrode The connected conductive portion can be connected to an external power source, so that the single light-emitting diode forms a light source of a single color and a multi-color, and has the characteristics of high voltage and low current, and can effectively derive the heat emitted by the wafer. However, in the packaging process, the light-emitting diodes need to be bonded to the conductive portion of the dream substrate and the wafers must be adjusted to match the wafers. The conductive portion of the silicon substrate, the manufacturing process more complicated. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for fabricating a wafer level light emitting diode package by cutting a wafer having a plurality of light emitting diode crystal grains and separating into a plurality of adjacent light emitting devices. a diode die, the adjacent light-emitting diode die is bonded to a base substrate, so that the wafer-level light-emitting diode package comprises a plurality of adjacent light-emitting diode crystal grains To increase the brightness of the LED package structure. A second object of the present invention is to provide a wafer level light emitting diode package structure, which utilizes a light emitting diode die and at least one other light emitting diode die package that is adjacent and uncut. In the LED package structure, the brightness of the LED package structure is increased. A further object of the present invention is to provide a wafer level light emitting diode package structure, wherein a plurality of conductive lines are formed to cover a light emitting diode die, and the lines are connected to the light emitting diode The body die and a base substrate simultaneously turn on and protect the light emitting diode die. According to the manufacturing method of the wafer level light emitting diode package of the present invention, firstly, a light emitting diode wafer is provided, the light emitting diode wafer comprising a plurality of light emitting diode crystal grains, each of the light emitting diodes The body grain system has a first electrode and a second electrode; and then the light-emitting diode 6 1271880 wafer is cut to separate into a plurality of light-emitting diode chip groups each of the light-emitting diode grain groups And comprising a plurality of adjacent light-emitting diode dies; and then bonding the adjacent light-emitting diode dies to a base substrate, the base substrate having a bonding surface, the bonding surface being formed with a plurality of a first interface and a plurality of second interfaces, the first interface of the base substrate is bonded to the first electrodes of the LED chips; and then the plurality of dikes are attached to the base substrate; Bonding a light-transmissive substrate, the light-transmissive substrate is formed with a plurality of conductive lines, one end of the conductive lines is electrically connected to the second electrodes of the light-emitting diode chips, and the other ends of the conductive lines are electrically connected Sexually connecting the base substrate Pad. [Embodiment] Referring to the drawings, the present invention will be described by way of the following examples. According to an embodiment of the present invention, a method for fabricating a wafer level light emitting diode package is as follows. Referring to FIGS. 1A and 2, first, a light emitting diode wafer 100 is provided. The light emitting diode is provided. The wafer 1 is selected from the group consisting of a gallium nitride semiconductor, a gallium arsenide semiconductor, a gallium arsenide semiconductor, an aluminum gallium phosphide semiconductor, an aluminum gallium indium semiconductor, and an indium gallium nitride semiconductor. The light-emitting diode wafer 1 includes a plurality of light-emitting diode chips 〇i 〇, and the structure of each of the light-emitting one-pole crystal grains 110 is as shown in FIG. 2, and the present embodiment is a gallium nitride semiconductor. For example, it has a sapphire substrate 1 ii [ sapphire substrate], and a surface of the sapphire substrate ill is formed with a first electrode 112 ′. The upper surface of the sapphire substrate 111 is formed with an n-type gallium nitride compound 113 [ n - GaN], the n-type gallium nitride compound 113 is formed with a light-emitting layer 114 on the light-emitting layer 114, and a p-type gallium nitride compound 11 5 [p-GaN] is formed on the light-emitting layer 114. The p-type gallium nitride compound is formed on the light-emitting layer 114. a cladding layer 116 is formed on the top of the crucible 5, A second electrode 117 is formed on the cladding layer 116. Referring to FIG. 1B, the LED wafer is cut to form a plurality of LED segments, each of which has two LEDs. The bulk crystal group may include a plurality of adjacent light-emitting diode crystal grains 11 〇 or only a single light-emitting diode 曰Θ grain 11 0. In this embodiment, a plurality of adjacent light-emitting diodes are used. The polar crystal grain 110 is taken as an example. Referring to FIG. 3, in another embodiment, the cutting line between the light-emitting diode grains 11 形成 is formed with a narrow notch 丨丨8, which is at least The light-emitting layer 114, the p-type nitriding chain compound 11 5 and the cladding layer 11 6 penetrating through the light-emitting diode crystal grains 110, so that the light rays are totally reflected in the individual light-emitting diode crystal grains 110, and the light-emitting layer 110 The first electrode 112 can be a single metal layer; then the adjacent light-emitting diode die is bonded to a base substrate 200'. The base substrate 200 has a bonding surface 210. The surface 210 is formed with a plurality of first interfaces 211 and a plurality of second pads 212, and the base substrate 200 The pads 2 11 are bonded to the first electrodes 112 of the LED die 110; further, referring to the 笫ic diagram, a plurality of dimples 300 are attached to the bonding surface 210 of the base substrate 200. The bank 300 has a line 31A for conducting the upper and lower surfaces thereof, and the lines 3 10 are connected to the second pads 212 of the base substrate 200, and the banks 300 surround the light-emitting diode grains 11 0. Preferably, the inner surface of the bank 300 and the bonding surface 2 10 of the base substrate 200 are mirror-finished to have a light reflection effect; and then refer to FIG. 1D, and then a transparent substrate 400 is bonded to The dike 300 covers the adjacent light-emitting diode crystal grains 1271880 110. The transparent substrate 400 has an upper surface 410 and a lower surface 42A, and the lower surface 42 of the transparent substrate 400 is formed. A plurality of conductive lines 43A are formed. If necessary, the transparent substrate 4A can be formed with a plurality of through holes (not shown) extending through the upper surface 4i and the lower surface 420. Connecting the conductive lines 430, one of the conductive lines 43 is lifted off the transparent substrate The lower surface of the 400 is 42 〇, or one of the bonding wires and the bumps (not shown) is bonded to electrically connect the second electrodes 117 of the light emitting diode dies 11 and the conductive The other end of the line 43 is connected to the lines 310 of the banks 3 to electrically connect the second pads 212 of the base substrate 2 . The manufacturing method of the wafer level LED package described above may be performed by cutting the LED wafer 100 to obtain a plurality of adjacent LEDs according to actual needs, such as brightness requirements or the size of the base substrate 200. The body die or the single light-emitting diode die 110, the adjacent light-emitting diode die 11 or a single light-emitting diode die ii 〇 is bonded to the base substrate 200, Then, the adjacent light-emitting diode die 11 or the single light-emitting diode die is covered by the transparent substrate 400 formed with the conductive line 430, so that the wafer level LED package is A plurality of adjacent LED dipoles 110 or a single LED dipole 11 〇 can be simultaneously packaged according to requirements, and the wafer-level LED package is connected to the transparent substrate. The germanium can simultaneously electrically conduct the light emitting diode die(s) 110 and protect the light emitting diode die(s) 110. The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. . 1271880 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are diagrams showing a manufacturing method of a wafer level light emitting diode package according to an embodiment of the present invention, a cross section of a light emitting diode die in a manufacturing process FIG. 2 is a cross-sectional view of a light-emitting diode die according to an embodiment of the present invention; and FIG. 3 is a plurality of light-emitting diode crystals according to another embodiment of the present invention. A schematic cross section of the grain. [Main component symbol description] 100 LED wafer 110 LED dipole die 111 Sapphire substrate 112 First electrode 113 n-type gallium nitride compound 114 Light-emitting layer 11 5 p-type gallium nitride compound 116 Coating layer 117 Second electrode 118 notch 200 base substrate 210 bonding surface 211 first pad 212 second pad 300 bank 310 line 400 transparent substrate 410 upper surface 420 lower surface 430 conductive line