TWI263314B - Multi-chip package structure - Google Patents

Multi-chip package structure Download PDF

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Publication number
TWI263314B
TWI263314B TW094137530A TW94137530A TWI263314B TW I263314 B TWI263314 B TW I263314B TW 094137530 A TW094137530 A TW 094137530A TW 94137530 A TW94137530 A TW 94137530A TW I263314 B TWI263314 B TW I263314B
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TW
Taiwan
Prior art keywords
surface
substrate
wafer
电 气
Prior art date
Application number
TW094137530A
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English (en)
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TW200717725A (en
Inventor
Chian-Chi Lin
Cheng-Yin Lee
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Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW094137530A priority Critical patent/TWI263314B/zh
Application granted granted Critical
Publication of TWI263314B publication Critical patent/TWI263314B/zh
Publication of TW200717725A publication Critical patent/TW200717725A/zh

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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/19107Disposition of discrete passive components off-chip wires

Description

1263314 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種半導體封裝結構,特別是一種内含有 一次封裝結構之封裝結構。 【先前技術】 參考圖1,顯示美國專利第US6838761號所揭示之習用 多重封裝之封裝結構之示意圖。該多重封裝之封裝結構 1 ,包括··一第一基板(substrate)ll 、一第一晶片 (chip)12、一第一黏膠(acjhesive)13、複數個第—導線 (connecting wires)14 、 一第一封膠(molding compound)l 5、一次封裝結構(sub-package)2、一第三黏膠 16、複數個第三導線17、一第三封膠18、一散熱片(heat spreader) 1 9及複數個銲球(s〇ider balls)20。該第一基板η 具有一上表面111及一下表面112。該第一晶片12係利用該 第一黏膠13黏附於該第一基板11之上表面丨丨1。該等第一 導線14係用以電氣連接該第一晶片12與該第一基板^之上 表面111。該第一封膠15係包覆該第一晶片12、該等第一 導線14及部份該第一基板丨丨之上表面丨丨1,且該第一封膠 15具有一上表面151。 該次封裝結構2包括一第二基板2 1、一第二晶片22、一 第二黏膠23、複數個第二導線24及第二封膠25。該第二基 板21具有一上表面211及一下表面212。該第二晶片22係利 用該第二黏膠23黏附於該第二基板2丨之上表面2丨丨。該等 第二導線24係用以電氣連接該第二晶片22與該第二基板2工 104144.doc 1263314 之上表面2Π。該第二封膠25係包覆部份該第二晶片u、 該等第二導線24及部份該第二基板21之上表面2丨^。 該次封裝結構2係疊設(stacked)於該第一封膠} 5之上表 面1S1上,且利用該第三黏膠16將該第二基板幻之下表面 212黏附於該第—封膠15之上表面151上。該第二基板^係 利用該等第三導線17電氣連接至該第一基板丨丨之上表面 111。該第三封膠18係包覆該次封裝結構2、該第一封膠15 及該第一基板u之上表面m。該散熱片19具有一散敎片 本體⑼及-支撐部192,該支撐部192係由該散熱片:體 191向外且向下延伸,用以支撐該散熱片本體191,且μ 熱片本體m係暴露於該第三封膠18之外。該等焊球= 位於該第-基板u之下表面112’用以連接一外界褒置。 該習用之多重封裝之封裝結構1之缺點為,其係利用該 等第三導線17電氣連接該第二基板21與該第一基板⑴而 當該次封裝結構2黏附於該第一封膠15之上表面ΐ5ι後,該 第二基板之外側係為懸空,增加打線作業之困難。: 外,該第一晶片12係利用該等第一導線㈣氣連接至該第 一基板U之上表面111,因此該第―晶片12及該等第二 線14必須先被該第-封夥15包覆後才可以疊上該次封裝社 構2 ’如此不僅增加—道轉(mGiding)之步驟,且總言^ 會隨之提高。 ^ & 因此’有必要提供-種創新且具進步性的多重封裝之 I結構’以解決上述問題。 、 【發明内容】 104144.doc 1263314

本發明之主要目的在於提供一種多重封裝之封裝結構, 包括一第一基板、一第一晶片、一次封裝結構及一第一封 膠。该第一基板具有一第一表面及一第二表面。該第_晶 片係以覆晶方式接合至該第一基板之第一表面。該次封裝 結構包括一第二基板、一第二晶片及一第二封膠。該第二 基板具有一第一表面及一第二表面,該第二基板係為一可 彎曲軟式基板(flexible substrate),其係與該第一基板之第 一表面連接。該第二晶片係與該第二基板電氣連接。該第 二封膠係包覆該第二晶片及部分該第二基板之第二表面。 該第-封膠係包覆該第-晶片、該次封裝結構及部份該第 一基板之第一表面。由於該第一晶片係以覆晶方式接合至 該第一基板之第一表面,因此可減少一道打線步驟,且可 降低總高度。此外’該第_基板及該第二基板係直接接 觸’因此又可減少一道打線步驟。 【實施方式】 麥考圖2 ’顯不本發明多重封裝之封裝結構之第一實施 例之剖視示意圖。該多重封裝之封裴結構3包括一第一基 板31、-第-晶片32、—次封裝結構4、—第一黏膠μ、 一第一封膠35及複數個銲球36。該第一基板31具有一第一 表面3 11 (上表面)、一第-矣-士 ; 乐—表面312(下表面)及一第一連接 端3 U。該第一晶片32係以覆晶叫啊)方式接合至該第 一基板31H面311 ’該第—晶片32具有-第一表面 321(上表面該第-晶心包括但不限於數位晶片、類比 晶片、光學晶片、邏輯晶片、微處理晶片及記憶體晶片。 104144.doc 1263314 該次封裝結構4包括一第二基板41、一第二晶片42、一 第一黏膠43、複數個第二導線44及一第二封膠45。該第二 基板41具有一第一表面411(上表面)、一第二表面412(下表 面)及一第二連接端413。該第二晶片42係利用該第二黏膠 43黏附於該第二基板q之第二表面4丨2。該第二晶片“包 括但不限於數位晶片、類比晶片、光學晶片、邏輯晶片、 微處理晶片及記憶體晶片。該等第二導線44係用以電氣連 接孩第一曰曰片42至該第二基板41之第二表面412。該第二 封膠45係包覆該部份該第二晶片42、該等第二導線44及部 伤孩第一基板41之第二表面412,該第二封膠仏具有一第 一表面451(下表面)。 該次封裝結構4係疊設於該第一晶片32之第一表面321 上,且利用該第一黏膠34將該第二封膠45之第二表面451 黏附於該第一日曰曰片32之第一表面321。此外,該第二基板 4 1係為 了焉曲軟式基板(flexible substrate),其第二連接 端413係與該第一基板31之第一連接端313之第一表面3ΐι 連接。在本實施例中,該第一基板31之第一連接端313之 第一表面3Π具有複數個第一接點(圖中未示),該第二基板 41之第二連接端413之第二表面412具有複數個第二接點 (圖中未不),該第二基板41之第二連接端之第二表面 412係直接接觸該第一基板31之第一連接端313之第一表面 3 11後,以熱壓合方式使得該等第一接點與該等第二接點 電氣連接。 該第一封膠35係包覆該第一晶片32、該次封裝結構4及 104144.doc 1263314 該等銲球36係形成於

3 1 3,在本貫施例中,該第一基板3丨之第一連接端3 1 3之第 一表面311具有複數個第一接點(圖中未示)。接著,以覆晶 °1M分该第一基板3 1之第一表面3 11。 該第一基板31之第二表面312,用以

上。該第一晶片32具有一第一表面32!。 接著,參考圖3b,提供一次封裴結構4。該次封裝結構4 而先經過測試,確定其為良品(G〇〇d Die)後,再繼續接續 之封裝製程。在本實施例中,該次封裝結構4包括一第二 基板4 1、一第二晶片42、一第二黏膠43、複數個第二導線 44及一第二封膠45。該第二基板41係為一可彎曲軟式基 板’其具有一第一表面411、一第二表面412及一第二連接 端413。在本實施例中,該第二基板41之第二連接端413之 第二表面412具有複數個第二接點(圖中未示)。該第二晶片 42係利用該第二黏膠43黏附於該第二基板41之第二表面 412 °該等第二導線44係用以電氣連接該第二晶片42與該 第二基板41之第二表面412。該第二封膠45係包覆部份該 104144.doc -10- 1263314 第二晶片42、該等第二導線44及部份該第二基板4ι之第二 表面4 12,該第二封膠45具有一第二表面451。 接著,參考圖3c,將該次封裝結構4翻轉18〇度後疊置於 該第一晶片32之第一表面321上,且利用一第一黏膠“將 該第一封膠45之第二表面451黏附於該第一晶片32之第一 表面321上。 接著,參考圖3d,以熱壓合方式將該第二基板41之第二 連接端413直接與該第一基板31之第一表面311接合,使得 該等第一接點與該等第二接點電氣連接。 于 接著 > 考圖3e,形成一第一封膠35,以包覆該第一晶 片32名人封裝結構4及部份該第一基板3丨之第一表面 者,苓考圖3f,形成複數個銲球36於該 —χΊτί Q 1 Ο 第二表面312,用以連接一外界裝置 參考圖4,顯示本發明多重封裝之封裝結構 例之剖視示意圖。太每施如+夕去 貝她 本只_之多重封裝之封裝結構3Α與該 第 貝施例之客舌&壯丄i t ϋ丄 一 ' 十衣結構3大致相同,不同處僅 晶片 土於貫施例之多重封裝之封裝結構 曰

==封㈣之該第一之第丄I 基板之第_ Ρ⑽38電氣連接至該第一 辰面311。該黛:曰 晶片、類比晶[光學晶片:: 限於數位 憶體晶片。 α耳日曰片、微處理晶片及記 參考圖5,顯示本發明多重封裝之封裳結構之第三實施 104144.doc 1263314

例之剖視示意圖。料重封裝之封裝結構5包括一第一基 板51、一第一晶片52、-次封裝結構6、一第一黏膠54、 一第一封膠55及複數個銲球56。該第一基板51具有一第一 表面511(上表面)、一第二表面512(下表面)及一第一連接 端5 13。該第一晶片52係以覆晶方式接合至該第一基板 之第一表面5U,該第一晶片52具有一第一表面521(上表 面)。該第-晶片52包括但不限於數位晶片、類比晶片、 光學晶片、邏輯晶片、微處理晶片及記憶體晶片。 該次封裝結構6包括一第二基板61、一第二晶片62、一 第二黏膠63、複數個第二導線64及一第二封膠65。該第二 基板61具有-第—表面611(上表面)、_第二表面612(下表 面)及一第二連接端613。該第二晶片62係利用該第二黏膠 63黏附於該第二基板61之第一表面611。該第二晶片以包 括但不限於數位晶[類比晶片、光學晶片、邏輯晶片、 微處理晶片及記憶體晶片。該等第二導線64係用以電氣連 接該第二晶片62至該第二基板61之第一表面6ιι。該第二 封膠65係包覆該部份該第二晶片62、該等第二導線以及部 份該第二基板61之第一表面6U。 該次封裝結構6係疊設於該第一晶片52之第一表面52 J 上,且利用該第一黏膠54將該第二基板61之第二表面612 黏附於該第一晶片52之第一表面521。此外,該第二基板 6 為 了專曲軟式基板(flexible substrate),其第二連接 端613係與該第一基板51之第一連接端5 13之第一表面511 連接。在本實施例中,該第一基板51之第一連接端513之 I04144.doc -12 - !263314 第表面5 11具有複數個第一接點(圖中未示),該第二基板 61之第二連接端613之第二表面612具有複數個第二接點 (圖中未示),該第二基板6】之第二連接端613之第二表面 12係直接接觸該第一基板5丨之第一連接端5 3之第一表面 511後,以熱壓合方式使得該等第一接點與該等第二接點 電氣連接。 第封膠5 5係包覆该第一晶片52、該次封裝結構6及 5亥第一基板51之第一表面511。該等銲球56係形成於 °亥第基板51之第二表面512,用以連接一外界裝置。 惟上述實施例僅為說明本發明之原理及其功效,而非用 以限制本發明。因此,習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示美國專利第US6838761號所揭示之習用多重封 裳之封裝結構之示意圖; 圖2顯示本發明多重封裝之封裝結構之第一實施例之剖 視示意圖; 圖3a至3f顯示圖2之第一實施例之製造流程示意圖; 圖4顯示本發明多重封裝之封裝結構之第二實施例之剖 視示意圖;及 圖5顯示本發明多重封裝之封裝結構之第三實施例之剖 視示意圖。 【主要元件符號說明】 104144.doc -13 - 1263314

1 多重封裝之封裝結構 2 次封裝結構 3 多重封裝之封裝結構 3A 多重封裝之封裝結構 4 次封裝結構 5 多重封裝之封裝結構 6 次封裝結構 11 第一基板 12 第一晶片 13 第一黏膠 14 第一導線 15 第一封膠 16 第三黏膠 17 第三導線 18 第三封膠 19 散熱片 20 鲜球 21 第二基板 22 弟二晶片 23 第二黏膠 24 第二導線 25 第二封膠 31 第一基板 32 第一晶片 104144.doc -14 - 1263314

34 第一黏膠 35 第一封膠 36 鲜球 37 弟二晶片 38 第一導線 41 第二基板 42 第二晶片 43 第二黏膠 44 第二導線 45 第二封膠 51 第一基板 52 第一晶片 54 第一黏膠 55 第一封膠 56 鮮球 61 第二基板 62 第二晶片 63 第二黏膠 64 第二導線 65 第二封膠 111 第一基板之上表面 112 第一基板之下表面 151 第一封膠之上表面 211 第二基板之上表面 104144.doc -15- 1263314

212 第 二 基板之 下表面 311 第 一 基板之 第- -表 面 312 第 一 基板之 第二 二表 面 313 第 一 連接端 321 第 一 晶片之 第一 -表 面 411 第 二 基板之 第- -表 面 412 第 二 基板之 第二表 面 413 第 —· 連接端 451 第 二 封膠之 第二表 面 511 第 一 基板之 第- -表 面 512 第 一 基板之 第二表 面 513 第 一 連接端 521 第 一 晶片之 第- -表 面 611 第 二 基板之 第- -表 面 612 第 二 基板之 第二 二表 面 613 第 連接端 104144.doc -16-

Claims (1)

1263314 、申睛專利範圍: 一種多重封裝之封裝結構,包括·· 一第一基板,具有一第一表面及—第二表面; 第日曰片,係以覆晶方式接合至該第一基板之第 表面; /人封裝結構,包括: 一第二基板,具有一第一表面及一第二表面,該第 係與該第-基板之第-表面連接; 基板係為—可彎曲軟式基板(flexiblesubstrate),其 與該篦_贫^^ . *日Θ片,與該第二基板電氣連接;及 —第二封膠,係包覆該第二晶部分 板;及 — 不一丞 罘封膠,係包覆該第一晶片、該次封裝姓播Ώ 邵份該第-基板之第一表面。 I構及 2·如請求項1之封 二黏膠,用、 中該次封裝結構更包括~第 面。7 Μ將該第二晶片黏附於該第二基板之第二表 3 ·如請求項2 > h u 而_ 羞結構,其中該第一晶片具有一第 面,该第二封砰θ 弟—表 .,封私具有一第二表面,該第二封膠之第_ ± 面係利用一笛 心弟一表 4.如請求項广點膠黏附於該第-晶片之第-表面。 二黏膠,、用之封裝結構’其中該次封裝結構更包括一第 面。 从將該第二晶片黏附於該第二基板之第—表 5 ·如請求項4 > 表 、 ^裝結構,其中該第一晶片具有一第 104144.doc 1263314 面,該第二基板之第二表面係利用一第一黏膠黏附於該 第一晶片之第一表面。 6. 如=求们之封裝結構,其中該次封裝結構更包括複數 個第二導線,用以電氣連接該第二基板及該第二晶片。 7. 如請求項丨之封裝結構,其中該第一基板之第一表面且 :複數個第-接點,該第二基板之第二表面具有複數個 第一接點’㈣二基板之第二表面係直接接觸該第一基 板之第-表面’使得該等第一接點與該等第二接點電: 連接。 8·如請求項1之封裝社槿,苴φ兮筮—甘Λ 、 η ,、中μ弟一基板係利用熱壓合 方式連接至該第一基板之第一表面。 9·如請求項1之封裝結 一 傅文匕秸弟二晶片,設置該第 二基板之第一表面上, θ 日片係利用複數個第一導 線電乳連接該第一基板。 I 0 ·如請求項1之封梦纟 嚷., 邊、、·°構,更包括複數個銲球,形成於該 弟一基板之該第二表面。 II ·如請求項1之封裝έ # a u . 4,§ , 、、°構,其中该第一晶片係選自由數位 晶片、類比晶Η 、 , ^ 片光學晶片、邏輯晶片、彳% i θ片及 記憶體晶片所組成之群。 u處理a曰片及 1 2 ·如請求項1之封駐 7展結構,其中該第二晶片 晶片、類比晶片、止 曰曰片係選自由數位 ^ I# ^ B u ^ 光學晶片、邏輯晶片、微處理晶片及 口匕U餸日日片所組成之群 免土 104144.doc
TW094137530A 2005-10-26 2005-10-26 Multi-chip package structure TWI263314B (en)

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JP4958257B2 (ja) * 2006-03-06 2012-06-20 オンセミコンダクター・トレーディング・リミテッド マルチチップパッケージ
US8059443B2 (en) * 2007-10-23 2011-11-15 Hewlett-Packard Development Company, L.P. Three-dimensional memory module architectures
US8064739B2 (en) * 2007-10-23 2011-11-22 Hewlett-Packard Development Company, L.P. Three-dimensional die stacks with inter-device and intra-device optical interconnect

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