TWI250592B - Multi-chip semiconductor package and fabrication method thereof - Google Patents

Multi-chip semiconductor package and fabrication method thereof Download PDF

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Publication number
TWI250592B
TWI250592B TW093135023A TW93135023A TWI250592B TW I250592 B TWI250592 B TW I250592B TW 093135023 A TW093135023 A TW 093135023A TW 93135023 A TW93135023 A TW 93135023A TW I250592 B TWI250592 B TW I250592B
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Taiwan
Prior art keywords
wafer
substrate
package
encapsulant
colloid
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TW093135023A
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English (en)
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TW200618132A (en
Inventor
Han-Ping Pu
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Siliconware Precision Industries Co Ltd
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Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW093135023A priority Critical patent/TWI250592B/zh
Priority to US11/026,933 priority patent/US7247934B2/en
Application granted granted Critical
Publication of TWI250592B publication Critical patent/TWI250592B/zh
Publication of TW200618132A publication Critical patent/TW200618132A/zh
Priority to US11/820,366 priority patent/US20070249094A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/151—Die mounting substrate
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    • H—ELECTRICITY
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
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    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Description

1250592 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體封裝件及其製法，尤指一種 多晶片半導體封裝件，係使一已封裝之晶片（packaged chip) 及一覆晶（flip chip)接置於基板上，以及一種製造該半導體 封裝件之方法。 【先前技術】 為符合電子產品日漸輕薄短小且具高效能之發展趨 ^ ’+導體封裝件亦相應地逐漸縮小其尺寸且較佳容設有( ^晶片以供電子產品之需。此種於單—封裝件中接置多 數半導體晶片之結構稱為多晶片半導體封裳件，其中該多 二” Μ垂直堆疊方式承載於晶片承載件（例如基板或 V線#)上’或者該多數晶片可個別接置於基板上。多晶 片^構之-大優點為使半導體封裝件具有大幅增進或倍增 之电f生及運作效能而適用於高效能電子產品中。 ^ 2專利第5,69M31及5,973,彻號案揭露—種多晶_ 體㈣件。如第5圖所示，此半導體封裝件係於一 _ 二反20上以覆晶(flip_chip)方式接置第一晶片2卜使該第 曰曰片21之作用表面21〇朝下並藉多數銲錫凸塊 (der bump)電性連接至基板2〇。然後，於第一晶片2】 3作用表面211上黏置第二晶片23,使該第二晶片23 糟夕數銲線24(bGndingwire)電性連接至基板2()。接著， 』土板2G上形成—封裝膠體25(e⑽㈣㈣。。b 覆住第m卜第二晶片23及料24。最後，於基板 6 18204 1250592 之相對的表面上植設多數銲球hu)，即完成 =多晶>1半導體封裝件。由於對第U 23進行銲線作業 4可此產生震動而導致銲錫凸塊22裂損㈣ek)，故需於第 曰曰片1 /、基板20間進行底部填膠（1111心也11)作業以填充 絕緣性材細如樹脂材料等)於相鄰銲錫凸塊22間之空隙 中俾立曰進！干錫凸塊22之機械強度使其不纟因受鲜線作業 中產生之震動而發生裂損。 、”
而，上述半導體封裝件在進行底部填膠作業時容^ 於填充輯性材料之過程中污染基板上預制以與鲜線木 位（如銲指）’而使銲線無法穩固地銲接至受污染的 、干才曰上，因此造成銲線作業良率降低以及第二日日日片與 ^性連接品f不佳，而損及整體半導體封裝件之^ ^再者，對於藉銲線電性連接至基板之第二晶片_、 半導體封裝將其直_』
品所不即，若未經過良率測試之第二晶片有 貝义5缺陷的情況，則會造成整體封裝件失能而估制 成品良率降低。 不叶天此而使製 片丰=專利公開第2004/0113275號案揭露另-種多晶 、版封裝件。如第6圖所 基板30上以霜曰封叙件係於一 之作用k 接置第—晶片3卜使該第—晶片 用表面310朝下並藉多數銲錫凸塊 3:且相鄰銲錫凸塊32間之空隙藉底部 緣性材_如樹脂材料等）。然後，將—柵格= 18204 1250592 array ’ LGA)封裝結構％ , 晶片”之非作用表=，置 %中之基板33G财數料％ 格㈣封裝結構 於基板30上形成連基板3〇。接著 格陣列封裝4 33i，35以包覆住第-晶片I相 i广。構33及銲線34。最後，於基板 表面上植設多數銲球36’即完成該 =的 圖所示之多曰良品(KGD)的問題，惟第6 K "料件的缺點與前述第5圖所干者 類似，在於相鄰銲錫凸塊 ⑽不者 以填充絕緣性材料 =進仃底部填膠作業 . 便錫凸塊32之機械強度提異而Τ # ^銲線作業中產生之震動而發生裂損，然而在填充 材料之過程中容易污染基板30上預設用以與銲線相巴接 :部位(如銲指)’使銲線34無法穩固地銲 曰公因此造成銲線作業良率降低以及栅格陣列封；:： =基板30間電性連接品f不佳，而損及整 : 裝件之信賴性。 丁 免A杯卜箱 出一種多晶片半導體封裝件，得以避 土板預&用以電性連接之部位受污染，且無是否為已 知良^KGD)之疑慮’俾確保製成封裝件之信賴性及良 率’實為一重要課題。 ^ 【發明内容】 本發明之-目的在於提供一種多晶片半導體封裝件 及其製法，無f進行底部填膠(underfil〇作業，目而能避免 基板上預設用以電性連接之部位受污染，俾確保半導體封 18204 8 1250592 裝件之電性連接品質及信賴性。 件及ίΓ明之另—目的在於提供一種多晶片半導體封裝 以二衣法’係容設有通過良率測試及性能檢測之前置封 二口 ’而能摒除是否為已知良品⑽。觀仙，Κ 旋思’俾確保半導體封震件之信賴性及良率。 ，發明之又一目的在於提供一種多晶片半導體封妒 、製法，於半導體封裝件中之下層覆晶與上層已封穿 之晶片之問數讲女谱Μ π 工尽匕封展 導敎f s又 …乡，使上層晶片所產生之熱量可經 遞至下層覆晶’再傳遞至基板而散逸至外界，俾 有效提昇整體半導體封裝件之散熱效率。 俾 體封裝件 面；至少 成j及其他目的’本發明揭露一種多晶片半導 1 ^ .基板，具有一上表面及一相對之下表 使兮第—a 晶片’具有—作用表面及—非作用表面， 至該餘用表if多數鲜錫凸塊接置並電性連接 少-接置並電::二 覆該第二晶片與部分導線竿之第二：曰曰片、及-用以包< 之外導腳露出該第—封穿脒〜一 ^使°亥¥線架 面，其中該第-封編於該基板之上表 間而使該第-晶片容置其中路::;卜導::基㈣成-空 成於料板間隙；一第二封裝膠體，形 成於。玄基板之上表面，用 前置封裝結構；以及多數鋒球，植：於=广錫凸塊及 本發明亦揭露上述多晶片半““反之下表面。 夕日日片+導體封裝件之製法，包括 18204 9 1250592 下列步驟：提供—A 4c ^. . 丁主· 、基板，该基板具有一上表面及一相對之 下表面，提供至少_第一曰 μ 弟日日片該罘一晶片具有一作用表 第用表面’亚藉多數銲錫凸塊接置及電性連接該 結構於蚌其此 °/基板之上表面；接置一前置封裝 二"土之上表面，該前置封裝結構包括-導線架、 > —接置並電性連接至該導線 s 包霜兮筮-曰八卞〈弟一日日片、及一用以 力：之Ιι—Γ n部分導線架之第—封裝膠體，使該導線 = ’、'：腳：出该第一封裝膠體外而接置於該基板之上表 間而二封裝膠體、露出之外導腳及基板形成-空 上二以罘一晶片容置其中，且該第一晶片之非作用表面 與该第一封裝膠體之間存有一 乂 7土板之上表面，使該第二封裝膠體包覆該第一、 銲錫凸塊及前置封裝姓構. 曰曰 丁主 衣、、、。構，以及植設多數銲球於該基板之 卜表面。 前揭多w半導體封裝件復可心減 括下列步驟：提供_其把ΰ 1 ^ a 有-上>^ I、'板片 餘片包括多數基板並具I 有上表面及一相對之下表面；接置至少一曰 《 該基板之上表面，該第一曰月且纟心主弟一曰曰片於各 主 、，一 日日片具有一作用表面及一非作用 -面’亚猎多數銲錫凸塊電性連接該 至各該基板之上表面；接罟乂罢方之作用表面 μ ± 衣自’接置1置㈣結構於各該基板之 2面，該前置封裳結構包括一導線架、至少一接置並電 „ ^ … 日日乃汉用以包覆該第二晶片 =導線架之第—封裝谬體，使該導線架之外導腳露出 〜弟-封歸體外而接置於該基板之上表面，並使該第— 18204 1250592 ^裝膠體、露出之外導腳及基板形成-空間而令該第—曰 片容置苴中，曰兮木曰曰 雕之門;士 δ亥乐一日日片之非作用表面與該第一封襞膠 =之間存有H形成—第二封裝膠體於該基板 J面’使該第二封繼包覆所有該第-晶片、銲錫凸塊 及两置封裝結構；植設多數鮮球於該基板片之下表面；= 一t早作業’以切割該第二封裝膠體及基板片，使 Q °玄基板分離而形成多數個別之半導體封裝件。 其中’前置封裝結構中之第二晶片係藉多數鲜線電性 至導線木，而該導線架包括—晶片座及多數導腳，夂 =由内導聊及外導腳構成，使第二晶片接置於晶片鼓 2 =性連接；内導卿，且内導聊及銲線為第-封裝 勺Φ ^於貝施例中，晶片座為該第一封裝膠體所 二弟二㈣！體填充於第一晶片與第一封裝膠體間 皁於另一貫施例中，晶片座之下表面外露出第一 封裝膠體而鄰接第—θ Η纺？ I ^ 形成第二封二:二與::::;，間隙’而在 隙填充有一導熱膠。“ “與弟一封裝膠體間之間· 上述本發明之多晶片半導體封裝件及其製法，係利用 一基板同時載接一已封裝之晶月及一覆晶，先將第一晶片. 式藉多數銲錫凸塊電性連接於基板上，再將一封 裝有第二晶片之導線架式前置封裝結構接置於基板上，其 中该則置封裝結構具有露出之外導腳藉表面黏著技術 (surface mount techn〇1〇gy)接置並電性連接至基板而使前 置封裝結構之第-封裝膠體、露出之外導腳及基板形成一 18204 11 1250592 —曰而7第a曰片谷置其中，且該第-封裝膠體架撐於第 =上方並與第—晶片間存有—間隙。由於前置封裝結 構稭表面黏著技術電性連接至基板，故位於第—晶片盘基 板=之鲜錫凸塊不會遭受習知技術中進行鲜線作業時產^ 之^而發生IU員㈣ek)，因此本發明無f進行底部填膠 凸挣作業以填充位於第一晶片與基板間之相鄰銲錫 其二―次模壓製_成第二封裝膠體使 第:Γ = ρ/Θ>1 U封裝結構並填充於第—封裝勝體與 弟、片間之間隙及相鄰銲錫凸塊間之空隙，且 業㈣基板上㈣用以與前置封裝結構之外導聊 立’俾確保前置封裝結構得良好地接置並電性連 =基：，而不會影響整體半導體封裝件之電性連接品質 過，由於前置封裝結構在製備完成後會先經 、良率測4及性能檢測再接置至基板上，換言之， 功通過良率測試及性能檢測义 、 /、 板上，故前置封裝結構仙 缺陷的第二晶片，因而摒；否良好或有< 疑慮，俾確保整體半導體封=疋否為已知良品（κ㈤)之 本發明之另一實二 出第-封裝膠體之晶片座有外露 前，使第-封細與第二m弟：卿體 膠，故承載於該晶片座上之第一曰：θ ^敷“-導熱 晶片座及導熱膠傳遞至第一 ^片—曰曰片所產生之熱量可經由 弟日日片’再經由與第一晶片相連 18204 12 1250592 錫凸塊以及基板傳遞至半導體封裝件外 可有效提昇整體半導體龍件之散熱效率。另外，本發1 :半導體封裝件為一多晶片(至少第-晶片及第二晶片“ 構’故使整體職件具有增㈣電性及運作效能。、、° 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 熟悉此技藝之人士可由本說明書所揭示之内容輕易地 7解本發明之其他優點與功效。本發明亦可藉由其他不同 =具體實例加以施行或應用，本說明書中的各項細節亦可· ί於不同觀點與制’在不悖離本發明之精神下進行各種 修倚與變更。 如第1圖所示，本發明第一實施例之多晶片半導 褒件，包括：一基板10,具有一上表面_及一相對之下 f面1〇1，至少一第一晶片U，以覆晶（flip-chip)方式藉多 數銲錫凸塊⑽derbump)接置並電性連接至基板⑺之 上表面100 ’ 一則置封裝結構13，藉露出其第一封裝膠體 16(encapsulationb〇dy)外之外導腳143接置並電性連接至· 基板10之上表面1〇〇,使第一封裝膠體16、外導腳143 =基板10形成一空間s而令第—晶片u容置其中，且使-弟一晶片11與第一封裝膠體16之間存有一間隙G ; 一第 1裝膠體17,形成於該基板1G之上表面⑽，用以包覆 邊弟一晶片11、銲錫凸塊12及前置封裝結構13並填充於 該空間S及間隙G中；以及多數銲球18⑽derball)，植 設於該基板10之下表面1〇1。 18204 13 1250592 該基板ίο可為一般之封裝基板且具有預設之線路佈 ，（cinmitry，未圖式）以供同時承載該前置封裝結構^及 第一U(覆晶）。該基板1〇可主要由一樹脂材料製成， 例如環氧樹脂（epoxy resin)、聚亞醯胺樹脂如 resin)、BT (bismaleimide triazine)樹脂或 FR4 樹脂等。 一該第一晶片11具有一作用表面110(activesurface)及 一相對之非作用表面111 (non_active surface)，其中該作用 表面m上佈設有多數電子元件、電子線路（未圖式)及録 ，112(b0ndPad)，該銲墊112係與銲錫凸塊12銲接而使 第一晶片π之作用表面110藉該銲錫凸塊12以覆晶方式 接置並電性連接至基板1 〇之上表面1 〇〇。 忒月ίι置封裝結構13包括一導線架14、至少一接置並 ，性連接至該導線架14之第二晶片15、及一用以包覆該 弟二晶片15與部分導線架14之第一封裝膠體16。其中， 忒$線木14包括一晶片座14〇(die pa句及多數導腳， 各導腳⑷由内導腳142及外導腳143構成，使第二晶片 15接置於晶片座140之上表面並藉多數鮮線19卜啊 ire)包f·生連接至内導腳142，並且該晶片座及内導腳 142為第一封裝膠體16所包覆。 另外，上述第一封裝膠體16與第二封裝膠體17可以 相同，不同之習用樹脂材料製成，例如，較常見的樹脂材 料為環氧樹脂等。 一第1圖所不之多晶片半導體封裝件得以第至圖 所示之製程步驟製得。 18204 14 1250592 且有百^如第2A圖所示，提供—基板1G，該基板10 具有一上表面1〇〇及一 一妒之本+壯苴4 相對之下表面101。該基板10可為 要^一好=土反且具有預設之線路佈局（未圖式），並可主
樹r * 料製成’例如環氧樹脂、聚亞醯胺樹脂、BT :’二樹料。*於基板之結構及製造技術俱為習 知，故於此不予贅述。 片ηΓ古示，提供至少一第一晶片11，該第一晶 一作用表面110* 一非作用表面⑴，其中該作 r執⑴上佈設有多數電子元件、電子線路（未圖式）及 =,12。接著’於第—晶片n之作用表面ιι〇的銲墊η] 曰方，夕錫凸塊12。然後，以作用表面110朝下之覆 曰曰"將第一晶片π藉該多數銲錫凸塊12接置並電性連 之上表面1〇。。由於第-晶片及銲錫凸塊之製 卞议為白知，故於此不予贅述。
如第2C圖所示，接置一前置封裝結構13於基板ι〇 ^表面igg。該！j置封裝結構13可為製成之使用 泉力:的扁平四邊形封裝件(QFP ’ quad flat package)，並 、士 k 4知良率測試及性能檢測（burn-in test)。該前置封裝 :構13包括一導線架14、至少一接置並電性連接至導線 之第二晶片Μ、及一用以包覆第二晶片15與部分導 =木|4之第一封裝膠體16，其中，第一封裝膠體丨6係以 :用樹脂材料（例如環氧樹脂等）製成。該導線架14具有一 曰曰片座140及多數導腳141，各導腳141由内導腳142及 外導腳143構成，其中，第二晶片15接置於晶片座14Q 18204 15 1250592 之上表面並藉多數銲線19電性連接至内導腳i42，且該晶 =座刚、内導腳142及鋒線19為第一封裝朦體16所包 復而使外導腳⑷露出第—封裝膠體w外。露出之外導 腳143用以將前置封裝結構13藉例如表面黏著技術 (Surface Mount Technology) ^ ^ E M t ^ ϋ ^ ^ Μ ^ 10 之上表面100，使第-封裝膠體16架撐於第一晶片η的 ^方並與露出之外導腳143及基板1〇形成一空間§而令 弟一晶片π容置其中，且使第一封裝膠體16與第一晶片 11之非作用表面U1間存有一間隙G。由於表面黏著技術φ 屬習知技術，故於此不予贅述。 如第2D圖所示，進行一模壓（molding)作業，使用一 二有上杈及下模之封裝模具（encapsulati〇n m〇ld，未圖 式）’其中上模開設有一模穴，❿下模可為一平坦式結構。 ^接設有第一晶片11及前置封裝結構13之基板1〇置入封 裝模具中，使第一晶片u及前置封裝結構13容置於上模 的模穴中，且使基板10夾置於上模與下模，而基板10之 =表面101則與平坦之下模緊密抵觸。接著，將一習用樹· $材料（例如裱氧樹脂等）注入上模之模六，使樹脂材料包 覆住位於基板10上表面1〇〇上的第一晶片u、銲錫凸塊-12及岫置封裝結構13且填充於上述空間s、第一晶片u 與第一封裝膠體16間之間隙g及相鄰銲錫凸塊12間之空 隙中，待該樹脂材料固化後即可自基板丨〇上移除封裝模 具，俾完成一形成於基板10之上表面1〇〇的第二封裝膠體 17,而基板10之下表面101由於與平坦之下模緊密抵觸則 16 18204 1250592 不會有樹脂材料或第二封 模具後令基板10之下表W 之形成，故於移除封裝 與第二封裝膠體17 :露。其中’第-封裝膠體 最後，如第2E圖所二:不::樹脂材料製成。 作業以於基板】〇之外霖 ^^(ball-implanting) …如此遂完成本發明ί多: 可作為半導體封裝件之輸人 a封衣件。該銲球18 外界裝置（例如印刷電路板等别未圖】1 ’1/〇)端以與 封裝件藉之與外界裝置成電°;，而使半導體 習知技術，故於此不予贅述。闕係。由於植球製程屬1 ⑽二:二1 Γ斤示之多晶片半導體封裝件亦得以批次 、， 圖所不之製程步驟製得。 f先，如第3A圖所示，提供一義 —)，該基板片i由多數一體开》紅土/反片1(*崎 板構成，並且有_^ 成（lntegrallyformed)之基 1中相m —相對之下表面101， ^預二=1G間以虛線所示之切割線為界。該基板片1 · :有預二線路佈局(未圖式)，並可主要由一樹脂材料製· 等。；A减脂、聚亞輯樹脂、βτ樹脂或剛樹脂 :第:B圖所示，提供多數第一晶片u，各第一晶片 面110及一非作用表面Ul，其中該作用 執119 t佈設有多數電子元件、電子線路（未圖式）及銲 。接者’於各第一晶片11之作用表面110的銲墊112 上形成多數銲錫凸塊12。然後，以作用表面11G朝下之覆 18204 17 1250592 晶 方式將至少一第_曰ΰ μ# 罢、，+从u 日日片1稭其上之多數銲錫凸塊12接 置亚電性連接至各基板10之上表面剛。 之上=C。圖所示，接置一前置封裝結構13於各基板10 示者，包括一導線架14 = 之結構可如第2C圖所 14 曰 y 接置亚電性連接至導線架 架14之；：二：及一用以包覆第二晶片15與部分導線 # β衣膠體16(例如由環氧樹脂等之樹脂材料製 曾μ V線木14具有一晶片座14〇及多數導腳Μ〗，各 ‘聊141由内導偷7 1 4 9 » al、音 腳142及外導腳143構成，其中，第二晶（ ^接置於晶片座140之上表面並藉多數銲線19電性連 f内導腳142 ’且該晶片座14〇、内導腳I"及銲線d 6外路出之外導腳143用以將前置封裝結構13葬 例如表面黏著技術等接置並電性連接至各基板Μ之上表’ 面1〇〇 ’使第-封裝膠體16架撐於第—晶片u的上方並 與露出^外導腳143及基板10形成-空間s而令第一晶 片11容置其中，且使第一封裝膠體16與第一晶片u之非孀 作用表面111間存有一間隙G。 如第3D圖所示，進行一模壓作業以於基板片丨之上 1〇〇形成一第二封裝膠體17。首先，將接設有多數第 T晶片11及前置封裝結構13之基板片丨置入封裝模具（未 圭弋）中，使忒多數第一晶片11及前置封裝結構13容置於 ^衣板具之杈穴中；接著，注入一樹脂材料（例如環氧樹脂 寻）於該模穴中，使該樹脂材料包覆住所有第一晶片n、 18 18204 1250592 Γ、錫第凸二二2 ,前置封裝結構13且填充於所有上述之空間 錫凸塊1曰2曰門Λ與第一封褒膠體16間之間隙〇及相鄰薛 凸光i間之空隙中;待該樹 1上移除封裝模呈 幻J目基板片 中，第一封壯、/、 凡成形成該第二封裝膠體17。其 衣膠體16與第二封彳 之樹脂材料製成。 f衣膠體Π可以相同或不同 然後’如第同# 一 10之下… ，進行一植球作業以於各基板 10之:表面101上植設多數銲球18。 以沿::片=3F圖所示，進行-切單(singulati°n)作業， 各基心ηΓ謂線切割該基板片1及第二封裝膠體 ° 分離而形成多數個別之半導體封f件。由 封裝件各具有多數銲球18，其半:雜 Ψ ^ Ρ； ^ Μ 八j ^為牛V體封裝件之輸入 , 〃外界裝置（例如印刷電路板等，未圖式）連接， 而使何㈣料狀與料裝置錢料㈣;)連接 第4圖顯示本發明篦-者 件，其與上述第一實施例之^體^曰半導^封裝 w ,, ,, ^ 扪乏牛寺體封裝件的不同處在於前 並、首::13係一具有外露晶片座之導線架式封裝件，使 A線架Η之晶片座14〇的下表面外露出第一封裝膠妒 广該晶片座14〇外露的下表面與第一封裝膠體16齊平且 鄰接第-晶片11與第—封裝膠體16間之間隙G，並於該 ^ 2(thermally conductive adhesive) 而f包覆第-晶片11用之第二封裝朦體17。該導熱膠2 使耵置封裝結構13藉其外露之晶片座14〇與第一晶片u 18204 19 1250592 成導熱連接（thermally connected)關係，因而接置於晶片座 140上之第二晶片15所產生之熱量可經由晶片座及導 熱膠2傳遞之第一晶片u，再經由與第一晶片相連之 銲錫凸塊12以及基板10傳遞至半導體封裝件外而散逸， 如此新增加之散熱路徑可有效提昇半導體封裝件之散熱效 率。 此第二實施例之多晶片半導體封裝件可與第2A至2E 圖所示類似之單一封裝件製法或與第3入至邛圖所示類似 之批次方法製得。第二實施例之半導體封裝件的製程與第 2A至2E圖或第3As 3F圖所示者之差異在於，當完成第 2A至2B圖或第3As 3B圖所示之基板ι〇製備以及第一 晶片11之接置後，於第一晶片n之非作用表面^丨上敷 又導先、^ 2 ’再進行第2C或3C圖所示之步驟以於基板 1〇上接置别置封裝結構13，使前置封裝結構η之晶片座 14〇外露的下表面及其第—封裝膠體16黏接至導熱膠2， ::導熱膠2填充於第一晶片u與第一封裝膠體“間之 ^二然後再進行第扣錢圖或第3d^f圖所示之< 於在進行第2〇或3〇圖所示之模壓作業前，使第 曰曰片-弟一封裝膠體16間之間隙〇填充有導孰膠 ，支忒間隙G不會為模壓作業所形成之第二封裝膠體p 所填充，且如上所述，導埶膠2 ^ 梦社槿n由— 敷έ又有助於散逸前置封 中罘一晶片15所產生的熱量，俾有效改盖敕 體半導體縣件之散熱效率。 俾有效改善整 上述本發明之多晶片半導體封裝件及其製法，係利用 18204 20 Ϊ250592 基板同時载接一已封裝之晶片及 覆晶，先將第 以覆晶方式μ客盤{曰姐几 σ〜町示日日片 梦右〜 數祕凸塊電性連接於基板上，再將-封 φ\二—晶片之導線架式前置封裝結構接置於基板上，直 並結構具有露出之外導腳藉表轉著技術接置 板，而使前置封裝結構之第一卿 °卜泠腳及基板形成-空間而令第-晶片容置苴中， ::第：封裝膠體架撐於第一晶片上方並與第一晶片間存 間隙。由於前置封裝結構藉表面黏著技術電性連接至 △故位於第一晶片與基板間之銲錫凸塊不會遭受習知 技術中進行銲線作業時產生之震動而發生裂損（咖幻，因 =，發明無需進行底部填膠（underfill)作業以填充位於第 曰曰日片14基板間之相鄰銲錫凸塊間的空隙，而可以一次模 壓製程形成第二封裝膠體使其包覆第一晶片&前置封装結 構並填充於第-封裝膠體與第一晶片間之間隙及相鄰鲜錫 凸塊j之空隙，且能避免底部填膠作業污染基板上預設用 =與前置封裝結構之外導腳相接的部位，俾確保前置封裝 結構得良好地接置並電性連接至基板，而不會影響整體半♦ V版封衣件之電性連接品質及信賴性。再者，由於前置封 裝結構在製備完成後會先經過良率測試及性能檢測再接置 至基板上，換言之，只有成功通過良率測試及性能檢測之 刖置封裝結構才會接置至基板上，故前置封裝結構不會封 裝有未知品質是否良好或有缺陷的第二晶片，因而摒除習 知是否為已知良品（kn〇wn g00d die，KGD)之疑慮，俾確保 正脰半導體封裝件之信賴性及良率。此外，本發明之另二 21 18204 1250592 二二前置封裝結構之導線架具有外露出第 月且I日日月座，佶讀日 / —晶片間之…/，1^=表面鄰接第—封裝膠體與第 膠體與第-晶片間之封裝:體前，使第—封農 片座上之第二曰片所“ 導熱膠’故承載於該晶 遞至第-曰曰π 熱量可經由晶片座及導熱膠傳 &曰曰，、、莖由與第一晶片相連之銲錫凸塊以及基 板傳遞至半導體封料“散逸，如此 ς 件之散熱效率…卜，本發明之半導體封裝= 株且古+、，、夕弟曰曰片及弟二晶片）結構，故使整體封裝 仵具有增進的電性及運作效能。 *上述實施例僅為例示性說明本發明之原理及其功 非用於限制本發明。任何熟習此項技藝之人士均可 =違背本發明之精神與範訂，對上述實施例進行修倚 ::’交化。因此’本發明之權利保護，應如後述之申 乾圍所列。 【圖式簡單說明】 為讓本發明之上述及其他目的、特徵以及優點能更明 顯易懂，將與較佳實施例，並配合戶斤附圖#，詳細說明本 發明之實施例，所附圖示之内容簡述如下·· 第1圖係本發明第一實施例之多晶片半導體封裝 剖視圖； 第2A至2E圖係第1圖之半導體封裝件的一組製程步 驟示意圖； 乂 第3 A至3F圖係第1圖之半導體封裝件的另一組製程 18204 22 1250592 步驟示意圖； 戶、轭例之多晶片半導體封裝件的 弟4圖係本發明第 剖視圖； 第5圖係一習知多 第6圖係另一習知 多晶片半導I 豐封裝件的剖視圖。 L主要元件符號說明】 1 基板片 10 基板 1〇〇 上表面 101 下表面 11 第一晶片 110 作用表面 111 非作用表面 112 銲墊 12 銲錫凸塊 13 前置封裝結構 14 導線架 140 晶片座 141 導腳 142 内導腳 143 外導腳 15 弟—晶片 16 第一封裝膠體 17 第二封裝膠體 18 銲球 19 銲線 2 導熱膠 20 基板 21 第一晶片 210 作用表面 211 非作用表面 22 辑錫凸塊 23 第二晶片 24 辉線 25 封裝膠體 26 鲜球 30 基板 31 第一晶片 310 作用表面 311 非作用表面 32 辉錫凸塊 33 柵格陣列封裝結構 18204 23 1250592 330 基板 34 銲線 35 封裝膠體 36 鲜球 G 間隙 S 空間 24 18204

Claims (1)

1250592 、申請專利範圍： 種多晶片半導體封裝件，包括·· -基板H上表面及—相對之下表面，· 面#V-一弟晶片’具有一作用表面及一非作用表 !·生遠：弟一晶片之作用表面藉多數銲鍚凸塊接置並ΐ 性連接至該基板之上表面； -前置封裝結構，包括―導 性連接至該導線架之第二晶片、及一用以：41 片與部分導線架之第一封铲# ^復^弟一曰1 釕衷胗體，使该導線架之外導夠 二出该弟：封裝膠體外而接置於該基板之上表面，其中 1，膠體、露出之外導腳及基板形成1間而使 邊弟一晶片容置其中，日兮筮_曰 « 44^ ^ 且5亥弟一日日片之非作用表面與該 第一封裝膠體之間存有一間隙；以及 用以包 梦上一第二封裝膠體，形成於該基板之上表面 覆該第一晶片、銲錫凸塊及前置封裝結構。 復包為 2. ^申請專利範圍第i項之多晶片半導體封裝件 多數銲球，植設於該基板之下表面。 其中言I 3. =申請專利範圍第1項之多晶片半導體封裝件 第二晶片係藉多數銲線電性連接至該導線架。 4. :申，專利範圍第3項之多晶片半導體封褒件六” V線木包括一晶片座及多數導腳，各該導腳由内導腳2 外導腳構成，使該第二晶片接置於該晶片座之上表面』 電性連接至該内導腳，且該内導腳為該第一封裝膠 包覆。 、^ 18204 25 1250592 5·如申請專利範圍第4項之多 日日片座為該第一封裝膠體所 6·如申請專利範圍第5項之多 第二封裝膠體填充於該第一 間隙中。 7·如申請專利範圍第4項之多 片座之下表面外露出該第 片與第一封裝膠體間之間 8·如申請專利範圍第7項之多 晶片半導體封裝件，其中該 包覆。 、^ 晶片半導體封褒件，其中該 晶片與第一封裝膠體間之 ΒΒ 晶片半導體封裝件，其中該 曰曰 一封裝膠體而鄰接該第一 隙。 第一晶片與第一封裝膠體間 晶片半導體封裝件，其中該 ------之間隙敷設有一導埶贩 …請專利範圍第β之多晶片半導體封上、:中 弟一封裝膠體與第二封裝膠體由 ”中4 U).如申請專利範圍第！ 材料製成。 咏+ 貝之夕日日片丰導體封裝件，J：中兮 膠體與第二封裝膠體由不同之樹脂材料製成： • -種多晶片半導體封|件之製法，包括下列步驟. 面；提供-基板，該基板具有—上表面及_相對之下表 提供至少一第一晶片，該第_晶片具有—作 藉多數銲錫凸塊接置及電性連接該 弟Β曰片之作用表面至該基板之上表面； 狀处接置1置封t結構於該基板之上表面，該前 二：包=導及線架用至少一接置並電性連接至該導線 之Μ 包覆該第二晶片與部分導線力子 之弟-封裝膠體’使該導線架之外導卿露出該第一封裝 18204 26 1250592 膠體外而接置於該基板之上表面，並使該第一封裝膠 體、露出之外導腳及基板形成—空間而令該第一晶^容 置其中，且該第一晶片之非作用表面與該第一封裝膠體 之間存有一間隙；以及 形成一第二封裝膠體於該基板之上表面，使該第二 封裝膠體包覆該第一晶片、銲錫凸塊及前置封裝結構。 !2.如申請專利範圍第⑽之製法，復包括植設多數 於該基板之下表面。 13.如申請專利範圍第21項之製法，其中該前置封裳 係以表面黏著技術（Surface M〇_ Techn〇i〇gy)接置於 該基板之上表面。 14·如申，範圍第u項之製法，其中該第二晶片係藉 多數銲線電性連接至該導線架。 μ曰 15.:申請專利範圍第14項之製法，其中該導線架包括一 Β曰片座及夕數導腳，各該導腳由内導腳及 使該第二晶片接置於該晶片座之上表面並電性 遠内導腳’且該内導腳為該第-封襞膠體所包覆。 K如申請專㈣圍第15項之製法， 一封裝膠體所包覆。 月从马。亥弟 17·如申凊專利範圍第丨6 ^ ^ ^ 埴充於兮楚一曰p負之衣法，其中該第二封裝膠體 ’、日日片與第一封裝膠體間之間隙中。 18·如申請專利範圍第15項之 面外露出該第一封事㈣而^ '、中“片座之下表 裝膠體間之間陈㈣而鄰接該第一晶片與第-封 18204 27 1250592 19.如申請專利範圍第18項之製法，其中該第一晶片與第 一封裝膠體間之間隙敷設有一導熱膠。 〃 2〇·如2請專利範圍第n項之製法，其中該第一封裝膠體 與第二封裝膠體由相同之樹脂材料製成。 21·如=請專利範圍帛u項之製法，其中該第一封裝膠體 與第二封裝膠體由不同之樹脂材料製成。 22·—種多晶片半導體封裝件之製法，包括下列步驟： 提供一基板片，該基板片包括多數基板並具有一上 表面及一相對之下表面； 接置至少一第一晶片於各該基板之上表面，該第一 晶片具有—作用表面及—非作用表面，並藉多數鮮錫凸 塊電性連接該第一晶片之作用表面至各該基板之上表 面； 接置一前置封裝結構於各該基板之上表面，該 封裝結構包括_ ^ isk ^ 2S I 綠加1 少—接置並電性連接至該導 :木之弟二晶片、及一用以包覆該第二晶片與部分導線 封f膠體，使該導線架之外㈣露出該第~封 ^二夕卜而接置於該基板之上表面，並使該第一封事膠 體、路出之外導腳及基板形成一空間而令該第二 之間存有之非作用表*與該第-封裝膠體 ::裝膠體包覆所有該第-晶片、銲錫凸塊及前置:； 18204 28 1250592 植設多數銲球於該基板片之下表面；以及 進行一切單作業，以切割該第二封裝膠體及基板 片’使各該基板分離而形成多數個別之半導體封裝件。 士申明專利範圍第22項之製法，其中該前置封裝結構 係以表面黏著技術接置於各該基板上。 24·:申請專利範圍第22項之製法，其中該第二晶片係藉 多數銲線電性連接至該導線架。 25.:申請專利範圍第24項之製法，《中該導線架包括一 栋Γ及夕數導腳，各該導腳由内導腳及外導腳構成， 該=二晶片接置於該晶片座之上表面並電性連接至 26如：ί:’且該内導腳為該第-封裝膠體所包覆。 一封裳膠體所包覆。衣&中5亥晶片座為該第 27·如申凊專利範圍第26項之f、、$，1 β 填充於所有以—曰μ #中§亥弟二封裝膠體 28.如申,f專;!阳片舁弟一封裝膠體間之間隙中。 T明專利乾圍第25項之fj、本，甘山》 面外露屮兮势 、、/ 中該晶片座之下表 裝膠體間之間隙。 妾μ弟一日日片與弟一封 29·如申請專利範圍第以項之製法 體間之間隙敷設有—導熱片與第 • 〇申凊專利範圍第22項之 ' 夕 與第二封裝膠〜，/、中該第一封裝膠體 31.如申請專Ϊ 之樹脂材料製成。 Τ明專利範圍第22項之努 與第二封裝膠體由不同^: 〃中该弟一封裝膠體 ^之树知材料製成。 18204 29
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