TWI247563B - Interposer and method of making same - Google Patents
Interposer and method of making same Download PDFInfo
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- TWI247563B TWI247563B TW089111488A TW89111488A TWI247563B TW I247563 B TWI247563 B TW I247563B TW 089111488 A TW089111488 A TW 089111488A TW 89111488 A TW89111488 A TW 89111488A TW I247563 B TWI247563 B TW I247563B
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- H—ELECTRICITY
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- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/01019—Potassium [K]
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- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
1247563 A7
本發明係關於積體電路與一如印刷♦ 、 的連接。本發明係更特別關於供_合二:支撑基板間 基板用之中介層。 積^路至-支撐 登明背景 ,積體電路係已生產製造多彳。傳統之製造係整合主動與 被動電路元件於一簡稱晶片之半導體材料中,及該日片係 包入-陶變或塑膠之謝。#裝通常㈣配置::裝周 邊之接腳連接至一印刷電路板。一電子系砵係藉連接不同 積體電路封裝至一印刷電路板而成。 半導體製造技術之精進係導致每一積體電路中晶體數量 增加,同也使每一積體電路功能增加.但功能增加,則致 使為積體電路與該電子系統其餘部份之積體電路間所連接 的輸入/輸出(I/O)數量必須增加。一因應解決輸入/輸出連 接增加需求之設計係僅增加額外之接腳於封裝。不幸,增 加額外接腳於封裝係會增加封裝之面積。另一使輸入/輸出 連接增加而不增加不可接受面積之因應設計係接腳栅極矩 陣(PGA)及球柵極矩陣(BGA)封裝之發展。在該種封裝中, 大量輸入/輸出連接接線端係以二次元排列方式配置於一封 裝之主表面上。接腳柵極矩陣及球柵極矩陣通常係包括一 積體電路晶片,及係連接至一如印刷電路板之支撐基板上。 雖接腳栅極矩陣及球柵極矩陣封裝係提供需求大量輸入/ 輸出連接之積體電路節省空間,但所用製造材料通常係不 能與積體電路晶片材料之膨脹係數相匹配。 -4 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
裝 訂
1247563 A7 B7 五、發明説明(2
% 因此需求一結構,該結構係應適合以電氣及機械方式李馬 合一積體電路至一支撐基板,該結構應具有完全與積體電 路相匹配之熱膨脹特性。更進一步需求係該結構製造方法。 發明概述 簡言之,一適合連接一積體電路至一支撐基板之結構係 應具有與該積體電路相匹配之熱膨脹特性,該結構係一中 介層°該積體電路與該中介層係包括具有相似膨脹係數之 本體。該中介層係具有一第一表面,該表面適於以電氣及 機械万式#禺合至該積體電路。該中介層具有一第二表面, 该表面適於以電氣及機械方式耦合至一支撐基板。導電通 路係棱供該中介層第一表面與第二表面間之信號通徑。 裝 本發明之另一概念係不同之電路元件皆可納入該中介層 中。電路元件可係主動,被動’或主動與被動兩用之元件。 訂
圖1係碎基積體電路晶片藉焊料凸塊辑合至一有機焊2 柵極矩陣封裝及該有機焊盤柵極矩陣封裝藉焊料球耦
合J 一 P刷4路板之簡要側視圖; 圖2係-有機焊盤柵極矩陣封裝之簡要截面圖; 係根據本發明之,中介層簡要截面圖; 之另—簡要截面圖,以說明連接接線端; 合之轉合電容本器發明之-W介層簡要截 圖6係根據本發 合之晶體; 明(一矽基中介層簡要截面圖 ,以說明結
1247563 A7 ______ B7________._ 五、發明説明(3 ) 圖7至圖1 0係說明根據本發明第〆實例製造一矽基中介層 之步驟,其中深-通路係在晶片側邊互接成形前成形; 圖7係深-通路蝕刻完成後之一中介層簡要截面圖; 圖8係圖7所示中介層於一絕緣層成形於深-通路側壁及該 深-通路已充填導電材料後之簡要截面圖; 圖9係圖8所示中介層於更進一步完成喷塗金屬操作後之 簡要截面圖; 圖10係圖9所示中介層於更進一步完成噴塗金屬操作後之 簡要截面圖; _ 圖1 1至圖1 4係說明根據本發明第二實例製造一矽基中介 層之步驟,其中深-通路係在晶片側邊互接成形前成形; 圖1 1係一具有一第一噴塗金屬層形成在中介層晶片側邊 上的中介層簡要截面圖; 圖1 2係圖1 1所示中介層於另一晶片側邊噴塗金屬層形成 後之簡要截面圖; 圖13係圖12所示中介層於一深-通路通過中介層本體成形 ,及一絕緣層係在深-通路側壁表面成形後之簡要截面圖; 圖14係圖13所示中介層於深-通路充填玄電材料後之簡要 截面圖; 圖15-16係通用於圖7至圖10以及圖η至圖14所示過程;. 圖1 5係根據本發明之一中介層於晶片側邊及板側之噴塗 金屬層已拋光及電鍍後之簡要截面圖; 圖1 6係圖1 5所示中介層於供晶片側邊焊料凸塊及板側焊 料球使用之錯/錫圖案成形後之簡要截面圖; • 6 *· 本紙張尺度適财S S家辟(CNS) A4規格(21GX 297公爱)— Ϊ247563
發明説明 圖1 7係說明根據本發明之過程的流程圖; 圖1 8至圖2 1係說明根據本發明第三實例製造一矽基中介 層之步驟,其中深-通路係以二階段成形,而使深·通路第 —部份具有一傾斜側邊; 圖1 8係一中介層於深_通路傾斜側邊蝕刻完成後之簡要截 面圖; 圖1 9係圖1 8所示中介層於一絕緣層在深-通路側邊成形及 導電材料填入深-通路後之簡要截面圖; 圖2 0係獨1 9所示中介層於更進一步噴塗金屬操作後之簡 要截面圖; 裝 圖2 1係圖2 0所示中介層於更進一步噴塗金屬操作後之簡 要截面圖。 詳細說明 ax. 訂
一最新連接矽基積體電路及印刷電路板之方法係包括使 用封裝或中介層。封裝及中介層係在其他物件間提供一空 間轉換之功能^此係因製造積體電路及印刷電路板之過程 會造成不同之互接間距,因此,封裝及中介層係需連接積 組%路之窄間距輸入/輸出連接接線端於印刷電路板之相當 大的間距輸入/輸出連接接線端。封裝及中介層通常係由與 構成碎基積體電路不同之材料形成。傳統封裝及中介層之 連接問題係在連接積體電路及基板所需之互接間距的不同 ’及封裝或中介層通過積體電路與基板間時,置於連接上 足電容,電阻及電感的限制。就互接間距而言,目前之標 本紙張尺度適用中國@家標準(cns) ^規格(⑽χ 297公复) 五、發明説明( 5 準製造需求係包括-通常少於·μ之緊密間距,供作積體電 :介面用,及約lmm之粗間距,供作基板如印刷電路 面用。 尤目㈤可用技藝而T,有機焊盤栅極矩陣(有機坪盤拇極 :陣)封裝係不可能用於製造晶體。此外,有機焊盤柵極矩 2封裝之溫度限制係不能有助於形成一具有高介電常數之 電介質丄如鈦酸鳃鋇(BaSrTi〇3)。鈦酸鳃鋇係也簡稱β§τ。 ^具有向介電常數材料構成的電容器係非常適於作去耦電 合器用。有機焊盤柵極矩陣封裝係也受限於所能達成之互 接。§矽基積體電路晶片係連接至有機焊盤柵極矩陣封裝 基板時,因其各自之熱膨脹係數不相匹配,故係需要一大 於200μ之C4凸塊間距。根據本發明供積體電路晶片及中介 層用之矽墓晶圓係可減低該差異,因而減低C4所受之機械 應力。機械應力之減少係可使用較小之凸塊及較緊密之間 距。就目如之製造技術而言,有機焊盤柵極矩陣封裝上之 互接間距係限制於約225μ或更大。 本發明實例係使用矽基互接技術製造一中介層,進而該 中介層用以替代有機焊盤柵極矩陣或其他種類之封裝,以 供連接碎基積體電路至如印刷電路板之基板。根據本發明 之中介層係可容易地達成緊密及粗疏互接間距,以及在一 中介層之上或之内形成的互接所需求之電阻,電容,及電 感。只要自晶片之緊密互接間距至印刷電路板,或其他種 類支撐基板’或電路基板之相當粗疏互接間距的空間轉換 發揮功能,此係簡稱扇出。此外,本發明實例係可使電路 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公爱) 1247563 A7
1247563 A7 B7 五、發明説明(7 ) 數而言。例如,有機聚合物,毫微海綿,含有有機聚合物 之矽基絕緣器,含氧化矽之氟係具有較二氧化矽低之低電 介常數。 字母k,通常係代表電介常數。同樣地,高-k及低-k,在 此領域中係分別代表高電介常數與低電介常數。 在此領域使用之内層電介質係指配置於一己知互接層中 互接線間之電介材料而言。即一内層電介質係在鄰近互接 線之間,而非在互接線之上或之下垂直。 外延層係一單晶半導體層。 _ 術語“閘”係靈敏度及可以二不同方式說明積體電路。在 本發明中,用於晶體電路構型時,閘係一三接線端場效應 晶體之絕緣閘接線端,及用於邏輯閘時,係一任意邏輯函 數之實現電路。當半導體本一併考量時,一場效應晶體係 可視為一四接線端之元件。 聚晶矽係一以隨機定向晶體構成之無孔矽。聚晶矽通常 係藉化學氣相澱積法或其他方法自一矽源氣體成形,及具 有一含大角顆粒邊界,雙邊界,或二者之組合結構。聚晶 矽通常係稱為聚矽。 源極/漏極接線端係一場效應晶體之接線端,在其間,導 電係受一電場之影嚮而發生,而後係半導體表面受加施於 閘接線端之電壓而導致之一電場的影嚮而反轉。源極及漏 極接線端通常係以幾何圖形對稱方式製造。幾何圖形對稱 源極及漏極接線端通常係簡稱源極及漏極接線端,及本發 明即使用該名稱。當該場效應晶體在一電路中操作時,設 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 五、發明説明(8 計者通常係依據加施於接線端之電壓指定一特殊之源極/漏 極接線端為“源極,,或為“漏極,,^ j發明使用之術語“垂直,,係指大致垂直於一物體之表面 而言。 參閱圖1知,係一傳統配置,其中一矽基積體電路晶片 102係連接至一有機焊盤柵極矩陣封裝104。焊料凸塊1〇6係 作提供積體電路晶片〗〇2及有機焊盤柵極矩陣封裝丨〇4間之 電氣連接用。焊料凸塊1〇6有時簡稱為C4凸塊,係因此種方 式之互接係用於c〇ntr〇Ued c〇Uapse chip連接(即c4)封裝之 故。有機焊盤栅極矩陣封裝1〇4係藉焊料球11〇連接至印刷 電路板108。焊料球110係提供有機焊盤柵極矩陣封裝ι〇4及 印刷电路板108間之電氣連接。以此方式,積體電路晶片 1〇2與印刷電路板108間之電氣連接係通過有機焊盤栅極矩 陣封裝104。 圖2係有機焊盤柵極矩陣ι〇4之簡要截面圖。由圖示知, 焊料凸塊106係藉互接112以電氣方式連接至焊料球11〇。互 接112通常係在一或更多互接層上之金屬線。當超過一互接 層使用時,各層金屬線間之連接通常係用通路達成。 圖3係根據本發明之一中介層U5的簡要截面圖。中介層 115係包括一本體部份116,焊料凸塊1〇6 ,焊料球,互 接118,絕緣材料120 ,及深·通路122。在本實例中,本體 部份116係一矽基基板。該矽基基板通常係小於用於生產積 體電路晶片102用之基板,該基板係連接至中介層ιΐ5。互 接118係可用一如銅之金屬製造,及可經金屬鑲嵌過程,雙 I1247563 A7 B7 五、發明説明(9 ) 金屬鑲嵌過程,減金屬過程,或其他適合之方法構成導電 之互接。焊料凸塊106係適於供連接至積體電路晶片102用 。焊料球110係適於供連接至印刷電路板1〇8用。深-通路 122係一在中介層115第一側邊與第二側邊間之通徑。密佈 焊料凸塊106之中介層Π5側邊係簡稱晶片側邊,或稱之為 頂端,或前端《密佈焊料球110之中介層U5侧邊係簡稱板 側邊,或稱之為底邊,後側邊。 圖4係根據本發明中介層U5之另一簡要截面圖。由圖示 可清晰得知,複數之焊料球係成為中介層n5之一部份。此 外’可知晶片侧邊互接間距係較板側邊互接間距更密集。 雖本發明未要求晶片側邊與板側邊之互接間距間有特殊之 關係,但通常晶片側邊之互接間距係較密集,即其小於板 側邊之互接間距。 圖5係根據本發明另一中介層115之簡要截面圖。由圖示 可知’電容器130及134係納於中介層115之中。電容器130 係包括一對金屬片及一絕緣層132。該金屬片基本上係與金 屬互接118相同。雖電容器130通常呈長方形之片狀,但該 金屬係可呈任何所希望形狀之圖案。絕緣材料132可係一高 絕緣常數之材料,如鈦酸鳃鋇。電容器134係包括由該基板 ,或本體部份116構成之一片,及由導電材料,如金屬或摻 雜多矽,但不僅限於二者,構成之第二片。一絕緣層136可 係一高絕緣常數之材料或氧化矽。本發明係不要求使用特 殊絕緣材料或厚度。置去糕電容器靠近積體電路晶片,而 非置於傳統封裝及中介層時,不希望附於傳統配置引線之 -12 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐) 裝 訂
1247563 A7 B7 五、發明説明(1〇 ) 寄生電感係充分減低。 圖6根據本發明另一中介層115之簡要截面圖。由圖示可 知,晶體140係納於中介層115中。晶體140係絕緣之閘控場 效應晶體(FET)及係包括源極/漏極終端142,選通電極144 ,及選通絕緣145,如圖6所示。晶體140係η-通道場效應晶 體或ρ -通道場效應晶體。精於此技藝及瞭解本明優點者係 知曉,η-通道及ρ-通道兩用場效應晶體係可配製於基板116 之上。本發明對場效應晶體140之電氣特性或尺寸係無特殊 之要求。本發明係可整合不同之被動及主羚電路元件於中 介層115中。 整合主動及被動電路元件於中介層中係可能使也整合電 路於中介層中。例如,靜電放電保護電路(ESD)係可包括於 中介層中,因而減少整合所有保護電路在積體電路晶片上 之負擔,該積體電路晶片係將連接至中介層。同樣地,其 他型別之電路功能係也可整合於中介層中。例如可包括但 不僅限於高速緩衝記憶電路,輸入/輸出緩衝電路,功率調 整電路,電壓電平移動電路。精於此技藝及瞭解本發明優 點者係知曉,根據本發明各不同實例,眾多電路功能係可 整合於提供主動及被動電路元件之中介層中。 晶體整合於中介層中,係可依照或不需依照在積體電.路 晶片上形成晶體之製造過程。例如’積體電路晶片上之晶 體及隨其形成之電路係可設計使之以一第一電壓範圍操作 ,而中介層上之晶體及隨其形成之電路係可設計使之以一 第二電壓範圍操作。同樣地,中介層上每一電路元件之電 -13- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 裝 訂
線 1247563 A7 B7 五、發明説明(11 ) 氣特性係不同於積體電路晶片上每一電路元件之電氣特性 。例如場效應晶體之電氣特性係可在中介層與積體電路晶 片間有所不同,其包括但不僅限於,門限電壓,閘電介質 擊穿電壓,載波機動性,關態耗散電流,接點耗散電流, 及接點電容。因該等電氣特性係晶體結構設計之有力函數 ,及可分別修改積體電路晶片及中介層之電路元件。例如 ,中介層上之電路係可設計使之以比積體電路晶片上電路 較高之一電壓操作。 參閱圖7至圖1 0知,係說明本發明採用之步驟。在本實例 中,深-通路係於頂端(即晶片側邊)噴塗金屬操作前,以通 過基板方式形成。 如圖7所示,一矽基基板202係具有一二氧化矽(Si02)層 204及一二氧化矽層206在相對表面上形成。在此特殊實例 中,二氧化矽層204及206係加熱使之達一約0·5μ之厚度。 一通常厚約0.2 μ之氮化矽(Si3N4)層208,係而後疊於二氧化 矽層206之上。氮化矽層208係可藉等離子體增強化學氣相 澱積(PECVD)形成。而後,一供蝕刻深-通路用之遮蔽層係 成形與構圖於二氧化矽層204之裸露表面上。然後蝕刻二氧 化矽層204之裸露表面部份,進而曝露矽基基板202之對應 部份。該已曝露之矽基基板202部份係蝕刻而形成如圖7所 示之深-通路開口 209。應瞭解,雖在圖7中示出供說明目的 用之一深-通路,但根據本發明在製造中介層時,係可形成 複數之深-通路。深-通路開口 209之蝕刻係至二氧化矽層206 為止。換言之,在深-通路開口 209形成時,二氧化矽層206 -14· 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) !247563
係餘刻之終止層用。 參閱圖8知’可瞭解深.通路開口謝形成後,叠 =口挪之二氧切層2_份係會㈣掉。氮切層2〇8 作蚀切層206之蚀刻終止層。而後,一氧化物層21〇 中、於木-通路開口 209之表面。在以圖8說明之本發明實例 ^氧化物層210係约0·5Ρ厚。氧化物層210係可簡稱側邊 氧化物層。氧化物層21G形成後,—阻擔層及—銅氣粒層係 1塗於深·通路開之中。嘴塗之阻擔層可㈣或氮化备 且八有10-50 nm厚度。噴塗之氣粒層係銅,且具有1〇〇_ 3〇〇 nm又厚度。另一種方式係銅氣粒層可藉化學氣相澱積 成形。化學氣相澱積成形銅氣粒層係可提供更佳之側邊敷 蓋。 而後,一銅層212係電鍍於深-通路209中,使之大致充填 以鋼’及一銅層係配置中介層之背側。在此階段處理之中 J層背側係包括二氧化矽層204,及該阻擋層與銅氣粒層係 开y成在一氧化碎層204之上以及鍍銅於其上。 參閱圖9知,一二氧化矽層214係約5 μ厚,及係疊於氮化 石夕層208之上。一通常包括光敏電阻遮蔽層(未示出)係成形 與構圖於二氧化矽層214之上。使用之圖案係對應於一溝槽 ’遠溝槽係成形於氧化物層214及氮化矽層208中以利鑲.銅 噴塗金屬操作。當圖案遮蔽層成形後,氧化物層214之曝露 部份即接受蝕刻。如此即使氮化矽層208部份曝露。此時, 光敏電阻遮蔽層係可移除。而後,氮化矽層2〇8之曝露部份 即接受蝕刻。一銅阻擋層及一銅氣粒層係隨之配置於中介 -15- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐)
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線 1247563
層晶片側邊表面之上及包括置入前述蝕刻氧化物層214及氮 化碎層208形成之溝槽中。一銅金屬層215係電鍍於銅氣粒 層之上。銅金屬層215係大致充填該溝槽及遮蓋配置在氧化 物層214之上的阻擔層表面。而後係執行飽平操作,該操作 係抛光銅金屬層215之背面,這樣,多餘之銅及在其下方之 阻擔層對應部份係自氧化物層214表面移除。該鉋平/拋光 背面操作通常係藉化學機械拋光法(CMP)完成。不同之漿 狀化學劑係可用於拋光該銅金屬及阻擋層,以求拋光操作 最佳化。而後係配置一氮化矽層216於銅金屬層215及氧化 物層214之上,如圖9所示。氮化矽層216通常係藉等離子體 增強化學氣相澱積成形及使其厚度達約〇 . 1 μ。 如圖1 0係說明額外之絕緣及雙鑲金屬導電層成形並構圖 於中介層頂部後之圖9所示結構。一氧化物層21 8係疊於氮 化石夕層216之上。氧化物層218係形成一内層電介質(乩〇)及 在實例中,該内層電介質係約1 〇 μ厚。根據傳統之雙鑲金屬 過程’係繪製一供内層電介質通路開口用之遮蔽層圖案, 而後姓刻該内層電介質通路開口於氧化物層218中,並移除 内層電介質通路開口遮蔽層。而後,繪製一供金屬-2 (M2) 溝槽用之遮蔽層圖案,並蝕刻該金屬-2 (M2)溝槽於氧化物 層218中。然後移除該金屬-2(Μ2)溝槽遮蔽層,及曝露於 内層電介質通路開口底部之氮化矽層216部份即可蝕刻以曝 露一銅金屬底層。而後噴塗銅阻擋層及銅氣粒層於金屬-2 (Μ 2 )溝槽及内層電介質通路開口中。然後電鍍一銅金屬 層220於該銅氣粒層上。銅金屬層220係充填該内層電介質 -16- 本紙張尺度適财S S家料(CNS) Α4規格(210X297公爱) 1247563 A7 B7 五、發明説明(14 ) —' '--- k路開π及金屬·2(Μ2)溝槽,及成形於氧化物層218之上 ^圖11至圖14知’係說明本發明採用之另—過程。在 此見例中,冰-通路係於頂部(即晶片側邊)噴塗金屬操作後 成形而通過該基板。 如圖11所不,一矽基基板202係具有一二氧化矽(Si02)層 204及^二氧化矽層2〇6在相對表面上形成。在此特殊實例 中,:氧化矽層204及206係加熱使之達一约〇·5μ之厚度。 一通常厚約0·2μ之氮化矽(以^4)層2〇8,係而後疊於二氧化 矽層206之上。氮化矽層2〇8係可藉等離子體增強化學氣相 澱積(PECVD)形成。而後,一二氧化矽層214係成形作内層 私介質用。在此實例中,二氧化矽層214係配置在氮化矽層 208之上並具有一約54之厚度。一通常為光敏電阻層之遮蔽 層(未示出)係成形於二氧化矽層214之上並繪製圖案,這樣 ,即曝露二氧化矽層214供形成鑲金屬過程溝槽所需之部份 。於繪製光敏電阻圖案後,即蝕刻二氧化矽層214之曝露部 份。氮化矽層208係作一二氧化矽蝕刻操作之止蝕刻層用。 二氧化矽蝕刻操作後,該光敏電阻即移除。一銅阻擋層及 銅氣粒層係噴塗於中介層之晶片側邊表面上。該阻擋層通 常係一如鈕或氮化鈕之材料,該材料係具有導電性可阻擋 銅之移動,及作銅之黏著層用。而後銅係電鍍於氣粒層之 上,這樣,該溝槽係充填以銅及一銅金屬層係成形於晶片 側邊表面剩餘部份之上。成形於溝槽外側之銅係多餘之銅 。而後,用化學機械掘光操作去除多餘之銅。個別銅互接線 •17- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
1247563 A7 B7 五、發明説明(15 ) 215之結果係示於圖1 1之簡要截面圖中。然後,氮化發層 216係配置在中介層晶片側邊表面上。氮化矽層216通常係 藉等離子體增強化學氣相澱積成形,且達一約〇 ·丨μ之厚度 。氮化矽層216係作後續通路成形操作之止蝕刻層用,同時 也阻擋銅之移動。 就前述去除多餘銅而言,因多餘之銅係配置在一阻擔層 上,該層係具有包括但不僅限於漿狀化學物,向下力量, 旋轉速度’溫度等,在電位上不同化學與機械特性,故該 銅金屬層與該阻擋層間係會變化以達預期之結果。 圖12係說明更進一步生產一額外層次金屬互接線之操作 完成後的圖11所示結構。在本實例中,係採用雙鑲金屬噴 塗步驟,以在互接層次構成額外之互接線與通路。精於此 技藝及瞭解本發明優點者係知曉,以此方式係可製造數層 之互接。在本實例中,一二氧化矽層218係配置於氮化矽層 216上,且使其厚度達約1〇μ,以形成一内層電介質(ild) ^ 一第一遮蔽層(未示出)通常係一光敏電阻層形成於二氧化 矽層21 8並繪製圖案於其上,以曝露部份二氧化矽層218, 該部份係應移除,以形成雙鑲金屬過程所需之通路。光敏 電阻繪製圖案後,即蝕刻二氧化矽層218之曝露部份。氮化 矽層216係作二氧化矽蝕刻操作之止蝕刻層用。二氧化矽蝕 刻操作後,光敏電阻層即移除。一第二遮蔽層(未示出)係 2成在二氧化矽層218之上並繪製圖案,以曝露應蝕刻之二 氧化矽層21 8部份,該部份係蝕刻形成金屬互接線所需之溝 槽。蝕刻 < 溝槽係移除二氧化矽至一深度,該深度大致對 1247563 A7 B7 五、發明説明(16 ) 應於金屬互接線所需之厚度。而後係移除該第二遮蔽層。 然後蝕刻曝露於通路開口底部之氮化矽層216部份,因此曝 露其下方之銅互接線215。一銅阻擋層及銅氣粒層係噴塗於 中介層晶片側邊表面上。而後電鍍鋼金屬至氣粒層上,這 樣,該通路與該溝槽即充填銅金屬及一銅金屬層係同時成 形於晶片側邊表面之剩餘部份上。成形在該溝槽外側之銅 金屬係屬多餘。 圖13係說明更進一步生產深-通路開口 2〇9之操作完成後 的圖1 2所示結構。一遮蔽層,如光敏電阻(未示出),係成 形於中介層背面(即板側)並繪製圖案於其上,以曝露部份 二氧化矽層,該部份係應移除,以形成深·通路2〇9。而後 ,蝕刻移除氧化物層204之曝露部份,而曝露中介層矽基基 板或本體202部份。然後以氧化物層2〇6作止蝕刻層,而蝕 刻通過矽基基板202之深-通路開口 2〇9。自背側表面視之圖 示深-通路開口 209係未限制其為任何特殊形狀,其可為圓 形,長方形,或其他多邊形形狀。深_通路開口2〇9成形後 ,一二氧化矽層210係成形在該曝露之内表面上,同時簡稱 通路開π 209之側邊。在本實例中之二氧切層21〇係厚約 〇·5μ,及係可藉化學氣相殿積法處理。而後,蝕刻藉深_通 路209曝露之氧化物層206部份。如圖13所示,氧化物層2〇6 曝露部份之移除係可曝露氮化碎層208之對應部份。狹後蝕 刻氮化矽層208之曝露部份,以曝露鋼金屬層215之對應部 份。 圖14係說明更進一步生產充填深·通路開口 2〇9,及同時 -19- 本紙張尺度制巾@ g家標準(CNS) Α4規格(2i〇x 297公爱)— ------- 裝 訂
線 1247563 A7
敷蓋中介層背面氧化物層綱之銅金屬層212的操作完成後 ,圖13所示結構。如圖14所示,深·通路開口 2〇9所曝露之 虱化矽層208部份係藉蝕刻移除。而後噴塗一銅阻擋層及一 銅氣粒層〜罙.通路開n2G9之上。然後鋼#'電鍍於深-通路 開口 209中與中介層背部表面之上。 、^ 15及圖16係說明通用於前述說明圖7至圖1〇(深-通路 足第一次處理)及圖11至圖14(深_通路最後處理)之處理操 作。 一參閱圖15知,在巾介層板側上多餘之銅係藉化學機械抛 光法移除。精於此技藝者應知曉,係可採用二步驟處理之 化學機械拋光法,其中一第一漿狀化學物係用以移除銅金 屬及一第二漿狀化學物係用以移除阻擋層。同樣地,在中 介層晶片側邊多餘之銅以及不需要之阻擋層部份係藉化學 機械拋光法移除。剩餘之裸露銅金屬係易於作鎳/金無電鍍 ,這樣,鎳/金層224即形成於晶片側邊及中介層板側之上 。無電鍍化學係提供曝露之金屬表面一選擇性之處理。 圖16係說明於數項額外處理完成後之圖15所示結構,令 數項處理係用於生產印刷低溶焊料網屏,該網屏係供連接 一積體電路晶片至中介層,及該中介層至電路基板用。圖 15所示結構,更特別係易於在其背面,即其板側作鉛/錫噴 塗處理。而後,噴塗形成之鉛/錫層係以傳統之光刻法繪製 圖案於其上,以構成焊料球預報結構226。而後係成形 醯亞氨層228在中介層晶片側邊之上,如圖1 6所示。聚酿= 氨層228係以傳統之光刻法繪製圖案於其上,以曝露部彳八錄 裝 訂
線 •20-
* 1247563 五、發明説明(18 ) /金層224。另一鉛/錫噴塗處理操作係在生產一敷蓋中介層 頂端,即晶片側邊之鉛/錫層。而後係在該晶片側邊層之鉛/ 錫上繪製形成焊料凸塊預定結構23〇圖案,如圖丨6所示。精 於此技藝及瞭解本發明優點者係知曉,處理操作之順序係 會變更,但仍能完成所預期之結構。在處理操作順序中所 有之變更係應在本發明範圍以内。 圖1 7係根據本發明作業之流程圖。一積體電路及一中介 層係耦合為302。根據本發明之原理,該中介層及該積體電 路係具有相似之膨脹係數。在特別實例中,該中介層該積 體電路係具有基板,也簡稱本體,該本體係用相同之材料 製成。例如,該中介層及該積體電路係皆可用矽基基板製 造。於中介層用一如矽基之材料製造時,各種不同之電路 元件,包括但不僅限於電容器及晶體,係可用傳統半導體 製造万法整合於該中介層中。一電路基板,如一印刷電路 訂 板,及該中介層係也可耦合為3〇4。該中介層係提供該積體 電路與該電路基板間之機械連接。此外,該中介層係提供 通過本體之導電信號通徑,使該積體電路以電氣方式耦合 至電路基板。 σ 本發明之另一實例係以圖丨8至圖2丨說明,該實例係說明 一矽基中介層之各種不同製造階段,其中深_通路係以二階 段之處理形成深-通路第一部份之傾斜側壁。形成該中介層 結構之處理係相似於圖7至圖1〇所說明之處理,但該深 路係具有一部份形成傾斜而非垂直之側壁。 參閱圖18知,係於具有傾斜側壁之深_通路蝕刻於其中的 巧張尺度適用中國國家標準(CNiTT4規格(篇X297公爱) 21 - 五、發明説明(19 ) 中介層簡要截面圖。更特別係一矽基基板202,其每一主要 表面上具有厚約〇 · 5 μ之熱生長氧化矽層204,206。一氮化 矽層係以0 · 1 μ之厚度疊置於氧化物層206之上。一深_通路 遮蔽層係遮蔽氧化物層204並繪製圖案,但需蝕刻成深_通 路開口區域除外。而後蚀刻氧化物層204之曝露部份,因而 曝露部份基板202。然後執行矽基基板202之均質姓刻,以 產生部份通過矽基基板202之傾斜側壁,如圖18所示。而後 執行各向異性蚀刻,以芫成圖1 8所示之深-通路開409 ^各 向異性蝕刻及各向同性蝕刻之合併使用係聲立一氧化物之 外伸部份410。 圖1 9係說明於一絕緣層成形於深-通路側壁,及一導電材 料充填深-通路後之圖18所示中介層的簡要截面圖。外伸部 份410係藉移除氧化物層204一半厚度之濕蝕刻移除。因外 伸部份410兩側係曝露於濕蝕刻劑,故該外伸部份之姓刻速 度係氧化物層204之二倍。外伸部份410移除後,一約〇·5μ 之側壁氧化物層210係生長於深·通路側壁之傾斜及垂直部 份之上。一銅擴散阻擋及氣粒層係噴塗於深-通路開口 4〇9 中。而後係鍍銅,使之充填深-通路開口 4〇9具有垂直側壁 之部份,以提供一導電塗層於深·通路409傾斜側壁之上, 及才疋供導廷層於氧化物層204之上。銅係隨深-通路開口 409傾斜側壁成形,這樣,即形成一溝型之結構,如圖19所 示。 圖20及圖21係說明二金屬層及二通路層之形成。每對金 屬與通路係藉前述以圖9與圖10以及圖13與圖4說明之雙鑲 1247563 A7
金屬處理形成。 結論 本發明實例係提供一適合 電路晶片至一基板之中介層 特性匹配,緊密互接間距, 該中介層中。 以電氣與機械方式韓合一積體 ’同時更進一步提供良好膨脹 及整合主動及被動電路元件於 本發明之一 於該中介層中 本發明之一 中。 特別優點係高電介常數之材料可容易地整合 此係便利其他用途如去耦電容器之形成。 特別優點係場效應晶體易於整合至該中介層 精於此技蟄及瞭解本明優點者係知曉,在本發明範圍内 係可此作多種設計選擇。例力,該積體電路晶片及該中介 層之本體係可由其他㈣基材料構成。同樣地,非銅之導 包材料係可採用構成該中介層及該積體電路之各種不同互 接另種方式係以一黏著層替代在中介層上之該銅阻擋 層泛中介層係未整合有晶體在其上或在晶體間係具有較 大足玉隙。例如孩黏著層之材料係包括但不僅限於鈦或氮 化鈦。另一種方式係使用包括但不僅限於摻氧化矽之氟, 而非二氧化♦之低叶材料作内層電介質用。 應瞭解,對前述說明之零件與步驟之細節,材料及配置 之各種其他改變,精於此技藝及瞭解本發明優點者係可在 不脫離申請專利範圍界定之本發明原理與範圍下執行。 -23·
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Claims (1)
- 1247 i 1488號專利申請案 中文申請專利範圍替換本(94年4月) 六、申請專利範圍 1· 一種製造中介層之方法,其包括 形成一第一組互連導線於一基板之一第一表面上; 形成一第二組互連導線於一該基板之第一表面上; 形成通路於該第一組互連導線與該第二組互連導線之 間,該方法進一步包括: 形成一第一氧化物層於一基板之一第一表面上,及一 第二氧化物層於該基板之一第二表面上; 形成一第一氮化矽層鄰接於該第一氧化物層之上; 圖案化該第一氮化矽層以曝露出部分該第一氮化矽 層; #刻該第一氮化矽層之曝露出部分以形成溝槽; 喷塗一銅阻擋層及一銅種子層於該基板之第一表面 上; 電鍍一導電材料於該銅種子層之上; 形成互連導線於該基板之第一表面上;及 沉積一第二氮化矽層於該基板之第一表面上; 2·如申請專利範圍第1項之方法,其進一步包括: 沉積一第三氧化物層於該第二氮化矽層之上; 圖案化該第三氧化物層以曝露出要被移除形成通路開 孔之該第三氧化物層的一第一部分; 餘刻該第三氧化物層之該第一部分; 圖案化該第三氧化物層以曝露出要被移除形成互連導 線之該第三氧化物層之第二部分; 钱刻該第三氧化物層之該第二部分 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1247563 六、申請專利範圍喷塗一銅阻擋層與一銅種子層於該基板之該第一表面 之上;及 電鍍一導電材料於該釾種子層之上。 3 ·如申請專利範圍第1項之方法,其進一步包括: 圖案化該第二氧化物層以曝露出要被移除之該第二氧· 化物層的部分以便形成一深-通路開孔; 蝕刻該第二氧化物層之曝露的部分以形成該深_通路 開孔; 喷塗一銅阻擋層與一銅種子層至該深-通路開孔之 中;及 4. 氮化梦層之 電鍍一導電材料至該銅種子層,之上。 如申請專利範圍第1項之方法,其中該第 厚度約0 · 2微米。 5. :==:r二:r:广- -2 -
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1999
- 1999-06-28 US US09/340,530 patent/US6617681B1/en not_active Expired - Lifetime
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2000
- 2000-05-26 WO PCT/US2000/014588 patent/WO2001001486A1/en not_active Application Discontinuation
- 2000-05-26 KR KR1020017016740A patent/KR20020016855A/ko not_active Application Discontinuation
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- 2000-05-26 JP JP2001506612A patent/JP5285829B2/ja not_active Expired - Fee Related
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- 2000-05-26 CN CNB008095671A patent/CN1199264C/zh not_active Expired - Fee Related
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US20050017333A1 (en) | 2005-01-27 |
US6671947B2 (en) | 2004-01-06 |
AU5166500A (en) | 2001-01-31 |
US20020081838A1 (en) | 2002-06-27 |
KR20020016855A (ko) | 2002-03-06 |
US6617681B1 (en) | 2003-09-09 |
EP1190449A1 (en) | 2002-03-27 |
JP5285829B2 (ja) | 2013-09-11 |
JP2003503855A (ja) | 2003-01-28 |
IL147304A0 (en) | 2002-08-14 |
WO2001001486A1 (en) | 2001-01-04 |
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