TWI238600B - Level converting circuit, semiconductor device and display apparatus having such level converting circuit - Google Patents

Abstract

A kind of level converting circuit, the semiconductor device and the display apparatus having such level converting circuit are revealed in the present invention. The main technique is featured with the followings. The control circuit of the control part responds to the input signal so as to make the gate voltage of the p-channel MOSFET in the exciter decrease from power source voltage to a level higher than the turning-on voltage value of the p-channel MOSFET. Additionally, the gate voltage of the n-channel MOSFET is made to increase from low level of input signal to a level higher than the turning-on voltage value of the n-channel MOSFET. Thus, when one of the p-channel MOSFET and the n-channel MOSFET shows stronger turning-on status, the other MOSFET shows weaker turning-on status.

Description

1238600 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the Invention (1) [Technical Field of the Invention] The present invention relates to a level conversion circuit for converting the voltage amplitude of an input signal into a larger voltage amplitude, and A semiconductor device and a display device having the level conversion circuit. [Technical background] According to the 'integrated integrated circuit used in recent years, there is a development of a microprocessor or memory and logic circuit mounted on the same chip', commonly known as "system integration on the chip" (SyStern on silicon). With its development, the development of technology for singulating a variety of circuits with design rules as fine as possible has been promoted. However, since each circuit type is designed with different design rules, it is inevitable that the integration of circuits with different design rules must be performed. As a result, most circuits operated by different power supply voltages are mixed in a single chip. In this case, the voltage level must be changed in the interface part between different circuits. By mixing most types of circuits on the same chip. Therefore, a level conversion circuit that performs voltage level conversion between different circuits must also focus on high-speed operation characteristics. Furthermore, display elements such as liquid crystal display devices and organic EL (electrol uminescence) devices are thin film transistors made of polycrystalline silicon. When such a display element and a level conversion circuit are co-designed on the same chip, the level conversion circuit will also be a thin film transistor formed of polycrystalline silicon. During the manufacturing process of H and ^, a threshold voltage value will be generated (threshold this ^ scale to turn around the house χ 297 public love 1 312308 illlllllj — ^ · I ---- 丨 Order i_ ---- (Please first Read the notes on the back and fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1238600 A7 B7 V. Description of the invention (2) Voltage) and other component characteristics are scattered (uneven). Especially in thin-film transistors made of polycrystalline silicon, the scattering of device characteristics such as threshold voltage is more serious. Therefore, it is expected that a kind of ultra-thin thin-film transistor will have scattered device characteristics such as threshold voltage. Level conversion circuit that can operate reliably. In addition, from the viewpoints of lower power consumption and higher definition in such display elements, a level conversion circuit that can operate and can operate at a high speed even when an input signal with a small amplitude is given is more needed. Figure 45 is a circuit diagram of a first example of a known level conversion circuit. The level conversion circuit 800 shown in FIG. 45 includes two p-channel MOSFETs (metal oxide semiconductor field effect transistors) 801 and 802, and two n-channel MOSFETs 803,804 and p-channel MOSFETs 801 and 802 are connected respectively. Between the power supply terminal receiving the power supply voltage VDD and the output nodes N11 and N12, the n-channel MOSFETs 803 and 804 are respectively connected between the output nodes N11, N12 and the ground terminal. The gates of the p-channel MOSFETs 801 and 802 are cross-connected to the output nodes N12 and N11, respectively. The gates of the n-channel MOSFETs 803 and 804 give complementary input signals CLK1 and CLK2. When the input signal CLK1 forms a high level and the input signal CLK2 forms a low level, the n-channel MOSFET 803 is in an ON state, and the n-channel MOSFET 804 is in an OFF state. Thereby, the p-channel MOSFET 802 is turned on, and the p-channel MOSFET 801 is turned off. As a result, the output voltage Vout of the output node N12 will rise. Conversely, when the input signal CLK1 forms a low level, and the input letter (please read the precautions on the back before filling this page) 1_ ^ 1 ϋ n ϋ · ϋ ^ -T * »J met II ϋ < This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 2 312308 1238600 A7 V. Description of the invention (3) When the CLK2 reaches a high level, the output voltage Vout of the output node N12 will decrease. (Please read the precautions on the back before filling this page) In this case, in order for the n-channel MOSFETs 803,804 to be turned on, the voltage amplitude of the input signals CLK1 and CLK2 must be greater than the threshold voltage value Vtn of the n-channel MOSFETs 803,804. . Therefore, the level conversion circuit 800 in FIG. 45 is suitable for a case where the voltage ratio of the input signal to the output signal is small.

For example, when the level conversion circuit 800 converts a 3V system signal into a 5V system signal, a 2.5V system signal into a 3V system signal, or a 1.8V system signal into a 2.5V system signal or a 3.3V system signal It works. Fig. 46 is a circuit diagram showing a second example of the known level conversion circuit. The level conversion circuit 810 in FIG. 46 includes a bias circuit 811, printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Affairs Co., Ltd. and a P-channel MOSFET 812 and an n-channel MOSFET 813. The p-channel MOSFET 812 is connected between the power terminal of the power supply voltage VDD and the output node 13, and the n-channel MOSFET 813 is connected between the output node 13 and the power terminal receiving a specific transformer VEE. The input signal clk is provided to the gate and bias circuit 811 of the p-channel MOSFET 812. The bias circuit 8 11 shifts the center level of the input signal CLK and gives the gate of the channel MOSFET813. Although the input #CLK is at a high level, the p-channel mSOSF812 is in a non-conducting state, while the n-channel MOSFET813 is in a conducting state. This reduces the turn-out voltage vout of the output node N13. When the input signal clk is at a low level, the ρ channel MOSFET812 is turned on, and the η 3 paper size is timely_ Home Standard (GNS) A4 Specification ⑵ Q 312308 1238600 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the invention (4) The channel MOSFET 813 is in a non-conducting state. This increases the output voltage Vout of the output node N13. At this time, since the center level of the input signal CLK is shifted by the bias circuit 811, the level conversion circuit 810 is used even when the voltage amplitude of the input signal CLK is smaller than the threshold voltage value Vtn of the n-channel MOSFET 813. , Can also act. Fig. 47 is a circuit diagram showing a third example of the known level conversion circuit. The level conversion circuit 820 in Fig. 47 includes a positioning circuit 821 and a current mirror type amplifier 822. The current mirror amplifier 822 series includes two p-channel MOSFETs 831,832 and two n-channel MOSFETs 833,834. The p-channel MOSFETs 831, 832 are respectively connected between the power supply terminal receiving the power supply voltage VDD and the output nodes N14, N15, and the n-channel MOSFETs 833, 834 are respectively connected between the output nodes N14, N15 and the ground terminal. The gates of the p-channel MOSFETs 831 and 832 are connected to the output node N14. The positioning circuit 821 shifts the center levels of the complementary input signals CLK1, CLK2, and assigns the gates of the n-channel MOSFETs 833,834. When the input signal CLK1 forms a high level and the input signal CLK2 forms a low level, the n-channel MOSFET 833 is turned on and the n-channel MOSFET 834 is turned off. As a result, the p-channel MOSFETs 831, 832 are turned on. As a result, the output voltage Vout of the output node N15 will rise. Conversely, when the input signal CLK1 forms a low level and the input signal CLK2 forms a high level, the output voltage Vout of the output node N15 will decrease. Zero-pack -------- 丨 order --------- (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297) (Mm) 4 312308 1238600 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (5) In this case, the position of the input signal CLK1, CLK2 is shifted by the positioning circuit 821, so The level conversion circuit 820 can operate even when the voltage amplitudes of the input signals CLK1 and CLK2 are smaller than the threshold voltage value Vtn of the n-channel MOSFET 83 3,834. Fig. 48 is a circuit diagram showing a fourth example of the known level conversion circuit. The level conversion circuit 840 in FIG. 48 includes a positioning circuit 841 and a PMOS cross couple type amplifier 842. The PMOS cross-coupled amplifier 842 series includes 2 p-channel MOSFETs 851, 8 52, and 2 n-channel MOSFETs 853,854 〇p-channel MOSFET 8 51, 852 are connected to the power terminal and output nodes N16, N17 that receive the power supply voltage VDD N, and n-channel MOSFETs 853,854 are connected between the output nodes N16, N17 and the ground terminal, respectively. The gates of the p-channel MOSFETs 851 and 852 are cross-connected to the output nodes N17 and N16, respectively. The positioning circuit 841 shifts the center levels of the complementary input signals CLK1 and CLK2 and assigns the gates of the n-channel MOSFETs 853 and 854, respectively. When the input signal CLK1 forms a high level and the input signal CLK2 forms a low level, the n-channel MOSFET 853 is turned on, and the n-channel MOSFET 8 54 is turned off. As a result, the p-channel MOSFET 851 is turned on, and the p-channel MOSFET 852 is turned off. As a result, the output voltage Vout of the output node N17 will rise. Conversely, when the input signal CLK1 forms a low level and the input signal CLK2 forms a high level, the output voltage Vout of the output node N17 will decrease. In this case, because the input signal is performed by the positioning circuit 841 (please read the precautions on the back before filling this page).

• III ί ami _1 I mlr ϋ · ϋ n ϋ II · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 5 312308 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1238600 A7 B7 5 6. Description of the invention (6) The displacement of the center level of CLK1 and CLK2, so the level conversion circuit 840 can operate even when the voltage amplitude of the input signals CLK1 and CLK2 is smaller than the threshold voltage value Vtn of the n-channel MOSFET 85 3,854. As described above, in the level conversion circuit 800 shown in FIG. 45, when the voltage amplitudes of the input signals CLK1 and CLK2 are smaller than the threshold voltage values Vtn of the n-channel MOSFETs 803 and 804, operation cannot be performed. In addition, in the level conversion circuit 810 shown in FIG. 46, the center level of the input signal CLK is shifted by the bias circuit 811, so even if the voltage amplitude of the input signal CLK is smaller than that of the n-channel MOSFET 813, It can also operate with the limited voltage value Vtn. Similarly, in the positioning circuits 820 and 840 shown in FIGS. 47 and 48, the center levels of the input signals CLK1 and CLK2 are shifted by the positioning circuits 821 and 841, so even if the voltages of the input signals CLK1 and CLK2 are Operation is also possible when the amplitude is smaller than the threshold voltage value Vtn of the n-channel MOSFETs 833, 834, 853, 854. However, in the level conversion circuits 810, 820, and 840 shown in Figs. 46 to 48, depending on the dispersion in the manufacturing process, if the threshold voltage value Vtn of the n-channel MOSFET deviates from the design value, the operation will fail. Happened.

Furthermore, regardless of any of the level conversion circuits 800, 810, 820, and 840 shown in Figures 45 to 48, during the manufacturing process, when the threshold voltage values of the p-channel MOSFET and the n-channel MOSFET are irregular, j is scattered. For example, the threshold voltage value Vtn of the n-channel MOSFET is large and the threshold voltage value Vtp of the p-channel MOSFET is small, or the n-channel MOSFET ---------- Γ--installation ---- ---- Order i (Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 6 312308 1238600 A7 B7 Employees ’Consumption of Intellectual Property, Ministry of Economic Affairs Cooperative printed 5. Invention description (7) When the threshold voltage value Vtn is small and the threshold voltage value Vtp of the p-channel MOSFET is large, the effect ratio of the output voltage waveform will deviate from a specific value. Especially when the level conversion circuit is used to generate a clock signal for a display element such as a liquid crystal display device or an organic EL device, the duty ratio of the clock signal must be set to 50%. When the duty ratio of the clock signal deviates by 50% due to the irregular change of the threshold voltage value Vtn of the n-channel MOSFET and the threshold voltage value Vtp of the p-channel MOSFET of the level conversion circuit, the pixels between the display elements light up and off When the lamp is turned on, the phenomenon of scatter will occur. In addition, in the level conversion circuit 800 in FIG. 45, when the switches of the n-channel MOSFETs 803 and 804 are reversed, the gate charge extraction operation of the p-channel MOSFETs 801 and 802 is performed. Therefore, it takes time to invert the level of the output voltage Vout, which makes it impossible to achieve the high-speed operation requirement. In particular, when the P-channel MOSFETs 801 and 802 are transistors with a small driving capability, such as thin-film transistors formed of polycrystalline silicon, the time required for the level of the output voltage Vout to increase will increase. When the level of the output voltage Vout is reversed, the through current will flow from the power supply terminal through the p-channel MOSFET 801 and the n-channel MOSFET 803, and the p-channel MOSFET 802 and the n-channel MOSFET 804, and flow to the ground terminal. Especially when it takes time for the level of the output voltage Vout to reverse, the passing time of the through current will increase, resulting in an increase in power consumption. In the bias circuit 811 of the level conversion circuit 810 in FIG. 46, a current flows through the resistance element to form the input signal CLK and the output signal (please read the precautions on the back before filling this page) J. · n I ϋ ϋ ail 1 11 1 ϋ ϋ ϋ ϋ I · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 312308 1238600 Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed clothing A7 V. Description of the invention (8) ----- The potential difference. At this time, it takes time until the setting of the difference between the input signal CLK and the output signal is completed, which prevents the execution of high-speed operation. In addition, in order to allow current to flow through the resistive element, a soft layout area is required. At the same time, because current is often flowing across the resistive element, power consumption will increase. In addition, because the high-speed: operation requirements cannot be achieved, the p-channel MOSFETW2 and n-channel MOSFET813 through-current in the output section will increase. Similarly, the positioning circuit 821 841 + of the level conversion circuit 82M40 shown in FIG. 47 and FIG. 48 is the same as the bias circuit 811 of the level conversion circuit 810 in FIG. 46, which hinders the high-speed operation. , And the need for a larger layout area will also lead to an increase in power consumption. [Summary of the Invention] In view of the above-mentioned problems, an object of the present invention is to provide _ a kind of reliable operation even when the threshold voltage value of the transistor is deviated from the design value due to the subtraction phenomenon of the manufacturing process. Level conversion circuit capable of high-speed operation, low power consumption, and small area effect. Another object of the present invention is to provide a reliable operation even when the threshold voltage value of the transistor deviates from the design value due to the disorder phenomenon in the manufacturing process, and can achieve high-speed operation and low power consumption. ^ A semiconductor device with a level conversion circuit with a small area effect. Another object of the present invention is to provide a reliable operation even when the threshold voltage value of the transistor deviates from the design value due to the disorder phenomenon in the manufacturing process, and the high-speed operation can be achieved at the same time. ^ Display device with level conversion circuit with small area effect. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 312308 · 丨 丨 丨 丨 丨 丨 Order · 丨 丨 丨 丨 丨 丨 (Please read the precautions on the back before filling this page) 8 1238600 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the Invention (9) According to one aspect of the present invention, a level conversion circuit is provided which includes a first transistor, a second transistor, and a control unit; The first transistor system is connected to the first receiving the i-th potential! Between the node and the two points of rotation; the second transistor system is connected between the second node and the output node receiving a second potential different from the first potential; the control unit receives the first input signal, and Controlling the conduction state of the first transistor and the second transistor separately, and controlling the degree of the conduction state of the first transistor and the second transistor corresponding to the level of the first input signal . In the level conversion circuit, the i-th transistor and the second transistor are controlled to be in a conducting state simultaneously by the control unit, and the i-th transistor is controlled according to the level of the first input signal. Degree of conduction with the second transistor. This increases or decreases the potential of the output node corresponding to the level of the i-th input signal. In this case, the potential of the output node is changed by controlling the degree of the conduction state between the first transistor and the second transistor that are always kept on, so even if the voltage amplitude of the i-th input signal is smaller than the first transistor It can also operate with the threshold voltage value of the second transistor. In addition, even if the threshold voltage of the first transistor and the second transistor greatly deviate from the design value, the action ratio of the potential change of the output node can accurately correspond to the action ratio of the first input signal. In this way, even if the threshold voltage value of the transistor deviates from the design value due to the disorder in the manufacturing process, the operation can be correctly generated. In addition, because the degree of conduction between the first transistor and the second transistor, which constantly maintains the conduction state, is controlled, the electric power of the output node is changed. ------ (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 9 312308 1238600 A7 V. Description of invention (10) Therefore, it can meet the requirements of high-speed operation. At the same time, as the high-speed operation is required, the excessive period of the potential level of the output node is shortened. (Please read the note on the back before filling this page.) Therefore, the period of through-current flow will be shortened. This reduces the power consumption. In addition, even if the voltage amplitude of the first input signal is small, a circuit for shifting the level is not required, so that the effect of reducing the area can be achieved. The first input 彳 g may be changed by a voltage amplitude smaller than a potential difference between the i-th potential and the second potential. In this case, the potential of the output node will change according to a voltage amplitude greater than the voltage amplitude of the first input signal. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the first and second levels of the first input signal system change; the first transistor system, the first conductive channel type electric field effect transistor, and the second transistor system. 2 conductive channel-type electric field effect transistor; the control unit sets the absolute value of the difference between the first potential and the gate potential of the first conductive channel-type transistor at the threshold voltage of the first conductive channel-type transistor The absolute value of the absolute value of the second conductive channel transistor and the absolute value of the difference between the gate potential of the second conductive channel transistor and the absolute value of the threshold voltage of the second conductive channel transistor According to the first level and the second level of the first input signal, the gate potential of the first conductive channel transistor and the gate potential of the second conductive channel transistor are set. In this case, the absolute value of the difference between the gate potential of the first conductive channel transistor and the gate potential of the first conductive channel transistor is greater than the absolute value of the threshold voltage value of the first conductive channel transistor. The i-th conductive channel-type transistor often remains on. In addition, the difference between the second potential and the paper size is subject to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1238600 A7 V. Description of the invention (11 2 The difference in the gate potential of the conductive channel transistor The absolute value is in a manner above the absolute value of the threshold voltage value of the second conductive channel type transistor, so that the second conductive channel type transistor always remains on. (Please read the note on the back? Matters before filling in this In this way, even when the threshold voltage value of the transistor deviates from the design value, it can reliably produce operation, and can achieve high-speed operation, low power consumption, and small area. At the same time, the first potential Is a positive potential, and the second potential may be a positive potential lower than the first potential, or a ground potential or a negative potential. In this case, because the first transistor and the second transistor are always kept on Mole-shaped mole, so the current flows from the node 丨 through the transistor 丨 and the second transistor to the node 2. The second potential can be changed to the ^ level and the complement of the 丨 input signal. 2 level 2nd input letter In this case, the i-th and second levels of the first input signal and the second round-in signal will be lower than the! Potential, and when the i-th input signal forms the first level, the The second input signal forms the second level, and printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. When the first input signal forms the second level, the second round of input signals forms the first level. The conductive channel-type electric field effect transistor system has a first threshold voltage value of the ιp channel-type electric field effect transistor; the second conductive channel-type electric field effect transistor has a second threshold voltage value of the ln-channel type electric field effect transistor Crystal; the control system is to set the inter-electrode potential of the first channel-type electric field effect transistor from the first potential to a low range above the absolute value of the first threshold value, and the first channel-type electric field effect The gate potential of the transistor is from the second paper scale to the Zhongguanjia Standard (CNS) A4 specification 〇〇 297 公 爱 7 312308 1238600 Α7 Β7 V. Description of the invention (12) The potential is set to the absolute value of the second threshold voltage Within the high range above the value. In this case, The lp channel type electric field effect transistor gate potential is set in a low range from the first potential to the absolute value of the first threshold voltage value, and the lp channel type electric field effect transistor will always remain on. When When the gate potential of the 1P channel-type electric field effect transistor falls within a range of this range, the lp channel-type electric field effect transistor exhibits a weak conduction state, and conversely, when the lp channel-type electric field effect When the gate potential of the transistor is at a low level within this range, the Ip-channel-type electric-field-effect transistor has a strong conduction state. In addition, the first η-channel-type electric-field-effect transistor gate is also turned on. The potential is set from the second potential to a high range above the absolute value of the second threshold voltage value, and the In-channel field-effect transistor will always maintain the on state. When the gate potential of the In-channel type electric field effect transistor is at a low level within the range, the 111th channel-type electric field effect transistor has a weak conduction state, and conversely, when the ln-channel type electric field effect When the gate potential of the transistor is at a high level within this range, the ln channel-type electric field effect transistor has a strong conduction state. The control unit includes a 2p channel-type electric field effect transistor, a 2n channel-type electric field effect transistor, and a control circuit. The source of the 2p channel-type electric field effect transistor receives an i-th potential, and the The gate and drain of the 2p-channel field-effect transistor are connected to the gate of the lp-channel field-effect transistor; the source of the 2n-channel field-effect transistor receives the first input signal or The second potential, and the gate and the drain of the 2ll channel-type electric field effect transistor are connected to the ln channel type (please read the precautions on the back before filling this page) I Jp · ϋ ϋ mmat · n meme 1 a_li ϋ I · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to the Chinese National Standard (CNS) A4 (21 × 297 mm) 12 312308 1238600 A7 V. Description of the invention (l3) Electric field effect transistor The control circuit is corresponding to the level of the first input signal and controls the drain potential of the 2p-channel field-effect transistor and the drain potential of the 2n-channel field-effect transistorIn this case, the gate potential of the lp-channel field-effect transistor is set to a lower range than the absolute value of the first threshold voltage value from the first potential by using the second-p-channel field-effect transistor. At the same time, the 2eta channel-type electric field effect transistor is also used to set the gate potential of the u-channel type electric field effect transistor from the second potential to a rising range that is greater than the absolute value of the second threshold voltage value. In addition, the gate potential of the 1P channel type electric field effect transistor is also controlled by the control circuit within the above range, and the gate potential of the In channel type electric field effect transistor is controlled within the above range. • The control circuit may also include the first load element and the second load element '. Among them, one end of the first load element receives the first! Input signal, and the other load of the first load element is connected to the closed pole of the ip-channel type electric field effect transistor; and one end of the second load element receives the first! And the other end of the second load element is connected to the gate of the ^ th channel field effect transistor. In this case, 'corresponding to the level of the first input signal, the level of the 帛 lp channel-type electric field effect transistor is controlled by the first and negative elements, and the gate of the transistor is controlled by the second load element. Pole potential. The first channel-type electric field effect 2 This structure t, because the level changes ㈣㈣_ ^ ^, can achieve the effect of small area ^ Fu

---------- 110 Μ --------------- (Please read the notes on the back before filling this page) 312308 A7 B7 1238600 V. Description of the invention (14 ) Each of the first load element and the second load element may be an electric field effect transistor or a resistance element. In this case, the electric field effect transistor or the resistance element can control the closed electrode potential of the lp channel type electric field effect transistor and the gate potential of the ln channel type electric field effect transistor. The control unit may further go further, and include the ancient ^^ 3P channel type electric field effect transistor and the 3n channel type electric field effect transistor; wherein, the source of the external channel type electric field effect transistor, Lanji & na, _ closed pole and drain are connected to the / primary pole, wheel-out node of the 2p channel-type electric field effect transistor and the drain of the 2p channel-type electric field effect transistor, respectively, and the 3n channel type The source and gate discs of the electric% effect transistor are not * * The two poles and poles are connected to the source and wheel of the 2η channel type electric% effect transistor and the 2η channel. Type electric field effect transistor on the drain. In this case, even when the difference between the first and the second electric potentials π li Λ 电位 and the second potential is small, the lp channel-type electric field effect φ ^, the dual response electric sun body, and the The In channel chirped% effect transistor can also function correctly. It is turned on, so that it can be driven at a low voltage. The control unit can also include the 2n channel type electric field effect transistor on page ^ ^ 3, where the second input signal of the h channel electric field effect transistor is received. Or the second potential, the gate of the crystal is connected to the intermediate electrode of the… channel-type electrical% effect transistor. The “control circuit” corresponds to the level of the first input signal and controls the first ln. The interpolarity, potential of the channel-type electric field effect transistor and the drain of the "^^ electric field effect transistor ... This paper ruler_ 财 _ ^^^^^ 7 ^ 717

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V. Description of the invention (1S) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In this case, the control circuit is used to set the gate potential of the first p-channel field-effect transistor to the i-th potential. Within the lower limit of the absolute value of the limit voltage value. At the same time, the gate potential of the In channel-type electric field effect transistor is also set by the second potential within the rising range above the absolute value of the second threshold voltage value using the 2n channel-type electric field effect transistor. In addition, the gate potential of the lp-channel type electric field effect transistor is controlled within the above range by the control circuit, and the gate potential of the ln channel-type electric field effect transistor is controlled within the above range. The control circuit may also include an i-th load element, a second load element, and a third load element; the first! One end of the load element receives the first potential, and the other end of the i-th load element is connected to the gate of the 0-channel type field effect transistor; one end of the second load element receives the first input signal or The second potential, and the other end of the σ μ coin 2 element is connected to the gate of the lp-channel field-effect transistor and one end of the third load element receives the third potential and the third element The other end is connected to the ln channel type = pole. In this case, the gate of the transistor is controlled by the load element and the second load element according to the level of the fourth input signal, and the gate potential of the " P-channel electric field crystal is controlled by the load element and the second load element. The gate potential of the third negative-electron-family electric channel-type electric field effect transistor. In this structure, the level conversion circuit is integrated, so it can achieve the effect of small area. Each of the first load element, the second load element, | ------ --_, and the third load element constructed with 6 elements. This paper size applies the Zhongguanjia Standard (CNS) A4 specification (210 X 297). 3— 312308 IIIIIIJ in --— It · — —--- II (Please read the notes on the back before filling this page) 15

1238600 V. Description of the invention (16) It can also be an electric field effect transistor or a resistance element. In this case, the gate potential of the Ip channel type electric field effect transistor and the interelectrode potential of the upper channel type electric field response transistor can be made by an electric field effect transistor or a resistor element. The level conversion circuit can also go further and include a blocking circuit. = The blocking circuit will be in the transition period from the first input signal to the first level 'the Ding /, Le 2 level. A circuit in which the node is blocked by the J-th transistor and the second electric solar body, and the current path of 々α to the point 2 卽 is blocked. In this case, since no current flows through the first transistor and the second transistor during the transition period between the first and second levels of the input signal, it is possible to prevent the current from flowing through. The power consumption caused is increased, so it can reduce the power consumption even further. The first transistor, the second transistor, and the control unit may be composed of a single crystal, a polycrystal, or an amorphous semiconductor on an insulating substrate. In this case, a level conversion circuit may be formed by a SOI (Silic0n on Insurat0r) device (dev㈣). According to another aspect of the present invention, a semiconductor device is provided, which includes a special circuit and a level connected to the specific circuit. A conversion circuit; wherein the level conversion circuit includes a first transistor, a second transistor, and an eight control neighbor, and the i-th transistor system is connected between the i-th node and the output node that receive the potential ; The second transistor system is connected between a second node and an output node that receive a second potential that is different from the f 1 potential; the control P system receives the i-th input signal and controls the i-th transistor and the The second electric = both are in a conducting state, and correspond to the paper size of the first input letter 剌 ψϋϋ ^ Νί5) Α4 size (2lG x 297 public ^ — -_ 312308 -lr ^ w ------- -^ --------- (Please read the note on the back? Matters before filling out this page) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 16 1238600 A7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs- --------______ B7_ V. Invent the level of 5 tigers' and control the The degree of conduction between the 1 transistor and the 2 transistor. The specific circuit refers to a complex logic circuit including an operation according to different power supply voltages. * The level conversion circuit can also be connected to the complex logic circuits. In this case, even in a semiconductor device provided with a plurality of logic circuits that operate according to different power supply voltages, even in the case where the threshold voltage values of the transistors are scattered widely during the manufacturing process, it can still be confirmed. The specific circuit can also include internal circuits provided on the chip and external circuits provided on the chip, and the level conversion circuit This internal circuit is connected to an external circuit. / In this case, in a semiconductor device having an internal circuit provided on the wafer and an external circuit provided on the wafer, even in the manufacturing process, the threshold of the transistor In the case of large voltage value dispersion, it can still operate reliably, and achieve high-speed operation, low power consumption and small area. The specific circuit may also include a semiconductor memory provided on the chip and a logic circuit provided on the chip, and the level conversion circuit is connected between the semiconductor memory and the logic circuit. In this case, 'mixed on the chip' In a semiconductor device having a semiconductor memory and a logic circuit, even in the case where the threshold voltage values of the transistor are scattered widely during the manufacturing process, it can still operate reliably, achieving high-speed operation, low power consumption, and The effect of small area. Specific circuits can also contain multiple detectors, multiple selection transistors, this paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 public love) 312308 (Please read the precautions on the back first (Fill in this page again) Assembling ---- Ordering ------------ 17 1238600 V. Description of the invention (ι〇 and peripheral circuits; among them, the selection uses a transistor system to select any one of the testers Use; the peripheral circuit is through a plurality of pianos. Those who wait for the plural detection to drive the plural debt detectors; and the level converter = select the transistor signal to perform the level conversion and provide it to the peripheral circuit. ㈣ In this specific case, 'in a semiconductor device having a plurality of selection transistors and semiconductor devices', it is possible to perform a reliable operation even if the value of the electrical conversion circuit is scattered during the manufacturing process. The effect of low voltage and low power consumption and small area. Web capture action, another layout of the present invention is to provide a display device that is an i-number display element, a plurality of selection transistors, a peripheral circuit, and a ^ 2 circuit; wherein, the selection transistor system is used to select these complex numbers. Any one of them; the peripheral circuit is used to move the complex detectors through a plurality of selection crystals; the level conversion circuit is to convert the special level and provide it to the peripheral circuit; and the level is changed It includes a first transistor, a second transistor, and a control unit, wherein the one transistor system is connected between the first node and the output node receiving the first potential; the second transistor system is connected to a different receiver Between the 2nd node and the output node of the * potential of the 1st potential 'The control unit receives the 2nd node! The input signal 'controls both the first transistor and the second transistor to be in a conductive state', and controls the first transistor and the second transistor according to the level of the first input signal. Degree of continuity. Under the situation of the second system, even in the display device with a plurality of selection transistors and level conversion circuits, even in the manufacturing process, the threshold value of the transistor is still relatively large. High-speed motion, t-scale is applicable to China 18

I 312308 1238600 A7 V. Description of the invention (19) The effect of low power consumption and small area. The plurality of display elements may also be liquid crystal elements; and the plurality of liquid crystal elements, the plurality of selection transistors, peripheral circuits, and level conversion circuits may also be formed on an insulating substrate. In this case, even in the manufacturing process, the threshold voltage value of the transistor is scattered and can still be reliably operated, and it can achieve high-speed operation, low power consumption, and small area. Liquid crystal display device. The plurality of display elements may also be organic electroluminescence elements; and the plurality of organic electroluminescence elements, the plurality of selection transistors, peripheral circuits, and level conversion circuits may also be formed in On an insulated substrate. In this case, even in the case where the threshold voltage of the transistor is scattered in the manufacturing process, it can still operate reliably, and it can achieve high-speed operation, low power consumption, and small area. Electromechanical excitation light device. The plurality of selection transistors and the first and second transistors of the level conversion circuit may be composed of thin film transistors. In this case, even in the case where the threshold voltage of the transistor is scattered widely during the manufacturing process, it can still operate reliably, and it can achieve the functions of ancient speed operation, low power consumption and small area. Display device. [Brief Description of the Drawings] Fig. 1 is a circuit diagram of a level conversion circuit in the first embodiment of the present invention. Fig. 2 is a diagram showing an example of a range of acquisition of the point potentials at the points 3 and 3 and the potential at the second node in the level conversion circuit shown in Fig. 1. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 312308 1238600

Fig. 3 is a diagram showing an example of a range of obtaining the potential of the first node and the potential of the second node in the level shift circuit shown in Fig. 1. Example of the acquisition range of the potential of the first node and the potential of the second node in the level conversion circuit shown in Fig. 1 Fig. 5 is an example of the operation of the level conversion circuit shown in Fig. 1 as a graph. The circuit diagram of the first example of the circuit configuration of the level conversion circuit shown in FIG. 6 and FIG. Fig. 7 is a circuit diagram of a second example of the circuit configuration of the level conversion circuit shown in Fig. 1. Fig. 8 is a circuit diagram of a third example of the circuit configuration of the level conversion circuit shown in Fig. 1. Fig. 9 is a circuit diagram of a fourth example of the circuit configuration of the level conversion circuit shown in Fig. 1. Fig. 10 is a circuit diagram of a fifth example of the circuit configuration of the level conversion circuit shown in Fig. 1. Fig. 11 is a circuit diagram of a sixth example of the circuit configuration of the level conversion circuit shown in Fig. 1. Fig. 2 is a circuit diagram of a level conversion circuit structure of the second embodiment of the present invention. Fig. 13 is a circuit diagram of a level conversion circuit structure of the third embodiment of the present invention. Figure 14 is a circuit diagram of the level conversion circuit structure of the fourth embodiment of the present invention. 0 This paper size is applicable to the Chinese National Standard (CNS) A4 specification ⑽χ 29? Meal. Page) Install ------II Order! Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

1238600 A7 B7 V. Description of the invention (21) The circuit diagram of the first example of the circuit structure of the level conversion circuit shown in Fig. 15 and Fig. 14 (Please read the precautions on the back before filling out this page) The circuit diagram of the second example of the circuit structure of the level conversion circuit shown in Figure 16 and Figure 14 The circuit diagram of the third example of the circuit configuration of the level conversion circuit shown in Fig. 17 and Fig. 14. Fig. 18 is a circuit diagram showing a configuration of a level conversion circuit according to a fifth embodiment of the present invention. Fig. 19 is a circuit diagram showing a configuration of a level conversion circuit according to a sixth embodiment of the present invention. Fig. 20 is a voltage waveform diagram of an example of the level conversion circuit in Fig. 19; Fig. 21 is a circuit diagram of a circuit configuration of an analog level conversion circuit. Figures 22 (A) and (B) are the voltage waveforms of the simulation results using the entire silicon transistor. Figures 23 (A) and (B) are graphs of voltage waveforms printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Electricity, using the simulation results of polycrystalline stone transistors.

Figures 24 (A) and (B) are the voltage waveform diagrams of the simulation results when the threshold voltage values of the p-channel MOSFET and the n-channel MOSFET are less than the set value.

Figures 25 (A) and (B) are simulation result voltage waveform diagrams when the threshold voltage values of the ρ-channel MOSFET and η-channel mqsfeT are set. Figures 26 (A) and (B) are the simulation results of the electric dust waveform when the threshold voltage value of the ρ-channel MOSFET and η-channel MOSFET is greater than the set value. ~ 丨 丨 丨 丨 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 312308 21 1238600 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (22) Figure 27 It is a circuit diagram of a level conversion circuit structure of a seventh embodiment of the present invention. Fig. 28 is a circuit diagram of a specific configuration example of the level conversion circuit of Fig. 27. Fig. 29 is a circuit diagram showing a configuration of a level conversion circuit according to an eighth embodiment of the present invention. Fig. 30 is a circuit diagram showing a configuration of a level conversion circuit according to a ninth embodiment of the present invention. Fig. 31 is a circuit diagram showing a structure of a level conversion circuit according to a tenth embodiment of the present invention. Fig. 32 is a circuit diagram showing a configuration of a level conversion circuit according to an eleventh embodiment of the present invention. Fig. 33 is a circuit diagram showing a configuration of a level conversion circuit according to a twelfth embodiment of the present invention. Fig. 34 is a circuit diagram showing the structure of a level conversion circuit according to the 13th embodiment of the present invention. Fig. 35 is a circuit diagram showing a configuration of a level conversion circuit according to a fourteenth embodiment of the present invention. Fig. 36 is a block diagram of a first example of a semiconductor device using a level conversion circuit of the present invention. Fig. 37 is a block diagram of a second example of a semiconductor device using a level conversion circuit of the present invention. Fig. 38 is a block diagram of a third example of a semiconductor device using a level conversion circuit of the present invention. ----------- Loading -------- Order ---------. (Please read the notes on the back before filling this page) This paper size is applicable to China Standard (CNS) A4 specification (210 x 297 mm) 22 312308 1238600 A7 V. Description of the invention (23) Figure 39 is a block diagram of a fourth example of a semiconductor device using the level conversion circuit of the present invention. Fig. 40 is a block diagram of an example of a liquid crystal display device using a level conversion circuit of the present invention. Figure 41 is a square-filled diagram of the voltage conversion circuit structure of the liquid crystal display device shown in Figure 40. Fig. 42 is a block diagram of an example of an organic EL device using the level conversion circuit of the present invention. Fig. 43 is a schematic cross-sectional view showing an example of a level conversion circuit according to the present invention using an SOI element. Fig. 44 is a block diagram of an example of a detector device using the level conversion circuit of the present invention. Fig. 45 is a circuit diagram of a first example of a known level conversion circuit. Fig. 46 is a circuit diagram of a second example of a known level conversion circuit. 4 to 7 are circuit diagrams of a third example of a known level conversion circuit. Fig. 48 is a circuit diagram of a fourth example of a known level conversion circuit. [Symbol description] 800 level conversion circuit 801,802 p channel m〇sfet 803,804 n channel m 0 SFET VDD power supply voltage N11, N12 round out node CLK1, CLK2 round in signal Vout output voltage Vtn threshold voltage value 810 bits Quasi conversion circuit 811 bias circuit

812 P-channel MOSFET 813 11-channel MOSFET 13 output node CLK input signal This paper size is applicable to China ^^ (CNS) A4 specification (21〇x 297 public love ^ ^ 23 (Please read the note on the back first? Matters before filling in (This page) · ϋ I ϋ 1 n H ϋ ^ -rOJ · n mm — I nn 1 1 < Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 312308 1238600 A7 B7 V. Description of the Invention (24)

Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, printed clothing, 820 level conversion circuits, 821 positioning circuits, 822 current mirror amplifiers, 831, 832 p-channel MOSFETs, 833,834 η-channel MOSFETs, N14.N15 output nodes, CLK1, CLK2 input signals, N15 output nodes, 840 bits Quasi-conversion circuit 841 Positioning circuit 842 PMOS cross-coupled amplifier 851,852 p-channel MOSFET 853,854 η-channel MOSFET N16, N17 output node N16, N17 output node CLK1, CLK2 Input signal 1 Level conversion circuit 10 Control unit 20 Exciter 3 Inverter 100 control circuit 101 p-channel MOSFET 102 η-channel MOSFET 201 p-channel MOSFET 202 η-channel MOSFET 11, 12 input node NP first node NN second node CLK1, CLK2 input signal VDD power potential NO output node NP first node Vtp threshold Voltage value Vtn Threshold voltage value VI Level 1 V2 Level 2 GND Ground potential V3 Level 3 VOUT Output potential 103 η Channel MOSFET 104 p Channel MOSFET 105 η Channel MOSFET 106 p Channel MOSFET ------ --- J 1_1 · Outfit -------- Order -------- (Please read the back first Note to note? Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 24 312308 A7 1238600 ____B7 V. Description of the invention (25) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 201 p-channel MOSFET 202 η-channel MOSFET R1 Resistive element R2 Resistive element Vee Negative potential 100a Control circuit R3 Resistive element R4 Resistive element CON Control signal 贯穿 Through-current blocking period 10A, 10B Control unit 20A.20B Exciter 30 PMOS cross-coupling type inching Amplifiers 301,302 p-channel MOSFETs 303,304 η-channel MOSFETs Ν01, Ν02 Output nodes ΝΟΑ, ΝΟΒ Output nodes la Level conversion circuits VOUTl, VOUT2 Output potential VDD Power potential 12 Input nodes 303,304 η Channel MOSFET 31 Current mirror amplifier 311,312 p-channel MOSFET 313,314 η channel MOSFET N01, N02 output nodes N03, N04 output nodes 3A, 3B inverter 5A, 5B inverter 500 chip 501 logic circuit 502 logic circuit 510 chip 511 logic circuit 512 logic circuit 513,514 logic circuit 1B , 1C, 1D level conversion circuit 520 chip 521 logic circuit This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 25 312308 (Please read the note on the back first? Please fill in this page for more information) Ί ti -------- ^ -------- 1238600 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (26) 520 Chip 521 Logic circuit 522 Logic circuit 530 Chip 531 Logic circuit 532 External circuit 540 Glass substrate Υ1, Υ2, · _ .., Yn Scan electrode χ1, χ2, .. .., Xm Data electrode 542 Liquid crystal element 541 Thin film transistor 543 Scan line drive circuit 544 Data driving circuit 600 Voltage conversion circuit 601 Boost power supply circuit 602 Negative voltage power supply circuit 1G, 1H, 1I, 1J Level conversion circuit 550 Glass substrate 551 Thin film transistor 552 Organic EL device 700 Voltage conversion circuit 570 Si (silicon) substrate 571 Insulating film 572 Silicon layer 573 P-type region 574 n-type region 575 Gate 580 Glass substrate 581 Thin film transistor 582 Detector device 583 Scan line driving circuit 584 Data driving circuit 710 Voltage conversion circuit 585 External control circuit Best Mode] FIG. 1 is a circuit diagram showing the structure of a level conversion circuit in the first embodiment of the present invention. In the first figure, the level conversion circuit 1 is provided with a control unit 10, an excitation ---------, 1-1 · installation -------- order ------- -(Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 26 312308 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1238600 A7 B7 V. Description of the invention (π) a driver 20, an inverter 3; The control unit 10 includes a control circuit 100, a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 101, and an n-channel MOSFET 102. The exciter 20 includes a P-channel MOSFET 201 and an n-channel MOSFET 202. The inverter 3 includes a CMOS circuit composed of a P-channel MOSFET and an n-channel MOSFET. The control circuit 100 of the control unit 10 is connected to the input nodes II, 12, the first node NP and the second node NN. The input nodes 11 and 12 are respectively provided with input signals CLK1 and CLK2 which are changed into complementary high and low levels. The source of the p-channel MOSFET 101 is connected to a power terminal receiving a power supply potential VDD, and the gate and the drain are connected to a first input node NP. The source of the n-channel MOSFET 102 is connected to the input node 11, and the gate and the drain are connected to the second input node NN. In the exciter 20, the source of the p-channel MOSFET 201 is connected to the power terminal receiving the power supply potential VDD, the drain is connected to the output node NO, and the gate is connected to the first node NP. The source of the n-channel MOSFET 202 is connected to the input node 12, the drain is connected to the output node NO, and the gate is connected to the second node NN. The potential difference between the high and low levels of the input signals CLK1 and CLK2 is smaller than the potential difference between the power supply potential VDD and the ground potential. In this embodiment, the low level of the input signals CLK1 and CLK2 is the ground potential, and the high level criterion is the potential between the power supply potential VDD and the ground potential. The control circuit 100 responds to the input signals CLK1 and CLK2 and controls the potential VNN of the first node NP and the second node NN. Electricity of Node 1 NP ----------- Order ---------. (Please read the precautions on the back before filling this page) The scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 27 312308 1238600 A7 B7 V. Description of the invention (28) Bit VNP is set by the power supply potential VDD to the threshold voltage value Vtp of the p-channel MOSFET101 Lower level above absolute value. The potential VNN of the second node NN is set to a rising level above the absolute value of the threshold voltage value Vtn of the n-channel MOSFET 102 by the lowering level of the input signal CLK1. The source potential of the n-channel MOSFET 102 is the level of the input signal CLK1. In this way, one of the ρ-channel MOSFET 201 and the η-channel MOSFET 202 is in a strong conducting state, and the other is in a weak conducting state, so that one of the ρ-channel MOSFET 201 and the η-channel MOSFET 202 of the exciter 20 is caused. Does not close completely. For example, when the p-channel MOSFET 201 is in a strong on-state, the n-channel MOSFET 202 is in a weak on-state. As a result, the on-resistance value of the p-channel MOSFET 201 will be smaller than the on-resistance value of the n-channel MOSFET 202. As a result, the output potential Vout of the output node NO will become high. Conversely, when the n-channel MOSFET 202 is in a strong on-state, the p-channel MOSFET 201 is in a weak on-state. As a result, the on-resistance value of the n-channel MOSFET 202 will be smaller than the on-resistance value of the p-channel MOSFET 201. As a result, the output potential Vout of the output node NO will become low. The inverter 3 converts the output potential Vout into an output potential VOUT for changing the power supply potential VDD and the ground potential. 2, 3 and 4 are schematic diagrams of examples of ranges that can be obtained from the potential VNP of the first node NP and the potential VNN of the second node NN in the level conversion circuit 1 of FIG. 1. As shown in Figures 2 to 4, the P-scale of the NP potential obtained at the first node is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 28 312308 (Please read the note on the back first? Matters (Fill in this page again) Packing -------- Order ---------. Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1238600 A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the Invention (29) The range is between the first level VI lowered from the power supply potential VDD to the threshold voltage value Vtp of the p-channel MOSFET 101 and the second level V2 lower than the first level VI. The second node NN potential VNN can be obtained between the third level V3 rising from the ground potential GND to the threshold voltage value Vtn of the n-channel MOSFET 102, and the fourth level V4 higher than the third level V3. . Figure 2 is a schematic diagram when the threshold voltage value Vtp of the p-channel MOSFET 101 and the threshold voltage value Vtn of the n-channel MOSFET 102 are relatively small. At this time, the potential VNP of the first node NP will be higher than the potential VNN of the second node NN, so that the current flowing to the p-channel MOSFET 201 and the n-channel MOSFET 202 of the exciter 20 becomes smaller. Therefore, the penetrating current in the exciter 20 will be relatively small, so that the operation speed becomes lower. Figure 3 shows the situation when the threshold voltage value Vtp of the p-channel MOSFET 101 and the threshold voltage value Vtn of the n-channel MOSFET 102 are slightly larger. At this time, the difference between the potential VNP of the first node NP and the potential VNN of the second node NN becomes smaller, so that the current flowing to the p-channel MOSFET 201 and the n-channel MOSFET 202 of the exciter 20 becomes a slightly larger value. Therefore, the penetrating current in the exciter 20 becomes slightly larger than the case shown in Fig. 2, and the operating speed becomes slightly higher than the case shown in Fig. 2. Figure 4 is a schematic diagram when the threshold voltage value Vtp of the p-channel MOSFET 101 and the threshold voltage value Vtn of the n-channel MOSFET 102 are relatively large. At this time, the potential VNP of the first node NP will be lower than that of the second node --------- install ------- order --------- (Please read the note on the back first Please fill in this page again for this matter) This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 29 312308 1238600 Α7 Β7 Printed clothing by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (3〇) NN The potential VNN causes the currents flowing to the p-channel MOSFET 201 and the n-channel MOSFET 202 of the exciter 20 to be relatively large. Therefore, the penetrating current in the exciter 20 will be relatively large, and the operating speed will be relatively fast. Fig. 5 is a radio wave pattern of an example of the operation of the level conversion circuit 1 of Fig. 1. The operation example of FIG. 5 corresponds to the case of FIG. 4, the potential VNP level of the first node NP is lower than the potential VNN level of the second node NN, and the low level of the potential VNP of the first node NP Low level higher than the potential VNN level of the second node NN. Therefore, in the operation example shown in Fig. 5, the through current in the exciter 20 will be relatively large, and the operation speed will be relatively fast. As shown in Fig. 5, the potential VNP of the first node NP and the potential VNN of the second node NN have the same change. When the input signal CLK1 forms a high level and the input signal CLK2 forms a low level, the potential VNP of the first node NP and the potential VNN of the second node NN will become high levels. As a result, the output potential VOUT becomes the ground potential GND. When the input signal CLK1 forms a low level and the input signal CLK2 forms a high level, the potential VNP of the first node NP and the potential VN1S [of the second node NN become low levels. As a result, the output potential VOUT becomes the power supply potential NDD. In the level conversion circuit 1 of this embodiment, the degree of the conduction state of the P-channel MOSFET 201 and the n-channel MOSFET 202 that constantly maintain the on-state is controlled. Therefore, even if the voltage amplitudes of the input signals CLK1 and CLK2 are smaller than the ρ-channel MOSFETs 201 and η Channel MOSFET202 ----------: —ί installed -------- order --------- (Please read the precautions on the back before filling this page) This paper size Under the application of the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 30 312308 1238600 A7 B7 V. Description of the invention (31) (Please read the precautions on the back before filling this page). Can also produce action. In addition, even when the threshold voltage values of the P-channel MOSFET 201 and the n-channel MOSFET 202 deviate greatly from the design values, an output potential Vout waveform corresponding to the level change of the input signals CLK1 and CLK2 can be obtained. With this, even if the threshold voltages of the P-channel MOSFET 201 and the n-channel MOSFET 202 are greatly deviated from the design due to the disorder in the manufacturing process, the operation can be surely performed. Fig. 6 is a circuit diagram of the first example of the circuit configuration of the level conversion circuit 1 in Fig. 1. As shown in FIG. 6, the control circuit 100 includes an n-channel MOSFET 103 and a p-channel MOSFET 104. The source of the N-channel MOSFET 103 is connected to the input node II, and the drain and gate are connected to the first node NP. The source of the p-channel MOSFET 104 is connected to the power terminal, the drain is connected to the second node NN, and the gate is connected to the input node 12. Therefore, the level conversion circuit 1 in the example shown in FIG. 6 is composed of 6 MOSFETs, so that the effect of reducing the area can be achieved. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Here, the threshold voltage value of the p-channel MOSFET 101 is Vtp, and the threshold voltage value of the n-channel MOSFET 102 is Vtn. In the manufacturing process, even if the threshold voltage value of the p-channel MOSFET and the threshold voltage value of the n-channel MOSFET are scattered in the quasi-conversion circuit 1, the P-channel MOSFET 101 is in the same level conversion circuit 1 The threshold voltage values of 104,201 will be the same, and the threshold voltage values of n-channel MOSFETs 102,103,202 will also be the same. This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 31 312308 1238600 A7 B7 V. Description of Invention (32) (Please read the precautions on the back before filling this page) The example shown in Figure 6 In the P-channel MOSFET 101 ′, the potential VNP of the first node NP is set to decrease from the power supply potential to an absolute value of the threshold voltage Vtp or higher, thereby keeping the P-channel MOSFET 201 always on. In addition, the n-channel MOSFET 102 is used to set the potential VNN of the second node NN to a level that rises from the ground potential to an absolute value of the threshold voltage Vtn or higher, so that the n-channel MOSFET 202 is always turned on. Corresponding to the level of the input signal CLK1, the n-channel MOSFET 103 is used to control the potential VNP of the first node NP to a high level or a low level. In addition, according to the level of the input signal CLK2, the potential VNN of the second node NN is controlled to a high level or a low level by the p-channel MOSFET 104. As a result, when one of the p-channel MOSFET 201 and the n-channel MOSFET 202 is in a strong conduction state, the other is in a weak on state. Fig. 7 is a circuit diagram of the second example of the circuit configuration of the level conversion circuit 1 of Fig. 1. The level conversion circuit 1 shown in FIG. 7 is printed by the employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is different from the level conversion circuit 1 in FIG. 6 in that the gate of the ρ channel MOSFET 104 of the control circuit 100 is Connected to the ground terminal. In this case, the p-channel MOSFET 104 often remains on, and has a load resistance function, so that the n-channel MOSFET 202 of the exciter 20 is always on. Corresponding to the level of the input signal CLK1, the potential VNN that controls the second node NN is at a high level or a low level, and the n-channel MOSFET 202 is in a strong or weak conduction state. The structure and operation of the other parts of the level conversion circuit 1 in FIG. 7 are in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm).

5. Description of the invention (33) The level conversion circuit i is as shown in FIG. The circuit diagram of the third example of the circuit configuration of the level conversion circuit i of the first diagram is not shown in FIG. (Please read the precautions on the back before filling this page) The level conversion circuit 1 shown in Figure 8 is different from the level conversion circuit 1 in Figure 7 in that the control circuit 100 replaces the p-channel MOSFET 104, Instead, it includes the point of the n-channel MOSFET 105. The source of the n-channel MOSFET 105 is connected to the second node NN, and the drain and gate are connected to the power terminal. In this case, the n-channel m0sfet105 always keeps the on-state, and has a load resistance effect, so that the n-channel MOSFET 202 of the exciter 20 is always on-state. Corresponding to the level of the input signal CLK1, the potential VNN controlling the second node NN is at a horse level or a low level, and the channel mSFET202 is in a strong or weak conduction state. The structure and operation of the other parts of the level conversion circuit 1 of FIG. 8 are the same as those of the level conversion circuit 1 of FIG. 6. Fig. 9 is a circuit diagram of a fourth example of the circuit configuration of the level conversion circuit 1 of Fig. 1. The level conversion circuit 1 shown in FIG. 9 is printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The difference from the level conversion circuit 1 shown in FIG. 6 is that the channel source of the ViOSFET 102 is connected to the ground terminal. on. In this case, the n-channel MOSFET 102 is used to set the potential vnN of the second node NN to a level higher than the threshold voltage Vtn absolute value caused by the ground potential rise, so that the ^ -channel MOSFET 202 of the exciter 20 is always turned on. . Corresponds to the level of the input signal CLK2, using the ρ channel This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 33 312308 1238600 A7 B7 V. Description of the invention (34) MOSFET104, which controls the second node NN The potential VNN is at a high level or a low level. The 俾 η channel M0SFET202 shows a strong conduction or a weak state (please read the precautions on the back before filling this page). The structure and operation of the other parts of the level conversion circuit 1 of FIG. 9 are the same as those of the level conversion circuit 1 of FIG. 6. Fig. 10 is a circuit diagram of a fifth example of the circuit configuration of the level conversion circuit 1 of Fig. 1. The level conversion circuit 1 shown in FIG. 10 is different from the level conversion circuit 1 in FIG. 6 in that the gate of the n-channel MOSFET 103 of the control circuit 100 is connected to the power supply terminal. In this case, the n-channel MOSFET 103 always maintains the on state and functions as a load resistor, corresponding to the level of the input signal CLK1, and controlling the potential vnp of the first node NP to a high level or a low level. Therefore, the p-channel MOSFET 201 of the exciter 20 is in a stronger or weaker conducting state. The structure and operation of the other parts of the level conversion circuit 1 of FIG. 10 are the same as those of the level conversion circuit i of FIG. 6. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 11 shows the circuit diagram of the sixth example of the circuit structure of the level conversion circuit 1 of Figure 1.

The level conversion circuit i shown in Fig. 11 is different from the level conversion circuit 1 in Fig. 6 in that the control circuit 100 uses a point composed of resistance elements R1 and R2. One end of the resistance element R1 is connected to the i-th node NP, and the other end is connected to the input node n. The resistor R2 is connected to the power terminal, and the other end is connected to the second node NN. In this case, corresponding to the level of the input signal clkI, the Jth

34 312308 1238600 B7 V. Description of the invention (35) The potential VNP control of the level NP is at a high level or the potential VNN control of the _ 2 level NN is at a high level or a low level. At the same time, the level conversion circuit of Fig. 11 is also changed! The other parts are related to the level conversion circuit in Figure 6! the same. . Figure 12 is a circuit diagram of the present invention 橥 2 眚 你 丨 > The level conversion circuit structure of the embodiment The level conversion circuit 1 shown in FIG. 12 is shown in FIG. 12. The level conversion circuit 1 in the picture of Le 1 is different in that the source of the η channel m0SFET2 02 of the exciter 20 is connected to the ground terminal. The level conversion circuit 1 in this embodiment In the second node and the potential VNN, the level of the input signal CLK1, CLK2 is set to a level that rises above the threshold voltage value vtn of the n-channel MOSFET 102. When the input signal CLK1 is at the low level, The potential VNN of the 2 node nn will rise from a low level to a level above the threshold voltage value vtn absolute value. At this time, the source of the n-channel MOSFET forms a ground potential, making the n-channel MOSFET 202 weaker. On state. When the input signal CLK1 is still high, the potential νNN of the second node NN rises from a high level to a level above the threshold voltage Vtn absolute value. In this case, the source of the n-channel MOSFET 202 is The ground potential is formed, so that the ^ channel MOSFET202 appears Strong on state. The structure and operation of the other parts of the level conversion circuit 1 of the second embodiment are the same as those of the level conversion circuit 1 of the first embodiment. Figure 13 shows the third embodiment of the present invention. Level conversion circuit structure 35 ♦ This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 public love) 312308 1238600 A7 s -----------__ 5. Circuit diagram of the description of the invention (36). Please read the precautions on the back before filling this page.) The level conversion circuit 1 shown in Figure 13 is different from the level conversion circuit 1 in Figure 1 in that the exciter 20 is the source of the channel MOSFET 202. Is connected to the power terminal that receives the negative potential Vee. In the level conversion circuit 1 of this embodiment, the potential VNN of the second node NN is set to the low level of the input signal CLK1 and rises to the threshold of the channel MOSFET 102 The voltage level Vtn is above the absolute value. § When the input j CLK number CLK1 is at a low level, the potential VNN 'of the second node NN will rise from the low level to the threshold voltage value Vtn absolute value. In this case, the n-channel MOSFET 202's The source develops a negative potential Vee, The channel MOSFET 202 is in a relatively weak conducting state. Conversely, when the input signal CLK1 is at a high level, the potential VNN of the second node NN will rise from the high level to the threshold voltage Vtn absolute value. In this case, the source of the n-channel MOSFET 202 A negative potential Vee is formed, thereby enabling the n-channel MOSFET 202 to be in a stronger conducting state. The rest of the level conversion circuit 1 in the third embodiment has the same structure and operation as the level conversion circuit 1 in the first embodiment. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. FIG. 14 is a circuit diagram showing a level conversion circuit structure of the fourth embodiment of the present invention. In the level conversion circuit χ shown in Fig. 14, the control unit includes a control circuit 100a and n channels] y [0SFET102. The control circuit 100a is connected to the input nodes 11 and 12, the first node NP and the second node NN. The input nodes 11 and 12 are connected to the first node NP and the second node NN. In the input nodes II, 12, like the level conversion circuit i of the first embodiment, this paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 meals) 36 312308

V. Description of the invention (37) 1238600 gives input signals CLK1 and CLK2 respectively. The source of the n-channel MOSFET 102 is connected to the input node 112, and the drain and gate are connected to the second node NN. In addition, the rest of the structure and operation of the level conversion circuit 1 shown in FIG. 14 are the same as the structure of the level conversion circuit 1 shown in FIG. The control circuit 100a controls the first node NP potential VNP and the second node NN potential VNN in response to the input signals CLK1 and CLK2. The potential VNP of the working node NP is set at a level between the power supply potential VDD and the level of the input signal CLK1 by using the control circuit 100a. In addition, the potential VNN of the second node NN rises from the low level of the input signal CLK1 to a level above the threshold voltage value vtn of the n-channel MOSFET 102. In this way, one of the p-channel MOSFET 201 and the n-channel MOSFET 202 of the exciter 20 is in a strong on state, and the other is in a weak on state. In this way, neither the p-channel mSFET20i of the exciter 20 nor the n-channel MOSFET 202 is turned off. The rest of the level conversion circuit of the fourth embodiment has the same structure and operation as those of the level conversion circuit 1 of the i-th embodiment. FIG. 15 is a circuit diagram of the first example of the level conversion circuit 1 of FIG. 14. As shown in FIG. 15, the control circuit 100a includes resistance elements R3, R4, and a p-channel MOSFET 104. One end of the resistance element R3 is connected to the power terminal, and the other end is connected to the node Np. Resistance element rule 4 6 ^ 钱 # 于 ^ 1 node NP, and the other end is connected to the turn-in node n This paper size applies-China National gIT ^ S) A4 size (210 x 297 public love 37 312308 ---- ------, 1- 丨 Installation -------- Order ---------. (Please read the phonetic on the back? Matters before filling out this page) Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative 1238600 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (38). The source of the p-channel MOSFET104 is connected to the power terminal, and the drain is connected to the second node NN. The pole is connected to the input node 12. In the example shown in FIG. 15, the potential VNP of the first node NP is set to a level between the power supply potential VDD and the level of the input signal CLK1 by using the resistance elements R3 and R4. The p-channel MOSFET 201 is always turned on. In addition, the n-channel MOSFET 102 is used to set the potential VNN of the second node NN to a level that rises from the ground potential to an absolute value of the threshold voltage Vtn, and the n-channel MOSFET 202 is always maintained. On state. The potential VNP of the first node NP corresponds to the level of the input signal CLK1. The control is at a high level or a low level. In addition, the potential VNN of the second node NN corresponds to the level of the input signals CLK1, CLK2, and the control is at a high or low level. As a result, the p-channel MOSFET 201 and the n-channel MOSFET 202 are controlled. When either one is in a strong conduction state, the other is in a weak conduction state. When the input signal CLK1 is in a low level state, the potential VNP of the first node NP is set to be between the power supply potential VDD and the input signal CLK1 The level between the low levels causes the p-channel MOSFET 201 to be in a strong on-state. In this case, the n-channel MOSFET 202 is in a strong on-state. Figure 16 shows the level conversion circuit 1 in Figure 14 The circuit diagram of the second example of the circuit configuration. The level conversion circuit 1 shown in FIG. 16 is different from the level conversion circuit 1 shown in FIG. 15 in that the other end of the resistance element R4 of the control circuit 100a is connected. To ground terminal.-丨 丨 丨 丨 丨 丨 丨 1,1 · • 丨 丨 丨 丨 丨 I —Order · 丨 丨 丨-丨 — 丨-. (Please read the precautions on the back before filling this page) This Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 38 312308 A7 1238600 _B7 V. Description of the invention (39) In this case, the potential VNN of the first node NP is fixed to a specific potential between the power supply potential VDD and the ground potential through the resistance elements R3 and R4, 俾The P-channel MOSFET 202 often remains on. When the n-channel MOSFET 202 is in a strong conducting state, the p-channel MOSFET 201 is in a weak conducting state. Conversely, when the n-channel MOSFET 202 is in a relatively weak on-state, the p-channel MOSFET 201 is in a relatively strong on-state. Fig. 17 is a circuit diagram of the third example of the circuit configuration of the level conversion circuit 1 of Fig. 14. The level conversion circuit 1 shown in FIG. 17 is different from the level conversion circuit 1 shown in FIG. 15 in that a p-channel MOSFET 106 is replaced in place of the resistance element R3 of the control circuit 100a. The source of the p-channel MOSFET 106 is connected to the power terminal, the drain is connected to the first node NP, and the gate is connected to the input node II. When the input signal CLK1 is in a high level state, the potential VNP of the first node NP becomes a high level, thereby making the p-channel MOSFET 201 in a weak on state. Conversely, when the input signal CLK1 is in a low level state, the potential VNP of the first node NP is at a low level, thereby making the p-channel MOSFET 201 in a strong on state. The level conversion circuit 1 of the first to fourth embodiments is An operation is generated in response to the input signals CLK1 and CLK2 which are complementary to each other. Then, the level conversion circuit 1 of the fifth embodiment shown is operated in response to a single input signal. Fig. 18 is a circuit diagram showing the structure of a level conversion circuit in the fifth embodiment of the present invention. --------- 1 — ^^ · Equipment -------- Order --------- (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau ’s Consumer Cooperatives applies the Chinese National Standard (CNS) A4 specification mo X 297 mm 39 39 312308 1238600 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7. 5. Description of the invention (*) Figure U The source of the control circuit 100 channel m0sfet103 is connected to the input node n that receives a single input signal clk, and the sum and gate are connected to the first node NP. The p-channel MOSFET 104 is connected to the second node NN, and the gate is connected to the ground. !! The source of the channel MOSFET 202 is connected to the ground terminal. The structure of the rest of the level conversion circuit 1 shown in Fig. 18 is the same as that of the level double conversion circuit 1 shown in Fig. 6. Fig. 19 is a circuit diagram showing the structure of a level conversion circuit in the sixth embodiment of the present invention. The configuration of the control unit in the level conversion circuit 1 shown in FIG. 19 is the same as that of the control unit 10 of the level conversion circuit j shown in FIG. In the exciter 20, a p-channel MOSFET 210 is connected between the source of the p-channel MOSFET 201 and the power terminal. The control signal cON is supplied to the gate of the P-channel MOSFET 210. The structure of the rest of the level conversion circuit i shown in Fig. 19 is the same as that of the level conversion circuit 1 shown in Fig. 6. Fig. 20 is a voltage waveform diagram showing an example of the operation of the level conversion circuit 1 of Fig. 19. As shown in Figure 20, the input signals Clk1 and CLK2 are complementary high and low levels. The output potential VOUT changes with a voltage amplitude greater than the voltage amplitude of the input signals CLK1, CLK2. The control system number CONT is in the high level state during the transition period between the input signals CLK1 and CLK2 between the high level and the low level. In other periods, the Chinese standard (CNS) A4 specification (210 X 297) applies. (Mm) 312308 I ΙΊ — III! — T — 11! —. (Please read the notes on the back before filling out this page) 1238600 Printed clothing A7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ______ _______ 5. Description of the invention ( 41) 'is at a low level. The period during which the control signal CON is in a high level state is referred to as a continuous current blocking period TH. During the through-current blocking period TH, the p-channel SFET2 () 1 is turned off, and the through-current flowing through the electric MOSFET + 0 and the n-channel MOSFET 202 is blocked. Therefore, the effect of reducing power consumption can be achieved. Here, a simulation test of the characteristics of the level conversion circuit of the present invention is performed. Figure 21 is a schematic diagram of the circuit structure of a level conversion circuit used in analog testing. The structure of the level conversion circuit i shown in FIG. 21 is the same as that of the level conversion circuit 1 shown in FIG. First, the high-speed operation of the level conversion circuit 1 in FIG. 21 will be investigated. Generally, in a transistor formed by bulk silicon, the threshold voltage value Vtp is (-0 · 9 ± 0.1) V, and the threshold voltage value vtn is (_〇7 ± ο · ι). ν. In addition, in a thin film transistor using polycrystalline silicon, the threshold voltage value Vtp is (-2 · 5 ± 1 to 1.5) V, and the threshold voltage value Vtn is (i.8 + i 丨 to 1.5) V. In this way, compared to transistors formed from monolithic silicon, thin film transistors using polycrystalline silicon will experience a more severe threshold voltage during the manufacturing process. FIG. 22 is a schematic diagram of the simulation test result when the level conversion circuit 1 is composed of a transistor formed of monolithic silicon. Set the frequency of the input signals CLK1 and CLK to 1 GHz, set the input voltage amplitude (oscillation amplitude of the input signals CLK1, CLK2) to 0.5 V, and set the output voltage amplitude (oscillation amplitude of the output potential VOUT) to 3.0 V. ---------- 1 ^ 1 * Packing -------- Order --------- (Please read the precautions on the back before filling this page) This paper size applies China National Standard (CNS) A4 specification (210 X 297 mm) 41 312308 1238600 A7 B7 V. Description of the invention (42) (Please read the precautions on the back before filling this page) Input shown in Figure 22 (A) Waveforms of signals CLK1, CLK2 and output potential VOUT. Figure 22 (B) shows waveforms of the potential VNP of the first node NP, the potential VNN of the second node NN, and the output potential VOUT of the output node NO. It is known from the simulation results in FIG. 22 that even at a high frequency such as 1 GHz, the output potential VOUT having an effective ratio of 50% can be obtained in response to the input signals CLK1 and CLK2. In this way, the level conversion circuit 1 composed of a transistor formed of monolithic silicon can achieve the effect of high-speed operation. Fig. 23 is a diagram showing a simulation test result when the level conversion circuit 1 is formed of a thin film transistor formed of polycrystalline silicon. The frequency of the input signals CLK1 and CLK2 is set to 20 MHz, the input voltage amplitude is set to 3.0V, and the output voltage amplitude is set to 12V. Figure 23 (A) shows the waveforms of the input signals CLK1, CLK2 and the output potential VOUT. Figure 23 (B) shows waveforms of the potential VNP of the first node NP, the potential VNN of the second node NN, and the output potential VOUT of the output node NO. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. According to the simulation results shown in Figure 23, even at a high frequency such as 20MHz, the output potential VOUT with a 50% effect ratio can be obtained in response to the input signals CLK1 and CLK2. In this way, even if the level conversion circuit 1 is composed of a thin film transistor formed of polycrystalline silicon, it can achieve the effect of high-speed operation. Secondly, for the case where the threshold voltage values of the p-channel MOSFET and the n-channel MOSFET of the level conversion circuit 1 are scattered, a voltage waveform simulation test is performed. In this simulation test, the paper size of the P channel of the level conversion circuit 1 is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 42 312308 1238600 A7 B7 V. Description of the invention (43) MOSFET communicates with η MOSFET is a thin film transistor made of polycrystalline silicon. The frequency of the input signals CLK1 and CLK2 is set to 2 MHz. (Please read the precautions on the back before filling this page.) Figure 24 shows the simulation results when the threshold voltage value of the ρ-channel MOSFET and η-channel MOSFET is lower than the set value. In the simulation results shown in Figure 24, the threshold voltage parameter (threshold voltage value) of the P-channel MOSFET is set to -2.0V, and the threshold voltage parameter (threshold voltage value) of the n-channel MOSFET is set to 1.3V. Figure 25 shows the simulation results when the threshold voltage values of the ρ-channel MOSFET and the η-channel MOSFET are set values. In the simulation result shown in Figure 25, the threshold voltage value parameter (threshold voltage value) of the p-channel MOSFET is set to -3.5V, and the threshold voltage value parameter (threshold voltage value) of the η-channel MOSFET is set It is 2.8V. Figure 26 is a schematic diagram of the simulation results when the threshold voltage values of the p-channel MOSFET and the n-channel MOSFET are higher than the set value. In the simulation results shown in Figure 26, the threshold voltage value parameter (threshold voltage value) of the p-channel MOSFET is set to -5.0V, and the threshold voltage value parameter (threshold voltage value) of the n-channel MOSFET is set to 4 · 3ν. According to the results of Figures 24, 25, and 26 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, even if the threshold voltage parameters of the ρ-channel MOSFET and the η-channel MOSFET deviate significantly from the set value, the response input is The signals CLK1 and CLK2 can also obtain an output potential VOUT with an effect ratio of 50%. Fig. 27 is a circuit diagram showing a configuration of a level conversion circuit in a seventh embodiment of the present invention. The level conversion circuit la shown in Figure 27 is equipped with 2 control units that are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 43 312308 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 44 1238600 A7 B7 V. Description of the invention (44) 10A, 10B, two exciters 20A, 20B, and a PMOS cross-coupling type micro-motion amplifier 30. The structures of the control sections 10A, 10B and the exciters 20A, 20B are the same as those of the control section 10 and the exciter 20 in the first to sixth embodiments. Among them, the input nodes 11 and 12 of the control unit 10A are respectively supplied with input signals CLK1 and CLK2, and the input nodes 11 and 12 of the control unit 10B are respectively supplied with input signals CLK2 and CLK1. 0 are provided to the n-channel MOSFETs 03 of the exciters 20A and 20B. Source, which supplies a specific potential VEE. The specific potential VEE means a positive potential, a ground potential, a negative potential, a clock signal CLK1, or a clock signal CLK2 which is lower than the power supply potential VDD. The micro-amplifier 30 series contains ρ-channel MOSFETs 301, 302, and η-channel MOSFET3 03, 3 04 〇ρ-channel MOSFET3 01, 302 The source is connected to the power terminal, and the drain is connected to the output nodes NO 1, N02, gate The system is cross-connected to the output nodes N01, N02. The sources of the N-channel MOSFETs 3 03 and 04 are supplied with a specific potential VEE, and their gates are connected to the output nodes NOA and NOB of the exciters 20A and 20B, respectively. In the level conversion circuit 1a of this embodiment, the micro-amplifier 30 outputs the output potentials VOUT1, VOUT2 which are complementary to each other. The output potentials VOUT1 and VOUT2 change between the power supply potential VDD and the ground potential. Fig. 28 is a circuit diagram showing a specific configuration example of the level conversion circuit la of Fig. 27. In Fig. 28, the structure of the control sections i0a, 10B is the same as the 6th paper size, which applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 312308 ---------- lr ^ w Μ -------- Order --------- line (please read the precautions on the back before filling this page) 1238600 Printed by Employee Consumer Cooperative of Intellectual Property Bureau of Ministry of Economic Affairs 45 A7 B7 5. Description of the invention (45) The structure of the control section 10 in the figure. The source of the n-channel MOSFET 202 of the control section 10A10B is connected to the input node 12. The source of the n-channel MOSFETs 03,304 of the micro-amplifier 30 is connected to the ground terminal. Fig. 29 is a circuit diagram showing a configuration of a level conversion circuit according to an eighth embodiment of the present invention. The level conversion circuit iB in FIG. 29 differs from the level conversion circuit la in FIG. 27 in that instead of the structure connected to the PM0s cross-coupling type micro-motion amplifier 30, a structure connected to the current mirror type amplifier 31 is used instead. . The current mirror amplifier 31 includes p-channel MOSFETs 311 and 312 and n-channel MOSFETs 313 and 314. The sources of the p-channel MOSFETs 3 1 and 3 12 are connected to the power supply terminals, the drain is connected to the output nodes N03 and N04, and the gate is connected to the output node no 03. A specific potential VEE is supplied to the sources of the N-channel MOSFETs 3, 3, 14 and the drains thereof are respectively connected to the output nodes No. 3 and No. 4, and the gates are respectively connected to the output nodes of the exciters 20A, 20B. On N02. In the level conversion circuit lb of this embodiment, an output potential νουτ is output from the output node No4 of the current mirror type amplifier 31. The output potential VOUT changes between the power supply potential VDD and the ground potential. Fig. 30 is a circuit diagram showing a configuration of a level conversion circuit according to a ninth embodiment of the present invention. In the level conversion circuit u in FIG. 30, a plurality of PMos cross-coupling type micro-motion amplifiers 30 are connected between the output nodes NOA and NOB of the exciter 20α2β. The structure of the rest of the level conversion circuit u in Fig. 30 is the same as that of the level conversion circuit u in Fig. 27. Applicable in this paper standard _ Tsukazumi Standard (CNS) A4 specification ⑽χ 297 Public hair 312308 Μ -------- ^ -------- (Please read the precautions on the back before filling this page) Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau 1238600 A7 B7 V. Explanation of the invention (46) In the level conversion circuit lc of this embodiment, the output nodes N01 and N02 of the plurality of micro-motion amplifiers 30 output complementary output potentials V 〇UT1, VOUT2. The output potentials VOUTl and VOUT2 change between the power supply potential VDD and the ground potential. Fig. 31 is a circuit diagram showing the structure of a level conversion circuit according to the tenth embodiment of the present invention. The level conversion circuit Id in Fig. 31 belongs to a dual type level conversion circuit. The level conversion circuit Id in FIG. 31 includes two control sections 10A, 10B, two exciters 20A, 20B, and two inverters 3A, 3B. The structures of the control units 10A and 10B are the same as those of the control unit 10 shown in FIG. The structures of the exciters 20A and 20B are the same as those of the exciter 20 shown in FIG. The gate of the p-channel MOSFET 104 of the control unit 10A, the source of the n-channel MOSFET 202 of the exciter 20A, the source of the n-channel MOSFET 102 of the control unit 10B, and the source of the n-channel MOSFET 103 of the control unit 10B are connected to the receiving clock. Signal CLK1 is at input node IA. The source of the n-channel MOSFET 102 of the control section 10A, the gate of the n-channel MOSFET 103 of the control section 10A, and the source of the n-channel MOSFET 202 of the exciter 20B are connected to the input node IB that receives the clock signal CLK2. In addition, the output nodes NOA, NOB of the exciters 20A, 20B are connected to the inverters 3A, 3B, respectively. The inverters 3 A, 3B output output potentials VOUT1, VOUT2 which are complementary to each other. The output potentials VOUT1 and VOUT2 change between the power supply potential VDD and the ground potential. Thereby, the level conversion circuit Id shown in Fig. 31 performs complementary operations. ^ The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 46 312308-丨 丨 丨 丨 丨-丨 If— · • 丨-丨 丨 11 Orders 丨-丨 丨 --- (Please (Read the precautions on the back before filling this page) 1238600 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 47 A7 B7 V. Description of the invention (47 Figure 32 shows the structure of the level conversion circuit of the nth embodiment of the present invention Circuit diagram. The level conversion circuit u in FIG. 32 belongs to the dual type ^ phase adjustment type level conversion circuit. The level conversion circuit in FIG. 32 is different from the level conversion circuit ld in FIG. 31 in that: The output node of the exciter 20A: NTOA and the output node of the exciter 20B are connected in opposite directions to each other for phase adjustment; a pair of inverters 5A, 5B are used for adjustment. The level conversion circuit le in this embodiment In the use of inverters 5 A and 5B, the output potentials of the nodes NOA and NOB can be made consistent. Thus, even in the manufacturing process, the threshold voltage values of the MOSFETs are scattered. In more severe cases, the phase shifts of the output potentials ν〇υτι and ν〇υτ can also be reduced. Fig. 33 is a circuit diagram showing the structure of a level conversion circuit in the twelfth embodiment of the present invention. The level conversion circuit in Fig. 33 is a low voltage drive type level conversion circuit. The level in Fig. 33 The conversion circuit lf is different from the level conversion circuit 1 in FIG. 6 in that the control unit 10 further includes a p-channel MOSFET 105 and an n-channel MOSFET 106. The source of the p-channel MOSFET 105 is connected to the power terminal, and the gate Is connected to the output node NO, and the drain is connected to the node Nρ. ^ The source of the channel MOSFET 106 is connected to the input node η, and the gate is connected to the output node NO, and the drain is connected to the second node ΝΝ As described above, in the level conversion circuit 1 in FIG. 6, the gate potentials of the P-channel MOSFET 201 and the n-channel MOSFET 202 of the exciter 20 are applied to the Chinese standard (CNS) A4 specification 〇χ297. (Public love) 312308 I--I--IIIJ Κ- -------- ^ «— — — — — — 1 —. (Please read the note on the back? Matters before filling out this page) 1238600 A7 B7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau Explanation (40) is shifted to the threshold voltage values Vtp of the P-channel MOSFET 101 and the threshold voltage value Vtn of the n-channel MOSFET 102 in the control unit 10, respectively. With this, the threshold voltage value of the MOSFET is made even by the manufacturing process When the shift phenomenon occurs in the dispersion phenomenon, the p-channel MOSFET 201 and the n-channel MOSFET 202 can also operate reliably. However, when the power supply potential VDD decreases and the design value is largely deviated due to the disorder in the manufacturing process, the p-channel MOSFET 201 and the n-channel MOSFET 202 of the exciter 20 will fail to operate. In the level conversion circuit If in this embodiment, in order to avoid such a phenomenon, a p-channel MOSFET 105 and an n-channel MOSFET 106 are designed. As described above, the obtainable range of the output potential Vout of the output node NO is larger than the obtainable range of the potential VNP of the first node NP and the obtainable range of the potential VNN of the second node NN. In other words, the accessible range of the gate potential of the p-channel MOSFET 101 and the gate potential of the n-channel MOSFET 102 is larger than the obtainable range of the output potential Vout of the output node NO. In this way, the gate potential of the p-channel MOSFET 105 and the gate potential of the n-channel MOSFET 106 can oscillate in a larger range than the potential VNP of the first node NP and the potential VNN of the second node NN. Therefore, the p-channel MOSFET 105 and the n-channel MOSFET 106 are in a strong on state. As a result, the potential VNP of the first node NP and the potential VNN of the second node NN are not affected by the threshold voltage value of the p-channel MOSFET 101 and the threshold voltage value of the n-channel MOSFET 102. Therefore, the level conversion circuit If shown in FIG. 33 can be sure even if the power supply potential VDD is low and the dispersion in the manufacturing process is serious. ------ Order -------- (Please read the notes on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 48 312308 1238600 A7 Fifth, the action of invention description (49). Fig. 34 is a circuit diagram showing a level shifting structure in the thirteenth embodiment of Daishen Zanyue of the present invention. Section 34® + # 进 磁 4 么 二, Circuits The level conversion circuit lg of Le 34 belongs to (Please read the precautions on the back before filling this page) Drive and dual level conversion circuits. The voltage-level conversion circuit lg of Fig. 34 is different from the level conversion circuit id of Fig. 31 in that the 'control unit 10A series further includes a p-channel MOSFET 1G5B and an n-channel mff1 () 6b. . In other words, the control units 10A and 10B have the same structure as the control unit ι0 in FIG. 33. In the level conversion circuit lg of this embodiment, the inverters 3A, 3B output the wheel output potentials VOUT1, VOUT2 which are complementary to each other, as in the level conversion circuit id 'in FIG. The output potential v〇UT1 v〇UT2 changes between the power supply potential VDD and the ground potential. This level conversion circuit can be operated like the level conversion circuit 1 £ shown in FIG. 33, even when the power supply potential VDD is low and the disorder in the manufacturing process is serious. FIG. 35 is a circuit diagram showing the structure of a level conversion circuit in the fourteenth embodiment of the present invention. The level conversion circuit lh in FIG. 35 is a level conversion circuit of a low voltage driving type, a dual type, and a phase adjustment type. The level conversion circuit of FIG. 35 is different from the level conversion circuit lg of FIG. 34 in that the output node NOA of the exciter 20A and the output node NOB of the exciter 20B are connected in opposite directions to each other for phase adjustment. One pair of inverters 5A, 5B. In the level conversion circuit 1 h of this embodiment, even in the case where the outgassing condition of the threshold voltage value of the MOSFET is severe in the manufacturing process, this paper size can be adapted to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 49 312308 1238600 A7 ----------- B7_________ V. Description of the invention (50) Phase shift phenomenon of low output potential VOUT1, VOUT2. At the same time, even when the power supply potential VDD is low, the operation can be reliably performed. Fig. 36 is a block diagram showing a first example of a semiconductor device using a level conversion circuit of the present invention. In the semiconductor device shown in FIG. 36, a logic circuit 501 operating at a power supply voltage of 2.5V, a logic circuit 502 operating at a power supply voltage of 33V, and a level conversion circuit 1A are mixed on a wafer 500. The level conversion circuit 1A converts the level of the 25V signal provided by the logic circuit 501 into a 3.3V signal and supplies it to the logic circuit 502. The level conversion circuit 1A uses any one of the level conversion circuits 1, 1 to 1h of the above-mentioned first to fourteenth embodiments. In this way, the semiconductor device shown in FIG. 36 can reliably operate even when the threshold voltage values of the p-channel MOSFET and the η-channel MOSFET are severely scattered during the manufacturing process. High-speed operation, low power consumption, and small area. Fig. 37 is a block diagram showing a second example of a semiconductor device using the level conversion circuit of the present invention. In the semiconductor device shown in FIG. 37, a logic circuit 511 operating at a power supply voltage of 1.2V, a logic circuit operating at a power supply voltage of 1.8V 512 ', and a logic circuit 513,514 operating at a power supply voltage are mixed on the chip 510. And level conversion circuits ib, 1C, 1D. The level conversion circuit 1B converts the 1.2V series signal provided by the logic circuit 511 into a 18V series signal and supplies it to the logic circuit 512. The level conversion circuit IC will be mentioned by logic circuit 512 (please read the precautions on the back before filling this page). -------- Order --------- · Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau ’s Consumer Cooperatives applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 50 312308 1238600 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economy A7 B7 V. Description of the invention (51) 1.8 V series signal, level conversion into 2 5V series signal? It is supplied to the logic circuit 514. This level conversion circuit 10 converts the 1.2V system signal provided by the logic circuit 5m to a level of 25V system signal and supplies it to the logic circuit 513. The level conversion circuits 1B, 1C, and 1D use any one of the level conversion circuits 1, 1 to 1 of the above-mentioned first to fourteenth embodiments. In this way, the semiconductor device shown in FIG. Η can reliably operate even when the threshold voltage values of the p-channel MOSFET and the η-channel MOSFET are severely scattered during the manufacturing process, and can reach the same time. High-speed operation, low power consumption, and small area. Fig. 38 is a block diagram showing a third example of a semiconductor device using the level conversion circuit of the present invention. In the semiconductor device shown in FIG. 38, a logic circuit 521 operating at a power supply voltage of 1.8V, a logic circuit 522 operating at a power supply voltage of 3.3V, and a level conversion circuit are mixed on a chip 520. Semiconductor memory 521 is such as DRAM (dynamic random access memory), SRam (static random access memory), FLASH (flash memory), FERAM (ferroelectric memory) and so on. The level conversion circuit 1E converts the level of the 1.8V system signal provided by the logic circuit 521 into a 3 3v system signal and supplies it to the logic circuit 522. The level conversion circuit 1E uses any one of the level conversion circuits 1, 1 to 1h of the first to 14th embodiments. In this way, even in the semiconductor device shown in FIG. 38, during the manufacturing process, the threshold voltage values of the p-channel MOSFET and the η-channel MOSFET have a severe scatter phenomenon, but also -1 ------- -· L -------- Order ·! (Please read the precautions on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × X 297 mm) 51 312308 1238600 A7 --------—— 口 7___ V. Description of the invention (52) The action can be surely generated, the same effect can be used to clean the ancient, hit the Dajian catch action, reduce power consumption, and reduce the area. Fig. 39 is a block diagram showing a fourth example of a semiconductor device using a level conversion circuit of the present invention. In the semiconductor device shown in Fig. 39, a logic circuit 531 operating at a power supply voltage of 2.5 V is formed inside a wafer. The internal circuit 531 is composed of a semiconductor element. The quasi-conversion power% 1F is level-converted by a logic circuit, such as a 2.5V system signal, into a 3 3v system signal, and is supplied to an external circuit 532 that operates with a power supply voltage of 3 · 3ν. The level conversion circuit 1F employs any one of the level conversion circuits 1, 1 to 1h of the above-mentioned first to fourteenth embodiments. In this way, the semiconductor device shown in FIG. 39 can reliably operate even when the threshold voltage values of the p-channel MOSFET and the η-channel MOSFET are severely scattered during the manufacturing process. It can achieve high-speed operation, low power consumption, and small area. Fig. 40 is a block diagram showing an example of a liquid crystal display device using a level conversion circuit of the present invention. In the liquid crystal display device of FIG. 40, a plurality of scanning electrodes Υ1, Υ25 ··, Υη, and a plurality of data electrodes χ1, χ2, ..., Xm are arranged on the glass substrate 5 40, and are arranged in an intersecting state. Among them, ^ and m are arbitrary integers. Liquid crystal elements 542 are respectively provided at the intersections of the plurality of scan electrodes Y1 to γη and the plurality of data electrodes XI to Xm using thin film transistors 541. The thin-film transistor 541 is, for example, a polycrystalline process that is performed on amorphous silicon by using laser annealing, and this paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 312308 (please (Please read the notes on the back before filling this page) Install i ------ Order --IIIII 1-Member of Intellectual Property Bureau of the Ministry of Economic Affairs ΗConsumer Cooperation Du Print 52 1238600 Employee Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Print A7 Five The invention (53) formed by the polycrystalline silicon obtained. In addition, on the glass substrate 540, a scanning line driving circuit 543, a data driving circuit 544, and a voltage conversion circuit 600 are provided. The scan electrodes γm to Υη are connected to the scan line driving circuit 543, and the data electrodes 2,2, ..., Xm are connected to the data driving circuit 544. The voltage conversion circuit 600 converts complementary basic small-amplitude clock signals supplied by the external control circuit 545 into levels of clock signals of different voltages, and provides them to the scanning line driving circuit 543 and the data driving circuit 544. Fig. 41 is a block diagram showing the structure of a voltage conversion circuit used in the liquid crystal display device shown in Fig. 40. In the voltage conversion circuit 600 shown in FIG. 41, a step-up power supply circuit 601, a negative voltage power supply circuit 602, and a level conversion circuit 1G, 1H, 1I, 1J are formed on a glass substrate 54 ′. The level conversion circuit 1 () supplies external power supply voltages of 8V and 3.3V. Here, the internal circuit 俦 篦 — Scanz drive circuit 543 and data drive circuit 544 shown in FIG.

The level conversion circuit 1G converts the basic clock signal 'level' supplied from the external control circuit of Figure 40A Dingtiandi 40 to a signal which changes in a range of '乂' and supplies it to the internal circuit and level conversion circuit. The level conversion circuit 1H is a signal supplied by the level change circuit. The signal supplied by the dry double conversion circuit 1G is based on the power supply voltage of the boost power supply circuit 601.

Electricity! The level is converted into a signal with a change of 0 to 12 V, and it is supplied to the internal thunder wide road and level conversion circuit 1Jq. The level conversion circuit II is a signal supplied by Wei Kang early conversion circuit ig. The voltage level of the negative power source of the circuit 602 is converted into a signal that changes in the range of -3 to 8V, and __ ^, ,, and ° are recognized in the internal circuit. This level change 'paper size applies Chinese National Standard (CNS) A4 specification 53 312308 -111 —I — Mi —I — ^ «— — — — 1 — 11 (Please read the precautions on the back before filling this page) 1238600 A7 V. Description of the invention (54) The switching circuit 1J converts the signal supplied by the level 辔 and + conversion circuit 1H according to the negative voltage level of the negative power supply circuit 002 into a signal ranging from -3 to 12V. , And supplied to the internal circuit. The level conversion circuit 1G m can be any of the level conversion circuits 1 u to 1h as in the first to fourteenth embodiments. In this way, even in the manufacturing process, when the threshold voltage values of the D-channel, P-channel MOSFET, and η-channel MOSFET generate a more severe scatter phenomenon, the operation can be reliably generated, and high-speed operation can be achieved at the same time. , Mn low power consumption, small area, and high precision. Fig. 42 is a block diagram showing an example of an organic EL device using the level conversion circuit of the present invention. In the organic device shown in FIG. 42, a plurality of scanning electrodes are formed on a glass substrate 55 °; ¾ νινο field electricity branches Υ1, Υ2, ··, Υη and a plurality of data electrodes X1, X2, ..., Xm And arranged in a cross state. At the intersections of the plurality of scanning electrodes Y1 to Y1 and the plurality of data electrodes XI to Xm, organic thin-film transistors 551 are respectively provided with the organic device ... The organic device 552 is formed by, for example, polycrystalline silicon obtained by subjecting an amorphous dream to a polycrystalline process, such as by laser annealing. In addition, on the glass substrate 550, a scanning line driving circuit 553, a data driving circuit 554, and a voltage conversion circuit 700 are provided. The scan electrodes γ1 to Yn are connected to the scan line driving circuit 553, and the data electrodes X1, X2, ..., Xm are connected to the data driving circuit 554. The voltage conversion circuit 700 is a small-amplitude basic clock signal that is complementary and changed by the external control circuit 555, and converts the level into a clock signal of different voltages, and refers to the paper size standard (CNS) A4 specification. G X 297 Public Love 312308 (Please read the precautions on the back before filling out this page) Ί Γ ------— It · —------- Printed by the Intellectual Property Bureau Staff Consumer Cooperatives 54 A7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 1238600 V. Description of the Invention (55) Provided for the scanning line drive circuit 553 and the data transfer & drive circuit 554. The structure of the voltage conversion circuit 700 is the same as the structure of the thunder line W / voltage conversion circuit 600 shown in FIG. 41. The voltage conversion circuit 700 series can use Rugao! s ί As any one of the level conversion circuits l, la to lh of the embodiments 1 to 14.蕻 士 | According to this method, the money EL device shown in FIG. 42 'can be reliably generated even when the threshold voltage values of the p-channel MosFET and the n-channel MOSFET are severely scattered during the manufacturing process. At the same time, it can achieve high-speed operation, low power consumption, small area, and high precision. Fig. 43 is a schematic cross-sectional view showing an example of a level conversion circuit using an SOI (SlllcON On Inui) device. In the SOI device shown in FIG. 43, an insulating film 571 is formed on a Si (silicon) substrate 57 and a silicon layer 572 of amorphous silicon, polycrystalline silicon, or single crystal silicon is formed on the insulating substrate 571. In the silicon layer 572, a plurality of pairs of p-type regions 573 and a plurality of pairs of n-type regions 574 are formed. Gate electrodes 575 are formed on each of the complex-pair ρ-type region 573 and the complex-pair n-type region 574. Thereby, the level conversion circuit 1 shown in Fig. 6 can be constructed using the SOI element. Furthermore, the level conversion circuit of the present invention is not limited to being formed using an SOI element, and can be formed using various semiconductor elements. Fig. 44 is a block diagram showing an example of a detector device using the level conversion circuit of the present invention. In the detector device of FIG. 44, a plurality of scanning electrodes Υ1, Υ2, ..., γη and a plurality of data electrodes are formed on a glass substrate 580 (please read the precautions on the back before filling this page) -install-- ------ Order · This paper size is applicable to China National Standard (CNS) A4 specification (21 × 297 mm) 55 312308 1238600 A7 B7 V. Description of the invention (56) (Please read the note on the back first? Matters Fill out this page again) xl, X2, ..., xm, and arranged in a cross state. In addition, instead of the glass substrate 580, a panel substrate made of plastic or the like may be used instead. Detector devices 582 are provided at the intersections of the plurality of scan electrodes Υ1 to Υη and the plurality of data electrodes 1 to 111, respectively, using thin film transistors 581. The thin fluorene transistor 5 8 1 is formed by using, for example, polycrystalline silicon obtained by subjecting amorphous silicon to polycrystallization by laser annealing. The picker 5 8 2 series can use, for example, a light receiving element. In this case, an image detector is constructed. Alternatively, the detector 582 may be a pressure detector that detects a pressure difference using a resistor or an electrostatic capacity. In this case, it constitutes a surface roughness detector that detects the roughness of the surface of the object, or a texture detection detector that detects patterns such as fingerprints. Printed by the Consumer Affairs Bureau of the Intellectual Property Office of the Ministry of Economic Affairs In addition, on the glass substrate 5 80, a scanning line driving circuit 5 83, a data driving circuit 584, and a voltage conversion circuit 71 are provided. The scan electrodes γι to Yn are connected to the scan line driving circuit 583, and the data electrodes χ1, χ2, ..., and χη are connected to the data driving circuit 584. The voltage conversion circuit 710 converts the complementary small amplitude basic clock signal supplied from the external control circuit 585 into a clock signal with a different voltage level, and provides it to the scan line drive circuit 583 and the data drive circuit 584. The structure of the voltage conversion circuit 710 is the same as that of the voltage conversion circuit 600 shown in FIG. 41. The voltage conversion circuit 710 can use any one of the level conversion circuits 1, 1 to 1h as in the i-th to 14th embodiments. In this way, the detector device shown in Figure 44 can be applied to this paper even if the threshold voltages of the p-channel MOSFET and n-channel MOSFET are severely scattered during the manufacturing process. National Standard (CNS) A4 Specification (210 X 297 Public Love) 56 312308

V. Description of the invention (57) 1238600 The action can be surely generated, and at the same time, it can achieve high capture and high precision. In addition, in the above-mentioned embodiment, although the voltage amplitude of an input signal CLK1, CLK2 is added from the cold, the level change when the output potential v0uT 掂 ^ ^ UUT amplitude The circuit structure will be described, but the level conversion circuit of the present invention can also receive input signals clK1, CLk2, such as a voltage amplitude change equal to the amplitude of the output potential VOUT (the potential difference between the power supply potential VDD and a specific potential VEE), or receive The input signals CLK1, CLK2, etc., are constructed in a manner such that the amplitude of the voltage is greater than the amplitude of the output potential VOUT. (Please read the notes on the back before filling out this page) II -------- ^ -------- The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies to Chinese national standards (CNS ) A4 size (210 X 297 mm) 57 312308

Claims (1)

1238600 A8 B8 CS D8 Member of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by Consumer Cooperative, patent application scope 1 · A level conversion circuit, which includes: a first transistor, connected to the first node and output that receives the first potential Between nodes; the second transistor is connected between the second node and the output node that receive a second potential different from the first potential, and the control unit receives the first input signal and controls the Both the first transistor and the second transistor are in a conducting state, and the degree of the conducting state of the first transistor and the second transistor are respectively controlled according to the level of the first input signal. 2. The level conversion circuit according to item 1 of the patent application range, wherein the first input signal changes with a voltage amplitude smaller than a potential difference between the first potential and the second potential. 3. The level conversion circuit according to item 1 in the scope of patent application, wherein the first input signal is changed between the first level and the second level; the first transistor system is a first conductive channel type electric field effect transistor The second transistor system second conductive channel type electric field effect transistor; the control unit is configured to make the absolute value of the difference between the first potential and the gate potential of the first conductive channel transistor in the first conductive The threshold value of the threshold voltage of the channel 漤 transistor is greater than the absolute value, and the absolute value of the difference between the second potential and the gate potential of the second conductive channel type transistor is equal to the threshold voltage of the second conductive channel type transistor. When the value is greater than the absolute value, the gate potential of the first conductive channel transistor and the gate of the second conductive channel transistor are set in response to the first level and the second level of the first input signal. Potential person. This paper size applies to Chinese National Standards (CNs) A4 specifications (210 X 297 mm) 58 312308 ------- 1 * " · Packing -------- Order ------- -(Please read the notes on the back before filling this page)! 238600 Α8 Β8 CS D8 Member of the Intellectual Property Office of the Ministry of Economic Affairs ΗConsumer Cooperation 枉 Printing 6. Application for patent scope 4, such as the level conversion circuit of the first scope of patent application Among them, the first! The potential is a positive potential, and the second potential is a positive potential lower than the first potential, or a ground potential or a negative potential. 5. For example, the level conversion circuit in the scope of the patent application, wherein the second potential is changed to a second input signal complementary to the first input signal and the second input signal of the second level. 6. The level conversion circuit according to item 4 of the scope of patent application, wherein, «1st conductive channel-type electric effect transistor is an lp channel-type electric field effect transistor with a first threshold value of electrical waste; the first The 2 conductive channel-type electric% effect transistor is an In-channel type electric-field-effect transistor having a second threshold voltage value; the control unit is configured to change the gate potential of the first channel-type electric-field-effect transistor by the first 1 potential is set to a low range above the absolute value of the threshold voltage, and the closed-electrode potential of the lnii channel-type electric field effect transistor is set by the second potential; ^ to the absolute value of the second threshold voltage Values in the high range. 7. The level conversion circuit according to item 6 of the scope of patent application, wherein the control unit includes a 2p channel type electric field effect transistor, a 2n channel type electric field effect transistor, and a control circuit; wherein the 2P The source of the channel-type electric-field-effect transistor receives the i-th potential, and the closed pole and the drain of the 2p-channel-type electric-field-effect transistor Zhao are connected to the gate of the lp-channel-type electric-field-effect transistor; the first The source plum of the 2n channel-type electric field effect transistor is to receive this book in time to close the house standard ¥ (CNS) A4 specification (21Q χ 297) ^ ----- ^ 312308. »1 Γ Aw ---- ---- ^ --------- (Please read the notes on the back before filling out this page) 1238600 Six ηδ cs D8 Employees ’cooperation in intellectual property bureau of the Ministry of Economic Affairs Du printed clothing application patent scope input 1 The gate of the signal or transistor is connected to the gate of the 211-channel type electric field effect transistor. The drain of the gate of the 211-channel type electric field effect transistor is connected to the 111-channel type electric field effect control circuit. Level of the 1st input signal, while controlling the drain of the 2n% effect transistor The potential is inferior to that of the channel-type electric field 8. As described in the patent application scope 7: Drain potential. The circuit system includes the level conversion circuit of the first term, wherein the control circuit is the first load and the second load element; among them, the Xi terminal] p terminal receives the first input signal, and: the other end of the thunder two component Is connected to the gate of the lp-channel type electric field effect transistor; the -end of the second load of 70 pieces receives the S 1 potential, and the other end of the second load of 70 pieces is connected to the In channel Type electric field effect transistor on the gate. 9. The level conversion circuit in item 8 of the scope of patent application, where each of the first load element and the second load element is an electric field effect transistor, or a resistance element. The quasi-transformation circuit, wherein the control unit further includes a 3p channel type electric field effect transistor and a 3n channel type electric field effect transistor; wherein the source, gate and The pole is connected to the source of the 2p-channel field-effect transistor, the output node, and the drain of the 2p-channel field-effect transistor; the paper size is in Chinese national standard eCNS) A4. (210 X 297 Gong 7 60 312308 (Please read the precautions on the back before filling this page) The scope of the patent application violates the source, gate, and drain of the 3n-channel field-effect transistor, which are respectively connected to the source wheel output node of the 2n-channel field-effect transistor and the 2m-channel field-effect transistor. On the drain of the crystal, such as patent application scope 6 Level conversion circuit, wherein the control unit includes a 2η-channel electric field effect transistor, and a control circuit, among which, 'The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed X's 2η-channel electric field effect transistor. The source receives the first input signal or the second potential, and the gate and the drain of the second n-channel type electric field transistor 2 are connected to the gate of the first channel-type electric field effect transistor; The control circuit controls the gate potential of the In channel electric field effect transistor and the drain potential of the 2n channel electric field effect transistor according to the level of the first input signal. 12 · 如The level conversion circuit of item u in the patent application scope, wherein the control circuit includes a first load element, a second load element, and a third load element; wherein one end of the first load element receives the first potential And the other end of the first load element is connected to the gate of the first ip-channel field-effect transistor; one end of the second load element receives the first input signal or the second potential, and the second negative The other end of the element is connected to the gate of the ip-channel field-effect transistor; and one end of the third load element receives the first potential, and the paper size is in accordance with China National Standard (CNS) A4. (21〇x 297 public love) 61 312308 (Please read the precautions on the back before filling this page) Install I ---- order -------- I I238600 6. The other end of the scope of the patent application is connected to the "channel-type electric field effect circuit 13. If the level conversion circuit of the 12th scope of the patent application, the first load element, the first ... 1", each of them is equal to $ 2 And the third load element with a% effect transistor, or a resistance element. No. 14, if the level conversion circuit of item 1 of the scope of patent application, there is a `` break circuit ''. The blocking circuit will be the transition between the first round of the signal and the second level: During this period, the first node passes the first transistor to the second transistor, and flows to the circuit that the second lightning current path is blocked. 15. The level conversion circuit according to item 1 of the scope of patent application, wherein the first transistor, the second transistor, and the control unit are single crystal, polycrystalline, or amorphous semiconductors on an insulating substrate. Constituted by. 'Semiconductor device, which is provided with a specific circuit and a level conversion circuit connected to the specific circuit; wherein the level conversion circuit includes an i-th transistor, a second body, and a control unit; and 9 The first transistor system is connected between the first node receiving the first potential and the output node; the second transistor system is connected between the second node receiving the second potential and the output node with different first electrical values The control unit receives the first input signal ′ and controls the first transistor and the second transistor to be in a conducting state, respectively, and at the same time, the level of the first input signal should be far away, And control the 1st electrical side and the paper size are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page). Installation ------- -Order -------- 1- Printed by Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Cooperatives 312308 1238600 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. Scope of patent application. 17. The semiconductor device according to item 16 of the patent application scope, wherein the circuit includes circuits produced according to different power supply voltages; and the complex logic of μ㈣, the level conversion circuit 'is connected to the complex logic. J 18 · If the semiconductor device of the 16th scope of the patent application, the specific circuit includes an internal circuit placed on the chip and an external circuit provided thereon; and Λ the level conversion circuit is connected to the internal circuit Between toilets. Fei Lu Road and the external circuit 19. For example, the semiconductor device under the scope of application for patent No. 16, wherein the circuit system includes; t: a semiconductor memory provided on the chip and a logic circuit provided on the chip; and the level The conversion circuit is connected between the semiconductor memory and the circuit. Λ 20 · If the semiconductor device of the 16th scope of the application for a patent, the special ... circuit includes a plurality of detectors, a plurality of selection transistors, and peripheral circuits; wherein the selection transistor system is used to select the plurality of debts The peripheral circuit is agitated by the plurality of detectors through the plurality of selected power consumption day and day waists; and this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 Mm) 63 312308 (Please read the precautions on the back before filling out this page) -------- Order · -------! · 1238600 The consumer property cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed and applied for patents to the peripheral circuits. Switching, and 21 · — a kind of display device, with crystal ", circuit, public quasi-change =: medium and plural select electricity to use Who: select to use electric crystal *, for the selection of these plural display elements Any one of the “peripheral circuits” is used to move the complex testers through the plurals; those who choose to use the “miscellaneous circuit” system to perform level conversion on the chirp signal and provide it to the peripheral circuits; the level conversion circuit includes There are a first transistor, a second transistor, and a control unit. Among them, the second transistor \ the first transistor 80 body 'is connected between the point ^ that receives the second potential and the output node; the second transistor The crystal is connected between the second node that receives the second potential of the first electric value and the output node; ^ The control unit receives the first input signal and controls the first transistor and the Both of the second transistors are in a conducting state, and at the same time, the degree of the conducting state of the first transistor and the second transistor is controlled according to the level of the first input signal. The display device of item 21, wherein the plurality of display elements are liquid crystal elements; and the plurality of display elements are liquid crystal elements; The liquid crystal element, a plurality of such electric crystal selection peripheral circuit, and the level converting circuit being formed on the insulating substrate by the Ke (Read Notes on the back and then fill the page) installed - This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 64 312308 1238600 A8 B8 CS D8 6. Application for patent scope 23 · If the patent application scope of the 21st display device, these multiple displays The element is an organic electroluminescent element; and the plurality of organic electroluminescent elements, the plurality of selection transistors, peripheral circuits, and level conversion circuits are formed on an insulating substrate. 24. The display device according to item 21 of the patent application, wherein the plurality of selection transistors and the first transistor and the second transistor of the level conversion circuit are formed by a thin film transistor. (Please read the notes on the back before filling this page) -------- Order · ------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs.