1237349 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種製作非揮發性記憶體之方法，尤指— 種製作SPVG SONOS型記憶體之方法。 【先前技術】 非揮發性記憶體由於具有不因電源供應中斷而造成儲 存資料遺失之特性，因此被廣泛使用。而依照單元記憶胞 儲存之為料位兀數’又可區分為早一位疋儲存（single-bit storage)非揮發性記憶體，例如^化物唯讀記憶體(Nitride Read_Only-Memory，簡稱為NROM)、金屬-氧化矽-氮化石夕 -氧化石夕·石夕型（Metal-Oxide-Nitride-Oxide-Silicon，簡稱為 MONOS)記憶體或秒-氧化珍-氮化發-氧化碎-秒型 (Silicon-Oxide_Nitride-Oxide-Silicon，簡稱為 SONOS)記憶 體’與雙位元儲存(dual-bit storage)非揮發性記憶體，例如 分離編程虛擬接地(split program virtual ground) SONOS 型 (簡稱為SPVG SONOS)記憶體或分離編程虛擬接地（spiit program virtual ground) MONOS 型（簡稱為 SPVG MONOS) 吕己憶體’其中SPVG SONOS型記憶體與SPVG MONOS型 °己憶體之單元記憶胞由於可儲存二位元之資訊，因此相較 於一般單一位元儲存非揮發性記憶體可儲存更大量的資 σ孔’已逐漸成為非揮發性記憶體之主流。 1237349 請參考第1圖與第2圖，第1圖與第2圖為一 SPVG SONOS型記憶體1〇之示意圖，其中第1圖為SpVGSONOS 型5己憶體10進行編程(programming)操作時之示意圖，第2 圖為SPVG SONOS型記憶體10進行抹除(erasing)操作時之 示意圖，且為清楚說明SPVG SONOS型記憶體10之結構 與運作原理，於第1圖與第2圖中僅顯示出單一記憶胞。 如第1圖所示，SPVG SONOS型記憶體10係形成於一 p 4摻雜井(p well)12上’其主要包含有一選擇閘極(seiect gate)14’以及二N型之埋入式位元線(buried bit line)位於 選擇閘極14相對侧邊之P型摻雜井12内，分別作為源極 16與汲極18。選擇閘極14與P型摻雜井12之間包含有一 閘極絕緣層20,而選擇閘極14上方則包含有一頂蓋層22。 此外，選擇閘極14之侧壁依序包含有一底氧化矽層24、 一氮化矽層20與一頂氧化矽層28，其中氮化矽層26係用 來作為捕捉電子或電洞的儲存媒介。另外，頂氧化矽層28 之上方則包含有一字元線30。 如第1圖所示，SPVG SONOS型記憶體1〇於進行編程 操作時係利用源極侧邊注入(source_sideinjecti〇n)機制，其 電壓操作為對字元線30施加一高正電壓，如6至9V之電 壓’對選擇閘極14施加一低正電壓，如lv，對源極18則 施加一正電壓，如4.5V，並使p型摻雜井12與汲極16之 1237349 電壓維持在0V。在此狀況下，穿越選擇閘極14下方通道 (channel)之電子會被捕捉並被侷陷於位於源極18之一侧之 氮化矽層26内（如圖中之箭號所示），藉此改變成不同之啟 始電壓（threshold voltage)，以達到儲存資料之功能。此外， 透過類似之反向電壓操作即可將電子侷陷於汲極16之一 侧之氮化矽層26内，以儲存另一位元之資料，形成雙位元 儲存記憶體。 如第2圖所示，當SPVGSONOS型記憶體10於進行抹 除操作時係利用帶對帶電洞注入（band-to-band hot hole injection)機制，其電壓操作為對字元線30施加一高負電 壓，如-6至-9V之電壓，對源極18則施加一正電壓，如 4.5V，將選擇閘極14之電壓低於啟始電壓，並使P型摻雜 井12與汲極16之電壓維持在0V。在此狀況下P型摻雜井 12中之電洞會注入源極18之一侧之氮化矽層26内並中和 侷陷於氮化矽層26内之電子，達到資料抹除之作用。此 外，侷陷於没極16之一侧之氮化石夕層26内之電子亦可利 用類似之電壓操作加以中和。 請參考第3圖至第6圖，第3圖至第6圖為習知製作 SPVG S0N0S型記憶體之方法示意圖，其中為方便說明， 圖中僅顯示出部分記憶胞。如第3圖所示，首先，提供— 半導體基底50 ’其包含有一 P型換雜井52，複數個選擇閑 1237349 極結構54形成於P型摻雜井52表面，且各選擇閘極結構 54由下至上依序包含有一閘極絕緣層56、一選擇閘極58 與一頂蓋層60，其中閘極絕緣層56係由一利用熱氧化製 程或沉積製程形成之氧化矽層構成，選擇閘極58係為一多 晶妙層，而頂蓋層60則為一氮化碎層或為一金屬碎化物 (polycide) 〇 如第4圖所示，接著於半導體基底50與選擇閘極結構 54之表面依序形成一底氧化砍層64、一氮化砍層66與一 頂氧化矽層68,以構成一氧化矽-氮化矽-氧化矽（0N0)之 複合介電層62。接著再於頂氧化矽層68之表面沉積一氧 化石夕層70，用以形成後續之犧牲侧壁子結構（sacrificial spacer)之用。 然後如第5圖所示，進行一回蝕刻製程，全面性地向下 蝕刻氧化矽層70以形成犧牲侧壁子結構72，並同時蝕穿 犧牲侧壁子結構72間之複合介電層62，直至半導體基底 50表面，以於各選擇閘極結構54之間的P型摻雜井52上 方形成一開口 74。接著再進行一離子佈植製程，經由各開 口 74進行離子佈植以於P型摻雜井52中形成複數個N型 摻雜區76，作為埋入式位元線之用。隨後再於頂氧化矽層 68與N型摻雜區76之表面全面沉積一絕緣層（圖未示），並 進行一回蝕刻製程以於各N型摻雜區7 6上方形成一阻擋膜 1237349 (bl〇Ckingfilm)78。如第6圖所示，進行一姓刻製程，去除 犧牲侧壁子結構72，最後再全面沉積一多晶矽層8〇，並利 用一微影暨银刻製程定義出字元線8〇，完成習知SpVG SONOS型記憶體之製作。 然而’前述習知製作SPVG s〇N〇s型記憶體之方法由 於係先形成複合介電層62後，再進行離子佈植製程以形成 N型摻雜區76,因此不但必須於形成N型摻雜區％之前， 先去除位於犧牲侧壁子結構72之間的複合介電層62，而 且亦須在形成子元線80之前先形成一阻擔膜78，或於去 除犧牲侧壁子結構72後再形成另一氧化矽層，以避免字元 線80與N型摻雜區（埋入式位元線)76形成短路，而使spVG SONOS型記憶體無法正常運作。再者，即使習知技術已利 用开>成阻擋膜78方式避免短路問題產生，但由於N型摻雜 區76上方之複合介電層62已不完整，或殘留蝕刻應力及 蝕刻均勻性等因素，因此造成SPVG SONOS型記憶體於進 行抹除操作時，字元線80與埋入式位元線需要更大的電壓 差，或各易發生漏電流的現象，如此一來極易導致字元線 與埋入式位元線產生随穿等情形，而導致Spvg SONOS型 記憶體之可靠度降低。 有鑑於此，申請人乃根據此等缺點及依據多年從事半導 1237349 體產業之相關經驗，悉心觀察且研究之，而提出改良之本 發明，以提升SPVG SONOS型記憶體之可靠度與良率。 【發明内容】 因此本發明之主要目的為提供一種製作SPVG SON〇s 型吕己丨思體之方法’以解決習知技術無法克服之難題。 為達上述目的，本發明之一較佳實施例提供一種製作 SPVG SONOS型記憶體之方法。首先，提供一半導體基底， 該半導體基底包含有至少一第一導電型式摻雜井位於該半 導體基底中，以及複數個平行且不相接觸之選擇閘極結構 位於該半導體基底之表面。接著於各該選擇閘極結構之相 對侧壁形成複數個犧牲側壁子結構(sacrificial spacer)，並利 用各該犧牲側壁子結構作為遮罩，進行—離子佈植製程， 以於各該選擇閘極結構之間的半導體基底中分別形成一第 一導電型式摻雜區。隨後去除該等犧牲侧壁子結構，並於 忒半導體基底與該選擇閘極結構表面形成一複合介電層。 最後於該複合介電層之表面形成複數個不相接觸且與各該 ^擇閘極結構正交之字元線。 為了使貝審查委員能更近一步了解本發明之特徵及1237349 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for making non-volatile memory, in particular-a method for making SPVG SONOS type memory. [Prior art] Non-volatile memory is widely used because it does not lose stored data due to power interruption. And according to the unit memory cell's storage level, it can be divided into single-bit storage non-volatile memory, such as Nitride Read_Only-Memory (NROM for short). ), Metal-Silicon Oxide-Nitride Stone Oxide-Oxide Stone-Silicon (Metal-Oxide-Nitride-Oxide-Silicon (abbreviated as MONOS)) (Silicon-Oxide_Nitride-Oxide-Silicon (SONOS for short)) Memory 'and dual-bit storage non-volatile memory, such as split program virtual ground SONOS (SPVG for short) SONOS) memory or separate program virtual ground MONOS type (SPVG MONOS for short) Lu Jiyi's' SPVG SONOS type memory and SPVG MONOS type memory cell can store two Bit information, so compared to the general single-bit storage non-volatile memory can store a larger amount of σ pores' has gradually become the mainstream of non-volatile memory. 1237349 Please refer to Figure 1 and Figure 2. Figures 1 and 2 are schematic diagrams of a SPVG SONOS type memory 10. Figure 1 shows the SpVGSONOS type 5 memory module 10 during programming operation. Schematic diagram, the second diagram is a schematic diagram of the erasing operation of the SPVG SONOS memory 10, and in order to clearly explain the structure and operating principle of the SPVG SONOS memory 10, only the first diagram and the second diagram are shown A single memory cell. As shown in Fig. 1, the SPVG SONOS type memory 10 is formed on a p 4 doped well 12 which mainly includes a selective gate 14 and a two N-type buried type. A buried bit line is located in the P-type doped well 12 on the opposite side of the selection gate 14 and serves as a source 16 and a drain 18, respectively. A gate insulating layer 20 is included between the selection gate 14 and the P-type doped well 12, and a cap layer 22 is included above the selection gate 14. In addition, the sidewall of the selection gate 14 includes a bottom silicon oxide layer 24, a silicon nitride layer 20, and a top silicon oxide layer 28 in this order. The silicon nitride layer 26 is used as a storage for capturing electrons or holes. medium. In addition, a word line 30 is included above the top silicon oxide layer 28. As shown in FIG. 1, the SPVG SONOS type memory 10 uses a source side injection (source_sideinjection) mechanism during programming operations, and its voltage operation is to apply a high positive voltage to the word line 30, such as 6 A voltage of 9V 'applies a low positive voltage to the selection gate 14, such as lv, and a positive voltage, such as 4.5V, to the source 18, and maintains the 1237349 voltage of the p-type doped well 12 and the drain 16 at 0V. Under this condition, the electrons passing through the channel under the selection gate 14 will be captured and trapped in the silicon nitride layer 26 on one side of the source 18 (as shown by the arrow in the figure). This is changed to different threshold voltages to achieve the function of storing data. In addition, through similar reverse voltage operation, the electronic circuit can be trapped in the silicon nitride layer 26 on one side of the drain 16 to store another bit of data and form a two-bit storage memory. As shown in FIG. 2, when the SPVGSONOS type memory 10 performs an erasing operation, a band-to-band hot hole injection mechanism is used. The voltage operation is to apply a high voltage to the word line 30. Negative voltage, such as -6 to -9V, applying a positive voltage to source 18, such as 4.5V, will select the voltage of gate 14 lower than the starting voltage, and make P-type doped well 12 and the drain The voltage of 16 is maintained at 0V. Under this condition, the holes in the P-type doped well 12 will be injected into the silicon nitride layer 26 on one side of the source 18 and neutralize the electrons trapped in the silicon nitride layer 26, thereby achieving the data erasure effect. In addition, electrons trapped in the nitride nitride layer 26 on one side of the electrode 16 can be neutralized by a similar voltage operation. Please refer to Fig. 3 to Fig. 6. Fig. 3 to Fig. 6 are the schematic diagrams of the conventional method for making SPVG S0N0S type memory. For the convenience of explanation, only part of the memory cells are shown in the figure. As shown in FIG. 3, first, a semiconductor substrate 50 ′ is provided. The semiconductor substrate 50 ′ includes a P-type doped well 52, a plurality of selective gate 1237349 pole structures 54 are formed on the surface of the P-type doped well 52, and each gate structure 54 is selected. From bottom to top, a gate insulating layer 56, a selective gate 58 and a cap layer 60 are included in order. The gate insulating layer 56 is composed of a silicon oxide layer formed by a thermal oxidation process or a deposition process. The electrode 58 is a polycrystalline layer, and the cap layer 60 is a nitrided layer or a polycide. As shown in FIG. 4, it is followed by the semiconductor substrate 50 and the selective gate structure 54. A bottom oxide layer 64, a nitride layer 66, and a silicon oxide layer 68 are sequentially formed on the surface to form a silicon oxide-silicon nitride-silicon oxide (0N0) composite dielectric layer 62. A silicon oxide layer 70 is then deposited on the surface of the top silicon oxide layer 68 to form a subsequent sacrificial spacer. Then, as shown in FIG. 5, an etching process is performed, and the silicon oxide layer 70 is etched down to form a sacrificial sidewall sub-structure 72, and the composite dielectric layer 62 between the sacrificial sidewall sub-structures 72 is etched at the same time. Up to the surface of the semiconductor substrate 50, an opening 74 is formed above the P-type doped well 52 between the selected gate structures 54. Next, an ion implantation process is performed. Ion implantation is performed through the openings 74 to form a plurality of N-type doped regions 76 in the P-type doped well 52 as buried bit lines. Subsequently, an insulating layer (not shown) is deposited on the surface of the top silicon oxide layer 68 and the N-type doped region 76, and an etching process is performed to form a barrier film 1237349 over each N-type doped region 76. (blO Ckingfilm) 78. As shown in FIG. 6, a lithography process is performed, the sacrificial sidewall substructure 72 is removed, and finally a polycrystalline silicon layer 80 is fully deposited, and a lithography and silver engraving process is used to define the character line 80 to complete the exercise. Know the production of SpVG SONOS memory. However, the aforementioned conventional method for making SPVG sonos memory is to first form a composite dielectric layer 62 and then perform an ion implantation process to form an N-type doped region 76, so it is not only necessary to form an N-type doped region 76. Before the doped region%, the composite dielectric layer 62 between the sacrificial sidewall substructures 72 is removed, and a resistive film 78 must be formed before the sub-line 80 is formed, or the sacrificial sidewall substructures are removed. After 72, another silicon oxide layer is formed to prevent the word line 80 from forming a short circuit with the N-type doped region (buried bit line) 76, so that the spVG SONOS type memory cannot operate normally. In addition, even though the conventional technology has used the method of forming a blocking film 78 to avoid the occurrence of a short circuit problem, the composite dielectric layer 62 above the N-type doped region 76 is incomplete, or residual etching stress and etching uniformity, etc. Because of this, when the SPVG SONOS type memory is being erased, the word line 80 and the embedded bit line need a larger voltage difference, or they are prone to leakage current, so it is very easy to cause the word Meta-wires and embedded bit-wires are subject to wear and so on, which reduces the reliability of Spvg SONOS memory. In view of this, the applicant based on these shortcomings and based on years of experience in the semiconductor 1237349 industry, carefully observed and researched, and proposed an improved invention to improve the reliability and yield of SPVG SONOS memory. . [Summary of the Invention] Therefore, the main purpose of the present invention is to provide a method for making SPVG SON0s Lu Ji 丨 thinking body 'in order to solve the problems that conventional techniques cannot overcome. To achieve the above object, a preferred embodiment of the present invention provides a method for making an SPVG SONOS type memory. First, a semiconductor substrate is provided. The semiconductor substrate includes at least one first conductive type doped well located in the semiconductor substrate, and a plurality of parallel and non-contact selective gate structures are located on a surface of the semiconductor substrate. Then, a plurality of sacrificial spacer sub-structures are formed on the opposite sidewalls of the selected gate structures, and the sacrificial sidewall sub-structures are used as a mask to perform an ion implantation process for each of the selected gates. A first conductive type doped region is formed in each of the semiconductor substrates between the structures. Subsequently, the sacrificial sidewall substructures are removed, and a composite dielectric layer is formed on the semiconductor substrate and the surface of the selected gate structure. Finally, a plurality of non-contacting word lines are formed on the surface of the composite dielectric layer and are orthogonal to each of the gate structures. In order to allow the review committee to further understand the features and