TWI233172B - Non-leaded semiconductor package and method of fabricating the same - Google Patents

Non-leaded semiconductor package and method of fabricating the same Download PDF

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Publication number
TWI233172B
TWI233172B TW092107461A TW92107461A TWI233172B TW I233172 B TWI233172 B TW I233172B TW 092107461 A TW092107461 A TW 092107461A TW 92107461 A TW92107461 A TW 92107461A TW I233172 B TWI233172 B TW I233172B
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Taiwan
Prior art keywords
patent application
scope
item
packaging process
semiconductor packaging
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TW092107461A
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English (en)
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TW200421502A (en
Inventor
Ke-Chuan Yang
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Siliconware Precision Industries Co Ltd
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Priority to TW092107461A priority Critical patent/TWI233172B/zh
Priority to US10/437,562 priority patent/US6774499B1/en
Publication of TW200421502A publication Critical patent/TW200421502A/zh
Application granted granted Critical
Publication of TWI233172B publication Critical patent/TWI233172B/zh

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    • H01L2924/181—Encapsulation
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Description

1233172 五、發明說明（1) ’ [發明所屬之技術領域] 本發明係有關於一種半導體封裝技術，特別是有關於 一種無接腳式半導體封裝結構及製程，其可用以製造無接 腳式之半導體封裝件，例如為無基座之四方扁平型無接腳 式（Carrierless Quad Flat No-lead, CQFN)封裝件。 [先前技術]
美國專利第 5, 8 3 0, 8 0 0號，，PACKAGING METHOD FOR A BALL GRID ARRAY INTEGRATED CIRCUIT WITHOUT UTILIZING A BASE PLATE ”揭露了一種無基座之四方扁平 型無接腳式（Carrierless Quad Flat No-lead，CQFN)半 導體封裝技術，其為半導體業界習用之一種晶片封裝技 術。第姻即顯示此習知之CQF断裝件的結構示意圖、。如 =IΛ CQFN封裝技#的特點在☆其中《外接電性接觸 底部S曰=计成突出於外緣的接腳，而係設計成非突出式之 中，即^ 術，rface Mount Technology)程序 印刷電:1 之底部••來將封裝# 10銲結ι外部之 上 （printed circuit board，PCB)上。 封裝技術一般係利用銲線丨2 (bonding 銲塾再且：Λ的晶#3 0於内部電性連接至外露之底ί 圖示）上 之cqfn封裝件通常係建構於金屬板（未 底部輝C片30安置於—金屬板的正面上，並ΐ 覆晶片屬板的…，並形成封裝膠體來Σ ~線、及輝墊。當除去金屬板後，銲墊 =
17214. ptd 第5頁 1233172 五、發明說明（2) ^ ^- m，底部 '然而當封裝件的厚度尺寸愈來愈小時，
I 以下時，由於銲線弧高的限制，現行之CQFN 封哀技術便難以再採用銲線技術來完成封裝此些厚度 J :的2裝件。半導體工業界因此需求_種新的CQFN封農 件何/、可不必採用銲線技術即可完成超薄型的CQFN封裝 [發明内容] 扭继if明之主要目的在於提供一種新的無接腳式半導體 子襄技t ’其可不必採用銲線技術來封裝晶片。 本發明之無接腳式半導體封裝結構及製程可用以 無i ϊ Τ ΐ之半導體封裝件，例如為無基座之四方扁‘型 件。 Carrierless Quad Flat No-lead，CQFN)封裝 採本ί:之無接腳式半導體封裝結構及製程的特點在於 序…該暫重配線路;支術來進行封裝程 形成無基板式之封；；載；：於t成製程之後將其剝除而 更適於用來封裝小^ t沾 技術則可較銲線技術 「〜 主化的晶片。 [貫施方式] 以下即配合所附 ， 腳式半導體封裝处槿月f式，詳細揭露說明本發明之無接 本發明之無接腳式丰i製程之實施例。於此些實施例中， 之四方扁平型i接腳=體封裝技術係例如用以製造無基座 N〇-lead，CQFNHiF Cvrierless Quad Flat 衣1千。此外，此處須注意的一點是，本
1233172 五、發明說明（3) 說明書中的圖式均為簡化之示意圖式，其僅係以示意方式 說明本發明之基本概念；因此其僅顯示與本發明有關之元 件，且所顯示之元件並非以實際實施時之數目、形狀、及 尺寸比例繪製；其實際實施時之數目、形狀、及尺寸比例 可為一種隨意性之設計選擇，且其元件佈局形態可能更為 複雜。 第一實施例（第1 A至1G圖） 請首先參閱第1 A圖，本發明之無接腳式半導體封裝技 術之第一實施例於製程上的初始步驟為預製一暫時性晶片 載具110，其材質可為銅或鋁，且其具有一正面110a和一 對向之背面1 1 0 b，且其正面11 0 a係預先經由佈局設計而劃 分出一中央之置晶區1 1 1和複數個外圍之外接區1 1 2。第1 B 圖之上視結構示意圖即顯示該暫時性晶片載具11 0之正面 1 1 0 a上的置晶區1 1 1和外接區1 1 2的佈局方式。 接著如第1 C圖所示，形成複數個銲墊1 2 0於該暫時性 晶片載具11 0的外接區1 1 2上，亦即每一個外接區1 1 2上形 成一個銲塾1 2 0。此些銲塾1 2 0的材質例如為銲錫、把、或 金。再將一晶片1 3 0安置於暫時性晶片載具1 1 0的置晶區 1 1 1上；其中該晶片1 3 0具有一正面1 3 0 a和一對向之背面 13 0b，且其正面1 3 0 a上形成有複數個電源及信號輸出入銲 墊1 3 1，而其背面1 3 Ob則係黏貼至暫時性晶片載具1 1 0的置 晶區 1 1 1上 ° 接著如第1 D圖所示，下一個步驟為覆蓋一電性絕緣層 1 4 0於暫時性晶片載具1 1 0的正面1 1 0 a和晶片1 3 0的正面
17214. ptd 第7頁 1233172 五、發明說明（4) 130a上，但曝露出外接區112上的銲墊ι2〇和晶片u〇上的 輸出入銲墊1 3 1。此電性絕緣層1 40的製程例如為首先進行 塗佈权序，藉以將一電性絕緣材料，例如為聚酿亞胺 (polyimide，PI)或苯環丁烯（benzoCyCi〇butene，bcB)， k佈於暫時性晶片載具Η 〇的所有正面1 1 〇 a和晶片1 3 〇的所 有正面1 30a上，亦即塗佈於整個半成品之封裝結構的上表 面’而後採用例如微影技術（1 i t h 〇 g r a p h y )來進行一選擇 性移除程序，用以將塗佈之電性絕緣材料中位於外接區 112上》的銲墊120和晶片13〇上的輸出入銲墊13丨上的部分移 除，藉此而曝露出外接區π 2上的銲墊1 2 〇和晶片1 3 〇上的 輸出入銲墊1 3 1。由於此處所採用的塗佈技術和 均為習知技術，因此以下將不對其細節步驟作進」步技;打 之說明。 ， 接著如第1Ε圖所示，下一個步驟為採用重配線路技術 (Redistribution Layer, RDL)來於該電性絕緣層14〇上形 成複數條重配線路層150,且其中各條重配線路層15〇係用 以將晶片130上的一個輸出入銲墊131電性連接至外接區 Π 2上的一個對應的銲墊1 20。此些重配線路層i 50的製°°程 例如^首先採用濺鍍技術或無電解式電鍍技術來進行一第 一覆蓋金屬程序，藉以將第一導電性金屬材料i 4丨，例如 為銅，鍍於所有外接區112上的銲墊12〇和晶片13〇上的 出入鲜墊131，再接進行一第二覆蓋金屬程序，藉以著以 電解電鍍技術將一第二導電性金屬材料i 4 2鍍於第一 性金屬材料141上；再接著例如採用微影技術來進行_選
第8頁 17214. ptd 1233172 五、發明說明（5) 擇性移除程序，藉以將鍍上之第一導電性金屬材料1 4 1和 第二導電性金屬材料1 4 2中的未預定部分移除，而移除部 分即作為前述之重配線路層1 5 0。由於此處所採用的錢鍍 技術、無電解式電鍍技術、和微影技術均為習知技術，因 此以下將不對其細節步驟作進一步詳細之說明。 此外，本發明之無接腳式半導體封裝結構中亦可選擇 性地加裝一散熱片（未於圖式中顯示），藉此而對晶片1 3 0 提供一散熱功能。 接著如第1 F圖所示，下一個步驟為為形成一封裝膠體 1 6 0於整個半成品之封裝結構的上表面，用以覆蓋住所有 的重配線路層1 5 0。接著進行一切割程序，其中係沿第1 F 圖所示之切割線A-A’和B-B’，亦即暫時性晶片載具1 1 0上 之外接區1 1 2的外緣，並同時將該暫時性晶片載具1 1 0剝 除，藉此而獲得如第1 G圖所示之個別的CQFN封裝件。於實 際應用上，此CQFN封裝件之底部的銲墊1 2 0即形成一種非 突出式的平面狀外部電性連接點，可藉該銲墊1 2 0來將該 CQFN封裝件電性連接至一外部的印刷電路板（未於圖式中 顯示）。 第二實施例（第2A至2(:圖） 第2A至2C圖為結構示意圖，其中顯示本發明之無接腳 式半導體封裝技術的第二實施例。請首先參閱第2A圖，本 發明之第二實施例的無接腳式半導體封裝製程中的初始步 驟為預製一暫時性晶片載具2 1 0，其具有一正面2 1 0 a和一 對向之背面2 1 0 b，且正面2 1 0 a係預先經由佈局設計而劃分
17214. ptd 第9頁 1233172 五、發明說明（6) 出一中央之置晶區2 1 1和複數個外圍之外接區2 1 2。 第二實施例與前述之第一實施例不同之處在於此處所 採用的暫時性晶片載具2 1 0係於其外接區2 1 2上形成凹狀銲 墊2 1 3。此些凹狀銲墊2 1 3的材質例如為銲錫、鈀、或金。 接著請參閱第2 B圖，接下來的製程步驟包括將一晶片 2 3 0安置於暫時性晶片載具2丨〇的置晶區2丨丨上、形成一電 性絕緣層240於暫時性晶片載具210的正面21〇咖晶片23〇 的正面2 3 0 a上、以及採用重配線路技術來於該電性絕緣層 上形成複數條重配線路層2 5 0。此些製程步驟的實施方 工、均與前述之第一實施例相同，因此於此將不對直作重複 之說明。 〃 妾μ著如第％圖所示，下一個步驟為為形成一封裝膠體 線路居%個半成ΐ之封裝結構上，用以覆蓋住所有的重配 片栽i ? 5 〇。接著進行一切割程序，並同時將該暫時性晶
封骏件。1 〇剝^除—’藉此而獲得如第2C圖所示之個別的CQFN 性接觸點於實際應用上，此CQFN封裝件之底部的凸塊狀電 由其來脉^ 5 1即形成一種突出式之外部電性連接點，可藉 (未於孩CQFN封裝件電性連接至一外部的印刷電路板 第=j式中顯示）。
〜，施例（第3圖） 實施ί ^圖^顯^示本發明之無接腳式半導體封裝技術的第三 施例包^ ; 之封裝件的剖面結構形態。如圖所示，此實 晶片3 3 個以堆豐方式封裝之晶片，包括一下層之第一 口上層之第二晶片43〇;其中下層之第一晶片
第10頁 1233172 五、發明說明（7) 330及#其所屬之電性絕緣層34〇和重配線路層35〇係採用前 述之第1 C至1 E圖所示之製程所製成，而上層之第二晶片 430及其所屬之電性絕緣層44〇和重配線路層45〇則係將相 同之程序重複一次而製成。 [總結] 綜而言之，本發明提供了 一種新穎之無接腳式半導體 封裝技術，其可用以製造無接腳式之半導體封裝件，例如 為CQFN封裝件；且其特點在於採用一暫時性晶片載具以及 重配線路技術來進行封裝程序；其中該暫時性晶片載具可 於完成製程之後將其剝除而形成無基板式之封裝件；^重 配線路技術則可較銲線技術更適於用來製做超薄型化的 裝件。本發明因此較習知技術具有更佳之進步性及實用、 —^上所述僅為本發明之較佳實施例而已，並 定本卷明之實質技術内容的範圍。本發明之者所〜 ^ 係廣義地定義於下述之申請專利範圍中。若二=術内容 成之技術實體或方法與下述之申請專利範圍所；：m 全相同、或是為一種等效之變t，均將被此： 利範圍之中。 ~叫盖於此專
17214. ptd 第11頁 1233172 圖式簡單說明 [圖式簡單說明 弟1 A至1 G圖為結構示意圖，i 式半導體封裝技術的笙 八中”、、員不本1明之無接腳 驟； 文術的第一貝鼽例於製程上的各個程序步 第2A至2C圖為結構示意圖，1 之無接腳式半導體封奘 ........八中，，、、員不本备明 々 、子粒封裝技術的第二實施例； 半導5封圖梦為;結構不意圖，纟中顯示本發明之無接腳式 襄技術的第三實施例所製出之封裝件的剖面結構 第 4圖顯示一習知之CQFN封裝件 110 暫時性晶片載具 11 0a 110b 載具11 0的背面 111 112 外接區 120 130 晶片 130a 130b 晶片1 3 0的背面 131 140 電性絕緣層 141 142 第二導電性金屬材料 150 160 封裝膠體 210 210a 載具2 1 0的正面 210b 211 置晶區 212 213 凹狀銲墊 220 230 晶片 23 0a 23 0b 晶片230的背面 231 載具1 1 0的正面 置晶區 銲墊 晶片1 3 0的正面 輸出入銲墊 第一導電性金屬材料 重配線路層 暫時性晶片載具 載具2 1 0的背面 外接區 銲墊 晶片2 3 0的正面 輸出入銲墊
17214. ptd 第12頁 1233172
圖式簡單說明 240 電性絕緣層 250 重配線路層 251 凸塊狀之外部 電性連接點 260 封裝膠體 330 弟一晶片 340 電性絕緣層 350 重配線路層 330 弟二晶片 340 電性絕緣層 350 重配線路層 360 封裝膠體 第13頁 17214. ptd

Claims (1)

1233172 六、申請專利範圍 1. 一種無接腳式半導體封裝製程，其至少包含： (1)預製一暫時性晶片載具，其具有一正面和一對 向之背面，且其正面係預先劃分出一置晶區和複數個 外接區； (2 )將一晶片安置於該暫時性晶片載具的置晶區 上；其中該晶片具有一正面和一對向之背面，且該正 面上形成有複數個輸出入銲墊，而該背面則係黏貼至 該暫時性晶片載具的置晶區上， (3)形成一電性絕緣層於該載具的正面和該晶片的 正面上，但曝露出該暫時性晶片載具上的外接區和該 晶片上的輸出入銲塾； (4 )形成複數條重配線路層於該電性絕緣層上；其 中該些重配線路層係用以將該晶片上的各個輸出入銲 墊電性連接至對應之一個外接區； (5)形成一封裝膠體於該電性絕緣層和該重配線路 層上；以及 (6 )將該暫時性晶片載具剝除。 2. 如申請專利範圍第1項所述之無接腳式半導體封裝製 程，其中於步驟（1 )中，該暫時性晶片載具的材質的種 類包括銅和銘。 3. 如申請專利範圍第1項所述之無接腳式半導體封裝製 程，其中於步驟（1 )中，該外接區上係形成銲墊，使得 於步驟（4 )中所形成之重配線路層覆蓋於該些銲墊上， 並使得該些銲墊作為非突出式的平面狀外部電性連接
17214. ptd 第14頁 1233172 六、申請專利範圍 點。 4. 如申請專利範圍第1項所述之無接腳式半導體封裝製 程，其中於步驟（1 )中，該些外接區係預先形成凹狀銲 墊。 5. 如申請專利範圍第1項所述之無接腳式半導體封裝製 程，其中於步驟（3)中，該電性絕緣層的製程包括： 進行一塗佈程序，藉以將一電性絕緣材料塗佈於 該暫時性晶片載具的正面和該晶片的正面上；以及 進行一選擇性移除程序，其中係將塗佈之電性絕 緣材料中位於該暫時性晶片載具之外接區和該晶片之 輸出入銲墊上的部分移除。 6. 如申請專利範圍第5項所述之無接腳式半導體封裝製 程，其中該電性絕緣材料為聚醯亞胺（p I )。 7. 如申請專利範圍第5項所述之無接腳式半導體封裝製 程，其中該電性絕緣材料為苯環丁烯（B C B )。 8. 如申請專利範圍第1項所述之無接腳式半導體封裝製 程，其中於步驟（4)中，該重配線路層的製程包括： 進行一第一覆蓋金屬程序程序，藉此而將一第一 導電性金屬材料鍍於該電性絕緣層和該暫時性晶片載 具上所有曝露出之外接區和該晶片上的輸出入銲墊； 進行一第二覆蓋金屬程序程序，藉此而將一第二 導電性金屬材料鍍於該第一導電性金屬材料；以及 進行一選擇性移除程序，其中係將鍍上之導電性 金屬材料中的預定部分移除，使得未移除部作為該些
17214. ptd 第15頁 1233172 六、申請專利範圍 重配線路層。 9.如申請專利範圍第8項所述之無接腳式半導體封裝製 程，其中該第一導電性金屬材料為銅。 1 0.如申請專利範圍第8項所述之無接腳式半導體封裝製 程，其中該第二導電性金屬材料為銅。 11.如申請專利範圍第8項所述之無接腳式半導體封裝製 程，其中該第一覆蓋金屬程序程序係採用濺鍍技術。 1 2.如申請專利範圍第8項所述之無接腳式半導體封裝製 程，其中該第一覆蓋金屬程序程序係採用無電解式電 鍍技術。 1 3.如申請專利範圍第8項所述之無接腳式半導體封裝製 程，其中該第二覆蓋金屬程序程序係採用電解電鍍技 術。 1 4. 一種無接腳式半導體封裝結構，其至少包含： 至少一晶片，其具有一正面和一對向之背面，且 該正面上形成有複數個輸出入銲墊； 複數個外部電性連接點，其係大致安置於與該晶 片的背面平行的一平面上； 一電性絕緣層，其係用以覆蓋該晶片，但未覆蓋 該晶片上的輸出入銲墊和該些外部電性連接點； 複數條重配線路層，其係形成於該電性絕緣層 上，用以將該晶片上的各個輸出入銲墊電性連接至其 對應之一個外部電性連接點；以及 一封裝膠體，其係用以覆蓋住該電性絕緣層和該
17214. ptd 第16頁 1233172 六、申請專利範圍 些重配線路層，但曝露出該些外部電性連接點。 1 5 .如申請專利範圍第1 4項所述之無接腳式半導體封裝結 構，其中該些外部電性連接點係為複數個銲墊，且該 些重配線路層係電性連接至該些銲墊，使得該些銲墊 作為非突出式的平面狀外部電性連接點。 1 6 .如申請專利範圍第1 4項所述之無接腳式半導體封裝結 構，其中該些外部電性連接點係形成凸塊狀之電性接 觸點，使得該些凸塊狀之電性接觸點作為突出式之外 部電性連接點。 1 7.如申請專利範圍第1 4項所述之無接腳式半導體封裝結 構，其中該電性絕緣材料為聚醯亞胺（P I )。 1 8 .如申請專利範圍第1 4項所述之無接腳式半導體封裝結 構，其中該電性絕緣材料為苯環丁烯（BCB)。
17214.ptd 第17頁
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