TWI224850B - Lead frame, and method for manufacturing semiconductor device and method for inspecting electrical properties of small device using the lead frame - Google Patents

Lead frame, and method for manufacturing semiconductor device and method for inspecting electrical properties of small device using the lead frame Download PDF

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Publication number
TWI224850B
TWI224850B TW092106017A TW92106017A TWI224850B TW I224850 B TWI224850 B TW I224850B TW 092106017 A TW092106017 A TW 092106017A TW 92106017 A TW92106017 A TW 92106017A TW I224850 B TWI224850 B TW I224850B
Authority
TW
Taiwan
Prior art keywords
lead
frame
wires
wire
semiconductor wafer
Prior art date
Application number
TW092106017A
Other languages
English (en)
Chinese (zh)
Other versions
TW200405537A (en
Inventor
Kazunari Michii
Naoyuki Shinonaga
Shinji Semba
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of TW200405537A publication Critical patent/TW200405537A/zh
Application granted granted Critical
Publication of TWI224850B publication Critical patent/TWI224850B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
TW092106017A 2002-07-26 2003-03-19 Lead frame, and method for manufacturing semiconductor device and method for inspecting electrical properties of small device using the lead frame TWI224850B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002217694A JP4111767B2 (ja) 2002-07-26 2002-07-26 半導体装置の製造方法および小型素子の電気特性検査方法

Publications (2)

Publication Number Publication Date
TW200405537A TW200405537A (en) 2004-04-01
TWI224850B true TWI224850B (en) 2004-12-01

Family

ID=30437653

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092106017A TWI224850B (en) 2002-07-26 2003-03-19 Lead frame, and method for manufacturing semiconductor device and method for inspecting electrical properties of small device using the lead frame

Country Status (6)

Country Link
US (1) US6836004B2 (https=)
JP (1) JP4111767B2 (https=)
KR (1) KR100538020B1 (https=)
CN (1) CN1288736C (https=)
DE (1) DE10306286A1 (https=)
TW (1) TWI224850B (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004253706A (ja) * 2003-02-21 2004-09-09 Seiko Epson Corp リードフレーム、半導体チップのパッケージング部材、半導体装置の製造方法、及び、半導体装置
US7271471B2 (en) * 2003-06-17 2007-09-18 Dai Nippon Printing Co., Ltd. Metal substrate apparatus, method of manufacturing an IC card module apparatus, and an IC card module apparatus
US7709943B2 (en) 2005-02-14 2010-05-04 Daniel Michaels Stacked ball grid array package module utilizing one or more interposer layers
US20060202320A1 (en) * 2005-03-10 2006-09-14 Schaffer Christopher P Power semiconductor package
US20080265248A1 (en) * 2007-04-27 2008-10-30 Microchip Technology Incorporated Leadframe Configuration to Enable Strip Testing of SOT-23 Packages and the Like
TW200921880A (en) 2007-11-12 2009-05-16 Orient Semiconductor Elect Ltd Lead frame structure and applications thereof
CN103855119A (zh) * 2012-12-07 2014-06-11 三垦电气株式会社 半导体模块、半导体装置及其制造方法
JP6673012B2 (ja) * 2016-05-26 2020-03-25 三菱電機株式会社 半導体装置およびその製造方法
JP7526980B2 (ja) 2019-10-24 2024-08-02 日電精密工業株式会社 Ｍａｐタイプのリードフレームの製造方法及び製造装置
CN111834323B (zh) * 2020-07-29 2025-08-19 北京燕东微电子科技有限公司 一种半导体封装件及其制造方法
CN118471867B (zh) * 2024-07-13 2024-09-24 中北大学 一种半导体封装测试装置及其测试方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541447A (en) * 1992-04-22 1996-07-30 Yamaha Corporation Lead frame
US5539251A (en) * 1992-05-11 1996-07-23 Micron Technology, Inc. Tie bar over chip lead frame design
JPH06132464A (ja) 1992-10-15 1994-05-13 Fuji Xerox Co Ltd 半導体集積回路の組立方法
GB2320964B (en) 1993-11-25 1998-08-26 Motorola Inc Method for testing electronic devices attached to a a leadframe
KR0145768B1 (ko) * 1994-08-16 1998-08-01 김광호 리드 프레임과 그를 이용한 반도체 패키지 제조방법
JP2806328B2 (ja) * 1995-10-31 1998-09-30 日本電気株式会社 樹脂封止型半導体装置およびその製造方法
JPH09129815A (ja) 1995-11-07 1997-05-16 Hitachi Ltd 半導体装置の製造方法およびその製造方法に用いるリードフレーム
JP3420057B2 (ja) * 1998-04-28 2003-06-23 株式会社東芝 樹脂封止型半導体装置
JP2000188366A (ja) * 1998-12-24 2000-07-04 Hitachi Ltd 半導体装置
KR100355796B1 (ko) * 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 반도체패키지용 리드프레임 및 이를 봉지하기 위한 금형 구조
JP3664045B2 (ja) * 2000-06-01 2005-06-22 セイコーエプソン株式会社 半導体装置の製造方法
JP3470111B2 (ja) * 2001-06-28 2003-11-25 松下電器産業株式会社 樹脂封止型半導体装置の製造方法

Also Published As

Publication number Publication date
JP4111767B2 (ja) 2008-07-02
KR20040010075A (ko) 2004-01-31
DE10306286A1 (de) 2004-02-12
US6836004B2 (en) 2004-12-28
KR100538020B1 (ko) 2005-12-21
JP2004063616A (ja) 2004-02-26
US20040018663A1 (en) 2004-01-29
CN1288736C (zh) 2006-12-06
TW200405537A (en) 2004-04-01
CN1471149A (zh) 2004-01-28

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MM4A Annulment or lapse of patent due to non-payment of fees