TWI223266B - Semiconductor memory device with structure of converting parallel data into serial data - Google Patents
Semiconductor memory device with structure of converting parallel data into serial data Download PDFInfo
- Publication number
- TWI223266B TWI223266B TW092116760A TW92116760A TWI223266B TW I223266 B TWI223266 B TW I223266B TW 092116760 A TW092116760 A TW 092116760A TW 92116760 A TW92116760 A TW 92116760A TW I223266 B TWI223266 B TW I223266B
- Authority
- TW
- Taiwan
- Prior art keywords
- data
- value
- circuit
- memory device
- semiconductor memory
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Image Input (AREA)
Description
1223266 才康$述外°卩所指定之行位址,以第(K 1 +1)至第 (Κ1+Κ2)(1$Κ2<;ν 2=(K1+K2) SN)之Κ2階段依序 對包含於前述各資粗蹈义^ 貝科匯>,,L排對群之資料匯流排對之資 料進行排序之輪出電路。 、 7·如申請專利範圍第6項之半導體記憶袭置,其中,前述 讀出電路,係同時讀出和前述外部所指定之行位址除了 最下位起N個位亓外夕u 卜之上位位元皆相同之行位址所指 定之記憶胞之資料, 前述讀出電路以及前述輸出電路,係對應進行排序 之各階段,而包含複數個開關電路,且 當K1 - 2時, 於對應包含於前述讀出電路内之第8階段。=1至 ㈤-υ)之各開關電路中,輪入由和行位址之最下位起 僅(Ν — S + 1)位元相里之?— 〜 〃 2個仃位址所指定之記憶胞之 2個資料’並根據前述外 卜邛所指定之行位址之最下位起 (N S+ 1)位兀的值,將前述輸入之其中一方之資 料’輸出至進行第(S + j)階, 二 )ό ^又之排序之開關電路中較輸 入前述輸入之另一古,丨 另方之貝料之開關電路先將輸入資料 =出之開關電路’將前述另-方之資料,輸出至進行第 (s+υ階段之排序的開關電路中較輸入前述—方之資料 的·開關電路後將輸入資料輸出之開關電路。 8·如申請專利範圍第7項丰 心千V體§己fe裝置,呈中,禆於 對應第K1階段之各開關帝敗由 ^ y东、 间關电路中,輸入由和行位址之最 下位起僅(N—K1+1)位元相显 相吳之2個订位址所指定之 (更正本)314805 3 1223266 記憶胞之2個資料,並根據前述外部所指定之行位址之 最下位起第(N—K1+ ”位元的值,將前述輸…中一 方之貧料’輸出至較輸出前述輪入之另_方之次 料匯流排對群中所含之資料匯流排對先將自讀出電路貝 接收之資料輸出至前述輸出電路之資料匯流排對 :含:資料匯流排對;將前述另一方之資料,輪出至較 輪出前述—方之資料之資料匯流排對群中所含之資料 匯流排對後將自讀出電路接收之資料輸出至前述輪出 電路之資料匯流排對群中所含的資料匯流排對。 (更正本)314805 4
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002330982A JP2004164769A (ja) | 2002-11-14 | 2002-11-14 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200407894A TW200407894A (en) | 2004-05-16 |
TWI223266B true TWI223266B (en) | 2004-11-01 |
Family
ID=32290113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092116760A TWI223266B (en) | 2002-11-14 | 2003-06-20 | Semiconductor memory device with structure of converting parallel data into serial data |
Country Status (4)
Country | Link |
---|---|
US (1) | US6914828B2 (zh) |
JP (1) | JP2004164769A (zh) |
KR (1) | KR100578036B1 (zh) |
TW (1) | TWI223266B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6965521B2 (en) * | 2003-07-31 | 2005-11-15 | Bae Systems, Information And Electronics Systems Integration, Inc. | Read/write circuit for accessing chalcogenide non-volatile memory cells |
JP4370507B2 (ja) * | 2003-11-27 | 2009-11-25 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
KR100546418B1 (ko) | 2004-07-27 | 2006-01-26 | 삼성전자주식회사 | 데이터 출력시 ddr 동작을 수행하는 비휘발성 메모리장치 및 데이터 출력 방법 |
KR100562645B1 (ko) * | 2004-10-29 | 2006-03-20 | 주식회사 하이닉스반도체 | 반도체 기억 소자 |
DE102004062282B4 (de) * | 2004-12-23 | 2014-08-21 | Infineon Technologies Ag | Speicheranordnung und Verfahren zur Verarbeitung von Daten |
JP2006277872A (ja) | 2005-03-30 | 2006-10-12 | Elpida Memory Inc | 半導体記憶装置及びそのテスト方法 |
US7358872B2 (en) * | 2005-09-01 | 2008-04-15 | Micron Technology, Inc. | Method and apparatus for converting parallel data to serial data in high speed applications |
JP4470183B2 (ja) | 2006-08-28 | 2010-06-02 | エルピーダメモリ株式会社 | 半導体記憶装置 |
DE102006053072B4 (de) * | 2006-11-10 | 2014-09-04 | Qimonda Ag | Verfahren zum Auslesen von Datenpaketen |
KR101027681B1 (ko) * | 2009-06-09 | 2011-04-12 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 데이터 정렬 회로 |
KR101187639B1 (ko) * | 2011-02-28 | 2012-10-10 | 에스케이하이닉스 주식회사 | 집적회로 |
KR20190058158A (ko) | 2017-11-21 | 2019-05-29 | 삼성전자주식회사 | 데이터 출력 회로, 데이터 출력 회로를 포함하는 메모리 장치 및 메모리 장치의 동작 방법 |
JP2022146494A (ja) * | 2021-03-22 | 2022-10-05 | キオクシア株式会社 | 半導体記憶装置およびメモリシステム |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2982618B2 (ja) | 1994-06-28 | 1999-11-29 | 日本電気株式会社 | メモリ選択回路 |
JP2000163969A (ja) | 1998-09-16 | 2000-06-16 | Fujitsu Ltd | 半導体記憶装置 |
US6707740B2 (en) * | 2001-08-03 | 2004-03-16 | Fujitsu Limited | Semiconductor memory |
-
2002
- 2002-11-14 JP JP2002330982A patent/JP2004164769A/ja active Pending
-
2003
- 2003-05-19 US US10/440,188 patent/US6914828B2/en not_active Expired - Lifetime
- 2003-06-09 KR KR1020030036670A patent/KR100578036B1/ko not_active IP Right Cessation
- 2003-06-20 TW TW092116760A patent/TWI223266B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US20040094780A1 (en) | 2004-05-20 |
KR20040042786A (ko) | 2004-05-20 |
KR100578036B1 (ko) | 2006-05-11 |
TW200407894A (en) | 2004-05-16 |
JP2004164769A (ja) | 2004-06-10 |
US6914828B2 (en) | 2005-07-05 |
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MM4A | Annulment or lapse of patent due to non-payment of fees |