TWI220253B - Method of operating a non-volatile memory - Google Patents

Method of operating a non-volatile memory Download PDF

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Publication number
TWI220253B
TWI220253B TW92128384A TW92128384A TWI220253B TW I220253 B TWI220253 B TW I220253B TW 92128384 A TW92128384 A TW 92128384A TW 92128384 A TW92128384 A TW 92128384A TW I220253 B TWI220253 B TW I220253B
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Taiwan
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memory cell
bias voltage
bit line
memory
patent application
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TW92128384A
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Chinese (zh)
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TW200514084A (en
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Chih-Chieh Yeh
Hung-Yueh Chen
Wen-Jer Tsai
Tao-Cheng Lu
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Macronix Int Co Ltd
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Abstract

A method of operating a non-volatile memory. A non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

Description

1220253 五、發明說明(1) 發明所屬之技術^^ 本發明是有關於一種快閃記憶體(flash託㈣;^),且 特別是有關於一種新的快閃記憶胞及其資料型樣(data pattern)與感測方案(sensing scheme)。 先前技術 用於貧訊的非揮發性儲存之記憶元件以被廣泛使用。 這種έ己憶元件的例子包括唯讀記憶體(R〇M)、可編程唯讀 記憶體(PR0M)、可抹除可編程唯讀記憶體(EpR〇M)、可電 除可編程唯讀記憶體(EEPR〇M)以及快閃可電除可編程唯讀 記憶體。 快閃記憶體通常是指一快閃可電除可編程唯讀記憶 體,其可取代一位元組,而一次被抹除一塊資料。許多現 代的電腦有其儲存於一快閃記憶晶片上的基本輸入輸出系1220253 V. Description of the invention (1) The technology to which the invention belongs ^^ The invention relates to a flash memory (flash memory; ^), and in particular to a new flash memory cell and its data type ( data pattern) and sensing scheme. Prior art memory devices for non-volatile storage of lean signals have been widely used. Examples of such memory devices include read-only memory (ROM), programmable read-only memory (PR0M), erasable programmable read-only memory (EpROM), and programmable memory. Read memory (EEPROM) and flash memory can be programmed to read only read-only memory. Flash memory usually refers to a flash-erasable programmable read-only memory, which can replace one byte and erase one piece of data at a time. Many modern computers have their basic input-output system stored on a flash memory chip.

統(basic input/output systein,簡稱BIOS),以便BIOS 在而要k能被輕易更新。這種B丨〇s有時稱為快閃β丨〇s。快 閃記憶體也廣泛應用於儀器中,如數據機。因為快閃記憶 體能使這些儀器被更新去支持如新協定(pr〇t〇c〇l )而變得 標準。 —I*夬門z隐元件通常包含排成列與行的記憶胞的陣 列。母一 §己憶胞包含一金氧半電晶體(M0S transistor)結 構,其中具有一閘極、—汲極、一源極與一通道區定義於 ,極與及極之間° 極對應於—字元線,而源極與没極對 t:記憶陣列的位元線。習知快閃記憶胞的閘極通常是-種又閘極(dua卜gate)結構,包含一控制閘極(c〇ntr〇iSystem (basic input / output systein, referred to as BIOS), so that the BIOS can be easily updated. Such B 丨 0s is sometimes called flash β 丨 0s. Flash memory is also widely used in instruments such as modems. Because flash memory enables these instruments to be updated to support Nu Skin (protto), it becomes standard. —I * The cardia z hidden element usually contains an array of memory cells arranged in columns and rows. The mother cell has a MOS transistor structure, which has a gate, -drain, a source, and a channel region defined between the pole and the pole. The pole corresponds to- Word line, and source and non-pole pair t: bit line of memory array. The gate of the conventional flash memory cell is usually a dua gate structure, including a control gate (c〇ntr〇i

12202531220253

gate) βι 一 淳罟 k / r 於兩介電層之門ifloating gate),其中浮置閘極被夾 「,間以捕捉如電子的載子(carrier),藉以 電ΐ i成^記憶胞。換言之,在一傳統的胞中,一第一介 ;通道上、浮置閘極形成於第一介電層上、一第 二f ® 7 ^成於浮置問極上以及控制閘極最後形成於第二 介電層上。 在ί式化期間,供應一套程式偏壓至被選字元線與位 22 ΐ於被選字元線與位元線的一或多個記憶胞被加 勹& ;王式狀態(pr〇gramming state)中。對於單一記憶 胞=言:供應不同的偏壓到其源極與汲極會沿著其通道…產 生了電%,而使電子得到足夠能量。這種熱電子之後會經 過第"電層穿隧至浮置閘極中而儲存於其中。由於浮置 閘極中儲存有電子,所以記憶胞的啟始電壓(threshold voltage)會被改變。啟始電壓之變化將判定是否程式化記 憶胞。 欲讀取一記憶胞,要供應讀取偏壓以及一感測器 (s e n s i n g d e v i c e)通過§己憶胞讀取一電流。如果記憶胞已 被程式化,或是有電子被儲存於其浮置閘極中,則其電流 度(cur rent level)與沒被程式化的記憶胞不同。因此, 根據測得的電流度,感測器能夠判定每一記憶胞的狀態。 欲抹除存於一快閃記憶體中的資訊,則需供應其抹除 偏壓,經由已知的F-N(Fowler-Nordheim)穿隧機制,迫使 儲存電子由浮置閘極穿隧出來。然而,習知的快閃記憶體 有一些問題,如高耗電、程式化與讀取干擾 _gate) βι is an ifloating gate at the gate of the two dielectric layers, in which the floating gate is sandwiched between the two, to capture carriers such as electrons, which can be used to form a memory cell. In other words, in a traditional cell, a first dielectric; on the channel, a floating gate is formed on the first dielectric layer, a second f ® 7 ^ is formed on the floating interrogator and the control gate is finally formed on On the second dielectric layer. During the formatting, a set of programs is biased to the selected word line and bit 22. One or more memory cells on the selected word line and bit line are added &; In the king state (pr0gramming state). For a single memory cell = to say: the supply of different bias voltages to its source and drain will follow its channel ... to produce electricity%, so that the electrons get enough energy. Such hot electrons will then be tunneled into the floating gate through the " electrical layer and stored therein. Since electrons are stored in the floating gate, the threshold voltage of the memory cell will be changed. The change in the starting voltage will determine whether the memory cell is programmed. To read a memory cell, a reading bias voltage must be supplied. And a sensor (sensing device) reads a current through its own memory cell. If the memory cell has been programmed or electrons are stored in its floating gate, its cur rent level and The memory cells that are not programmed are different. Therefore, based on the measured current, the sensor can determine the state of each memory cell. To erase the information stored in a flash memory, you need to provide the erase Biasing, through the known Fowler-Nordheim tunneling mechanism, forces the stored electrons to tunnel through the floating gate. However, conventional flash memory has some problems, such as high power consumption, programming and Read interference _

1220253 五、發明說明(3) (disturbance)。高耗電係由於需要高程式化與抹除電 壓,以感應電子之穿隧來進行程式化與抹除操作。程式化 與讀取干擾係與當程式化或讀取某記憶胞時發生於未^選 的鄰近記憶胞(non-selected neighboring memory cell) 之漏電流有關。 在一快閃記憶陣列中的一干擾通常關於一種現象係當 記憶陣列中一被選胞被讀取或程式化時,另一個共用相同 $元線或位元線的被程式化記憶胞可能會因被選胞的電子 穿隧而遭受漏電流,且儲存於浮置閘極中的電子可能會導 致從f被程式化」到「被抹除」的狀態改變。而讀取干擾 用第1圖作解釋’其係包括傳統扶植閘極記憶胞的一種 快閃記憶陣列。 請參照第1圖,一快閃記憶陣列100包括數個字元線 、WL2、〜乳6以及數個位元線BL1、BL2、…BL5。字元 線^位元線的每一交叉處(intersecti〇n)定義一記憶胞。 =:=憶胞也包括一浮置閘極(未繪示)。如所示,對應到 的^線WL3與位元線BL2和BU之記憶胞a藉由加偏壓至相應 壓為3^、和值元線而被選。舉例來說,字元線壯3被加偏 為/、、、位元線BL2被加偏壓為〇·3νΑ位元線乩3被加偏壓 (ov),。而字元線礼1、WL2、WU、WL5與WL6被接地 這種力π i ΐ70線礼1、Bu與虬5無偏壓或是浮置的〇〇。在 同日士塾條件下,儲存於胞A的資訊會被讀取。 處於某^值,胞A共用相同字元線或位元線的記憶胞也是 壓下。例如’胞β與胞A共用同樣的字元線WL31220253 V. Description of Invention (3) (disturbance). Due to the high programming and erasing voltage required for high power consumption, programming and erasing operations are induced by tunneling of induced electrons. Programming and reading disturbances are related to leakage currents that occur in non-selected neighboring memory cells when programming or reading a memory cell. An interference in a flash memory array is usually related to the phenomenon that when one selected cell in the memory array is read or programmed, another programmed cell that shares the same $ or bit line may The selected cell suffers a leakage current due to the tunneling of the electrons, and the electrons stored in the floating gate may cause a state change from "f programmed" to "erased". The read disturbance is explained in the first figure, which is a flash memory array including a traditional gate-grown memory cell. Referring to FIG. 1, a flash memory array 100 includes a plurality of word lines, WL2, ˜6, and a plurality of bit lines BL1, BL2,... BL5. Each intersection of word lines and bit lines (intersection) defines a memory cell. =: = Yi Cell also includes a floating gate (not shown). As shown, the memory cell a corresponding to the ^ line WL3 and the bit line BL2 and BU is selected by applying a bias voltage to the corresponding voltage of 3 ^ and the value element line. For example, the character line Z3 is biased to / ,, and the bit line BL2 is biased to 0.3 V, and the bit line 乩 3 is biased (ov). The character line rites 1, WL2, WU, WL5, and WL6 are grounded. This force π i ΐ70 line rites 1, Bu, and 虬 5 is not biased or floating. Under the same conditions, the information stored in cell A will be read. At a certain value, the memory cell in which cell A shares the same word line or bit line is also depressed. For example, 'Cell β shares the same word line WL3 with Cell A

1220253 五、發明說明(4) 和位元線BL2。因此,假定位元線BL2對應胞B的汲極,則 胞B的源極與汲極之間將存在一電場,而感應經過胞B的一 漏電流。經過胞B的漏電流取決於其啟始電壓,其係依據 胞B之浮置閘極中的電子密度。一較低的啟始電壓將導致 一較高的漏電流。同理,由於在位元線BL2與位元線BL3的 偏壓,胞C與D也可能分別遭受漏電流。經過鄰近胞如胞 B、C與D的漏電流將流經位元線B L 2與B L 3,並會產生胞A的 感測錯誤(sens i ng error ) ° 内容1220253 V. Description of the invention (4) and bit line BL2. Therefore, the false positioning element line BL2 corresponds to the drain of the cell B, then there will be an electric field between the source and the drain of the cell B, and a leakage current will be induced through the cell B. The leakage current through cell B depends on its starting voltage, which is based on the electron density in the floating gate of cell B. A lower starting voltage will result in a higher leakage current. Similarly, due to the bias voltages on bit line BL2 and bit line BL3, cells C and D may also suffer leakage currents, respectively. Leakage currents passing through neighboring cells such as cells B, C, and D will flow through the bit lines B L 2 and B L 3, and a sense error (sens i ng error) of cell A will be generated.

本發明的目的就是在提供一種操作非揮發性記憶胞的 方法,以降低耗電、降低漏電問題與簡化製程。 〜 本發明的再一目的是提供一種操作快閃記憶胞的方 法,以降低耗電、降低漏電問題與簡化製 本發明的又一目的是提供一種^憶=的操作方法, 以降低耗電、降低漏電問題與簡化製程。The purpose of the present invention is to provide a method for operating non-volatile memory cells, so as to reduce power consumption, reduce leakage problems, and simplify the manufacturing process. ~ Another object of the present invention is to provide a method for operating a flash memory cell to reduce power consumption, reduce leakage problems, and simplify manufacturing. Another object of the present invention is to provide a method of operation for reducing memory consumption and reducing power consumption. Leakage issues and simplified processes.

本赉明徒出一種操作非揮發性記憶胞的方法,直 揮發性記憶胞包括一字元線、一第_位元線以及一第一 元線’此方法包括程式化記憶胞,其包括供應一言1 至第一位元線、供應一接地偏壓至第m乂 I供肩 高負偏壓至字元線,其中記憶胞包括一控制閑極、二^ 區、一汲極區、一通道區定義於源極區與汲極" 捕捉層被提供於通道區i以及一介電層被 = 區其中之-對應於第一位元線以及The present invention provides a method for operating non-volatile memory cells. Straight volatile memory cells include a word line, a first bit line, and a first line. This method includes a programmed memory cell, which includes supply. In a word, from 1 to the first bit line, a ground bias voltage is supplied to the m 第 I for shoulder high negative bias voltage to the word line, wherein the memory cell includes a control idler, two ^ regions, a drain region, a The channel region is defined in the source region and the drain " The capture layer is provided in the channel region i and a dielectric layer is in the region-corresponding to the first bit line and

五、發明說明(5) 另一對應於第二^r - 電層穿隧至捕捉層;:’而且其中帶正電荷的電洞經由介 本發明還提屮 ^ ,σ ^ 記憶胞包括—ί二:種,作快閃記憶胞的方法,其中快閃 此種方法包括抹除=二:二位元線以及-字元線, 位元線、供應 :::广舌供應-第-偏壓至第一 至字元線,其中ΐ =堡至第二位元線、供應一第三偏塵 義於源極與汲極 以 ^ 及極、一通道區定 捕捉層形成於第— f、二,層形成於通道區上、一 上以及一控制f彳j : a 、一弟二介電層形成於捕捉層 應於字元線層上,其中控制閘極對 -、第二以及對應於第二位元線,以及其中第 介電層其中被選擇以使電子經由第-與第二 牙隧至捕捉層中。 本發明另外;^ ψ _ % β ^ 供-記憶陣列包括:個:件的操作方法,包括先提 個行定義。之後,$ 胞,其十記憶胞被數個列與數 列,其中每-ί憶;每-字元㈣應於-兀線,每一位元線對應二二/子兀線然後,提供數個位 第一位元線與一第二:j 一仃,其中每一記憶胞對應於一 胞。而程式化此一記惟旳Ί 之後,程式化至少一個記憶 胞的第一位元線上、ϋ 一包括供應一第一偏壓於此記憶 元線上以及供應一第三厂:第二偏壓於此記憶胞的第二位 第三偏壓的電壓值低於=壓於此記憶胞的字元線上,其中 及第二偏壓的電壓值。 m 10500twf.ptd 1220253 五、發明說明(6) " ------ 為讓本發明之上述和其他目的和特徵能更明顯易懂, 下文特舉-較佳貫施例,並配合所附圖式,作詳細說明如 下。 實施方式 以下將詳細描述本發明之較佳實施例,並以附圖作說 明。而在圖不中所使用之相同標號盡可能是指相同或類 的部件。 、 ⑽根據本發明,提供一種「藉熱電子注入氮化電子儲存 為中以程式化(programming by h〇t h〇le injecti〇n nit/ide electron storage ,縮寫為PHINES)」之新的快 閃記憶元件及其方法,其中記憶元件可包括含有記憶胞矩 陣(a matrix of memory cells)的一記憶陣列。 第2圖是依據本發明之一示範用的pHINES記憶胞2〇〇的 2包結構。請參照第2圖,提供一半導體基底2〇2,具有兩擴 政區形成於其上,即一源極2〇4與一汲極2〇β。半導體基底 20 2可包括傳統的半導體材料如矽。一通道區2〇8被定義為 位於源極204與汲極20 6間的半導體基底2〇2之區域。一多 層閘極結構2 1 0被形成於通道區上,包括一第一介電層 212、一 捕捉層(trapping layer)214、一第二介電層 216 以及一控制閘極2 1 8。第一介電層2 1 2可由氧化石夕構成、第 二介電層2 1 6可由氧化矽構成以及控制閘極2 1 8可由多晶質 的矽、金屬、金屬矽化物或其組成物所構成。 一方面,控制閘極2 1 8對應於記憶陣列的一字元線, 且源極2 04與汲極2 0 6對應於記憶陣列的位元線。所以,每V. Description of the invention (5) Another corresponding to the second ^ r-electric layer tunneling to the capture layer; and 'wherein the positively-charged hole is also provided through the present invention, σ, σ ^ memory cells include-ί Two: a method for flash memory cells, which includes flashing = two: two bit lines and-character lines, bit lines, supply :: wide tongue supply-first-bias To the first to the character line, where ΐ = fort to the second bit line, supplying a third partial dust meaning the source and drain electrodes and the ^ and pole, a channel area fixed capture layer is formed in the first-f, two The layer is formed on the channel region, one above and one control f 彳 j: a, one and two dielectric layers are formed on the capture layer should be on the word line layer, among which the control gate pair-, the second, and the corresponding The two-bit line, and wherein the first dielectric layer is selected so that electrons tunnel through the first and second teeth into the capture layer. In addition to the present invention, the ^ ψ _% β ^ donor-memory array includes: operation methods of the pieces, including the first line definition. After that, the cell, its ten memory cells, is composed of several columns and sequences, each of which is a single character; each character should be on a line, and each bit line corresponds to a two / two line. Then, provide several The first bit line and the second: j are a pair, where each memory cell corresponds to a cell. After stylizing this record, stylizing at least one memory cell on the first bit line, one including supplying a first bias voltage to this memory cell line and supplying a third factory: a second bias voltage on The voltage value of the second and third bias voltages of the memory cell is lower than the voltage value of the memory cell, and the voltage value of the second bias voltage. m 10500twf.ptd 1220253 V. Description of the invention (6) " ------ In order to make the above and other objects and features of the present invention more comprehensible, the following specific examples are given-preferred embodiments, and cooperate with The drawings are described in detail below. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Wherever possible, the same reference numbers used in the drawings refer to the same or similar parts. According to the present invention, a new flash memory is provided, which is "programmed by h〇th〇le injecti nit / ide electron storage (abbreviated as PHINES)" The device and the method thereof, wherein the memory device may include a memory array including a matrix of memory cells. Fig. 2 is a two-pack structure of pHINES memory cells 2000, which is an exemplary use according to the present invention. Referring to FIG. 2, a semiconductor substrate 202 is provided, and two expansion regions are formed thereon, that is, a source 204 and a drain 20β. The semiconductor substrate 202 may include a conventional semiconductor material such as silicon. A channel region 208 is defined as a region of the semiconductor substrate 202 located between the source 204 and the drain 206. A multi-layer gate structure 210 is formed on the channel region, and includes a first dielectric layer 212, a trapping layer 214, a second dielectric layer 216, and a control gate 218. The first dielectric layer 2 1 2 may be composed of oxidized stone, the second dielectric layer 2 1 6 may be composed of silicon oxide, and the control gate 2 1 8 may be composed of polycrystalline silicon, metal, metal silicide, or a composition thereof. Make up. In one aspect, the control gate 2 1 8 corresponds to a word line of the memory array, and the source 2 04 and the drain 2 06 correspond to bit lines of the memory array. So every

l〇5〇〇twf pt(jl〇5〇twf pt (j

1220253 五、發明說明(7) ___ η心胞具有―相應的字元線 第一位元線與—第二位元線。 位凡線或是 電子ί μ前^捉層川中 示的電子ί;去tribUtl〇n Pr〇file)。可知第2圖所 (M〇s) /構Λ亚是?Λ例描繪。且已知一個金氧半導體 2第二與之後的描述中,記憶胞2。。的源極=極因戈 形下都是可;:: 線在不影響本發明的範圍或其功效的情 胞20 0的操作將於之後用第2圖解釋。於程 ^應—套程式化偏壓到字元線與位元線,^ 0 Λ" fV"21 8 ^ ^ ^ ^ Γ, ,;_5V , ; -位元Λ 線或源極204是接地,幻己憶胞2〇〇的/ 著是=^ 社槿?1 η么* /〇者通迢208會產生一水平電場並且穿過 S產生一垂直電場。水平電場會將帶正電荷的電 i、、r、r^lvely-chargeci hole)從汲極206 拉到源極204。 旦丰=水平電場加速至一較高的能量。當電洞達到足夠能 破第一介電層212的障勢(barrier P〇tential)時, 垂直電場的誘導,-些電洞會_皮「注人」或經由第 ^ "電層212穿隧到捕捉層214中’且被捕捉在此。特別的 =力電洞被注入捕捉層2 1 4的右側。捕捉層2丨4的左側通常 有電洞的。因此,被捕捉的電洞會減緩在捕捉 4 中的電荷分佈。1220253 V. Description of the invention (7) ___ The heart cell has ―corresponding character line first bit line and-second bit line. Weifan line or electrons ^ ^ catch the electrons shown in Chuanchuan; go to tribUtl〇n Pr0file). It can be seen that the (M0s) / structure Λ sub-picture in Fig. 2 is an example of Λ. It is known that in the second and subsequent descriptions of a metal-oxide semiconductor 2, the memory cell 2 is stored. . The source = pole ingo is ok in the form of ::: The operation of the line 20 in the case that it does not affect the scope of the present invention or its efficacy will be explained later with reference to FIG. 2.于 程 ^ 应 —Set of stylized bias to word and bit lines, ^ 0 Λ " fV " 21 8 ^ ^ ^ ^ Γ,,; _5V,; -bit Λ line or source 204 is grounded, Magical self-remembering cell 200 / 着 是 = ^ hibiscus? 1 η Mod * / 0 will generate a horizontal electric field through 208 and a vertical electric field across S. The horizontal electric field will pull positively charged electric charges i,, r, r ^ lvely-chargeci hole) from the drain 206 to the source 204. Danfeng = Horizontal electric field accelerates to a higher energy. When the hole reaches a barrier potential sufficient to break the first dielectric layer 212, the induction of the vertical electric field, some holes will be "injected" or penetrated through the first " electrical layer 212 Tunneled into the capture layer 214 'and is captured there. Special = Force holes are injected to the right of the capture layer 2 1 4. There are usually holes on the left side of the capture layers 2 丨 4. Therefore, the trapped holes slow down the charge distribution in trap 4.

12202531220253

已知可供應不同套的偏 位元線去程式化記憶胞,只 場,以使電洞獲得足夠能量 捉層2 1 4中。 壓電壓到字元線與第一和第二 要加偏壓情形提供必要的電 而經第一介電層2 1 2穿隧到捕 為了讀取記憶胞2 0 0,供應3V的偏壓到字元線或 閘極218,同時將汲極20 6接地。供應15¥的偏壓到I 204。結|,在通道區208中產生一通道。由於源極2〇、4與 汲極20-6間的偏壓差異,之後在記憶胞2〇〇外的一感測電路 (未繪不)會感測穿過通道之電流。如果記憶胞2〇〇被程式 化,則捕捉層2 1 4會包含被捕捉的帶正電荷的電洞。因 此’與一無程式化的記憶胞2〇〇比較之下,一已被程式化 的纪憶胞2 0 0的啟始電壓因為被捕捉的電洞而低於無程式 化的記憶胞2 0 0,結果已被程式化的記憶胞2〇〇被感測電路 感測的電流會較高。 如果π 1π代表一種具有較高感測電流的狀態以及” 〇”代 表一種具有較低感測電流的狀態,則已被程式化的記憶胞 2 0 0有"1π的狀態以及無程式化的記憶胞2 〇 〇則有” 〇,,的狀 態。 為了抹除記憶胞2 0 0,字元線或控制閘極2 1 8是被加偏 壓為一高負電壓如-8V,而記憶胞2 00的第一位元線與第二 位元線或源極2 0 4與汲極2 0 6是被加偏壓為一高正電壓如 + 10V。控制閘極218與源極204、汲極20 6之間會產生一強 垂直電場,且控制閘極2 1 8中的電子會被「拉」入或經第 二介電層216穿隧至捕捉層214中。電子與帶正電荷的電洞It is known that different sets of bias line can be supplied to program the memory cells, only the field, so that the holes get enough energy in the trap layer 2 1 4. The voltage to the word line and the first and second cases to be biased provide the necessary electricity and tunnel through the first dielectric layer 2 1 2 to capture. In order to read the memory cell 2 0 0, a bias voltage of 3V is supplied to A word line or gate 218 while grounding the drain 20 6. Supply a bias of 15 ¥ to I 204. Knot |, a channel is generated in the channel area 208. Due to the bias difference between the source 20, 4 and the drain 20-6, a sensing circuit (not shown) outside the memory cell 200 will sense the current passing through the channel. If memory cell 200 is programmed, capture layer 2 1 4 will contain the positively charged holes that are captured. Therefore, compared with an unprogrammed memory cell 2000, the start voltage of a programmed Ji Yi cell 2 0 is lower than that of an unprogrammed memory cell 2 0 0, the result is that the programmed memory cell 200 has a higher current sensed by the sensing circuit. If π 1π represents a state with a higher sensing current and "〇" represents a state with a lower sensing current, the programmed memory cell 2 0 0 has a state of " 1π and a non-programmed The memory cell 2 has the status of “〇,”. In order to erase the memory cell 200, the word line or control gate 2 18 is biased to a high negative voltage such as -8V, and the memory cell The first bit line and the second bit line or source 2 0 4 and drain 2 6 of 2 00 are biased to a high positive voltage such as + 10V. Control gate 218 and source 204, drain A strong vertical electric field will be generated between the electrodes 20 6, and the electrons in the control gate 2 1 8 will be “pulled” into or tunneled through the second dielectric layer 216 into the capture layer 214. Electrons and positively charged holes

1220253 五、發明說明(9) 將在捕捉層2 1 4中再!士人十,ι ^ 成程式化前狀態(pre-pr^ a、、·。結果,捕捉層214被恢夜 ΟΠΛ P 〇gramming status)以及記憶胞 2 0 0的啟始電壓被提升到—^ ^ 一、 攸捉开引 較尚程度,相當於” 0,,的狀態。 同樣地用來碩取與抹除記憶胞20 0之可應用偏壓並 未受限於前述作為範例用全两、 _ 祀⑺用的偏壓。而可供應不同套的偏 壓,只要能獲得所需之讀取與抹除結果。 因此,記憶胞20 0的操作如前述是低耗電的操作,且 適於大量儲存應用。同樣根據本發明,可編排數個記憶胞 20 0以形成一記憶陣列。-方面,形成記憶陣列如—垂直 接地陣列(ground array),其中位元線係埋入式擴散區 (buried diffusion area),而字元線是閘極接觸點,如 多晶質矽條(polycrystal line silic〇n strip)。在同一 行的記憶胞共用相同的位元線或埋入式擴散區,而在同一 列的記憶胞共用相同的字元線。所以,記憶陣列無接觸窗 (contact-less)以及不需任何場隔絕物(field isolation)。因此,本發明可實現非常高密度的記憔元 件。 心 同樣依照本發明,提供一種快閃記憶元件的新資料型 樣(data pattern),其中的快閃記憶元件具有降低的綠 干擾(read disturbance)。第3圖顯示一資料型樣的、'取 一實施例,以降低讀取干擾。第4圖顯示一資料型樣—$ 第二實施例,以降低讀取干擾。 ’的一 請參照第3圖’一快閃記憶陣列3 〇 〇包括數個字一 WL1、WL2、".WL6以及數個位元線BL1、BL2、·· c:兀線 。字元1220253 V. Description of the invention (9) Will be in the capture layer 2 1 4 again! Scholars 10, ^ ^ into the pre-stylized state (pre-pr ^ a, .... As a result, the capture layer 214 was restored to 〇ΠΛ P 〇gramming status) and the starting voltage of the memory cell 2 0 0 was increased to-^ ^ I. The relatively high degree of decoupling, equivalent to the state of "0,". The applicable bias voltage used to obtain and erase the memory cell 20 0 is not limited to the foregoing two as an example. _ Bias for worship. Different sets of bias voltages can be supplied, as long as the desired reading and erasing results can be obtained. Therefore, the operation of the memory cell 20 as described above is a low-power operation and suitable for Mass storage applications. Similarly, according to the present invention, several memory cells 200 can be arranged to form a memory array. On the one hand, a memory array is formed, such as a vertical ground array, in which bit lines are buried diffusion regions ( buried diffusion area), and the word line is the gate contact point, such as polycrystalline line silicon strip. The memory cells in the same row share the same bit line or buried diffusion area, and Memory cells in the same row share the same character line. So, memory Contact-less columns and no field isolation are required. Therefore, the present invention can realize a very high density memory element. According to the present invention, a new data of a flash memory element is provided. Data pattern, in which the flash memory element has reduced read disturbance. Figure 3 shows a data pattern, 'take an embodiment to reduce read disturbance. Figure 4 shows a Data type—a second embodiment to reduce read interference. 'One please refer to Figure 3' A flash memory array 3 00 includes several words-WL1, WL2, " .WL6 and several bits Yuan line BL1, BL2, ·· c: Wu line. Character

10500twf.ptd 第16頁 1220253 五、發明說明(ίο) 線與位元線的父叉處(i n t e r s e c t i ο η)定義數個記憶胞,每 一記憶胞對應到一字元線與一對位元線。第3圖也指出一 資料型樣其中記憶胞的連貫的行被程式化在捕捉層的交替 側(alternating side)。特別是,例如,位於位元線BL1 與BL2間之記憶胞的一第一行被程式化於捕捉層的右側, 位於位元線BL2與BL3間之記憶胞的一第二行被程式化於捕 捉層的左側,且位於位元線BL3與BL4之間記憶胞的一第三 行被私式化於捕捉層的右侧。當熱電洞穿隧入記憶胞之捕 捉層的右側並被儲存於此時,記憶胞被定義成已「程式化 在右側上」。然而,可知「左側」與「右側」只是根據記 fe胞的配置而定的一種相對的用語,且此用語可被替換而 不影響記憶胞的功能。 請再參照第3圖,對應到字元線WL3與位元線虬2和bL3 之Z丨思胞A藉由加偏壓至相應的字元線和位元線而被選。 特別是,字元線WL3被加偏壓為3V、位元線BL2被加偏壓為 0· 3V及位元線BL3被加偏壓為1 · 5V。而字元線WL1、WL2、 W曰L4、WL5與WL6被接地,且位元線BL1、儿4與儿5無偏壓或 是浮置的。在這種加偏壓條件下,儲存於胞A的資訊會被 讀取。 胞B的捕捉層被程式化在右側。因此,在捕捉層中的 電子分佈是在右側低但在左側高。因為對應於胞6左側之 位元線BL1是浮置的,所以胞β中的電場不足以引起位元線 BL1與BLj間經過胞Β的漏電流。同樣地,胞c在捕捉層右側 不會有高電子密度,且因此也有一降低的漏電流。10500twf.ptd Page 16 1220253 V. Description of the Invention (ίο) The parent cross of the line and the bit line (intersecti ο η) defines several memory cells, each memory cell corresponds to a word line and a pair of bit lines . Figure 3 also indicates a data pattern in which consecutive rows of memory cells are stylized on the alternating side of the capture layer. In particular, for example, a first row of memory cells located between bit lines BL1 and BL2 is stylized to the right of the capture layer, and a second row of memory cells located between bit lines BL2 and BL3 is stylized at A third row of the left side of the capture layer and a memory cell located between the bit lines BL3 and BL4 is privatized on the right side of the capture layer. When the thermoelectron tunnels into the right side of the capture layer of the memory cell and is stored at this time, the memory cell is defined as “programmed on the right side”. However, it can be seen that "left side" and "right side" are only relative terms according to the configuration of the memory cell, and this term can be replaced without affecting the function of the memory cell. Please refer to FIG. 3 again, and the cell A corresponding to the word line WL3 and the bit lines 虬 2 and bL3 is selected by biasing the corresponding word line and bit line. In particular, the word line WL3 is biased to 3V, the bit line BL2 is biased to 0.3 V, and the bit line BL3 is biased to 1.5 V. The word lines WL1, WL2, W4, L4, WL5 and WL6 are grounded, and the bit lines BL1, 4 and 5 are unbiased or floating. Under this bias condition, the information stored in cell A will be read. The capture layer of cell B is stylized on the right. Therefore, the electron distribution in the capture layer is low on the right but high on the left. Because the bit line BL1 corresponding to the left side of the cell 6 is floating, the electric field in the cell β is not sufficient to cause a leakage current through the cell B between the bit lines BL1 and BLj. Similarly, cell c will not have a high electron density on the right side of the capture layer, and therefore will also have a reduced leakage current.

1220253 五、發明說明(ll) 因為位元線BL1與BL2間記憶胞的漏電流被降低,所以 讀取記憶胞A可藉著測量或感測流經取代位元線BL3之位元 線B L 2的電流,以降低感測錯誤(s e n s i n g e r r 〇 r )。換句話 說,讀取記憶胞可藉著感測流經位於與記憶胞之被編程側 相同側的一位元線的電流。舉例來說,於第3圖中,胞a被 程式化至左侧,且可藉感測存在於位元線BL2上的電流而 被讀取,位元線BL2也在胞A的左側。1220253 V. Description of the invention (ll) Since the leakage current of the memory cell between bit lines BL1 and BL2 is reduced, reading memory cell A can measure or sense the bit line BL 2 flowing through the bit line replacing the bit line BL3. Current to reduce sensing errors (sensingerr 〇r). In other words, reading the memory cell can sense the current flowing through a bit line on the same side as the programmed side of the memory cell. For example, in Figure 3, cell a is programmed to the left and can be read by sensing the current existing on bit line BL2, which is also on the left of cell A.

本發明的第二實施例之方法與陣列係顯示於第4圖, 其表示一不同的資料型樣,其中在一記憶陣列4 〇 〇中所有 的圮憶胞被程式化至相同側,如左側。因為前述理由,可 降低未被選擇讀取的記憶胞之漏電流。同樣地,讀取胞A 可藉著測量或感測流經取代位元線BL2之位元線虬3的電 /爪,以降低感測錯誤。換句話說,讀取記憶胞可藉著减測 流經位於與記憶胞之被編程側相反側的一位元線的電流。' =來說:於第4圖中,胞心程式化至左側,且可藉感測 =於位兀線BL3上的電流而被讀取,位元線BL3係在胞A 如前述, 本發明提供一 流0 藉由感測通過一位元線的電流,感測方法與 降低的讀取干擾相符,且其具有降低的漏電 PP — 士 t本發明已以較佳實施例揭露如上,铁豆並非用以 限定本發明,任何熟習此 ^ ^非用以 和範圍βt可作1許之更門;^脫離本發明之精神 範圍當視後附之申&真剎》R人澗飾,因此本發明之保讀 I甲明專利粑圍所界定者為準。The method and array of the second embodiment of the present invention are shown in FIG. 4, which shows a different data pattern, in which all the memory cells in a memory array 400 are programmed to the same side, as shown on the left . For the foregoing reasons, the leakage current of memory cells that are not selected for reading can be reduced. Similarly, the reading cell A can reduce the sensing error by measuring or sensing the current / claw flowing through the bit line 虬 3 instead of the bit line BL2. In other words, reading the memory cell can reduce the current flowing through a bit line on the opposite side of the programmed side of the memory cell. '= To speak: in Figure 4, the cell heart is stylized to the left and can be read by sensing = the current on the bit line BL3, the bit line BL3 is in cell A as described above, the present invention Provide first-class 0 By sensing the current passing through a one-bit line, the sensing method is consistent with reduced read interference, and it has reduced leakage PP — the present invention has been disclosed in the preferred embodiment as above, iron beans are not To limit the present invention, anyone who is familiar with this ^ ^ is not used and the range βt can be changed by 1; ^ Depart from the spirit of the present invention as the attached application & Zhencha "R person decoration, therefore The guarantee of the invention shall be as defined in the patent application.

1220253 圖式簡單說明 第1圖是習知的快閃記憶陣列之電路圖,且繪示出與 習知的快閃記憶陣列有關係的漏電問題。 第2圖是本發明之一記憶胞的剖面示意圖。 第3圖是本發明之一記憶陣列的一第一資料型樣的電 路圖。 第4圖是本發明之一記憶陣列的一第二資料型樣的電 路圖。 【圖式標示說明】1220253 Brief Description of Drawings Figure 1 is a circuit diagram of a conventional flash memory array, and illustrates the leakage problem related to the conventional flash memory array. FIG. 2 is a schematic cross-sectional view of a memory cell according to the present invention. Fig. 3 is a circuit diagram of a first data pattern of a memory array according to the present invention. FIG. 4 is a circuit diagram of a second data pattern of a memory array of the present invention. [Schematic description]

2 0 0 :記憶胞 2 0 2 :基底 2 0 4 :源極 2 0 6 :汲極 2 08 :通道區 2 1 0 :多層閘極結構 212、216 :介電層 2 1 4 :捕捉層 2 1 8 :控制閘極 A、B、C、D :記憶胞2 0 0: Memory cell 2 0 2: Base 2 0 4: Source 2 0 6: Drain 2 08: Channel area 2 1 0: Multi-layer gate structure 212, 216: Dielectric layer 2 1 4: Capture layer 2 18: Control gates A, B, C, D: Memory cells

10500twf.ptd 第19頁10500twf.ptd Page 19

Claims (1)

1220253 六、申請專利範圍 記憶1胞包發!胞的方法,"該非揮發性 該方法包括:、〃第—位元線以及一第二位元線, 程式化該記憶胞, 供應一南正偏 供應一接地偏 供應一高負偏 包括: 壓至遠第一位元線; 其中該記憶胞 極區、一通道區定義於 層被提供於該通道區上 該通道區之間,其中該 區與該沒極區其中之一 與該汲極區其中之另一 其中帶正電荷 層中。 2 ·如申請專利範圍 的方法,其中該捕捉層 留電洞。 3 ·如申請專利範圍 的方法,其中電洞穿隧 壓至4第二位元線;以及 麼至該字元線, 包括一控制閘極、一源極區、一汲 該源極區與該汲極區之間、一捕捉 以及一介電層被提供於該捕捉層與 控制閘極對應於該字元線、該源極 對應於該第一位元線以及該源極區 對應於遠第二位元線,而且 的電洞經由該介電層穿隧至該捕捉 第1項所述之操作非揮發性記憶胞 捕捉從通道區穿隧而來的電洞並保 第1項所述之操作非揮發性記憶胞 至鄰近該第一位元線之部分該捕捉 層。 4·如申請專利範圍第丨頊所述之操作非揮發性記憶胞 的方法,更包括讀取該記憶胞’包括: 供應一第四偏壓於該第’位元線上;1220253 6. Scope of patent application The method includes: a non-volatile bit line and a second bit line, stylizing the memory cell, supplying a south bias supply, a ground bias supply, and a high negative bias, including: Pressing to the far first bit line; wherein the memory cell region and a channel region are defined between the channel region on the channel region, and one of the region and the non-polar region and the drain electrode The other of the regions is in a positively charged layer. 2 · A method as claimed in the patent application, wherein the capture layer has holes. 3. The method as claimed in the patent application, wherein the tunneling tunneling voltage is 4 to the second bit line; and the word line includes a control gate, a source region, a source region and a source region. Between the polar regions, a capture and a dielectric layer are provided in the capture layer and the control gate corresponds to the word line, the source corresponds to the first bit line, and the source region corresponds to the far second Bit line, and the hole is tunneled through the dielectric layer to the operation described in item 1 of capturing the non-volatile memory cell, which captures the hole tunneled from the channel region and guarantees the operation described in item 1 Non-volatile memory cells to the capture layer adjacent to the first bit line. 4. The method for operating a non-volatile memory cell as described in the scope of the patent application, further comprising reading the memory cell ', comprising: supplying a fourth bias voltage to the bit line; 1220253 六、申請專利範圍 ;# ^ 供應〆第五偏壓於該第二位、、泉上;以及 供應一第六偏壓於該字元線上。σ 5如申請專利範圍第4項所述之知作非揮發性記憶胞 的方法,其中該第六偏壓的電廢值而於該第四偏壓的電壓 值及該第五偏壓的電壓值。 、 口 6.如申請專利範圍第1項所述之操作非揮發性記憶胞 的方法,更包括測量流經該記憶胞的一電流,以決定其狀 態。 7 · 一種操作快閃記憶胞的方法’其中該快閃記憶胞包 括一第一位元線、一第二位元線以及一字元線,該方法包 括: 抹除該記憶胞’包括: 供應一第一偏壓至該第一位元線; 供應一第二偏壓至該第二位元線; 供應一第三偏壓至該字元線, 其中該記憶胞包括一源極、一汲極、一通道區定 義於該源極與該汲極之間、一第一介電層形成於該通道區 上、一捕捉層形成於該第一介電層上、一第二介電層形成 於該捕捉層上以及一控制閘極形成於該第二介電層上,其 中该控制閘極對應於該字元線、該源極與該没極其中之一 對應於該第一位元線以及該源極與該汲極其中之另一對應 於該第二位元線,以及 其中該第一、第二以及第三偏壓係被選擇以使電 子經由該第一與第二介電層其中之一穿隧至該捕捉層中。1220253 VI. Patent application scope; # ^ supply a fifth bias voltage to the second position, the spring; and supply a sixth bias voltage to the character line. σ 5 The method known as a non-volatile memory cell as described in item 4 of the scope of patent application, wherein the electrical waste value of the sixth bias voltage is the voltage value of the fourth bias voltage and the voltage of the fifth bias voltage value.口 6. The method for operating a non-volatile memory cell as described in item 1 of the scope of the patent application, further includes measuring a current flowing through the memory cell to determine its state. 7. A method of operating a flash memory cell, wherein the flash memory cell includes a first bit line, a second bit line, and a word line, the method includes: erasing the memory cell, including: supplying A first bias voltage to the first bit line; a second bias voltage to the second bit line; a third bias voltage to the word line, wherein the memory cell includes a source, a drain And a channel region are defined between the source and the drain, a first dielectric layer is formed on the channel region, a capture layer is formed on the first dielectric layer, and a second dielectric layer is formed A control gate is formed on the capture layer and on the second dielectric layer, wherein the control gate corresponds to the word line, and one of the source and the non-pole corresponds to the first bit line. And the other of the source and the drain correspond to the second bit line, and wherein the first, second, and third bias systems are selected so that electrons pass through the first and second dielectric layers One of them tunnels into the capture layer. 10500twf.ptd 第21頁 122025310500twf.ptd Page 21 1220253 •如申請專利範圍第7項所述之操作快閃記憶胞的方 其中該捕捉層包括一氮化物。 ^ 9 ·如申請專利範圍第7項所述之知作快閃記憶胞的方 二’其中該第一偏壓與該二偏壓具有一電壓值高於該第二 偏壓的電壓值。 法,1〇·如申請專利範圍第7項所述之操作快閃記憶胞的方 二 其中該第一偏壓與該二偏壓都是高正電壓,以及爷第 二偏壓是一高負偏壓。 〜 法,1 1 ·如申請專利範圍第7項所述之操作快閃記憶胞的方 更包括程式化該記憶胞,包栝: 供應一第四偏壓於該第一位元線上; 供應一第五偏壓於該第二位元線上; 供應一第六偏壓於該字元線上, 芦“中该第六偏壓的電壓值低於該第四及第五偏壓的電 法,1 2·如申請專利範圍第7項所述之操作快閃記憶胞的方 更包括讀取該記憶胞,包括: 供應一第七偏壓於該第一位元線上; 供應一第八偏壓於該第二位元線上; 供應一第九偏壓於該字元線上, 含/中°亥第九偏壓的電壓值高於该苐七偏壓的電壓值及 μ弟八偏壓的電壓值。 1 3 · 一種記憶元件的操作方法,包括: 提供一記憶陣列包括多數個記憶胞,其中該些記憶胞• The method for operating a flash memory cell as described in item 7 of the scope of the patent application, wherein the capture layer includes a nitride. ^ 9 The second method known as a flash memory cell as described in item 7 of the scope of the patent application, wherein the first bias voltage and the second bias voltage have a voltage value higher than the second bias voltage value. 10. The second method of operating a flash memory cell as described in item 7 of the scope of the patent application, wherein the first bias voltage and the second bias voltage are both high positive voltages, and the second bias voltage is a high negative voltage. bias. ~ Method, 1 1 · The method of operating the flash memory cell as described in item 7 of the scope of the patent application further includes stylizing the memory cell, including: supplying a fourth bias voltage to the first bit line; supplying a A fifth bias voltage is on the second bit line; a sixth bias voltage is supplied on the word line, and the voltage value of the sixth bias voltage is lower than that of the fourth and fifth bias voltages, 1 2. The method of operating a flash memory cell as described in item 7 of the scope of patent application further includes reading the memory cell, including: supplying a seventh bias voltage to the first bit line; supplying an eighth bias voltage to The second bit line; a ninth bias voltage is supplied on the word line, and the voltage value of the ninth bias voltage including / middle ° is higher than the voltage value of the 27th bias voltage and the voltage value of the μ bias voltage 1 3 · A method for operating a memory element, comprising: providing a memory array including a plurality of memory cells, wherein the memory cells 第22頁 六 申請專利範圍 被多數個列與多數個行定義; 中之?供2:f線j每-該些字元線對應於該些列其 # :母一该些記憶胞對應於一字元線; 中之一 ’、=數個位兀線,每一該些位元線對應於該些行其 一办_ 中每一該些記憶胞對應於一第一位元線與一第 一位凡線;以及 、 程式=該些記憶胞中之至少一記憶胞,包括: 供應一第一偏壓於被程式化的該至少一記憶胞的 3第一位元線上; 供應一第二偏壓於被程式化的該至少一記憶胞的 4第二位元線上;以及 供應一第三偏壓於被程式化的該至少一記憶胞的 該字元線上, 其中該第三偏壓的電壓值低於該第一及第二偏壓 的電壓值。 1 4 ·如申請專利範圍第1 3項所述之記憶元件的操作方 法,其中每一該些記憶胞包括一通道區定義於源極與汲極 之間、一捕捉層被提供於該通道層上以及一介電層被提供 於該捕捉層與該通道層之間,而真其中帶正電荷的電洞經 由該介電層穿隧至該捕捉層中。 1 5·如申請專利範圍第丨3項所述之記憶^件的操作方 法,更包括讀取該些記憶胞中之I少忑匕胞’包括: 供應一第四偏壓於被讀取的該裏乂 °己丨思胞的該第一 位元線上;Page 22 VI. The scope of patent application is defined by most columns and rows; For 2: f line j each-the character lines correspond to the columns and #: mother-the memory cells correspond to a character line; one of the ', = several bit lines, each of these The bit lines correspond to each of the rows, each of the memory cells corresponds to a first bit line and a first bit line; and, program = at least one memory cell of the memory cells, The method includes: supplying a first bias voltage to the 3 first bit lines of the at least one memory cell being programmed; supplying a second bias voltage to the 4 second bit lines of the at least one memory cell being programmed; And supplying a third bias voltage to the word line of the at least one memory cell that is programmed, wherein the voltage value of the third bias voltage is lower than the voltage values of the first and second bias voltages. 1 4 · The method of operating a memory element as described in item 13 of the scope of the patent application, wherein each of the memory cells includes a channel region defined between a source and a drain, and a capture layer is provided on the channel layer An upper layer and a dielectric layer are provided between the capture layer and the channel layer, and the positively charged holes therein are tunneled into the capture layer through the dielectric layer. 15. The method for operating the memory device described in item 3 of the scope of the patent application, further including reading the I cells in the memory cells, including: supplying a fourth bias voltage to the read cells. The first place is on the first bit line; l〇50〇twf.ptd 第23貢 1220253 六、申請專利範圍 供應一第五偏壓於被讀取的該至少一記憶胞的該第二 位元線上;以及 供應一第六偏壓於被讀取的該至少一記憶胞的該字元 線上’ 其中該第六偏壓的電壓值高於該第四及第五偏壓的電 壓值。 1 6.如申請專利範圍第1 3項所述之記憶元件的操作方 法,其中該記憶陣列係一虛擬接地記憶陣列。 1 7.如申請專利範圍第1 3項所述之記憶元件的操作方 法,更包括抹除該些記憶胞中之至少一記憶胞,包括: 供應一第七偏壓於被抹除的該至少一記憶胞的該第一 位元線上; 供應一第八偏壓於被抹除的該至少一記憶胞的該第二 位元線上; 供應一第九偏壓於被抹除的該至少一記憶胞的該字元 線上, 其中該第九偏壓的電壓值低於該第七及第八偏壓的電 壓值。 1 8.如申請專利範圍第1 3項所述之記憶元件的操作方 法,其中該記憶元件包括一基底,其中該些位元線係形成 於該基底中的埋入擴散區,以及該些字元線包括形成於該 基底上的接觸條,以及其中在同一行的該些記憶胞共用至 少一位元線,且在同一列的該些記憶胞共用至少一字元 線。l05050twf.ptd 23rd tribute 1220253 6. The scope of the patent application supplies a fifth bias voltage to the second bit line of the at least one memory cell being read; and a sixth bias voltage to be read The word line of the at least one memory cell is taken, wherein the voltage value of the sixth bias voltage is higher than the voltage values of the fourth and fifth bias voltages. 16. The method for operating a memory element according to item 13 of the scope of the patent application, wherein the memory array is a virtual grounded memory array. 1 7. The method of operating a memory element as described in item 13 of the scope of patent application, further comprising erasing at least one memory cell of the memory cells, including: supplying a seventh bias voltage to the erased at least one Supply an eighth bias voltage to the second bit line of the at least one memory cell that is erased; supply a ninth bias voltage to the at least one memory that is erased On the word line of the cell, the voltage value of the ninth bias voltage is lower than the voltage values of the seventh and eighth bias voltages. 1 8. The method of operating a memory element according to item 13 of the scope of the patent application, wherein the memory element includes a substrate, wherein the bit lines are formed in a buried diffusion region in the substrate, and the characters The element line includes a contact bar formed on the substrate, and the memory cells in the same row share at least one bit line, and the memory cells in the same column share at least one word line. 10500twf.ptd 第24頁 1220253 六、申請專利範圍 1 9.如申請專利範圍第1 3項所述之記憶元件的操作方 法,其中在連貫的該些行中的該些記憶胞被程式化於該捕 捉層的交替側邊中。 2 0.如申請專利範圍第1 9項所述之記憶元件的操作方 法,更包括讀取該些記憶胞中之至少一記憶胞,其中讀取 該至少一記憶胞包括感測經過該位元線的一電流,該位元 線即位於該至少一記憶胞如該程式化側邊的同一側邊上。 2 1.如申請專利範圍第1 3項所述之記憶元件的操作方 法,其中在該記憶陣列中的所有該些記憶胞被程式化於該 捕捉層的同一侧上。 2 2.如申請專利範圍第2 1項所述之記憶元件的操作方 法,更包括讀取該些記憶胞中之至少一記憶胞,其中讀取 該至少一記憶胞包括感測經過該位元線的一電流,該位元 線係位於相對於該至少一記憶胞之該程式化側邊的該至少 一記憶胞之一侧邊上。10500twf.ptd Page 24 1220253 6. Application for patent scope 1 9. The operation method of the memory element as described in item 13 of the scope of patent application, wherein the memory cells in the consecutive rows are stylized in the Snap layers in alternating sides. 20. The method for operating a memory element according to item 19 of the scope of patent application, further comprising reading at least one memory cell of the memory cells, wherein reading the at least one memory cell includes sensing passing through the bit. A current of the line, the bit line is located on the same side of the at least one memory cell as the stylized side. 2 1. The method of operating a memory element as described in item 13 of the scope of patent application, wherein all the memory cells in the memory array are programmed on the same side of the capture layer. 2 2. The method of operating a memory element according to item 21 of the scope of patent application, further comprising reading at least one memory cell of the memory cells, wherein reading the at least one memory cell includes sensing passing through the bit A current of the line, the bit line is located on one side of the at least one memory cell opposite to the stylized side of the at least one memory cell. 10500twf.ptd 第25頁10500twf.ptd Page 25
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