TW578379B - Level shifting circuit - Google Patents

Abstract

A kind of level shifting circuit having plural transistors for outputting the corresponding signal level based on the inputted differential signal pair. The enable control circuit is coupled to the inner transistor of the level shifting circuit for outputting the enable signal to control the action of the level shifting circuit. When the enable signal is in the first level, the level shifting circuit operates normally. When the enable signal is in the second level, the level shifting circuit enters a waiting state, and only a single signal level is outputted without being influenced by the inputted differential signal pair.

Description

578379 V. Description of the invention (1) [Technical field to which the invention belongs] A kind of level shift circuit ', in particular, a level shift circuit for controlling the page. [Prior art] The entire voltage circuit (le'el shifting curcuit) is used to adjust the U.S. patent series' to make the voltage suitable for specific components. Figure 系 shows the traditional level shift circuit disclosed in the case of the display: Two ΓΗ cases. The control level shift circuit selects to output a low level signal or a high level signal. The conventional level shift circuit includes a PM0S transistor connected to the power supply VDD (for example, 9V), and Y1, which breaks xvln and Vin, and the transistors N1 and N1 are coupled to the power supply VDD, and its source is Coupled to the other two transistors, N_M () S transistor P1, the poles = are coupled to each other, and the connection point is the output terminal xvout / series, the transistor P1, the poles are lighter than each other Then, and. The output terminals vout and xvout are lightly connected to the amplifiers 10A and 10B as buffers, respectively, for outputting corresponding voltage levels. When XVin is at the high level, the signal level of Vin is at the low level, and the PMOS transistor P1 is turned on. Therefore, the output ^ high level is output, and the low level signal is output through the inverter m. Since the above 1 0632-8926TWf (nl); AU91215; Robert.ptd page 5 578379 V. Description of the invention (2) '一 " Transistors N1 and N1 are kept on, so the voltage output by the output terminal XVout is Low level, and output high level signal via inverter 10B. On the contrary, when XV i η is at a low level, the signal level of V i η is at a high level, and at this time, the pmos transistor P1 is turned on. Therefore, the voltage output from the output terminal XVout is at the south level, and via the inverter 1 0B Output low level signal. Since the off transistors N1 and M are kept on, the voltage output from the output terminal vout is at a low level, and a high level signal is output through the inverter 10A. In addition, by designing the inverters 10A and 10B, the output of the level shift circuit can be made more stable. When the voltage level output from the output terminal yout is lower than the threshold voltage of the inverter 10 A, the inverter outputs a high level signal; the voltage level output from the output terminal Vout is higher than the inversion The arrival of the device 10A. In the case of the voltage field, the inverter 10A outputs a low level signal. Similarly, when the voltage level output by the output terminal xv〇ut is lower than the threshold voltage of the inverter 10B, the inversion fi0B outputs a high level signal; when the voltage level output by the output terminal xv〇utm = At the threshold voltage of the inverter 10B, the inverter 丨 〇B outputs a low level signal. However, since the power VDD is fixedly supplied to the gate of _s N1, the NM0S transistor N1 is referred to as ^ and the package Every day, Nichi 1 and N1 are narrated by Bao. The greedy, quasi-shift circuit only fell to the right seven J N Tochigi at a specific time, such as the differential little news song χ v ·

When Vin is only a pulse of a specific period, if the basin bluffs ^ ⑺ to ^ τ to the right, there are thousands of noise NMOS transistors N1 and N1 at the other source, then prepare the anvil > Λ 卞 silly question Ub action . Will cause the level shift circuit to malfunction.

V. Description of the invention (3) Figure 2 shows another list

The gate of transistor P10 is connected to the circuit diagram of the circuit. PMOS power supply VDD m) qPMOS power source is connected to the drain of external body P10 and connected to Γ = body? The source of 12 is coupled to the PMOS transistor holder, and the η connection point is labeled 丨 2. The PMOS, P1, P9, and P10 poles and the drain are coupled to each other, and the drain of NMOS P12 and the drain of N10 are coupled to the connection section 4 as "labeled". NMOS transistor input XVin, and the gate is lightly connected to the connection, and the gate is coupled to the PM0S transistor =. 〇S transistor P14 contact (connection node "), and 3 = S transistor N10 non-connected output terminal is lightly connected to PM0S transistor P14. Μ ^-A ^ v. Contact. NMOS transistor The source of Ν12 is coupled to the input i ^ vin, and the gate is coupled to the connection node 12. The level shift circuit shown in Figure 2 operates as follows: The signal levels of vln & xVin are mutually It is inverted. When yin is high (take 3.3V as an example), the signal level of XVin is low. Due to the voltage level (9V) of the external power supply VDD and the high level signal provided by the input terminal ⑴ ( The potential difference of 3.3V) is higher than the threshold voltage (about 2.5V) of the pMOS transistor ρ. Therefore, the PMMOS transistor ρ is turned on. It can be found here that regardless of the signal level provided by the input terminal Vin Why 'As long as it is in the range of 0-3 · 3V, the pM0s transistor P10 will be turned on. The PM0S transistor Pi0 after the turn-on will cause the voltage level of the connection node 12 to rise'. Therefore, NM0S transistor N10 It is also connected to N12. Then, the low level signal provided by the inverting input terminal XVin passes through the problem of conduction. Body 0632-8926TWf (nl); AU91215; Robeitptd Page 7 578379 V. Description of the invention (4) N10 reduces the voltage level of the connection node 14 and causes the PM0 transistor P14 to be turned on. Because the PMOS transistor is at this time Both P14 and NMOS transistor N1 2 are turned on. According to the voltage division principle, the voltage value output from the output terminal is determined by the impedance value of pM0s transistor P1 4 and N M 0 S transistor N1 2 at this time. Therefore, generally The level of the high-level signal output from the output terminal will be controlled by adjusting the impedance value of the PMOS transistor P1 4 and the NMOS transistor N1 2 so that the output terminal Vout will output a VDD voltage close to 9V. Similarly, adjust the voltage The crystal impedance can be changed by changing the input gate voltage, or by changing the size of the transistor to achieve 0. Crystal N1 2 keeps conducting and the quasi signal is transmitted to the output terminal state. Vout When Vin is low, due to the power off, The low level 'provided by the input terminal V i η causes it to output a low level signal. However, in practical application ±, the (in the figure at the input terminal Vln and the inverting input terminal XVln are transmitted through the control signal / t differential signal pair Affected. That, when there is the idle control actuator "Tiger nervous to enter the malfunction level shift circuit to level shift circuits. John an irrigation discharge hole, making

578379 V. Description of the invention (5) [Summary of the Invention] In view of this, in order to solve the above problem, the United States provides a position with enabled control, the purpose is to ensure that the level circuit + 2 when the bit circuit is in standby . Do not cause malfunction due to noise interference To & achieve the above purpose, the present invention proposes a level shifting Thunderbolt-PMOS transistor, which is coupled to a shift: circuit. ; On the first source and the first pole of the power supply. Second =; =, the surface has a second pole connected lightly to the first pole, and the surface has two questions: _ transistor, which has a light connection to the second source pole ;; Chu power supply The third source electrode and the idler electrode connected to the output terminal, the fourth drain electrode connected to the second source electrode and the light source fourth source electrode. The third delete transistor has light five = Yu; the fifth terminal of the outgoing terminal and the second terminal of the seventh terminal: and the second seventh terminal of the second terminal and the seventh source terminal connected to the ground. The enable signal supply circuit is used to signal, when the enable signal is at a high voltage level, the m level. From the gate to the early f, the output terminal outputs a predetermined voltage 0632-8926TWf (nl); AU91215; Robeit.ptd Page 9 578379 5. Description of the invention (6) In addition, the present invention proposes a bit body having a coupling to an enable signal The first pole and the first drain pole. The second PMOS power source has a second source electrode, a second gate electrode, and a second PMOj transistor having a third source electrode coupled to the second source and a fourth source electrode coupled to the output crystal having a fourth source electrode coupled to the first drain electrode. The drain and the inverting input transistor have a fifth drain coupled to the first drain and the non-inverting input transistor has a sixth drain coupled to the enable signal and coupled to The ground-level crystal has a seventh drain coupled to the enable signal and a ground-level circuit 'to provide the enable signal, and the output terminal outputs a predetermined voltage level. [Embodiment] The first embodiment: FIG. 3 is a circuit configuration diagram of a bit shift circuit according to the first embodiment of the present invention. The gate of the PM0s transistor p20 is coupled to the enable signal ENB provided by the external enable control circuit 21, and the source is connected to the external power supply VDD (about 9V). The drain of NM0S transistor N20 is connected to the intervening pole, and is coupled to the drain of PM0s transistor p20. The connection node is a quasi-shift gate, and the crystal is the fourth one at the end of the second drain. The fifth enable signal, the sixth enable signal, the seventh enable signal, and the seventh enable signal circuit. Lightly connected to the third gate with a transfer gate, three sinks, coupled to the fourth source, light fifth source, six-source, transfer source. No. High The first source of the first PM0S transistor is the second source of the first source. The first pole is coupled to electricity. The first NMOS is electrically connected to the second drain. The second NMOS is connected to the output terminal. The third NMOS is connected to the second gate. The fourth NMOS is at the voltage level of the enable signal supply voltage of the first drain, 〇632-8926TWf (nl); AU91215; Robeit.ptd Page 10 578379 5. Description of the invention (7) The pole j # NAM〇S The drain of the crystal N22 is coupled to the source of the NMOS transistor N2G.The connection point is 24, and its source is connected to the inverting input. The gate is coupled to the connection node 22 ° PM0S transistor P22. Gate 1 = to the source of the long transistor N20 and the drain VDD of the transistor N22. Point (connection node 24), and the source is coupled to an external power source In addition, the output terminal Vout of the level shift circuit is coupled to the drain connection of KpM0S, -2 ^ NM〇S transistor N24 point. The NMOS transistor N24 has a pole coupled to the input terminal y i n and a gate coupled to the connection node M. = ^: The gates of the NM0S transistor N26 and the NMOS transistor N28 are both coupled to the ENB ′ and the source is coupled to the ground level. The drain of the transistor N26 is coupled to the connection node 24, and the drain of the transistor N28 is coupled to the connection node 22. According to the level shift circuit according to the first embodiment of the present invention, the circuit operation is as follows: First, when the enable signal ENB is at a low level, the level shift circuit is in an operating state at this time. Here, the NMOS transistors N26 and N28 have been turned off by the enable signal ENB, and the pMOS transistor P20 is turned on. The PMOS transistor ^ P20 after the turn-on will increase the voltage level of the connection node 22, so the NMOS transistor N22 and N24 are also turned on. Then, the signal provided by the inverting input terminal XVin is at a low level, and since the PMOS transistor P20, NMOS transistor N20, and N22 are all turned on, the impedance values of the PMOS transistor P20 and the NMOS transistor N20 and 22 are adjusted. That is, the level of the low-level signal output from the connection node 24 can be controlled, and the PMOS transistor P22 is turned on. Here, the transistor impedance is adjusted.

0632-8926TWf (nl) * AU91215 Robert.ptd page 11 578379 5. The method of the invention description (8) can be achieved by changing the size of the transistor. Similarly, since the PMOS transistor P22 and the NMOS transistor N24 are both turned on at this time, according to the voltage dividing principle, the voltage value output by the output terminal Vout is determined by the PMOS transistor P22 and the NMOS transistor N24 at this time. The impedance value, therefore, by adjusting the impedance values of the PMOS transistor P22 and the NMOS transistor N24 to control the level of the high-level signal output from the output terminal Vout, the output terminal Vout can output a VDD voltage close to 9V. Here, the way to adjust the transistor impedance can be achieved by changing the voltage of the input gate, or changing the size design of the transistor. sVin is the low-level quasi-day guard; χΗη is the south-level. Since the nmos transistor = 4 and the N22 system are kept on, and the pMos transistor p22 is close to the off state, the low level signal provided by the input Vin is transmitted to the output Vout to cause it to output a low level signal. When the enable signal ENB is at a high level ', the level shift circuit is in a standby state. Here, the NMOS transistors N26 and N28 are turned on by the enable signal ENβ. Therefore, the levels of the connection nodes 22 and 24 are pulled down to the low level. Therefore, == fN22 and N24 are both closed, so the differential signal pair cannot enter the position through the electric sun body N 2 2 and N 2 4 ^ r »/, ,,,, and 4 are used to shift the eight-phase dry shift circuit, and at this time the pMOS transistor ^ 1 is turned on because the mountain is the ancient connection section Λ24 is low / level, so the output Vout is fixed = drama: level The chemistry number 'is not affected by the level of the differential signal pair received at the input Vin and the inverting input χ ~. # To avoid the input of noise, page 12 0632-8926TWf (nl); AU91215; Robeit. ptd 578379 V. Description of the invention (9) Operation error of the level shift circuit The first embodiment is shown in Fig. 4. Fig. 4 shows a circuit structure diagram of the level = bit circuit according to the second embodiment of the present invention. The gate of the PM0s transistor p30 is coupled to the enabling signal ENB provided by the enabling control circuit 31 of the evening part, and the source is coupled to the external power supply VDD (9V). The pM0s transistor ΪsourceΪρΐ is connected to the drain of the PMOS transistor P30, and the connection node is labeled 2. The gate and the drain of the PMOS transistor P32 are coupled to each other. The drain of the NMOS transistor N30 is coupled to the connection node: its source is connected to the inverting input XVin, and the gate is connected to the junction 32. The gate of the PMOS transistor P34 is coupled to the pMOS transistor p = "nmos transistor N30's drain connection point (connection node 34), and the source is connected to the external power contact. In addition, the bit The output terminal V Quat of the quasi-shift circuit is coupled to the drain of PMOS transistor p34 and the gate transistor M〗. The source of NMOS transistor N32 is connected to the input terminal Vin and the gate. The pole is stolen: ΪίΪΓ2. In addition, the _S transistor N34_〇S transistor N36 J gate is white-coupled to the enable signal ENB 'and the source is coupled to the ground ^ 没 N-terminal of the transistor N34 To the connection node 34, and the drain of the transistor N36 is coupled to the connection node 32. The level shift operation according to the second embodiment of the present invention is as follows: Electricity 1: Road First, when the enable signal ENB is When the level is low, the level shifter is at this time. Page 1332-8926TWf (nl); AU91215; Robert.ptd 578379 V. Description of the invention (10) The circuit is in the operating state. Here, NMOS transistors N34 and N36 have been caused. The energy signal ENB is turned off, and the pMOS transistor P30 is turned on. When it is at a high level (taking 3 · 3 V as an example), the level of the X 彳 § number is the low level The p% $ transistor P30 after the turn-on will increase the voltage level of the connection node 32, so the NMOS transistor N30 and N32 are also turned on. Then, the signal provided by the inverting input terminal XVin * is a low level, And because the PMMOS transistor P30 and P32, and the NMOS transistor N30 are all turned on, therefore, the connection node 34 can be controlled by adjusting the impedance values of the pMOS transistor p30 and? 32, and the NMOS transistor N30. The level of the low level signal is output, which causes the PMOS transistor P34 to be turned on. Here, the way to adjust the transistor impedance can be achieved by changing the size of the transistor. Compared to the same, because PMOS transistor P34 and NMOS at this time Transistor N32 is white-on. According to the voltage division principle, the voltage value output by the output terminal V 0ut is determined by the resistance value of the ^ MOS transistor P34 and the NMOS transistor N32 at this time. Therefore, the PMOS transistor P34 is adjusted by 5 weeks. And the resistance of the NMOS transistor N32 and controlling the level of the high level signal output from the output terminal Vout can make the output terminal Vout output close to the VDD voltage of 9V. Here, the way to adjust the transistor impedance is to use only the input gate Voltage Or change the design of the transistor scale to achieve. When Viri is low, XVin is high. Because the NMOS transistor NjO and N32 series are kept on, and the pMos transistor p34 is close. Therefore, the input terminal The low level signal provided by V1 n is transmitted to the wheel output terminal V 0ut 'to output a low level signal.

578379 V. Description of the invention (11) = Enable signal ENB is high level +, at this time, the level shift circuit is in standby state m. Here, the NMOS transistors N34 and N3β are turned on by the enable signal EM. Therefore, the level of the connection nodes 32 and 34 is pulled down to a low level. Because the crystals 0 and 32 are both closed, the differential signal pair cannot enter the level shift circuit through Λ and N32. At this time, the EEG crystal is fixed. Output the high level signal, which is not affected by the level difference of the received differential signal pair. The level shift circuit operates incorrectly. The input Vin and the inverting input XVin ring 'to avoid noise input and f-Λ * The connection node 34 is turned on for the low-level parameter, and therefore the position of the output terminal: Therefore, according to the embodiment of the present invention, it has an enabling control circuit, which ensures that the level-shift circuit is in standby by the uniform energy signal and the opening of the ground. In the state, even if the leakage is caused by the miscellaneous brake, the malfunction will still not occur. ', ^ Although the present invention is disclosed in the preferred embodiment as above, the scope of the present invention is' anyone who is familiar with this to limit the scope of protection should consider the attached application applicant's present invention 0632-8926TWf (nl) i AU91215 »Robert , ptd j103 I y

In order to make the above-mentioned following of the present invention a preferred embodiment: the features, advantages, and advantages can be more clearly understood, and in accordance with the accompanying drawings, a detailed description is illustrated as an illustration: FIG. 1 shows a transmission # &. m _, the circuit structure of the first level shift circuit _. The figure shows the circuit structure of another level shift circuit. FIG. Is a circuit diagram showing a level shift circuit according to the first embodiment of the present invention. Fig. 4 is a circuit diagram showing a level shift circuit according to a second embodiment of the present invention.

Explanation of symbols: 1 0 A, 1 〇 B ~ inverter; 12, 14, 22, 24, 32, 34 ~ connection node; 2 1, 31 ~ enable control circuit; ENB ~ enable signal; N1 > ΝΓ , N10, N12, N20, N22, N24, N26, N28, N30, N32, N34, N36 ~ NMOS transistors;

PI, P1 ', P10, P12, P14, P20, P22, P30, P32, P34 ~ PMOS transistors; V i η ~ input terminal; XVin ~ inverting input terminal; VDD ~ power supply;

Vout ~ output.

0632-8926TWf (nl); AU91215; Robeit.ptd page 16

Claims (1)

^ 、 Applicable patent scope1. A level shift circuit, including a brother PMOS transistor, with a gate and a wheel connected to one of the power sources f = No. 1-1 first NMOS The transistor has a coupling ^ # second drain; a source two gates, and I are connected to one of the above second electrodes, and [= 了 = one of the first electrodes; first and> electrodes, and one The first and second PMOS transistors have three idle poles and are connected to the above power source: one of the second source terminals and the third non-polar terminal; the rt source and the four gates coupled to the -wheel out : The fTs transistor, which is coupled to the second closed-pole-one of the inverting input signals, the fourth source: the younger brother of the pole, the four poles and connected to-Wumen: the third delete transistor, with light Connected to the fifth source of one of the second gate-phase input signals and connected to the fourth positive NMOS transistor, which has six poles coupled to the third idle pole and ten = Ground level-the sixth source; "the first and the seventh pole and coupled to-a fifth NMOS transistor, which has seven gates coupled to the second idle pole—m JU of One of said ground idle position registration seventh source electrode 2 and a brother seven and coupled to the said actuator: No. 1 to provide the above-described circuit Ϊΐ enable signal when the pressure level. When the electric sink is dry ’, the above output terminal outputs- 578379 ——---- 6. Scope of patent application 2. As mentioned in the patent application scope, the above-mentioned transistors are all thin-film transistors: of which, quasi-shift circuits, of which TFT). Next Day Solar (Thln Film Transistor, 3 · — a level shift circuit, including · · a first PMOS transistor with a gate, coupled to one of a power source first; a 5-energy signal A first one 筮 -PMN 赍 赍 μ source and a first drain; the first PMOS electric solar body has a coupling-two sources, a first-intertemporal I coupled to one of the above-mentioned one-drain The first pole; the second gate is connected to one of the second electrodes, and the second PMOS transistor has a light-, two-gate, and one chip coupled to the power source; one of the L-drain The first terminal is the third drain; the second source is coupled to an output and the first NMOS transistor, and the right and left electrodes are connected to the second terminal;-of-the inverting input signal One of the fourth source; / ♦ and coupled to one or five gates: the N: 0S transistor 'has the fifth coupled to the -drain-the fourth phase of the input-the set + ^ 徇 out of the fifth The drain and a fifth source coupled to a phase turn-in; the gate: fN: transistor 'has a light-ground connection to one of the above-mentioned enabling signals-the sixth source , Pole; ^, and pole and surface are connected to a seventeen ^ Γ secret transistor 'has been connected to one of the above enabling signals, lightly connected to the first drain-seventh ... and surface connected to = escape One of the seventh source of the ground level; and page 18, 0632-8926TWf (nl); AU91215; Robeit.ptd 578379 6. Patent application scope uniform energy signal supply circuit, used to provide the above enable signal, when the above enable When the signal is at a high voltage level, the above output terminal outputs a predetermined voltage level. 4. The level shift circuit as described in item 3 of the patent application range, wherein the above transistors are thin film transistors (Thin Film Transistor) , TFT). 0632-8926TWf (nl); AU91215; Robert.ptd page 19