TW550446B - Internal clock generation circuit - Google Patents

Internal clock generation circuit Download PDF

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Publication number
TW550446B
TW550446B TW089104574A TW89104574A TW550446B TW 550446 B TW550446 B TW 550446B TW 089104574 A TW089104574 A TW 089104574A TW 89104574 A TW89104574 A TW 89104574A TW 550446 B TW550446 B TW 550446B
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TW
Taiwan
Prior art keywords
delay
delay line
internal clock
signal
circuit
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TW089104574A
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Chinese (zh)
Inventor
Takako Kondo
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Oki Electric Ind Co Ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

The invented internal generation circuit is used for synchronously operating a system clock of synchronous semiconductor device. The internal generation circuit includes plural delay lines; and each of the delay lines has different delay steps. Therefore, the internal generation circuit can provide internal clock generation circuit, avoid the chip size increase, and generate an internal clock having wide frequency range.

Description

550446 5〇36pifl.doc/〇〇8550446 5〇36pifl.doc / 〇〇8

Λ7 \M 經濟部智慧財產局員工消費合作社印製 五、發明說明() 本發明是有關於一種內部時脈產生電路,且特別是 有關於一種同步半導體裝置內之內部產生電路,其同步操 作於系統時脈。 此申請案係相同於於1999年三月31日申請之日本 申請案號091590/1999,其標的物在此一倂做爲參考。 當成對系統加速,內部產生電路,比如鎖相迴路(PLL) 或延遲鎖迴路(DLL),係運用於同步半導體裝置內,其同 步操作於系_統時脈。 第14圖係顯示習知內部產生電路之電路圖。 內部產生電路係包括··輸入緩衝器103,其將外部信 號cpext整形(shaping)成系統時脈;延遲線102,產生延遲 時間以減少外部信號cpext與資料輸出cpout之延遲;控制電 路200,控制延遲線1〇2 ;驅動器104,放大從延遲線102 所輸出之內部時脈信號(pint;以及監控電路106,監控在 驅動器104內之延遲時間。 控制電路200係包括相位比較器100與移位暫存器 (shift-register)lOl。相位比較器100係比較輸入緩衝器103 所整形之外部信號cpext與被監控電路106所延遲並回授之 內部時脈信號(pint之相位。接著,相位比較器100偵測到 相位。接著,相位比較器1〇〇輸出偵測信號φΐ至移位靈 在显_101。移位暫存器101往上計數偵測信號φΐ並回應於 偵測信號φΐ而控制延遲線1〇2,並輸出控制信號φ2至延 遲線102。延遲線102係回應於控制信號φ2而被控制,並 調整延遲時間以減少外部信號cpext與資料輸出cpout之延 4 — — — — — — — _ — — — — I 一 δ,« — — — — — — I— I I f I I wi (請先閱讀背面之注意事項再填寫本頁) 本紙張&度適用中國國家標準(CNS)Al規烙(21〇x 297公t ) 經濟部智慧財產局員工消費合作社印製 550446 6〇36pifl.doc/008 H7 五、發明說明() 遲。 如上所述,內部產生電路可藉由對照外部信號oext 來產牛’以避免外部ί目5虎Φext與貝料輸出(pout之延遲。 第15圖係顯示習知內部產生電路之延遲線之電路 圖。 如第15圖所示,延遲線1〇2包括具有延遲線控制電 路402之複數個延遲電路202。延遲線102控制有效延遲 電路之數量,並回應於控制信號’藉由選擇TAP之一(從 TAP1至ΤΑΡη)來調整外部信號cpext。在此,延遲步階定義_ 延遲電路202之單位延遲時間。 在習知技術中,必需避免晶片尺寸之增加’且需要 產生廣頻率範圍之內部時脈。 本發明的目的之一就是在提供一種內部時脈產生電 路,其能避免晶片尺寸之增加,並產生廣頻率範圍之內部 時脈。 根據本發明的目的,爲達成上述目的,提供一種用 於同步半導體裝置內之內部產生電路,其同步操作於系統 時脈,內部產生電路包括分別具有不同延遲步階之複數個 延遲線。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 圖式之簡單說明: 第1圖係本發明第一實施例之內部產生電路之電路 5 本紙張尺度適用中國國家標準(CNS)A4規烙(210 X 297公釐) ϋ ϋ ϋ ϋ »i_i 1 ϋ VI an n ϋ ϋ · -ϋ ϋ βΜ§ 1 n n ϋ 一 I an·* I aav · am· ι 麵 «1· ϋ (JtS先閱讀背面之注意事項再填寫本頁) 550446 Λ7 經濟部智慧財產局員工消費合作社印製 6036pifl.doc/008 五、發明說明() 圖。 第2圖是本發明第一實施例之第一延遲線之電路圖。 第3圖是本發明第一實施例之第二延遲線之電路圖。 第4圖是本發明第一實施例之第一與第二延遲線之 調整範圍示意圖。 第5圖是顯示於第1圖中之本發明第一實施例之內 部產生電路之時序圖。 第6圖係本發明第二實施例之內部產生電路之電路 圖。 第7圖是本發明第二實施例之具有小延遲步階之延 遲線之電路圖。 第8圖係本發明第二實施例之監控電路之電路圖。 第9圖是本發明第二實施例之延遲步階大於其他延 遲線之第一延遲線之電路圖。 第10圖是之本發明第二實施例之內部產生電路之時 序圖。 第11圖是之本發明第二實施例之第二延遲線之操作 時序圖。 第I2圖是之本發明第二實施例之控制第二延遲線之 方法之時序圖。 第13圖是之本發明第三實施例之內部產生電路之電 路圖。 第Η圖是習知內部產生電路之電路圖。 第15圖是習知內部產生電路之延遲線之電路圖。 _ 6 本紙張K度適用中國國家標準(cns)a4 規烙(210 X 297公釐) I I I I Λι I I d I I I I ·1111111 一-口,« — — — — — — I— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 550446 Λ7 6036pifl . doc/008 五、發明說明() 標號說明: 103 :輸入緩衝器 10 2 :延遲線 200 :控制電路 104 :驅動器 β 106 :監控電路 100 :相位比較器 101 :移位暫存器 402 :延遲線控制電路 202 :延遲電路 302 :相位比較器 303 :移位暫存器; 304 :濾波器 305、306 :監控電路 3 0 0 :第一延遲線 3 01 :第_^延遲線 401、501 :延遲線控制電路 較佳實施例 本發明第一實施例之內部產生電路係參考所附圖示 而做詳細說明。 第1圖是顯示本發明第一實施例之內部產生電路之 電路圖。 如第1圖所示,內部電路產生電路較好包括相位比 較器302,移位暫存器(shift-:register)303,濾波器304,監 7 本紙張尺度適用中國國家標準(CNSW規烙(210 X 297公t ) ϋ ϋ ϋ— ϋ _·1 an VI emmmmm ·ϋ ΛΜ§ ·· ·ηβ > I w·· I an·· η··· μβμ I μμ· I 1 ϋ_· —ϋ n (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 550446 Λ7 5〇36pifl .doc/008 B7 五、發明說明() 控電路305,以及複數個延遲線’比如第一延遲線300、 第二延遲線301。 第一延遲線300與第二延遲線301分別具有不同延 遲步階。第一延遲線300之延遲步階大於第二延遲線301。 監控電路305監桦由半導體記憶體之輸出_電路接收 內部時脈cpint到其所輸出之資料輸出cpcmt而生之一延遲 dout ° 相位比較器302比較外部時脈cpext與回授時脈cpfb間 之相位,該回授時脈cpfb係由監控電路305將內部時脈(pint 延遲一個延遲dout之量而成。因此,相位比較器302輸 出偵測信號φΐ至移位暫存器303,以表示是否回授時脈cpfb 相位落後於外部時脈cpext。移位暫存器303累積偵測信號 φΐ,接著輸出控制信號φ2以控制第一延遲線300與第二 延遲線301之延遲時間。偵測信號φΐ也移轉至濾波器304。 濾波器304藉由將偵測信號φΐ閂住(latch)以輸出控制信號 φ3。在此,當控制信號φ3爲低電位時,係選擇第一延遲 線300。第一延遲線300係由控制信號φ2而控制延遲時間。 在第一延遲線300中,延遲時間係被調整,且相位 比較器302偵測到延遲時間再也無法調整。當偵測信號φΐ 在此時被傳送到濾波器304時,控制信號φ3改變至高電 位。因此,第一延遲線300之延遲時間被閂住,接著電路 被鎖相。在此時,第二延遲線301係被選擇,且控制信號 Φ2係改變以控制第二延遲線301之延遲時間。 第2圖顯示本發明第一實施例之第一延遲線之電路 8 本紙張Κ度適用中國國家標準(CNS)A4規烙(210 X 297公釐) — — — Ι1ΙΙΔ1Ι — — — · I I I I I I I « — — — — — — I— . (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 550446 Λ/ 6036pifl . doc / 008 [《7 五、發明說明() 圖。 如第2圖所示,當控制信號φ3爲低電位時,延遲線 控制電路401係被控制信號φ2所控制,以控制這些TAP 之選擇與當成選擇這些TAP之時序時脈之控制時脈 cpCTL。 因此,這些TAP之一從TAP1至ΤΑΡη —個接著一個 被選擇,且被選擇之TAP變成高電位。 比如,當被選擇之TAP係TAPm(l^mSn)時,有效延 遲電路之數量變成m-1。當延遲電路411之延遲步階爲tdc 時,第一延遲線300之延遲時間是tdcx (m_l)。因此,輸 入至第一延遲線300之外部時脈cpext係被延遲tdcx (m-1),接著外部時脈cpext係當成CLKf而輸出。當第一延遲 線300之延遲時間係調整成外部時脈cpext與回授時脈cpfb 之延遲時間爲最小時,控制信號φ3變成高電位。因此, 電路被鎖相,且延遲時間被閂住。 第3圖係本發明第一實施例之第二延遲線之電路圖。 如第3圖所示,當控制信號φ3在低電位時,在第二 延遲線內之ΤΑΡ0 —般係被延遲線控制電路501變成高電 位。當控制信號φ3改變成高電位時,被延遲線控制電路501 所選擇之ΤΑΡ0、TAPL1〜TAPL3與TAPR1〜TAPR3之一係 被控制信號φ2所控制,且變爲高電位。在此時,當控制 信號φ2爲低電位時,第二延遲線301之TAP係往左側方 向將延遲時間減少,一次移位一級(stage)。當控制信號φ2 爲高電位時,第二延遲線301之TAP係往右側方向將延遲 9 本紙張义度適用中國國家標準(CNS)A4規格(210 x 297公釐) —*—·-------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 550446Λ7 \ M Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () The present invention relates to an internal clock generation circuit, and in particular to a synchronous internal circuit in a semiconductor device, which operates synchronously with System clock. This application is the same as Japanese application No. 091590/1999, which was filed on March 31, 1999, and its subject matter is hereby incorporated by reference. When a paired system is accelerated, internally generated circuits, such as a phase-locked loop (PLL) or a delay-locked loop (DLL), are used in synchronous semiconductor devices, which operate synchronously at the system clock. FIG. 14 is a circuit diagram showing a conventional internal generating circuit. The internal generation circuit includes an input buffer 103 that shapes the external signal cpext into the system clock; a delay line 102 that generates a delay time to reduce the delay between the external signal cpext and the data output cpout; a control circuit 200 that controls The delay line 102; the driver 104 amplifies the internal clock signal (pint) output from the delay line 102 and the monitoring circuit 106 to monitor the delay time in the driver 104. The control circuit 200 includes a phase comparator 100 and a shift A shift-register 101. The phase comparator 100 compares the external signal cpext shaped by the input buffer 103 with the internal clock signal (the phase of the pint) delayed and fed back by the monitoring circuit 106. Then, the phase comparison The phase is detected by the device 100. Then, the phase comparator 100 outputs the detection signal φΐ to the shifting display _101. The shift register 101 counts up the detection signal φΐ and responds to the detection signal φΐ. Controls the delay line 102 and outputs a control signal φ2 to the delay line 102. The delay line 102 is controlled in response to the control signal φ2 and adjusts the delay time to reduce external signals cpext and data Extension of cpout 4 — — — — — — — — _ — — — — I a δ, «— — — — — — — I — II f II wi (Please read the notes on the back before filling this page) This paper & Applicable to the Chinese National Standard (CNS) Al Regulation (21 × 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 550446 6〇36pifl.doc / 008 H7 V. Description of the invention () Late. The internal generating circuit can generate cattle by comparing the external signal oext to avoid the external delay of 5μΦΦ and the output delay of the shell material. Figure 15 is a circuit diagram showing the delay line of the conventional internal generating circuit. As shown in Fig. 15, the delay line 102 includes a plurality of delay circuits 202 having a delay line control circuit 402. The delay line 102 controls the number of effective delay circuits, and responds to the control signal by selecting one of the TAPs (from TAP1 to TAPn) to adjust the external signal cpext. Here, the delay step is defined _ the unit delay time of the delay circuit 202. In the conventional technology, it is necessary to avoid the increase of the chip size 'and the internal clock of a wide frequency range needs to be generated. One of the objectives of the present invention is to provide an internal clock generating circuit which can avoid an increase in chip size and generate an internal clock in a wide frequency range. According to the purpose of the present invention, in order to achieve the above object, a synchronous semiconductor is provided. The internal generating circuit in the device operates synchronously with the system clock. The internal generating circuit includes a plurality of delay lines with different delay steps. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. The circuit of the internal generating circuit of the first embodiment of the invention 5 The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm)) ϋ ϋ ϋ »i_i 1 ϋ VI an n ϋ ϋ · -ϋ ϋ βΜ § 1 nn ϋ I an · * I aav · am · ι Face «1 · ϋ (JtS read the precautions on the back before filling this page) 550446 Λ7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6036pifl.doc / 008 V. Description of the invention () Figure. FIG. 2 is a circuit diagram of a first delay line according to the first embodiment of the present invention. FIG. 3 is a circuit diagram of a second delay line according to the first embodiment of the present invention. Fig. 4 is a schematic diagram showing the adjustment ranges of the first and second delay lines according to the first embodiment of the present invention. Fig. 5 is a timing chart showing the internal generating circuit of the first embodiment of the present invention shown in Fig. 1. Fig. 6 is a circuit diagram of an internal generating circuit according to a second embodiment of the present invention. Fig. 7 is a circuit diagram of a delay line having a small delay step according to the second embodiment of the present invention. FIG. 8 is a circuit diagram of a monitoring circuit according to a second embodiment of the present invention. Fig. 9 is a circuit diagram of a first delay line having a delay step larger than that of other delay lines in the second embodiment of the present invention. Fig. 10 is a timing chart of the internal generating circuit according to the second embodiment of the present invention. Fig. 11 is an operation timing chart of the second delay line of the second embodiment of the present invention. Figure I2 is a timing chart of the method for controlling the second delay line according to the second embodiment of the present invention. Fig. 13 is a circuit diagram of an internal generating circuit according to a third embodiment of the present invention. The second figure is a circuit diagram of a conventional internal generating circuit. FIG. 15 is a circuit diagram of a delay line of a conventional internal generation circuit. _ 6 The K degree of this paper applies the Chinese National Standard (cns) a4 gauge (210 X 297 mm) IIII Λι II d IIII · 1111111 One-mouth, «— — — — — — I— (Please read the note on the back first Please fill out this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 550446 Λ7 6036pifl .doc / 008 V. Description of the invention () Symbol description: 103: Input buffer 10 2: Delay line 200: Control circuit 104: Driver β 106: monitoring circuit 100: phase comparator 101: shift register 402: delay line control circuit 202: delay circuit 302: phase comparator 303: shift register; 304: filter 305, 306: monitoring circuit 3 0 0: first delay line 3 01: first delay line 401, 501: preferred embodiment of delay line control circuit The internal generation circuit of the first embodiment of the present invention is described in detail with reference to the accompanying drawings. Fig. 1 is a circuit diagram showing an internal generating circuit according to a first embodiment of the present invention. As shown in Figure 1, the internal circuit generating circuit preferably includes a phase comparator 302, a shift-: register 303, a filter 304, and a monitor. This paper standard is applicable to Chinese national standards (CNSW regulations ( 210 X 297 male t) ϋ ϋ ϋ— ϋ · 1 an VI emmmmm · ϋ ΛΜ§ ··· ηβ > I w ·· I an ·· η ·· μβμ I μμ · I 1 ϋ_ · —ϋ n (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 550446 Λ7 5〇36pifl .doc / 008 B7 V. Description of the invention () Control circuit 305, and multiple delay lines' such as The first delay line 300 and the second delay line 301. The first delay line 300 and the second delay line 301 have different delay steps, respectively. The delay step of the first delay line 300 is larger than that of the second delay line 301. The monitoring circuit 305 monitors The output of the semiconductor memory_circuit receives the internal clock cpint to output a data output cpcmt and generates a delay dout ° The phase comparator 302 compares the phase between the external clock cpext and the feedback clock cpfb. The clock cpfb is the internal clock (pin t is delayed by the amount of delay dout. Therefore, the phase comparator 302 outputs the detection signal φΐ to the shift register 303 to indicate whether the phase of the feedback clock cpfb is behind the external clock cpext. The shift register 303 The detection signal φΐ is accumulated, and then the control signal φ2 is output to control the delay time of the first delay line 300 and the second delay line 301. The detection signal φΐ is also transferred to the filter 304. The filter 304 filters the detection signal ΐ Latch to output the control signal φ3. Here, when the control signal φ3 is low, the first delay line 300 is selected. The first delay line 300 controls the delay time by the control signal φ2. At the first delay In line 300, the delay time is adjusted, and the phase comparator 302 detects that the delay time can no longer be adjusted. When the detection signal φΐ is transmitted to the filter 304 at this time, the control signal φ3 changes to a high potential. Therefore, The delay time of the first delay line 300 is latched, and then the circuit is phase locked. At this time, the second delay line 301 is selected, and the control signal Φ2 is changed to control the delay time of the second delay line 301. 2 Figure The circuit of the first delay line showing the first embodiment of the present invention 8 This paper is K-degree compatible with Chinese National Standard (CNS) A4 (210 X 297 mm) — — — ΙΙΙΙΔ1Ι — — — IIIIIII «— — — — — — I—. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 550446 Λ / 6036pifl. Doc / 008 [《7 5. Description of Invention (). As shown in FIG. 2, when the control signal φ3 is low, the delay line control circuit 401 is controlled by the control signal φ2 to control the selection of these TAPs and the control clock cpCTL which is the timing clock of selecting these TAPs. Therefore, one of these TAPs is selected one after another from TAP1 to TAPN, and the selected TAP becomes high. For example, when the selected TAP is TAPm (l ^ mSn), the number of effective delay circuits becomes m-1. When the delay step of the delay circuit 411 is tdc, the delay time of the first delay line 300 is tdcx (m_l). Therefore, the external clock cpext input to the first delay line 300 is delayed by tdcx (m-1), and then the external clock cpext is output as CLKf. When the delay time of the first delay line 300 is adjusted so that the delay time of the external clock cpext and the feedback clock cpfb is the minimum, the control signal φ3 becomes a high potential. Therefore, the circuit is phase locked and the delay time is latched. FIG. 3 is a circuit diagram of a second delay line according to the first embodiment of the present invention. As shown in FIG. 3, when the control signal φ3 is at a low potential, TAPO in the second delay line is generally changed to a high potential by the delay line control circuit 501. When the control signal φ3 is changed to a high potential, one of TAPO, TAPL1 to TAPL3 and TAPR1 to TAPR3 selected by the delay line control circuit 501 is controlled by the control signal φ2 and becomes a high potential. At this time, when the control signal φ2 is at a low potential, the TAP of the second delay line 301 decreases the delay time to the left and shifts by one stage at a time. When the control signal φ2 is at a high potential, the TAP of the second delay line 301 will be delayed to the right by 9 sheets. The paper's meaning is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) — * — · --- ---------- Order --------- line (Please read the precautions on the back before filling this page) 550446

Λ7 \M 6036pifl.doc/008 五、發明說明() 時間增加,一次移位一級。因此,當依步階而後續之第一 延遲線300具有大於第二延遲線301之延遲步階時’第一 實施例之適當架構係爲,儲存於第一延遲線3〇〇中之延遲 時間係增加或減少。 第4圖係顯示本發明第一實施例之第一與第二延遲 線之調整範圍。 如第4圖所示,第二延遲線301具有第一延遲線300 之延遲步階tdc以及小於延遲步階tdc之延遲步階tdf。 增加或減少第二延遲線3 〇 1之延遲時間之適當S周整 範圍係如下。 (l/2x n)x tdf>tdc 在此,η定義第二延遲線301之延遲電路之數量(比 如 η=6)。 藉由如上所述之方式來設定能將第一延遲線3 〇 1之 增加或減少延遲時間之調整範圍602 ’第一延遲線300可 細(fine)調整閂住延遲時間。第二延遲線301可增加或減 少第一延遲線300之延遲時間。因此,第一延遲線300之 延遲時間可調整而無需交換延遲線。 第5圖係顯示本發明第一實施例中之第1圖之內部 產生電路之時序圖。 如第5圖所示,移位暫存器303之控制信號φ2之輸 出係由相位比較器302所輸出之偵測信號φΐ。第一延遲線 300之TAP係由控制信號φ2所控制,逐步地(τ001〜τ〇〇3), 以增加同步於控制時脈cpCTL之延遲時間。藉由偵測信號 I ϋ n ϋ^··— I ί ϋ ϋ ϋ ϋ 一一口,I I n II ϋ ·ϋ (請先閱讀背面之注意事項再填寫本頁) 線- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規恪(210 x 297公釐) 550446 Λ7 6036pifl.doc/008 B7 五、發明說明() (請先閱讀背面之注意事項再填寫本頁) φΐ,濾波器304之控制信號φ3變成高電位。因此,電路 係被鎖住(τ〇〇4),且其從具有較大延遲步階之第一延遲線 300轉換成具有較小延遲步階之第二延遲線301(τ005)。在 此時,第一延遲線300之ΤΑΡ4係維持在高電位(τ006)。 甚至,第二延遲線301之TAP係由控制信號φ2逐步地控 制(τ007〜τ008)。 如上所述,第一實施例之內部產生電路,藉由具有 較大延遲步階之第一延遲線300轉換成具有較小延遲步階 之第二延遲線301,可產生具有外部時脈相位cpext與回授 時脈cpfb間之相位差之小內部時脈信號。 第6圖係本發明第二實施例之內部產生電路之電路 圖。 如第6圖所示,本發明第二實施例之特徵在於,比 如第一實施例多加一個監控電路306。監控電路306監控 是否在第二延遲線301之調整範圍內。 第7圖顯示本發明第二實施例之具小延遲步階之延 遲線之電路圖。 經濟部智慧財產局員工消費合作社印製 如第7圖所示,cpEDGR與cpEDGL加入當成第1圖中 之第二延遲線301之第一實施例之TAP,TAPR3與TAPL3 之監控信號。第二延遲線301以右側方向移位,使得TAP 由控制信號φ2增加延遲時間。因此,當選擇TAPR3時, cpEDGR變成高電位,且監控電路306偵測到超過第二延 遲線301之調整範圍。第二延遲線301以左側方向移位, 使得TAP由控制信號φ2減少延遲時間。因此,當選擇TAPL3 11 本紙張义度適用中國國家標準(CNS)A4規恪(21〇χ 297公爱) 經濟部智慧財產局員工消費合作社印製 550446 A7 6036pifl.doc/008 B7 五、發明說明() 時,cpEDGL變成高電位,且監控電路306偵測到超過第 二延遲線301之調整範圍。 第8圖係本發明第二實施例之監控電路之電路圖。 如第8圖所示,監控電路306監控cpEDGR與cpEDGL 來了解是否處於第二延遲線301之調整範圍。當cpEDGR 與cpEDGL之一變成高電位時,cpEDG變成高電位。因此, 監控電路3〇6傳送至第二延遲線301以超過第二延遲線301 之調整範圍。當cpEDG變成高電位時,第二延遲線301係 被重設◦因此,控制信號φ2係轉換成第一延遲線300。 第9圖是本發明第二實施例之延遲步階大於其他延 遲線之第一延遲線之電路圖。 如第9圖所示,當第二延遲線301在延遲時間增加 方向上超過調整範圍時,控制信號φ2係從延遲步階小於 其他延遲線之第二延遲線301切換至延遲步階大於其他延 遲線之第一^延遲線300。因此’第一^延遲線300之延遲時 間增加一個步階。同樣地,當第二延遲線301在延遲時間 減少方向上超過調整範圍時,控制信號Φ2係從第二延遲 線301切換至第一延遲線300。因此,第一延遲線300之 延遲時間減少一個步階。 第10圖是之本發明第二實施例之內部產生電路之時 序圖。 如第10圖所示,第一延遲線300之TAP,回應於控 制時脈cpCTL(Tl01〜τ103),而由控制信號φ2之狀態以各步 階來控制。 12 ϋ ϋ ϋ I Γ— ^1 ϋ «Γ I n ϋ I I ϋ n n 1 I I 一SJI ϋ I I 1 ϋ n I I ϋ «Γ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNSM4規烙(210 x 297公t ) Λ7 550446 6 0 36pifl . doc / 008 ____—- 五、發明說明() 在控制第一延遲線300中,當沒有偵測到相位差時’ 電路係由控制信號φ3所鎖住(τ104)。因此,第一延遲線3〇〇 之延遲時間係被鎖住(τ112)。甚至,延遲線切換至第二延 遲線301 (τ 105)。因此,控制信號φ2傳送至第二延遲線301 ° 第二延遲線301之延遲時間係以延遲時間減少方向方向’ 階段式控制。當第二延遲線3〇1之q>EDGL變成高電位’ 監控電路306監控至超過調整範圍。因此,監控電路306 之監控信號cpEDG變成高電位(τ109)。在此時,第二延遲 線301係重設(τ110),且控制信號φ2從第二延遲線301切 換至第一延遲線300。因此,被鎖住之TAP4((pD)之電位從 高電位變成低電位,且ΤΑΡ3(φ〇之電位從變成高電位 (τΐΐΐ)。因此,第一延遲線300之延遲線從被鎖住之延遲 時間減少一個步階。 第11圖是之本發明第二實施例之第二延遲線之操作 時序圖。 如第11圖所示,第一延遲線300係由控制信號φ2所 控制(τ201〜τ203)。當電路被鎖住時(τ204)時,第一延遲線 300之延遲時閭__被鎖住,且延遲線切換至第二延遲線 301(τ205)。因此,控制信號φ2傳送至第二延遲線301。第 二延遲線301係以延遲時間減少方向階段式被控制 (τ206〜τ208)。當第二延遲線301之cpEDGR變成高電位, 監控電路306監控至超過調整範圍。因此,監控電路306 之監控信號q>EDG變成高電位(τ209)。此時,第二延遲線301 被重設(τ210),且控制信號φ2從第二延遲線301切換至第 13 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) "" ----i--------I ------丨訂·-------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 550446 Λ7 H7 6〇36pifl.doc/〇〇8 五、發明說明() 一延遲線300。因此,被鎖住之TAP4(cpD)之電位從高電位 變成低電位,且ΤΑΡ5(φΗ)之電位從變成筒電位(Till) ’且 第一延遲線300之延遲時間增加一個步階。 第12圖是之本發明第二實施例之控制第二延遲線之 方法之時序圖。 如第12圖所示,第二延遲線301係從具大延遲步階 之電路切換至具小延遲步階之電路(τ105,τ205)。第二延 遲線301係被控制信號φ2控制,以第一延遲線300之延 遲時間增加方向(τ206〜τ208)或第一延遲線300之延遲時間 減少方向(τ106〜τ108)。當延遲時間超過第一延遲線300之 延遲時間增加方向(τ206〜τ208)時,控制信號φ2係從第二 延遲線301切換至第一延遲線300。因此,第一延遲線300 之延遲時間增加一個步階(τ211)。此時,第二延遲線301 係重設於延遲線之中間(τ210)。同樣地,當延遲時間超過 第一延遲線300之延遲時間減少方向(T106〜τ108)時,控制 信號φ2係從第二延遲線301切換至第一延遲線300。因此, 第一延遲線300之延遲時間減少一個步階(Tlll)。此時, 第二延遲線係重設於延遲線之中間(τ 110)。 第13圖是之本發明第三實施例之內部產生電路之電 路圖。 如第I3圖所示,在第二延遲線301中,TAP被控制 信號φ2以增加延遲時間方向遂步地移位至右側。位於調 整範圍之右側邊緣之TAPR3被選擇。甚至,只有當TAP 之被控制方向係增加一個步階時,TAPR才會被選擇。只 14 本紙張义度適用中國國家標準(CNS)A4規格(210 x 297公f ) ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 550446 6036pifl . doc/〇〇8 ^ 五、發明說明() 有當TAPR被選擇時,cpEDGR變成高電位。因此,第二 延遲線301偵測到以增加方向上超過調整範圍。第二延遲 線301被重設,且控制信號φ2切換至第一延遲線300。 同樣地,在第二延遲線301中’ TAP被控制信號q>2 以減少延遲時間方向上移位。因此’ TAPL3在調整範圍內 被選擇。接著,只有當TAP被控制信號φ2以延遲時間減 少方向上更進一步移位時,虛擬之TApL才會被選擇,且 cpEDGL變成高電位,延遲時間維持於TAPL3被選擇之狀 態。因此,監控電路306監控在延遲時間減少方向上超過 調整範圍。 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明,任何熟習此技藝者,在不脫離 本發明之精神和範圍內’當可作各種之更動與潤飾,因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 ----·—.-------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 15 本紙張&度適用中國國家標準(CNS)A4規格(21〇x 297公f )Λ7 \ M 6036pifl.doc / 008 5. Description of the invention () Time increases and shifts one level at a time. Therefore, when the subsequent first delay line 300 has a delay step larger than the second delay line 301 according to the step, the appropriate structure of the first embodiment is a delay time stored in the first delay line 300. Department increase or decrease. Fig. 4 shows the adjustment range of the first and second delay lines according to the first embodiment of the present invention. As shown in FIG. 4, the second delay line 301 has a delay step tdc of the first delay line 300 and a delay step tdf smaller than the delay step tdc. The appropriate S-rounding range for increasing or decreasing the delay time of the second delay line 301 is as follows. (l / 2x n) x tdf > tdc Here, η defines the number of delay circuits of the second delay line 301 (e.g., η = 6). By setting the adjustment range 602 that can increase or decrease the delay time of the first delay line 301 by the method described above, the first delay line 300 can finely adjust the latching delay time. The second delay line 301 may increase or decrease the delay time of the first delay line 300. Therefore, the delay time of the first delay line 300 can be adjusted without exchanging the delay lines. Fig. 5 is a timing chart showing the internal generating circuit of Fig. 1 in the first embodiment of the present invention. As shown in Fig. 5, the output of the control signal φ2 of the shift register 303 is a detection signal φΐ output by the phase comparator 302. The TAP of the first delay line 300 is controlled by the control signal φ2 and gradually (τ001 ~ τ〇〇3) to increase the delay time synchronized with the control clock cpCTL. With the detection signal I ϋ n ϋ ^ ·· —— I ί ϋ ϋ ϋ ϋ 一 一, II n II ϋ · ϋ (Please read the precautions on the back before filling this page) Line-Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 (210 x 297 mm) 550446 Λ7 6036pifl.doc / 008 B7 V. Description of the invention () (Please read the precautions on the back before filling this page ) φΐ, the control signal φ3 of the filter 304 becomes a high potential. Therefore, the circuit is locked (τ〇04), and it is switched from the first delay line 300 having a larger delay step to the second delay line 301 (τ005) having a smaller delay step. At this time, the TAP4 of the first delay line 300 is maintained at a high potential (τ006). Furthermore, the TAP of the second delay line 301 is gradually controlled by the control signal φ2 (τ007 to τ008). As described above, the internal generation circuit of the first embodiment can generate an external clock phase cpext by converting the first delay line 300 having a larger delay step into the second delay line 301 having a smaller delay step. Small internal clock signal with a phase difference from the feedback clock cpfb. Fig. 6 is a circuit diagram of an internal generating circuit according to a second embodiment of the present invention. As shown in Fig. 6, the second embodiment of the present invention is characterized by adding a monitoring circuit 306 as compared with the first embodiment. The monitoring circuit 306 monitors whether it is within the adjustment range of the second delay line 301. Fig. 7 shows a circuit diagram of a delay line with a small delay step according to a second embodiment of the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs As shown in Fig. 7, cpEDGR and cpEDGL are added as the monitoring signals of TAP, TAPR3 and TAPL3 of the first embodiment of the second delay line 301 in Fig. 1. The second delay line 301 is shifted in the right direction, so that the TAP increases the delay time by the control signal φ2. Therefore, when TAPR3 is selected, cpEDGR becomes high, and the monitoring circuit 306 detects that the adjustment range of the second delay line 301 is exceeded. The second delay line 301 is shifted in the left direction, so that the TAP reduces the delay time by the control signal φ2. Therefore, when TAPL3 11 is selected, the meaning of this paper applies to Chinese National Standard (CNS) A4 (21〇χ 297 public love). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 550446 A7 6036pifl.doc / 008 B7 V. Description of the invention (), CpEDGL goes high, and the monitoring circuit 306 detects that the adjustment range of the second delay line 301 is exceeded. FIG. 8 is a circuit diagram of a monitoring circuit according to a second embodiment of the present invention. As shown in FIG. 8, the monitoring circuit 306 monitors cpEDGR and cpEDGL to know whether it is within the adjustment range of the second delay line 301. When one of cpEDGR and cpEDGL becomes high, cpEDG becomes high. Therefore, the monitoring circuit 306 is transmitted to the second delay line 301 to exceed the adjustment range of the second delay line 301. When cpEDG goes high, the second delay line 301 is reset. Therefore, the control signal φ2 is converted into the first delay line 300. Fig. 9 is a circuit diagram of a first delay line having a delay step larger than that of other delay lines in the second embodiment of the present invention. As shown in Figure 9, when the second delay line 301 exceeds the adjustment range in the direction of increasing delay time, the control signal φ2 is switched from the second delay line 301 with a delay step smaller than other delay lines to a delay step larger than other delays. The first ^ delay line 300 of the line. Therefore, the delay time of the 'first ^ delay line 300 is increased by one step. Similarly, when the second delay line 301 exceeds the adjustment range in the direction in which the delay time decreases, the control signal? 2 is switched from the second delay line 301 to the first delay line 300. Therefore, the delay time of the first delay line 300 is reduced by one step. Fig. 10 is a timing chart of the internal generating circuit according to the second embodiment of the present invention. As shown in Fig. 10, the TAP of the first delay line 300 responds to the control clock cpCTL (Tl01 ~ τ103), and is controlled by the state of the control signal φ2 in each step. 12 ϋ ϋ ϋ I Γ— ^ 1 ϋ «Γ I n ϋ II ϋ nn 1 II-SJI ϋ II 1 ϋ n II ϋ« Γ (Please read the precautions on the back before filling this page) This paper size is applicable to China Standard (CNSM4 gauge (210 x 297mm t) Λ7 550446 6 0 36pifl .doc / 008 ____ —- 5. Description of the invention () In the control of the first delay line 300, when no phase difference is detected 'circuit system Locked by the control signal φ3 (τ104). Therefore, the delay time of the first delay line 300 is locked (τ112). Even the delay line is switched to the second delay line 301 (τ 105). Therefore, the control The signal φ2 is transmitted to the second delay line 301 °. The delay time of the second delay line 301 is reduced in the direction of the delay time. The phase control is performed. When the q > EDGL of the second delay line 3〇1 becomes high, the monitoring circuit 306 monitors To exceed the adjustment range. Therefore, the monitoring signal cpEDG of the monitoring circuit 306 becomes high (τ109). At this time, the second delay line 301 is reset (τ110), and the control signal φ2 is switched from the second delay line 301 to the first A delay line 300. Therefore, the potential of the locked TAP4 ((pD) The high potential becomes low, and the potential of TAP3 (φ0 changes from high potential (τΐΐΐ). Therefore, the delay line of the first delay line 300 is reduced by one step from the locked delay time. FIG. 11 is the present invention Operation timing diagram of the second delay line of the second embodiment. As shown in FIG. 11, the first delay line 300 is controlled by the control signal φ2 (τ201 ~ τ203). When the circuit is locked (τ204), The delay time of the first delay line 300 is locked, and the delay line is switched to the second delay line 301 (τ205). Therefore, the control signal φ2 is transmitted to the second delay line 301. The second delay line 301 is a delay The time decreasing direction is controlled in stages (τ206 ~ τ208). When the cpEDGR of the second delay line 301 becomes a high potential, the monitoring circuit 306 monitors beyond the adjustment range. Therefore, the monitoring signal q > EDG of the monitoring circuit 306 becomes a high potential (τ209 ). At this time, the second delay line 301 is reset (τ210), and the control signal φ2 is switched from the second delay line 301 to the 13th. This paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) " " ---- i -------- I ------ 丨· -------- (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 550446 Λ7 H7 6〇36pifl.doc / 〇〇8 V. Description of the invention () One delay line 300. Therefore, the potential of the locked TAP4 (cpD) changes from a high potential to a low potential, and the potential of TAP5 (φΗ) changes from a potential to a barrel potential (Till) ', and the delay time of the first delay line 300 increases by one step. Fig. 12 is a timing chart of the method for controlling the second delay line according to the second embodiment of the present invention. As shown in Fig. 12, the second delay line 301 is switched from a circuit with a large delay step to a circuit with a small delay step (τ105, τ205). The second delay line 301 is controlled by the control signal φ2, and the delay time of the first delay line 300 increases (τ206 to τ208) or the delay time of the first delay line 300 decreases (τ106 to τ108). When the delay time exceeds the delay time increasing direction (τ206 ~ τ208) of the first delay line 300, the control signal φ2 is switched from the second delay line 301 to the first delay line 300. Therefore, the delay time of the first delay line 300 is increased by one step (τ211). At this time, the second delay line 301 is reset in the middle of the delay line (τ210). Similarly, when the delay time exceeds the delay time reduction direction (T106 ~ τ108) of the first delay line 300, the control signal φ2 is switched from the second delay line 301 to the first delay line 300. Therefore, the delay time of the first delay line 300 is reduced by one step (T11). At this time, the second delay line is reset in the middle of the delay line (τ 110). Fig. 13 is a circuit diagram of an internal generating circuit according to a third embodiment of the present invention. As shown in Fig. I3, in the second delay line 301, the TAP is gradually shifted to the right by the control signal? 2 to increase the delay time direction. TAPR3 located on the right edge of the adjustment range is selected. Furthermore, TAPR will only be selected if the direction of control of the TAP is increased by one step. Only 14 copies of this paper are applicable to China National Standard (CNS) A4 (210 x 297 male f) --------------------- Order ------ --- line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 550446 6036pifl .doc / 〇〇8 ^ V. Description of Invention () When TAPR is selected, cpEDGR Goes high. Therefore, the second delay line 301 detects that the adjustment range is exceeded in the increasing direction. The second delay line 301 is reset, and the control signal φ2 is switched to the first delay line 300. Similarly, in the second delay line 301, the 'TAP is controlled by the signal q> 2 to reduce the shift in the direction of the delay time. Therefore, 'TAPL3 is selected within the adjustment range. Then, only when the TAP is further shifted in the direction of decreasing the delay time by the control signal φ2, the virtual TApL will be selected, and cpEDGL will become high, and the delay time will be maintained in the state where TAPL3 is selected. Therefore, the monitoring circuit 306 monitors that the adjustment range is exceeded in the direction in which the delay time decreases. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. ---- · —.------------- Order --------- Line (Please read the precautions on the back before filling this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 15 papers printed by the Consumer Cooperative Co., Ltd. Applicable to China National Standard (CNS) A4 specifications (21〇x297mmf)

Claims (1)

550446 as B8 C8 6036pif1.doc/008 D8 六、申請專利範圍 一延遲線監控電路,連接至該些延遲線,用以決定 是否每一該些延遲線之該延遲量超過各自的延遲線之一可 調範圍,以及其中當該延遲線監控電路決定該細延遲線之 該延遲量超過該細延遲線之該可調範圍時,該粗延遲改變 一步階。 ^如申請專利範圍第4項所述之內部時脈產生電路, 其中該細延遲線之該可調範圍大於粗延遲之一步階。 i如申請專利範圍第1項所述之內部時脈產生電路, 其中該預定延遲時間係由測量該內部時脈信號之延遲時間 所決定。 ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 广 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 修正日期:2002.10.14 申請曰期 案 號 類 别 {/〇 y (以上各攔由本局塡註) A4 C4550446 利説明書 專 中 文 發明 新型 名稱 內部時脈產生電路 (修正本) 英 文 姓 名 國 籍 發明 創作 人 住、居所 姓 名 (名稱) 近藤孝子 日本 曰本東京都港區虎)門1 丁目7番12號 沖電氣工業股份有限公司 經濟部智慧財產局員工消費合作社印製 國 籍 日本 三、申請人 住、居所 (事務所) 代表人 姓 名 日本東京都港區虎7門1 丁目7番12號 篠塚勝正 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 550446 6036pifl.doc/008 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 t一種內部時脈產生電路,其最少化在一內部時脈信 號與一外部時脈信號之間的相位差異,包括: 複數個延遲線’其具有不问延遲量,每一該些延遲 線提供該些延遲量之一以回應一控制信號,而該些延遲線 -被選擇以回應一選擇信號; 一監控電路,連接至該些延遲線,該監控電路產生 一回授時脈信號以回應該內部時脈信號,該回授時脈信號 係從該內部時脈信號延遲一預定延遲時間; 一相位比較器,連接至該監控電路,該相位比較器 偵測該回授時脈信號與該外部時脈信號之間的相位差異, 並產生一偵測信號以回應此相位差異; 一移位暫存器,連接至該相位比較器及該些延遲線, 該移位暫存器產生該控制信號以回應該偵測信號;以及 一濾波器電路,連接至該些延遲線及該相位比較器, 該濾波器電路產生該選擇信號以回應該偵測信號。 ^如申請專利範圍第1項所述之內部時脈產生電路, 其中該些延遲線包括用以將訊號延遲一粗延遲步階的一粗 延遲線以及用以將訊號延遲一細延遲步階的一細延遲線。 1^如申請專利範圍第2項所述之內部時脈產生電路, 其中該細延遲線之一延遲量被初始設定在其可變延遲範圍 的中點,且該細延遲線之該延遲量係由該控制信號來調 整。 ^如申請專利範圍第2項所述之內部時脈產生電路, 更包括: 16 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) ---------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁)550446 as B8 C8 6036pif1.doc / 008 D8 VI. Patent application scope-Delay line monitoring circuit connected to the delay lines to determine whether the delay amount of each of the delay lines exceeds one of the respective delay lines. The adjustment range, and when the delay line monitoring circuit determines that the delay amount of the fine delay line exceeds the adjustable range of the fine delay line, the coarse delay changes by one step. ^ The internal clock generating circuit described in item 4 of the scope of the patent application, wherein the adjustable range of the fine delay line is larger than one step of the coarse delay. i The internal clock generation circuit as described in item 1 of the scope of patent application, wherein the predetermined delay time is determined by measuring the delay time of the internal clock signal. --------------------- Order --------- Line (Please read the notes on the back before filling this page) Intellectual Property of the Ministry of Economic Affairs The paper size printed by the Bureau ’s Consumer Cooperatives applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Date of amendment: 2002.10.14 Application date type category {/ 〇y (The above blocks are endorsed by the Bureau. ) A4 C4550446 Lee Instruction Manual Chinese Invented New Name Internal Clock Generation Circuit (Revised) English Name Nationality Inventor Name of Residence, Home (Name) Kondo Takako Japan, Japan, Tokyo, Minato-ku, Tokyo) Gate 1 7-chome 12 OKI Electric Industrial Co., Ltd. Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative, Printed Nationality Japan III. Applicant's Residence, Domicile (Office) Representative's Name Paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 550446 6036pifl.doc / 008 A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs An internal clock generation circuit that minimizes the phase difference between an internal clock signal and an external clock signal includes: a plurality of delay lines' which have no delay amount, each of these delay lines One of the delay amounts is provided in response to a control signal, and the delay lines are selected in response to a selection signal; a monitoring circuit is connected to the delay lines, and the monitoring circuit generates a feedback clock signal to respond to Internal clock signal, the feedback clock signal is delayed from the internal clock signal by a predetermined delay time; a phase comparator connected to the monitoring circuit, the phase comparator detects the feedback clock signal and the external clock A phase difference between the signals and a detection signal is generated in response to the phase difference; a shift register is connected to the phase comparator and the delay lines, and the shift register generates the control signal to return The signal should be detected; and a filter circuit connected to the delay lines and the phase comparator, the filter circuit generates the selection signal in response to the detection signal. ^ The internal clock generating circuit described in item 1 of the scope of the patent application, wherein the delay lines include a coarse delay line for delaying the signal by a coarse delay step and a delay line for delaying the signal by a fine delay step. A thin delay line. 1 ^ The internal clock generation circuit as described in item 2 of the patent application range, wherein a delay amount of one of the fine delay lines is initially set at a midpoint of its variable delay range, and the delay amount of the fine delay line is It is adjusted by this control signal. ^ The internal clock generating circuit as described in item 2 of the scope of patent application, further including: 16 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ---------- ----------- Order --------- line (Please read the precautions on the back before filling this page)
TW089104574A 1999-03-31 2000-03-14 Internal clock generation circuit TW550446B (en)

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US4165490A (en) * 1977-12-19 1979-08-21 International Business Machines Corporation Clock pulse generator with selective pulse delay and pulse width control
KR0152421B1 (en) * 1996-01-08 1998-12-15 김광호 Digital delay synchronizing loop circuit
JP3320651B2 (en) * 1998-05-06 2002-09-03 富士通株式会社 Semiconductor device

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