539952 A7 B7 五、發明說明（1) (請先閱讀背面之注意事項再填寫本頁) 本發明係關於於使用記憶體模組等之記憶體系統中， 抑制起因於配線之分支之傳送信號之反射之技術，適用於 高速存取對應之記憶體系統有效之技術。 記憶體模組專用之小振幅界面有SSTL(Stub Senes Terminated Transceiver Logic :短截線串列終結無線電收發 機邏輯）。關於SSTL，例如被記載於1 999年3月，電子資 訊通信學會發行、英文論文誌V〇L.E82-C，No.3，Yasuhiro KONISHI 著，「Interface Technologies for Memories and ASICs-Review and Future Direction」。 藉由SSTL之記憶體系統主要由被構裝於主機板之記憶 體控制器、信號配線、連接器以及記憶體模組所構成。記 憶體模組在模組基板之兩面分別具有m個之記憶體晶片， 經濟部智慧財產局員工消費合作社印製 以m個單位，個記憶體晶片之資料端子被接續於模組資料 端子，個記億體晶片之位址端子等之存取控制資料端子分 別被接續於對應之模組存取控制端子。前述信號配線之一 端被接續於記憶體控制器之信號端子，另一端被終結於指 定之電壓。複數之記憶體模組透過連接器被並列接續於前 述信號配線。此處，如設記憶體晶片之資料端子之數目爲η 、被搭載於個記憶體模組之單面之記憶體晶片之數目爲m ，本記憶體系統具有m X η之資料信號配線，於1次之存取 中，藉由記憶體控制器發生之晶片選擇信號，被搭載於複 數之記憶體模組內之1片之單面之m個之記憶體晶片被選 擇。前述信號配線之終端透過終端電阻被接續於終端電壓 。又，記憶體控制器用短截線電阻被串列接續於連結記憶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Α7 Β7 五、發明說明（2) 體控制器與連接器之信號配線。 (請先閱讀背面之注意事項再填寫本頁) 此處，連結記憶體模組之模組端子與記憶體晶片之端 子之模組配線構成由主機板之信號配線透過連接器分支之 配線。短截線電阻被配置於這些模組配線。這些短截線電 阻具有緩和信號配線之信號反射用之匹配負荷之功能。一 般在配線之分支點，特性阻抗產生不匹配，需要緩和其用 之短截線電阻。如設配線之特性阻抗爲Z0、短截線配線之 特性阻抗爲ZsO，短截線電阻之電阻値以Zs0-Z0/2爲適當。 但是，如使短截線電阻之電阻値變大，由於電阻之電壓降 低變大，因此，位址或資料等之信號電壓衰減，有記憶體 動作產生錯誤之虞。雖說如此，爲了避免信號電壓之衰減 ，如使短截線電阻之電阻値抑制的很小，反之，信號反射 顯著化，信號波形錯亂，相同地，有產生誤動作之虞。隨 著動作被高速化，信號頻率被提高，而且，欲藉由短截線 電阻以作爲對策之分支配線愈長，接收端之信號波形之錯 亂變得更大。 經濟部智慧財產局員工消費合作社印製 另一方面，作爲別的記憶體系統，本發明者檢討：在 主機板上被接續於記憶體控制器之信號配線透過連接器串 列接續複數之記憶體模組之形式。本發明者檢討：在記憶 體模組上，複數之記憶體晶片透過模組資料信號配線以一 直線配線路徑被接續之構成。在此記憶體系統中，如設記 憶體元件之資料信號端子數爲η，不管被搭載於記憶體模 組之單面之記憶體元件之數目m，具有η個模組資料信號 配線，在1次之存取中，複數之記憶體晶片內之1個之記 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（3) 憶體晶片被選擇。 (請先閱讀背面之注意事項再填寫本頁) 於上述別的記憶體系統中，對於主機板之信號配線， 全部之記憶體模組係串列被接續，記憶體模組內之模組信 號配線被串列接續於排成一列之記憶體晶片全部，沿著記 憶體模組之長邊方向被敷設。因此，如前述之SSTL般地， 對於主機板上之信號配線，記憶體模組幾乎不形成分支配 線，很少由於在分支配線所產生之非所期望之信號反射之 波形之錯亂之問題。 但是，信號配線之長度增加，由記憶體控制器至最遠 端之記憶體晶片之信號傳播時間變長，由本發明者弄淸楚 了存取時間之延遲會變大。 如上述般地，在SSTL形式中，記憶體模組之模組配線 在記憶體系統上成爲構成分支配線，產生由於此之信號反 射之誤動作，有變成限制了記憶體動作之高速化之問題， 經濟部智慧財產局員工消費合作社印製 又，在串列接續記憶體晶片之形式的記憶體模組中，如前 述SSTL之信號配線之分支幾乎不存在之故，由於分支配線 之問題雖然少，但是由於記憶體模組內之信號配線變長， 存取時間延遲，由本發明者弄淸楚有無法對應更高一層之 高速存取之虞。 本案發明者在完成本案發明後，認識以下之周知例。 在特開平5 -2343 5 5號公報、特開平6- 1 50085號公報中揭示 ••於記憶體模組之兩方之長邊部份設置連接器，可以串列 接續複數之記憶體模組之發明。但是，在其中並未揭示記 憶體模組內部之配線構造。在特開平7-3344 1 5號公報中揭 -0 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（4) (請先閱讀背面之注意事項再填寫本頁) 示：具有可以串列接續擴張用記憶體模組之擴張用連接器 之記憶體模組。在特開平7-26 1 892號公報中揭示：於記憶 體模組設置入口連接器與出口連接器，以記憶體模組上之 記憶體總線連接其間，將記憶體元件串列接續於該記憶體 總線，以抑制非所期望之信號反射之發明。但是，前述第 1至第3之周知例不過是提供可以串列接續記憶體模組以 構成記憶體系統之技術而已，第4周知例不過是顯示在記 憶體模組上之記憶體總線以串列形態接續複數之記憶體元 件之方式，任何一種之周知例皆係未到達本案發明之構想 者。 發明摘要 本發明之目的在於提供：抑制由於信號反射之信號波 形之錯亂，可以提升信號傳送之信賴性之同時，增加記憶 體動作之安定性，又，可以抑制存取時間之增加之記憶體 系統。 本發明之別的目的在於提升使用記憶體系統之電腦系 統之資料處理速度。 經濟部智慧財產局員工消費合作社印製 本發明之前述以及其它之目的與新的特徵由本詳細說 明書之記述以及所附圖面理應可以變得淸楚。 如簡單說明於本案所揭示之發明中之代表性者之槪要 ，則如下述。 [1]記憶體系統係於系統基板上具備：可以控制記憶體 動作之控制器；以及可以裝置記憶體模組之記憶體連接器 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（5) (請先閱讀背面之注意事項再填寫本頁) ◦前述記憶體模組具有被接續於第1模組配線與第2模組 配線之複數之記憶體晶片。前述記憶體連接器具有：在記 憶體模組間串列接續被裝置之複數之記憶體模組之第1模 組配線之串列路徑（133、134、1 35 );以及並列接續於 被裝置之複數之記憶體模組之第2模組配線之並列路徑（ 137、138、139)。前述系統基板具有：接續於前述串列 路徑之第1系統配線（1 07 );以及共通接續於前述並列 路徑之第2系統配線（108 )。 前述第1模組配線以及前述串列路徑例如與第1系統 配線形成串列接續形態，構成接續於前述控制器之記憶體 存取資料總線，前述並列路徑對於供給電源之第2系統配 線，構成分支電源配線。 別的形態爲前述第1模組配線以及串列路徑例如與第 1系統配線形成串列接續形態，構成接續於前述控制器之 時脈配線。 進而別的形態爲前述第1模組配線以及串列路徑與第 1系統配線形成串列接續形態，構成接續於前述控制器之 指令·位址配線。 經濟部智慧財產局員工消費合作社印製 在上述記憶體系統中，記憶體模組之第1模組配線（ 模組資料配線）構成記憶體存取資料總線之故，在並列複 數個之記憶體模組之記憶體系統中，各記憶體模組之模組 資料配線被一連串接續，個個之模組資料配線不構成對於 記憶體系統之系統基板上之第1系統配線之分支配線。因 此，不產生起因於對於系統基板上之第1系統配線之資料 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（6) (請先閱讀背面之注意事項再填寫本頁) 總線之分支之信號反射。電源等透過並列路徑由系統基板 並列供給於各記憶體模組之故，電源之供給安定化。例如 ，如將電源串列供給記憶體模組，在中途，1個之記憶體 模組如產生電源雜訊，其之影響有傳播於後段之虞。在上 述手段中，沒有此種虞慮，於記憶體動作可以保證高信賴 性。 經濟部智慧財產局員工消費合作社印製 [2]依據更具體之觀點之記憶體系統係在系統基板具備 :可以控制記憶體之控制器；以及可以裝置記憶體模組之 記憶體連接器。前述記憶體模組具有：具有晶片資料端子 之複數之記憶體晶片、對應複數之記憶體晶片之個別之晶 片資料端子，個別被設置之複數之模組資料配線、以及模 組電源配線。前述記憶體連接器具有：在記憶體模組間串 列接續被裝置之複數之記憶體模組之前述模組資料配線之 串列路徑；以及並列接續被裝置之複數之記憶體模組之模 組電源配線之並列路徑。前述系統基板具有：接續於前述 串列路徑之系統資料配線；以及共通接續於前述並列路徑 之系統電源配線。前述串列路徑與被裝置於記憶體連接器 之記憶體模組之模組資料配線以及系統資料配線一齊地構 成記憶體存取資料總線，前述並列路徑與被裝置於記憶體 連接器之記憶體模組之模組電源配線以及系統電源配線一 齊地構成電源配線。 藉由此手段也與上述同樣地，不產生起因於對於記憶 體系統之主機板上之資料總線之分支之信號反射。進而電 源等透過並列路徑由系統基板並列供給於各記憶體模組之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 539952 A7 B7 五、發明說明（7) 故，電源之供給安定化。之外，在上述記億體系統中，記 憶體模組被保證因應記憶體存取資料總線之寬幅之位元數 之並列存取。藉由此，一邊抑制存取時間之增加，一邊抑 制由於信號反射之信號波形之錯亂，可以提升信號傳送之 信賴性。 [3]進而依據別的觀點之記憶體系統係在系統基板具備 :可以控制記憶體動作之控制器；以及可以裝置記憶體模 組之記憶體連接器，前述記憶體模組具有被接續於模組資 料配線之複數之記憶體晶片，前述記憶體連接器作爲在記 憶體模組間串列接續被裝置之複數之記憶體模組之模組資 料配線之串列路徑。而且，前述系統基板具有：一端接續 於前述串列路徑，另一端被接續於終端電阻，前述控制器 之資料端子被接續於中間部之系統資料配線。 特別是如依據此手段，控制器之資料端子直接被接續 於系統資料配線之故，由系統資料配線對控制器之非所期 望之分支實質上不存在，在該部份也不產生非所期望之信 號反射。 如欲積極表明在前述系統資料配線與前述控制器之資 料端子之接續點不產生非所期望之分支，可以定義該接續 點係被包含於一直線之配線路徑。或即使產生分支，與應 保證正常動作之信號之狀態轉換時間相比，使該信號往返 分支部份之配線路徑之時間短地，使該分支部份之配線路 徑長變短便完全沒有問題。 呼應藉由前述控制器之記憶體晶片之寫入動作，可以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） --------------------訂---------線" (請先閱讀背面之注意事項再填寫本頁) 539952 A7 B7 五、發明說明（8) (請先閱讀背面之注意事項再填寫本頁) 使前述終端電阻由前述系統資料配線分離。記憶體控制器 側之終端電阻假定由記憶體晶片被讀出之信號反射之故， 呼應記憶體晶片之寫入動作，如使前述終端電阻由前述系 統資料配線切離，可以低消費電力與使信號振幅變大。 [4] 如著眼於輸出電路之形式與終端電阻，記憶體系統 係在系統基板具備：可以控制記憶體動作之控制器；以及 可以裝置記憶體模組之記憶體連接器，前述記憶體模組具 有晶片資料端子被接續於模組資料配線之複數之記憶體晶 片，前述記憶體連接器具有在記憶體模組間串列接續被裝 置之複數之記憶體模組之模組資料配線之串列路徑，前述 系統基板具有接續於前述串列路徑之一端部之同時，被接 續於前述控制器之資料端子之系統資料配線。此時，前述 記憶體晶片具有結合於晶片資料端子之開放汲極輸出電路 時，不於前述系統資料配線設置終端電阻，在前述串列路 徑之另一端接續終端電阻即可。反之，前述控制器具有結 合於其之資料端子之開放汲極輸出電路時，不於前述串列 路徑之另一端設置終端電阻，於前述系統資料配線接續終 端電阻即可。 經濟部智慧財產局員工消費合作社印製 開放汲極輸出電路之輸出阻抗高，輸出動作時之輸出 阻抗幾乎保持一定之故，對於由該開放汲極輸出電路被輸 出之信號之傳播終端部，即使不設定終端電阻，不易受到 非所期望之電壓反射之影響。藉由此，可以低消費電力與 使信號振幅變大。 [5] 上述記憶體系統例如利用於個人電腦、工作站、或 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 — B7 五、發明說明（9) 伺服器之需要大容量之資料處理系統特別有效。此時，設 置被接續於前述記憶體系統之控制器，可以存取前述記憶 體系統之記憶體晶片之資料處理器，構成資料處理系統。 即使使記憶體系統之頻率變高，依據上述，信號波形不易 變亂，高速資料傳送也變可能，有助於藉由電腦系統之資 料處理速度之提升。 [6]終端電阻可以接續於系統資料配線地內藏於前述控 制器，依循對於記憶體晶片之存取形態等控制與系統資料 配線之接續亦可。 發明之詳細說明 《第1記憶體系統》 圖1係本發明之記憶體系統之平面圖，圖2係記憶體 系統之正面圖。 被顯示於同圖之記憶體系統雖然沒有特別限制，係於 主機板101具有：記憶體控制器102、連接器104A、104B 、終端電阻10 5、10 6、信號配線1 0 7、電源配線1 0 8、終 端電壓電源配線1 09，例如前述記憶體模組1被裝置於連接 器104A、104B而構成。 前述信號配線1 07係由被例示於圖2之資料信號配線 1 1 2、位址·指令信號配線1 1 3、時脈信號配線1 1 7所構成 〇 如被顯示於圖2般地，被搭載於1個之記憶體模組1 之同一面之記憶體晶片1 1之記憶體位址·指令輸入端子與 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------#i (請先閱讀背面之注意事項再填寫本頁) ·. •線· 經濟部智慧財產局員工消費合作社印製 539952 Α7 Β7 五、發明說明（3 (請先閒讀背面之注意事項再填寫本頁) 位址·指令緩衝器晶片1 2之位址·指令信號輸出端子分別 藉由模組指令·位址分配配線1 9被接續。記億體模組1上 之記憶體晶片1 1係由前述位址·指令緩衝器晶片12透ϋ 模組指令·位址分配配線1 9接受位址·指令信號。又’被 搭載於1個之記憶體模組1之同一面之記憶體晶片1 1之 時脈輸入端子與位址·指令緩衝器晶片1 2之時脈輸入端子 與PLL晶片1 3之時脈輸出端子分別藉由時脈分配配線20被 接續，記憶體晶片1 1與位址·指令緩衝器晶片1 2係由 PLL晶片1 3透過時脈分配配線20接受時脈信號。 又，如被顯示於圖2般地，被搭載於1個之記憶體模 組1之同一面之記憶體晶片1 1之記憶體資料端子被接續於 被形成在記憶體模組1之模組資料配線1 5，指令·位址緩 衝器晶片1 2之指令·位址輸入端子被接續於被形成在記憶 體模組1之模組指令·位址配線1 6，PLL晶片1 3之時脈輸 入端子被接續於被形成在記憶體模組1之時脈配線1 7。 如被例示於圖1般地，複數個之記憶體模組1在主機 板1 0 1上被平行配置，記憶體模組1藉由左右之連接器 104Α、104Β相互以串列形態被接續。 經濟部智慧財產局員工消費合作社印製 如參考圖1，前述連接器104Α、104Β具有在個別之 記憶體模組1之間串列接續被裝置之複數之記憶體模組1之 模組資料配線1 5 (模組指令·位址配線、模組時脈配線1 7 )之連接器內配線1 3 5、1 3 3，這些連接器內配線1 3 5、 1 33構成以串列形態接續模組資料配線1 5 (模組指令·位 址配線、模組時脈配線17 )之串列路徑。又，雖然在圖1 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 539952 A7 B7 五、發明說明（1]) (請先閱讀背面之注意事項再填寫本頁) 以及圖2省略圖示，但是，模組基板形成有比較寬幅之數 種之電源圖案之模組電源配線。此模組電源配線並列接續 於連接器內電源配線137、138、139，構成並列路徑。 如被例示於圖2般地，連接器104A、104B具有由主 機板1 0 1對記憶體模組1供給電源用之電源配線1 〇8 ’又’ 具有接續相鄰記憶體模組之信號端子間之信號配線1 〇7 ( 112、113、117)。前述信號配線107構成接續於前述串 列路徑之第1系統配線，前述電源配線1 08構成共通接續 於前述並列路徑之第2系統配線。在主機板上信號配線1 〇7 通過記憶體控制器1 02之下，導通於複數之記憶體模組1 1 內以及連接器104A、104B內，在其兩端或至少單側之端 部，透過前述終端電阻105、106於終端電壓電源配線1〇9 中，被終結於指定之電壓VTT。 經濟部智慧財產局員工消費合作社印製 如被顯示於圖2般地，前述記憶體控制器1 〇2之信號 端子在記憶體控制器1 02下面側接續於通過記憶體控制器 1 02之下之信號配線1 07。如圖1般地，記憶體模組1上之 記憶體晶片1 1之資料端子接續於通過記憶體模組1之資料 信號配線1 1 2。又，對於位址·指令信號配線1 1 3以及時脈 信號配線1 1 7，記憶體控制器1 02側終端電阻1 1 4也可以沒 有。位址·指令信號以及時脈信號係只在單方向被傳播之 信號之故。記憶體模組1上之位址·指令緩衝器1 2之位址 .指令輸入端子分別接續於通過記憶體模組1之位址·指 令信號配線1 1 3。記憶體模組1上之PLL晶片1 3之時脈輸 入端子接續於通過記憶體模組1之時脈信號配線1 1 7。此處 -T4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（θ (請先閱讀背面之注意事項再填寫本頁) ’設記憶體晶片1 1之資料端子數爲η，被搭載於記憶體模 組1之單面之記憶體晶片丨1之數目爲m，圖1之記憶體系 統具有mxn之資料信號配線丨丨2，於1次之存取中，藉由記 憶體控制器1 02發生之指令信號之中之晶片選擇信號，被 搭載於複數之記憶體模組內之1個之記億體模組之單面之 m個之記憶體晶片1 1被選擇。 圖3係圖1以及圖2之記億體系統之槪略等效電路圖， 特別是顯示1條之資料信號配線系統。如電路地來看此資 料信號配線系統，主要是終端電源1 〇9、終端電阻1 05、 經濟部智慧財產局員工消費合作社印製 106、主機板之資料信號配線112、連接器104A之內部配 線、連接器1 04B之內部配線1 35、記憶體模組1之模組資 料配線1 5被串列接續。此處，主機板1 〇 1之資料信號配線 1 1 2以及記憶體模組之模組資料配線丨5之全體之長度成爲 數10mm之故，電路上被當成傳送線處理。而且，在主機板 1 〇 1之資料信號配線1 1 2之終端電阻1 05側之單端具有記憶 體控制器1 02之記憶體控制器I/O端子1 28，記憶體控制器 102之輸出電路123之輸出電容以及記憶體控制器102之輸 入電路1 24之輸入電容等被視爲記憶體控制器I/O負荷電容 1 25。又，同樣地，在各記憶體模組1之模組資料配線1 5之 中途具有記憶體晶片1 1之資料端子（I/O端子）1 29，記憶 體晶片1 1之輸出電路1 20之輸出電容以及輸入電路1 2 1之 輸入電容等被視爲記憶體I/O負荷電容1 22。記憶體控制器 輸出電路1 23以及記憶體晶片1 1之輸出電路1 20中，電路 方式在此處並不過問爲推拉型（push-pull )型、開放汲極 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 539952 Α7 Β7 五、發明說明（β 型等。又，雖然未特別圖示出，例如，也可以有控制通過 率之機構，或控制輸出阻抗之機構。於此資料信號配線系 統中，兩側以終端電阻被終結係由於：對於由記憶體控制 器輸出電路1 23被傳送於記憶體晶片1 1之輸入電路1 2 1之 信號與由記憶體晶片1 1之輸出電路1 20被傳送於記憶體控 制器輸入電路1 24之信號之兩方防止反射之目的。因此， 對於如記憶體控制器1 02之位址輸出或指令輸出之只有單 方向之信號傳達路徑，只在遠端配置終端電阻即可，如前 述般地，省略圖1之終端電阻1 1 4也沒有問題。 此處，說明前述記憶體模組1之一例。圖4係記憶體 模組1之平面圖，圖5係側面圖。被顯示於圖4以及圖5之 記憶體模組1係複數個之記憶體晶片1 1、指令·位址緩衝 器晶片1 2、以及PLL晶片1 3分別被構裝於以環氧樹脂等形 成之槪略長方形之模組基板1 0之表裏。 記憶體模組1作爲模組內之配線，在模組基板1 〇之短 邊方向具有：模組資料配線1 5、模組指令·位置配線16、 模組時脈配線1 7，在模組基板1 0之長邊方向具有：模組指 令·位址分配配線19、以及模組時脈分配配線20。在模組 指令·位址分配配線1 9以及模組時脈分配配線20設置終端 電阻22、23。終端電阻22、23將模組指令·位址分配配 線1 9、模組時脈分配配線20之末端終結於終端電源’具有 被接續之配線之特性阻抗或實效之特性阻抗之電阻値。這 些配線15、16、17、19、20同等被形成在模組基板1〇 之表裏。又，記憶體模組上之標記28係將記憶體模組1裝 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -16- -------------φί — (請先閱讀背面之注意事項再填寫本頁) . 丨線 539952 Λ7 B7 五、發明說明（Μ 置於連接器之際，指示記憶體模組1之裝置方向者。 (請先閱讀背面之注意事項再填寫本頁) 記憶體模組1作爲模組外部端子，在模組基板1 0之對 向之長邊部份具有：模組資料端子對24R、24L、模組指令 •位址端子對25R、25L、以及模組時脈端子對26R、26L 。這些模組外部端子24R、24L、25R、25L、26R、26L 被同等形成在模組基板1 0之表裏。 前述模組資料配線1 5接續左右之對應之模組資料端子 對24R、24L。而且，記憶體晶片1 1之記憶體資料端子Dm 被接續在模組資料配線1 5之中途。記憶體晶片1 1例如係 陣列狀具有電路基板構裝用之凸緣（bump )電極之覆晶（ 或覆晶型半導體積體電路）。記憶體資料端子Dm例如被設 爲覆晶之焊錫凸緣電極。於記憶體晶片1 1中，在此種記 憶體資料端子Dm被賦予〇標記。 經濟部智慧財產局員工消費合作社印製 前述模組指令·位置配線1 6係接續左右之對應之模組 指令·位址端子對25R、25L。而且，指令·位址緩衝器晶 片1 2之緩衝器指令·位址輸入端子CAi被接續於模組指 令·位置配線1 6之中途。例如，指令·位址緩衝器晶片 1 2也示前述覆晶。前述緩衝器指令·位址輸入端子CA: 也被設爲焊錫凸緣電極，於指令·位址緩衝器晶片1 2中 ，此種緩衝器指令·位址輸入端子CAi被賦予〇標記。 前述模組時脈配線1 7接續左右之對應之模組時脈端子 對26R、2 6L。而且，PLL晶片13之PLL時脈輸入端子CLi 被接續於模組時脈配線1 7之中途。例如，PLL晶片1 3爲覆 晶，PLL時脈輸入端子CLi被設爲焊錫凸緣電極，於PLL晶 本紙張尺度適用中國國家標準（CNS)A4規格（2]0 X 297公釐） 539952 A7 B7 五、發明說明（3 片1 3中，此種PLL時脈輸入端子CLi被賦予〇標記。 (請先閱讀背面之注意事項再填寫本頁) 前述模組指令·位址分配配線1 9係沿著模組基板1 〇之 長邊方向被敷設’其之中間部份被接續於前述指令.位址 緩衝器晶片1 2之緩衝器指令·位址輸出端子c A」。同樣 地，模組時脈分配配線20係沿著模組基板1 〇之長邊方向被 敷設，其之中間部份被接續於PLL時脈輸出端子CLj。前 述緩衝器指令·位址輸出端子CA]與PLL時脈輸出端子CLj 係以三角形被顯示之緩衝器之輸出端子被接續地象徵地被 顯示著。 前述記憶體晶片1 1之指令·位址輸入用之記憶體指 令·位址端子（未圖示出）被接續於前述模組指令·位址 分配配線1 9，又，前述記憶體晶片1 1之時脈輸入用之記憶 體時脈端子（未圖示出）以及緩衝器晶片1 2之時脈輸入用 之緩衝器時脈端子（未圖示出）被接續於前述模組時脈分 配配線20。記憶體晶片1 1以及緩衝器晶片1 2與由PLL晶 片1 3透過模組時脈分配配線20被供給之時脈信號同步，使 得記憶體動作以及栓鎖動作成爲可能。 經濟部智慧財產局員工消費合作社印製 又，在圖4中，前述記憶體指令·位址端子、記憶體 時脈端子、緩衝器時脈端子、以及晶片電源端子並無明白 圖示。又，於圖4中，動作電源用之模組電源端子以標號 202L、202R 顯示之。 圖6係顯示關於前述記憶體模組1之記憶體晶片之佈線 之例。模組基板1 0於表裏各具有第1層（表層）以及第2 層（內層）之2層配線構造，第1層之配線以實線表示， 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） 539952 A7 B7 五、發明說明（1今 ---------------- (請先閱讀背面之注意事項再填寫本頁) 第2層之配線以虛線表示。圖中，〇標記係記憶體晶片之 凸緣電極之類的外部端子，•標記係配線層之孔（層間孔 )。圖之記憶體晶片係以同步D R A Μ爲一例者，A 0〜A 1 3爲 位址，DO〜15爲資料，CLK、/ CLK係2相時脈。CKE係 時脈啓動，DML、DMU係資料遮罩，/ CS係晶片選擇， / RAS係列位址選通脈衝，/ CAS係欄位址選通脈衝，/ WE係寫入啓動，DQSL、DQSU係資料選通脈衝之存取控 制信號或指令信號。被顯示於圖6之VCCQ、VSSQ、VCC 、VSS、VSSQ係電源端子。 模組指令·位址分配配線1 9以及模組時脈分配配線20 係以正交於模組基板1 0上之模組資料配線1 5之形式被佈線 。由圖6可以明白地，個別之信號配線1 9、20與記憶體晶 片1 1之對應端子透過可以一直線之配線路徑被接續。如依 據此一直線配線路徑，很淸楚模組指令·位址分配配線1 9 以及模組時脈分配配線20其本身沒有分支。 -線. 經濟部智慧財產局員工消費合作社印制农 如由非所期望之信號反射之抑制的觀點來看，前述一 直線路徑雖然係最適當，但是並不是否定全部之配線分支 者。大略如滿足以下之條件，不產生非所期望之信號反射 。即，DO、D 1等用之模組資料配線1 5被形成在模組基板 1 0之第2層之配線層，透過孔（層間孔）接續於記憶體晶 片1 1之記憶體資料端子Dm時，孔之部份形成少許分支部 。因此，模組資料配線1 5雖然成爲可以一直線之第1配線 路徑，但是由此第1配線路徑分支，接續於記憶體資料端 子Dm之孔之部份構成第2配線路徑。此時，前述第2配線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（Μ (請先閱讀背面之注意事項再填寫本頁) 路徑之配線路徑長只要被設定爲例如與應保證正常動作之 信號的狀態轉換時間相比，該信號往復前述第2配線路徑 之時間變短即可。總之，在信號反射之點可以忽視之信號 路徑之短的分支部份實質上可以視爲一直線配線路徑之一 部份。 如圖6之DO、D 1般地，如將前述記憶體資料端子至少 在鄰接端子相互間於模組資料配線之延伸存在方向錯開配 置，記憶體資料端子Dm與模組資料配線1 5之接觸可以容 易形成。 圖7係槪略顯示連接器104A、104B之資料配線部份之 縱剖面圖。連接器1 04A在一方之側面具有1條之水平溝， 在此水平溝之內面之上面以及下面形成連接器端子列1 30 。連接器端子列1 30係每一連接器端子透過連接器內配線 135被接續於資料信號配線112之對應配線。連接器104 B係 在兩側面具有各1條之水平溝，在此水平溝之內面的上面 以及下面形成連接器端子列131、132。此處之連接器端子 列1 3 1之端子與連接器端子列1 32之端子其對應端子間係藉 由連接器內配線133、134而被串列接續。 經濟部智慧財產局員工消費合作社印製 圖8係槪略顯示連接器104A、連接器104B之電源配線 部份之縱剖面圖。電源配線1 08被設置於主機板1 0 1，被包 含於連接器端子列1 30之電源連接器端子透過連接器內配 線1 37被接續於前述電源配線1 08，被包含於連接器端子列 1 3 1之電源連接器端子透過連接器內配線1 3 8被接續著，被 包含於連接器端子列1 32之電源連接器端子透過連接器內 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Α7 __ Β7 五、發明說明（1 (請先閱讀背面之注意事項再填寫本頁) 配線1 39被接續著。關於電源雖然採用圖7之接續也可能， 但是採用圖8之接續形態對於記億體晶片1 1等之電源供給 可以安定化。關於前述指令·位址配線Η 3也與電源配線 136相同地，也可以接續於連接器104Α、連接器104Β之連 接器端子列130、131、132。 圖9係在連接器104Α、連接器104Β裝置上述記憶體模 組1之際之斜視圖。在前述連接器104Α、連接器104Β裝置 上述記憶體模組1時，如圖9所示般地，記憶體模組1之端 子列插入連接器104Α、連接器104Β之端子列130、131地 進行插入。此時，連接器之標記140係指示記憶體模組1之 面的面向與方向者，使記憶體模組1之裝置方向指示標記 28與連接器之標記140成爲最接近地調整記憶體模組1之面 與方向。 經濟部智慧財產局員工消費合作社印製 圖10係在連接器104Α、連接器104Β裝置上述記憶體 模組1時之剖面圖。在圖1 0中，爲了方便，將接續於記憶 體模組1之上側之記憶體晶片之路徑當成信號路徑，接續 於記憶體模組1之下側之記憶體晶片之路徑當成電源路徑 。資料信號路徑被設爲不分支連接器104Α、連接器104Β 以及記憶體模組1而通過之配線路徑。又，各記憶體模組1 之電源配線也透過主機板1 0 1之電源配線1 08以及分別被裝 置之連接器104Α、連接器104Β被接續之故，可以實現充 分之電力供給，能夠防止電源之電壓降低。 如依據上述第1記憶體系統，可以獲得以下之作用效 果。由圖1以及圖2可以明白地，記憶體模組1上之模組 -'Z\ ~ 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（1 (請先閱讀背面之注意事項再填寫本頁) 資料配線1 5與主機板1 〇 1上之資料信號配線π 2 —齊構成 記憶體存取資料總線之故’在串列接續複數個之記憶體模 組1之記憶體系統中，各記憶體模組1之模組資料配線15 被一連串接續，個個之模組資料配線1 5不構成對於記憶體 系統之主機板1 〇 1上之資料信號配線11 2之分支配線。因此 ，不會產生起因於對於記億體系統之主機板1 〇 1上之資料 信號配線1 1 2之分支之信號反射。例如，在具有圖Π以及 圖12之SSTL介面之比較例之記憶體系統之情形，對於主 機板上之總線，記憶體模組被分支接續之故’於每一分支 配置短截線電阻以對應非所希望之信號反射。因此，在比 較例中，主機板上之總線本身之延遲成分變大，妨礙高速 動作。在圖1以及圖2之記憶體系統中，主機板上之信號 配線之非所期望之負荷不變大，阻止信號反射之構成不會 妨礙高速動作。 進而，於個個之記憶體模組1上，記憶體晶片1 1之資 料端子D m直接與前述模組資料配線1 5接繪之故’起因於 對於模組資料配線1 5之分支之信號反射也不會產生。 經濟部智慧財產局員工消費合作社印製 而且，記憶體模組1被保證因應記億體存取資料總線 之總線寬之位元數的並列存取。藉由此’可以一面抑制存 取時間之增加，一面抑制由於信號反射之信號波形之錯亂 ，能夠提升信號傳送之信賴性。在被顯示於圖1 3以及圖1 4 之比較例之情形，在記憶體模組上複數之記憶體晶片共以 模組內資料總線，記憶體模組被串列接續於串列總線’該 記憶體模組未被分支接續於串列總線之故’雖然實質上不 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 — B7 五、發明說明（q 會產生起因於分支之信號反射，但是，總線變長，配線負 荷增加之故，在高速存取有界限。 (請先閱讀背面之注意事項再填寫本頁) 電源等透過由前述連接器內配線1 3 7、1 3 8、1 3 9形成 之並列路徑，由主機板1 0 1並列被供給於各記憶體模組1之 故，電源或時脈之供給安定化。例如，如將電源串列供給 記憶體模組，在中途如1個之記憶體模組產生電源雜訊， 其影響會有傳播於後段之虞。在由並列路徑並列供給動作 電源之情形，沒有那種虞慮，於記憶體動作可以保證高信 賴性。 模組資料端子對24L、24R或模組資料配線1 5之形態 在前述複數之記憶體晶片1 1沿著模組基板1 0之長度方向被 排列時，前述模組資料端子對24L、24R配置於模組基板 1 〇之記憶體晶片搭載面之一方之長邊部份與另一方之長邊 部份。換言之，使前述模組資料配線1 5由模組基板1 0之記 憶體晶片之搭載面之一方之長邊部份朝向另一方之長邊部 份而延伸存在。藉由此，模組資料配線1 5之配線長必然變 短，配線之寄生電容或配線電阻變小。 經濟部智慧財產局員工消費合作社印製 使模組資料配線1 5在模組基板1 0之短邊方向直線狀敷 設、槪略十字狀敷設模組指令·位置配線1 6、20之故，最 適合於縮短模組資料配線與模組指令·位置配線支配線長 〇 又，結合模組位址端子對25R、25L之前述模組指令· 位置配線1 6透過指令·位址緩衝器晶片1 2被與指令·位址 分配配線1 9分離之故，也可以阻止在模組指令·位置配線 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（ 1 6上形成不能忽視之阻抗不匹配點。 對於前述模組指令·位址分配配線1 9配線，藉由以具 有其之特性阻抗之電阻元件22、23終結之，模組指令·位 址分配配線1 9之端部被匹配終結，於該配線1 9中，可以極 力抑制由於信號反射之波形之錯亂。 此處，說明圖1以及圖2之記憶體系統之資料信號波 形之模擬結果。 首先，作爲比較例，圖15顯示圖1 1之形式之記憶體 系統之SSTL之模擬電路。圖16Α顯示圖15之模擬電路之寫 入時之SSTL信號波形模擬之結果。圖16Β顯示圖15之模擬 電路之讀取時之SSTL信號波形模擬之結果。在如圖1 1之 電路形式之SSTL中，於高速動作或分支配線長之情形，有 接收端之信號波形產生錯亂之情形。 圖1 7係例示關於在圖2說明之記憶體系統之資料信號 之模擬電路。此處，寫入動作模擬時，驅動器20 1 0設爲在 記憶體控制器1 02，讀取動作模擬之情形，設爲在記憶體 模組。驅動器20 10係假定爲具有輸出電阻2009之推拉型輸 出電路。此處，設輸出電阻爲50 Ω。又，終端電阻Rt設爲 與資料信號配線之實效特性阻抗幾乎相同之値。記憶體控 制器側之終端電阻55 Ω爲記憶體控制器與近端記憶體模組 間之傳送線之特性阻抗幾乎相同之値。 圖1 8 A係圖1 7之模擬電路（圖2中說明之記憶體系統 )之寫入動作之模擬結果。如觀看被輸入記憶體晶片之資 料信號bQRO〜3(200 1〜2004)，與被顯示於比較例之圖16A之 本纸張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ------餐·II (請先閱讀背面之注意事項再填寫本頁) ·- --線_ 經濟部智慧財產局員工消費合作社印製 539952 A7 ___—_ B7 五、發明說明（θ (請先閱讀背面之注意事項再填寫本頁) 寫入動作之模擬結果之被輸入記億體晶片之資料信號 bQRO〜3(2101〜2104)相比，了解到波形之錯亂比較小。圖 1 8B係圖1 7之模擬電路（圖4中說明之記憶體系統）之讀 取動作之模擬結果。圖中DQRSIN1〜DQRSIN4係分別輸出記 憶體晶片之資料信號bQRO〜3(200 1〜2004)時，分別被輸入記 憶體控制器之資料信號〇(^31則〜4(2006)。如與圖163之比 較例之記憶體系統之讀取動作之模擬結果之以記憶體晶片 被輸入之資料信號DQRSIN 1〜4(2 106)相比，了解到波形之錯 亂比較小。於使輸出電阻爲1 5 Ω之系統中，同樣地可以獲 得良好之波形。在此情形，消費電力雖然增加，但是有可 以使邏輯振幅變大之效果。 《第2至第5記憶體系統》 經濟部智慧財產局員工消費合作社印製 圖1 9係依據本發明之第2記憶體系統之資料信號配線 系統之等效電路圖。在本記憶體系統中，如與圖3之第1 記憶體系統比較，第1開關230新被追加於記憶體控制器 1 02側之終端電阻1 05，又，第2開關23 1新被追加於與記 憶體控制器1 02相反側之終端電阻1 06。其中藉由在記憶體 之讀取（讀出）時使第1開關230開啓，而且，在記憶體 之寫入時，使之關閉，在記憶體之讀取（讀出）時，可以 使信號配線1 1 2之記憶體控制器1 02側之終端阻抗匹配。又 ，藉由使第2開關23 1在記憶體之寫入時開啓，在記憶體 之讀取（讀出）時關閉，在記憶體之寫入時，可以使由記 憶體控制器102連接於最遠端之信號配線135之終端阻抗匹 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（2弓 配。 (請先閱讀背面之注意事項再填寫本頁) 第1開關230以及第2開關23 1例如可以以MOS電晶 體形成之開關元件實現，其控制以記憶體控制器1 02因應 存取動作而控制即可。又，也可以使指令·位址緩衝器晶 片1 2具有該開關控制機能。 在上述圖3之第1記憶體系統中，由信號配線1 1 2以 及連接器內配線1 3 5等形成之串列配線路徑之兩端之終端 經常被電阻終結，記憶體之寫入時與記憶體之讀取（讀出 )時，在兩方之電阻流過電流，消費電力變大。在圖1 9之 第2記憶體系統中，由信號配線1 1 2以及連接器內配線1 3 5 等形成之串列配線路徑之兩端之終端中，因應記憶體之寫 入時與記憶體之讀取（讀出）時，只有一方被電阻終結， 只在一方之終端電阻流過電流之故，與第1記憶體系統相 比，可以謀求低消費電力。又，可以使邏輯振幅變大之故 ，可以使雜訊裕度變大。 經濟部智慧財產局員工消費合作社印製 圖20係依據本發明之第3記憶體系統之資料信號配線 系統之等效電路圖。被顯示於同圖之記憶體系統相對於圖 3之記憶體系統，在記憶體控制器1 〇2側之終端電阻1 〇5追 加開關230之點爲不同。藉由使開關230與記憶體之讀取（ 讀出）時開啓，在記憶體之寫入時關閉，在記憶體之讀取 (讀出）時，可以使信號配線1 1 2之記憶體控制器1 〇2側之 終端阻抗匹配。又，開關230可以以MOS電晶體實現，其 控制以記憶體控制器1 02進行即可。在上述第1記憶體系 統中，信號配線1 1 2之兩端之終端經常被電阻終結，於記 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Λ7 五、發明說明（21 (請先閱讀背面之注意事項再填寫本頁) 憶體之寫入時與讀出時，在兩方之電阻流過電流，消費電 力變大。相對於此，在第3記憶體系統中，信號配線1 1 2 之兩端之終端中，在記憶體之寫入時，只有與記憶體控制 器1 0 2相反側之終端以電阻1 〇 6被終結，只有一方流過電流 之故，與第1記憶體系統相比，可以低消費電力化。又， 也可以使寫入時之雜訊裕度變大。又，在第2記憶體系統 中，在信號配線1 1 2以及連接器內配線1 33、1 35之串列路 徑之兩端需要2個之開關，製造成本變大。於此點，在第 3記憶體系統中，開關成爲1個，與第2記億體系統相比 ，可以低成本化。 經濟部智慧財產局員工消費合作社印製 圖2 1係依據本發明之第4記憶體系統之資料信號配線 系統之等效電路圖。在本記憶體系統中，相對於圖3之第 1記憶體系統，記憶體控制器1 02側之終端電阻1 05被去除 ，進而，作爲記憶體晶片1 1之輸出電路，採用開放汲極型 之輸出電晶體2 3 3。推拉型輸出電路於動作時，電晶體之 輸出電阻變動之故，弄亂由信號配線1 1 2等形成之資料用 串列配線路徑之等效之特性阻抗，容易引起反射。相對於 此，如採用藉由開放汲極型輸出電晶體233構成之開放汲 極輸出電路，可以使動作時之輸出電阻高，幾乎爲一定之 故，於動作時，不會弄亂前述資料用串列配線路徑之實效 特性阻抗。藉由此理由，在本記憶體系統中，只以電阻106 阻抗匹配與記憶體控制器1 02相反側之終端。藉由此，終 端電阻成爲1個之故，與第1記憶體系統相比，可以低成 本化而且低消費電力化。 -'1!- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Λ7 B7 五、發明說明（2今 (請先閱讀背面之注意事項再填寫本頁) 圖2 2係第4記憶體系統之指令·位址信號配線之等效 電路圖。在指令·位址信號配線系統中，由記憶體控制器 1〇2朝向指令·位址緩衝器晶片1 2，只有單方向被傳送之 故，與其它例同樣地，終端電阻可以只爲與記憶體控制器 102相反側之終端之電阻106。 圖2 3係依據本發明之第5記憶體系統之資料信號配線 系統之等效電路圖。在被顯不於同圖之記憶體系統中，相 對於前述第1記憶體系統，與圖2 1之第4記憶體系統相 反，係與記憶體控制器1 02相反側之終端電阻1 06被去除， 記憶體控制器1 02之輸出電路係採用構成開放汲極型輸出 電路之開放汲極輸出電晶體235。藉由此，依據與圖2 1之 第4記憶體系統同樣之理由，與第1記憶體系統相比，可_ 以低成本化而且低消費電力化。 《記憶體控制器》 經濟部智慧財產局員工消費合作社印製 圖24係最適合於依據本發明之第1記憶體系統（參考 圖3 )之記憶體控制器1 02之電路圖。被顯示於同圖之記 憶體控制器1 02內藏與資訊信號配線1 1 2之實效特性阻抗匹 配之電阻1 05 A，被接續於資料信號端子240與記憶體控制 器內部之終端電源1 09A。藉由在第1記憶體系統使用採用 被顯示於同圖之構成之記憶體控制器1 02，圖1所示之主 機板1 0 1之記憶體控制器1 02側之外加終端電阻1 05變成不 需要，可以低成本化。 圖2 5係最適合於依據本發明之第2記憶體系統（參考 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（2今 (請先閱讀背面之注意事項再填寫本頁) 圖1 9 )之記億體控制器1 0 2之電路圖。被顯示於同圖之記 憶體控制益1 〇 2具有桌1開關切換信號端子2 4 1以及第2開 關切換信號端子242，輸出切換分別被設置於記憶體控制 器102之外部之第1開關243以及第2開關244之開啓、關 閉之信號。這些信號端子24 1、242之輸出係藉由輸出電路 246將記憶體控制器102之輸入模式信號245輸出於第1開 關切換信號端子24 1，又，反轉輸出電路247將記憶體控制 器之輸入模式信號245反轉輸出於第2開關切換信號端子 2 4 2而被輸出。此處，記憶體控制器1 〇 2之輸入模式信號 245在資料輸入時，被設爲位址“ Η "，在資料輸出時，被 設爲位準“ L"。又’被設置於記憶體控制器1 〇2之外部之 第1開關243以及第2開關244例如以MOS電晶體構成， 以閘極位準"Η "被設爲開啓，以閘極位準“ L “被設爲關 閉。藉由將本記憶體控制器1 02使用於第2記憶體系統， 如前述般地，可以抑制不需要之終端電阻之電力消費。終 端電阻1 05如圖24般地，也可以內藏於記憶體控制器1 〇2 〇 經濟部智慧財產局員工消費合作社印製 圖26係最適合於依據本發明之第3記憶體系統（參考 圖20 )之記憶體控制器1 〇2之電路圖。被顯示於同圖之記 憶體控制器1 02對於圖24之第1記憶體系統之記憶體控制 器，控制對內藏終端電阻105Α之信號端子240之接續之開 關250被內藏。此開關250以記憶體控制器102之輸入模式 信號2 4 5被開啓、關閉。藉由此，終端電阻1 〇 5 Α只在其成 爲需要之定時（Urrnng )，即記憶體控制器102之輸入時成 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A. 五、發明說明（ (請先閱讀背面之注意事項再填寫本頁) 爲有效。藉由此，藉由於第3記憶體系統採用圖2 6之記憶 體控制器1 02之構成，不需要之終端電阻之電力消費被抑 制，可以提供低消費電力之記憶體系統。不需要在記憶體 控制器1 0 2側之主機板1 01上設置終端電阻1 0 5之故，可以 低成本化。 圖27係顯示最適合於依據本發明之第3記憶體系統（ 參考圖20 )之記億體控制器1 02之進而別的電路圖。被顯 示於同圖之記憶體控制器1 02係圖25之第2記憶體系統之 記憶體控制器之反轉輸出電路247以及開關切換信號端子 242被去除者。藉由於第3記憶體系統之記憶體控制器1 〇2 採用圖27之構成，不需要之終端電阻之電力消費被抑制， 可以提供低消費電力之記憶體系統。 經濟部智慧財產局員工消費合作社印製 圖28係最適合於依據本發明之圖2 3之第5記憶體系 統之記憶體控制器之電路圖。被顯示於同圖之記憶體控制 器1 02係於圖2 4之第1記憶體系統之記憶體控制器1 02之 輸出電路採用構成開放汲極型輸出電路之開放汲極電晶體 25 1者。藉由於本發明之第5記憶體系統之記憶體控制器 1 02採用此構成，主機板1 0 1之記憶體控制器側之終端電阻 1 05成爲不需要，可以低成本化。當然如圖1所示般地，也 可以將終端電阻（1 05 )設置在記憶體控制器之外側。 《其它之記憶體系統之例》 圖29A、B、C係顯示與圖4不同構造之第2記憶體模 組之剖面。圖29A係1倉儲庫（bank )形式之記憶體模組 本紙張尺度適用;國國家標準（CNS)A4規格（210 X 297公釐） _ 3U _ 539952 B7 __ 五、發明說明（9 請先閱讀背面之注意事項再填寫本頁} 之資料信號配線之剖面圖。於本記億體模組2中’模組資 料端子對24L、24R係沿著模組基板1〇之一方之長邊部份 被配置於兩面。模組資料配線1 5透過貫穿孔200接續模組 資料端子對24R、24L。模組資料配線15與第1記憶體模 組1相同地，具有一直線之配線路徑，在模組資料配線15 與記憶體晶片1 1之晶片資料端子Dm之間，產生由於前述 孔（層間孔）被形成之實質上可以忽視程度之小的分支。 此分支部份由前述可以明白地，不成爲非所期望之信號反 射之原因。 圖29B係2倉儲庫形式之記憶體模組之情形的信號配 線之剖面圖。相對於在圖29A之記憶體模組2中，相對於1 條之模組資料配線1 5被接續於被設置在模組基板1 〇之單面 之1個之記憶體晶片1 1之記憶體資料端子Dm，在圖29B 之記憶體模組中，1條之模組資料配線1 5係一直線被接續 於被設置在模組基板1 0之兩面之記憶體晶片1 1、1 1之記 憶體資料端子D m、D m。 經濟部智慧財產局員工消費合作社印製 圖29C係記憶體模組2之電源配線之剖面圖。模組電源 配線20 1雖然被配線於記憶體晶片1 1之晶片電源端子Dp， 但是沒有必要以一直線配線路徑接續，由模組電源端子 20 2L、202R分別分支延伸存在。又，模組指令·位置配線 1 6或模組時脈配線1 7也可以與模組電源配線20 1同樣地處 理，也可以如圖4般地，與模組資料配線1 5同樣地處理。 圖30A係著眼於信號配線顯示第2記憶體模組2用之連 接器2 1 0。連接器2 1 0具有1條之垂直溝，連接器端子列在 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） H " 539952 Λ7 B7 五、發明說明（q (請先閱讀背面之注意事項再填寫本頁) 紙面之表裏方向被形成於垂直溝之左右內面，圖中顯示連 接器端子2 1 1、2 1 2爲代表。主機板上之資料信號配線1 1 2 被接續於連接器端子2 1 1、2 1 2，在此處被分開。 圖30B係著眼於電源配線顯示第2記憶體模組2用之連 接器2 1 0。作爲電源用之連接器端子被代表顯示之連接器 端子2 1 3、2 1 4分別被接續於由電源配線1 08被分支之分支 配線2 1 5、2 1 6，電源配線1 08在中途並未被電氣地分開。 圖3 1 A係關於信號配線顯示裝置記憶體模組2之記憶體 系統之剖面。於被顯示於同圖之記憶體系統中，記憶體模 組2如被裝置於連接器2 1 0，在連接器2 1 0被分開之資料信 號配線1 1 2透過記憶體模組2之模組資料配線1 5接續。 圖3 1 B係關於電源配線顯示裝置記憶體模組2之記憶體 系統之剖面。於本記憶體系統中，記憶體模組2如被裝置 於連接器2 1 0，記憶體模組2之模組電源端子透過連接器 2 1 0之電源連接器端子2 1 3、2 1 4接續於主機板1 0 1之電源 配線108。又，前述指令·位址信號配線1 13與圖30B之電 源配線1 0 8相同地，可以由主機板1 〇 1之指令.位址信號線 1 1 3透過連接器2 1 0接續於記憶體模組2，當然也可以如圖 經濟部智慧財產局員工消費合作社印製 3 1 B般地接續。 依據第2記憶體模組2，與上述同樣地，不製作成爲 非所期望之信號反射之原因之分支，可以不招致配線長之 增加，於主機板1 0 1之資料信號配線電氣導通接續記憶體 晶片。 圖32係本發明之第3記億體模組之平面圖。於被顯示 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 539952539952 A7 B7 V. Description of the invention (1) (Please read the precautions on the back before filling out this page) The present invention relates to the suppression of transmission signals caused by branches of wiring in memory systems using memory modules and the like Reflective technology is effective for high-speed access to the corresponding memory system. The small amplitude interface dedicated to the memory module is SSTL (Stub Senes Terminated Transceiver Logic: Stub Serial Termination Radio Transceiver Logic). About SSTL, for example, it was recorded in March, 1999, published by the Institute of Electronic Information and Communication, and English essay Vol. E82-C, No. 3. By Yasuhiro KONISHI, "Interface Technologies for Memories and ASICs-Review and Future Direction". The memory system by SSTL is mainly composed of a memory controller, signal wiring, connectors, and memory modules that are built on the motherboard. The memory module has m memory chips on each side of the module substrate. The employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints m units. The data terminals of the memory chip are connected to the module data terminals. The access control data terminals such as the address terminals of the memory chip are connected to the corresponding module access control terminals. One end of the aforementioned signal wiring is connected to the signal terminal of the memory controller, and the other end is terminated to a specified voltage. The plurality of memory modules are connected in parallel to the aforementioned signal wiring through a connector. Here, if the number of data terminals of the memory chip is η, and the number of single-sided memory chips mounted on each memory module is m, the memory system has data signal wiring of m X η. During one access, the chip selection signal generated by the memory controller is used to select one single-sided m memory chip mounted in a plurality of memory modules. The terminals of the aforementioned signal wiring are connected to the terminal voltage through a terminal resistor. In addition, the stub resistors for the memory controller are connected in series to the connected memory. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 Α7 B7 V. Description of the invention (2) The body controller and Signal wiring of the connector. (Please read the precautions on the back before filling out this page.) Here, the module wiring connecting the module terminals of the memory module and the terminals of the memory chip constitutes the wiring branched by the signal wiring of the motherboard through the connector. Stub resistors are arranged in these module wirings. These stub resistors have the function of alleviating the matching load for signal reflection of signal wiring. Generally, at the branch point of the wiring, the characteristic impedance does not match, and it is necessary to reduce the stub resistance used for it. If the characteristic impedance of the wiring is Z0, and the characteristic impedance of the stub wiring is ZsO, the resistance of the stub resistor 値 should be Zs0-Z0 / 2. However, if the resistance 値 of the stub resistance is increased, the voltage drop of the resistance is increased, so that the signal voltage of the address or data is attenuated, which may cause an error in the memory operation. Nevertheless, in order to avoid the attenuation of the signal voltage, for example, the resistance 値 of the stub resistance is suppressed to be very small. On the contrary, the signal reflection becomes prominent and the signal waveform is disordered. Similarly, there is a risk of malfunction. As the operation is speeded up, the signal frequency is increased, and the longer the branch wiring to be countermeasured by the stub resistor, the larger the waveform distortion at the receiving end becomes. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. On the other hand, as another memory system, the inventor reviewed: the signal wiring connected to the memory controller on the motherboard is serially connected to multiple memories through the connector. Modular form. The present inventors reviewed: on a memory module, a plurality of memory chips are connected by a linear wiring path through the module data signal wiring. In this memory system, if the number of data signal terminals of a memory element is set to η, regardless of the number of memory elements m mounted on one side of the memory module, there are η module data signal wirings at 1 During the next access, the paper size of one of the plurality of memory chips applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) 539952 A7 B7 V. Description of the invention (3) The memory chip is select. (Please read the precautions on the back before filling this page) In the other memory systems mentioned above, for the signal wiring of the motherboard, all the memory modules are connected in series, and the module signals in the memory modules The wiring is connected in series to all the memory chips arranged in a row, and is laid along the long side direction of the memory module. Therefore, like the aforementioned SSTL, for signal wiring on the motherboard, the memory module hardly forms a branch wiring, and rarely has the problem of disordered waveforms due to undesired signal reflections generated in the branch wiring. However, as the length of the signal wiring increases, the signal propagation time from the memory controller to the farthest memory chip becomes longer, and the inventors have figured out that the delay of the access time will increase. As described above, in the SSTL form, the module wiring of the memory module becomes a branch wiring on the memory system, and due to this signal reflection error operation, there is a problem that the speed of the memory operation is limited, Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In a memory module in the form of a serially connected memory chip, the branch of the signal wiring of the SSTL as described above hardly exists. However, as the signal wiring in the memory module becomes longer and the access time is delayed, the inventors have figured out that there is a risk that it cannot cope with higher-level access at a higher level. After the inventor of the present case has completed the present invention, he recognizes the following well-known examples. Disclosed in JP-A No. 5-2343 5 and JP-A No. 6-1 50085. • Connectors are installed on the long sides of the memory module, and multiple memory modules can be connected in series. Invention. However, the wiring structure inside the memory module is not disclosed. Revealed in JP-A 7-3344 1-5-0-This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) 539952 A7 B7 V. Description of Invention (4) (Please read the Note: Please fill in this page again.) Note: Memory modules with expansion connectors that can be serially connected to expansion memory modules. Japanese Patent Application Laid-Open No. 7-26 1 892 discloses that an inlet connector and an outlet connector are provided in a memory module, and a memory bus on the memory module is used to connect between the memory modules, and the memory elements are serially connected to the memory. The invention of a body bus to suppress undesired signal reflection. However, the first weekly known examples of the first to the third are merely providing a technology that can serially connect the memory modules to form a memory system, and the fourth weekly known examples are only the memory buses displayed on the memory modules. The manner in which a plurality of memory elements are connected in a row form, and any of the well-known examples are those who have not reached the conception of the present invention. SUMMARY OF THE INVENTION The object of the present invention is to provide a memory system which can suppress the disorder of signal waveform due to signal reflection, can improve the reliability of signal transmission, increase the stability of memory operation, and can suppress the increase of access time. . Another object of the present invention is to improve the data processing speed of a computer system using a memory system. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The foregoing and other objects and new features of the present invention should become clear from the description in the detailed description and the drawings. If the summary of the representative of the invention disclosed in this case is briefly described, it is as follows. [1] The memory system is provided on the system substrate: a controller that can control the movement of the memory; and a memory connector that can install the memory module. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297). (Mm) 539952 A7 B7 V. Description of the invention (5) (Please read the precautions on the back before filling out this page) ◦ The aforementioned memory module has a plurality of connections to the first module wiring and the second module wiring Memory chip. The aforementioned memory connector has: a serial path (133, 134, 1 35) for connecting the first module wiring of the plurality of memory modules of the device in series between the memory modules; and the parallel connection to the device of the device Parallel path of the second module wiring of multiple memory modules (137, 138, 139). The system substrate includes: a first system wiring (107) connected to the parallel path; and a second system wiring (108) connected to the parallel path in common. The first module wiring and the serial path form, for example, a serial connection form with the first system wiring, and constitute a memory access data bus connected to the controller. The parallel path is configured for the second system wiring that supplies power. Branch power wiring. Another form is that the first module wiring and the serial path form, for example, a serial connection form with the first system wiring, and constitute a clock wiring connected to the controller. Furthermore, another form is that the first module wiring, the serial path and the first system wiring form a serial connection form, and constitute a command and address wiring connected to the controller. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in the above-mentioned memory system, the first module wiring (module data wiring) of the memory module constitutes the memory access data bus. In the memory system of the module, the module data wiring of each memory module is connected in series, and each module data wiring does not constitute a branch wiring for the first system wiring on the system substrate of the memory system. Therefore, no information is generated due to the wiring of the first system on the system substrate. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 V. Description of the invention (6) (Please read first Note on the back, please fill in this page again) Signal reflection of the branch of the bus. Since the power supply and the like are supplied in parallel to each memory module through the system substrate through the parallel path, the power supply is stabilized. For example, if a power supply is serially supplied to a memory module, halfway through, if one memory module generates power noise, its influence may spread in the later stage. In the above-mentioned method, there is no such concern, and high reliability can be ensured in the memory operation. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [2] According to a more specific point of view, the memory system is equipped with a controller on the system substrate that can control the memory; and a memory connector that can install a memory module. The aforementioned memory module includes a plurality of memory chips having chip data terminals, individual wafer data terminals corresponding to the plurality of memory chips, a plurality of module data wirings individually provided, and a module power wiring. The aforementioned memory connector has: a serial path of the aforementioned module data wiring of a plurality of memory modules connected in series between the memory modules; and a module of a plurality of memory modules connected in parallel to the device Parallel path for group power wiring. The system substrate includes: system data wiring connected to the parallel path; and system power wiring connected to the parallel path in common. The serial path and the module data wiring and the system data wiring of the memory module installed in the memory connector constitute the memory access data bus together, and the parallel path and the memory installed in the memory connector The module power wiring and system power wiring of the module form the power wiring together. By this means, as in the above, no signal reflection due to the branch of the data bus on the motherboard of the memory system is generated. Furthermore, the power supply, etc. are supplied in parallel to each memory module from the system substrate through a parallel path. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. V. Description of the invention (7) Therefore, the power supply is stabilized. In addition, in the above-mentioned memory system, the memory module is guaranteed to be accessed in parallel according to the wide number of bits of the memory access data bus. By this, while suppressing the increase of the access time, while suppressing the distortion of the signal waveform due to signal reflection, the reliability of signal transmission can be improved. [3] According to another point of view, the memory system is provided on the system substrate: a controller that can control the movement of the memory; and a memory connector that can install a memory module, which is connected to the module For a plurality of memory chips for data wiring, the aforementioned memory connector serves as a serial path for the module data wiring of the plurality of memory modules connected in series between the memory modules. In addition, the system substrate has one end connected to the serial path, the other end connected to a terminating resistor, and the data terminal of the controller connected to the system data wiring in the middle. Especially if according to this method, the data terminal of the controller is directly connected to the system data wiring, the undesired branch of the controller by the system data wiring does not exist substantially, and the unexpected is not generated in this part. The signal is reflected. If you want to positively show that the connection point between the system data wiring and the data terminal of the controller does not produce an undesired branch, you can define that the connection point is included in a straight wiring path. Or even if there is a branch, compared with the state transition time of the signal that should ensure normal operation, it is no problem to make the signal travel to and from the branch part of the wiring path in a short time, and shorten the length of the distribution line of the branch part. In response to the writing action of the memory chip of the aforementioned controller, the Chinese paper standard (CNS) A4 specification (210 X 297 public love) can be applied to this paper size --------------- ----- Order --------- line " (Please read the precautions on the back before filling this page) 539952 A7 B7 V. Description of the invention (8) (Please read the precautions on the back before (Fill in this page) Separate the aforementioned terminating resistor from the aforementioned system data wiring. The termination resistor on the side of the memory controller is assumed to be reflected by the read signal from the memory chip. In response to the writing action of the memory chip, if the aforementioned termination resistor is cut off by the aforementioned system data wiring, it is possible to reduce power consumption and use The signal amplitude becomes larger. [4] Focusing on the form of the output circuit and termination resistance, the memory system is provided on the system substrate: a controller that can control the movement of the memory; and a memory connector that can install a memory module, the aforementioned memory module A plurality of memory chips having a chip data terminal connected to the module data wiring, and the aforementioned memory connector has a series of module data wiring connected in series between the memory modules and a plurality of memory modules connected to the device. Path, the system substrate has a system data wiring connected to the data terminal of the controller while being connected to one end of the serial path. At this time, when the memory chip has an open-drain output circuit combined with the data terminal of the chip, a termination resistor is not set in the system data wiring, and a termination resistor may be connected to the other end of the serial path. Conversely, when the aforementioned controller has an open-drain output circuit coupled to its data terminal, it is not necessary to set a terminating resistor at the other end of the serial path, and connect the terminating resistor to the aforementioned system data wiring. The output impedance of the open-drain output circuit printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is high, and the output impedance during the output operation remains almost constant. No termination resistor is set, and it is not easily affected by undesired voltage reflection. This makes it possible to reduce power consumption and increase signal amplitude. [5] For example, the above memory system is used in personal computers, workstations, or this paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 539952 A7 — B7 V. Description of the invention (9) Server requirements Large-capacity data processing systems are particularly effective. At this time, the controller connected to the aforementioned memory system is set to access the data processor of the memory chip of the aforementioned memory system to constitute a data processing system. Even if the frequency of the memory system is increased, according to the above, the signal waveform is not easy to be chaotic, and high-speed data transmission is also possible, which helps to improve the data processing speed of the computer system. [6] The terminating resistor can be connected to the system data wiring ground and built in the aforementioned controller, and it can also be connected to the system data wiring according to the control of the memory chip's access mode. Detailed Description of the Invention "First Memory System" Fig. 1 is a plan view of the memory system of the present invention, and Fig. 2 is a front view of the memory system. Although the memory system shown in the same figure is not particularly limited, it is attached to the motherboard 101. It has a memory controller 102, connectors 104A, 104B, terminal resistors 10 5, 10, signal wiring 1 0 7, power wiring 1 0 8. Terminal voltage power supply wiring 109. For example, the aforementioned memory module 1 is configured by being mounted on the connectors 104A and 104B. The aforementioned signal wiring 1 07 is composed of the data signal wiring 1 1 illustrated in FIG. 2, the address and command signal wiring 1 1 3, and the clock signal wiring 1 1 7. As shown in FIG. 2, The memory address and command input terminal of the memory chip 1 1 mounted on the same side of one memory module 1 and the paper size apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --- ------ # i (Please read the notes on the back before filling this page). • Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 539952 Α7 Β7 V. Description of the invention (3 (please read the precautions on the reverse side before filling out this page) Address · Instruction buffer chip 1 2 Address · Instruction The signal output terminals are connected by the module command and address allocation wiring 19 respectively. The memory chip 11 on the memory module 1 is recorded by the aforementioned address and command buffer chip 12 module commands and bits. The address assignment wiring 19 receives the address and command signals. It is also mounted on the clock input terminal of the memory chip 1 1 on the same side of one memory module 1 and the address and command buffer chip 1 2 The clock input terminal and the clock output terminal of the PLL chip 13 are connected by the clock distribution wiring 20 respectively. The memory chip 11 and the address and instruction buffer chip 12 are distributed by the PLL chip 13 through the clock. The wiring 20 receives a clock signal. As shown in FIG. 2, the memory data terminals of the memory chip 11 1 mounted on the same side of one memory module 1 are connected to the memory data terminals formed in the memory. Module data wiring 1 of body module 1, 5, command and address buffer The instructions and address input terminals of the processor chip 12 are connected to the module instructions and address wiring 16 formed in the memory module 1, and the clock input terminals of the PLL chip 13 are connected to the formed memory Clock wiring 17 of module 1. As shown in FIG. 1, a plurality of memory modules 1 are arranged in parallel on the motherboard 1 0 1, and the memory modules 1 are connected by left and right connectors 104A. And 104B are connected in series with each other. As printed with reference to Figure 1 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the aforementioned connectors 104A and 104B have a plurality of devices connected in series between the individual memory modules 1. Module data wiring 1 5 of the memory module 1 (module command / address wiring, module clock wiring 1 7) Wiring in the connector 1 3 5, 1 3 3, Wiring in these connectors 1 3 5 , 1 33 constitutes a serial path for connecting module data wiring 1 5 (module command / address wiring, module clock wiring 17) in series. Also, although Figure 1-this paper scale applies Chinese national standards (CNS) A4 specifications (210 X 297 public love) 539952 A7 B7 V. Description of the invention (1)) (please first Read the precautions on the back and fill in this page) and Figure 2 is omitted. However, the module substrate has a wide range of module power wirings with several power patterns. This module power wiring is connected in parallel in the connector. The power supply wirings 137, 138, and 139 constitute a parallel path. As illustrated in FIG. 2, the connectors 104A and 104B have a power supply wiring 1 008 for supplying power to the memory module 1 from the motherboard 110. 'It has signal wiring 1 107 (112, 113, 117) between signal terminals connected to adjacent memory modules. The signal wiring 107 constitutes a first system wiring connected to the serial path, and the power supply wiring 108 constitutes a second system wiring commonly connected to the parallel path. The signal wiring 1 on the motherboard passes through the memory controller 10 02 and is connected to the plurality of memory modules 1 1 and the connectors 104A and 104B, at both ends or at least one side of the end, Through the terminal resistors 105 and 106, the terminal voltage power supply wiring 109 is terminated at a specified voltage VTT. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as shown in FIG. 2, the signal terminal of the aforementioned memory controller 10 is connected to the lower side of the memory controller 10 02 and passes under the memory controller 102. The signal wiring 1 07. As shown in FIG. 1, the data terminals of the memory chip 11 on the memory module 1 are connected to the data signal wiring 1 12 passing through the memory module 1. The address / command signal wiring 1 1 3 and the clock signal wiring 1 1 7 may be omitted from the memory controller 10 02 side termination resistor 1 1 4. Address, command and clock signals are signals that are propagated only in one direction. Address on memory module 1Address of instruction buffer 12 The command input terminals are connected to the address and command signal wiring 1 1 3 through the memory module 1, respectively. The clock input terminals of the PLL chip 1 3 on the memory module 1 are connected to the clock signal wiring 1 1 7 passing through the memory module 1. Here-T4- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 539952 A7 B7 V. Description of the invention (θ (Please read the precautions on the back before filling this page) 'Set up memory The number of data terminals of chip 1 1 is η, and the number of single-sided memory chips 丨 1 mounted on memory module 1 is m. The memory system of FIG. 1 has data signal wiring of mxn 丨 2 at 1. During the second access, the chip selection signal among the command signals generated by the memory controller 102 is mounted on one side of m of the memory module of one of the plurality of memory modules. The memory chip 11 is selected. Fig. 3 is a schematic equivalent circuit diagram of the record billion system of Fig. 1 and Fig. 2, especially showing a data signal wiring system. See the data signal wiring system in circuit ground Mainly are terminal power supply 1 09, terminal resistance 105, printed by employee consumer cooperatives 106 of the Intellectual Property Bureau of the Ministry of Economic Affairs, data signal wiring 112 of the motherboard, internal wiring of connector 104A, internal wiring of connector 1 04B 1 35 Module data wiring 1 for memory module 1 5 is connected in series. Here, the data signal wiring 1 12 of the main board 1 0 and the module data wiring of the memory module 丨 5 the entire length is several 10mm, so the circuit is treated as a transmission line In addition, the data signal wiring 1 12 of the main board 1 12 has a single-ended terminal resistance on the 05 side and a memory controller I / O terminal 1 28 on the memory controller 102 and a memory controller 102 on the memory controller 102. The output capacitance of the output circuit 123 and the input capacitance of the input circuit 1 24 of the memory controller 102 are regarded as the memory controller I / O load capacitance 1 25. Also, in the same manner, in the model of each memory module 1 Group data wiring 15 has the data terminal (I / O terminal) 1 29 of the memory chip 11 1 in the middle, the output capacitance of the output circuit 1 20 of the memory chip 1 1 and the input capacitance of the input circuit 1 2 1 etc. It is the memory I / O load capacitance 1 22. In the memory controller output circuit 1 23 and the memory chip 1 1 output circuit 1 20, the circuit method here is not a push-pull type, Open-drain paper standard is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 539952 Α7 Β7 V. Description of invention (β type etc.) Also, although not specifically illustrated, for example, there may be a mechanism for controlling the passing rate. Or the mechanism that controls the output impedance. In this data signal wiring system, the two sides are terminated with a terminating resistor because the memory controller output circuit 1 23 is transmitted to the memory chip 1 1 input circuit 1 2 1 The signal and the output circuit 120 of the memory chip 11 are transmitted to the memory controller input circuit 1 24 to prevent reflection. Therefore, for the signal transmission path with only one direction, such as the address output of the memory controller 102 or the command output, only the termination resistor can be configured at the far end. As mentioned above, the termination resistor 1 1 4 in FIG. 1 is omitted. No problem. Here, an example of the memory module 1 will be described. Fig. 4 is a plan view of the memory module 1, and Fig. 5 is a side view. The memory module 1 shown in FIG. 4 and FIG. 5 is a plurality of memory chips 1 1, the instruction / address buffer chip 1 2, and the PLL chip 1 3 are each formed by being formed of epoxy resin or the like. The surface of the module substrate 10 is slightly rectangular. The memory module 1 is used as the wiring in the module. In the short side of the module substrate 10, it has: module data wiring 1 5. module command and position wiring 16; module clock wiring 17; The longitudinal direction of the substrate 10 includes a module instruction / address allocation wiring 19 and a module clock allocation wiring 20. Termination resistors 22 and 23 are provided in the module command / address distribution wiring 19 and the module clock distribution wiring 20. The terminating resistors 22 and 23 terminate the module command and address allocation wiring 1 9. The end of the module clock distribution wiring 20 is terminated at the terminal power supply ', which has the characteristic impedance or the effective characteristic impedance of the connected wiring 値. These wirings 15, 16, 17, 19, and 20 are equally formed in the table of the module substrate 10. In addition, the mark 28 on the memory module is the memory module 1 installed on this paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -16- ---------- --- φί — (Please read the notes on the back before filling this page). 丨 Line 539952 Λ7 B7 V. Description of the invention (M is placed on the connector and indicates the device direction of memory module 1. (Please read the precautions on the back before filling this page) Memory module 1 as the module The external terminals are on the long side of the module substrate 10 in the opposite direction: module data terminal pairs 24R, 24L, module instructions • address terminal pairs 25R, 25L, and module clock terminal pairs 26R, 26L These module external terminals 24R, 24L, 25R, 25L, 26R, 26L are equally formed in the table of the module substrate 10. The aforementioned module data wiring 15 is connected to the corresponding module data terminal pair 24R, 24L. In addition, the memory data terminal Dm of the memory chip 11 is connected in the middle of the module data wiring 15. The memory chip 11 is, for example, an array-shaped flip chip with bump electrodes for circuit board construction. (Or flip-chip semiconductor integrated circuit). The memory data terminal Dm is, for example, a flip-chip solder flange electrode. In the memory chip 11, the memory data terminal Dm is given a 0 mark. Economy Consumer Cooperatives of Ministry of Intellectual Property Bureau The aforementioned module commands and position wiring 16 are connected to the corresponding module commands and address terminal pairs 25R and 25L. In addition, the command and address buffer terminal 12 of the command and address buffer chip 12 are Continuing in the middle of the module command and position wiring 16. For example, the command and address buffer chip 12 also shows the aforementioned flip chip. The buffer command and address input terminal CA: is also set as a solder flange electrode, In the command / address buffer chip 12, this buffer command / address input terminal CAi is given a 0 mark. The aforementioned module clock wiring 17 is connected to the corresponding module clock terminal pair 26R, 2 6L. In addition, the PLL clock input terminal CLi of the PLL chip 13 is connected in the middle of the module clock wiring 17. For example, the PLL chip 13 is a flip chip and the PLL clock input terminal CLi is a solder flange electrode. ， Applicable to China National Standard (CNS) A4 specification (2] 0 X 297 mm) for PLL crystal paper size. 539952 A7 B7 V. Description of the invention (3 pieces 1 in 3, this kind of PLL clock input terminal CLi is given.) (Please read the notes on the back before filling this page) The aforementioned module instruction and address allocation wiring 19 is laid along the long side direction of the module substrate 10, and its middle part is connected to the aforementioned instruction. Address Buffer command and address output terminal c A ″ of the buffer chip 12. Similarly, the module clock distribution wiring 20 is laid along the long side direction of the module substrate 10, and the middle portion thereof is connected to the PLL clock output terminal CLj. The buffer command and address output terminal CA] and the PLL clock output terminal CLj described above are successively and symbolically displayed as the output terminals of the buffer. The instructions of the aforementioned memory chip 111, the memory instructions for the address input, the address terminals (not shown) are connected to the aforementioned module instructions, the address allocation wiring 19, and the aforementioned memory chip 1 1 Memory clock terminals (not shown) for clock input and buffer clock terminals (not shown) for clock input of the buffer chip 12 are connected to the clock distribution wiring of the aforementioned module 20. The memory chip 11 and the buffer chip 12 are synchronized with the clock signal supplied from the PLL chip 13 through the module clock distribution wiring 20, thereby enabling the memory operation and the latching operation. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In addition, in FIG. 4, the memory instruction / address terminal, the memory clock terminal, the buffer clock terminal, and the chip power terminal are not clearly shown. In addition, in Fig. 4, the power terminals of the module for the action power supply are shown with reference numerals 202L and 202R. FIG. 6 shows an example of the wiring of the memory chip of the memory module 1 described above. The module substrate 10 has a two-layer wiring structure of the first layer (surface layer) and the second layer (inner layer) on the surface. The wiring of the first layer is indicated by a solid line. This paper standard applies Chinese National Standard (CNS) A4 Specifications (210x 297 mm) 539952 A7 B7 V. Description of the invention (1 today ---------------- (Please read the precautions on the back before filling this page) Wiring is indicated by dashed lines. In the figure, the 0 mark is an external terminal such as a flange electrode of a memory chip, and the mark is a hole (interlayer hole) in a wiring layer. The memory chip in the figure is a synchronous DRA M as an example A 0 ~ A 1 3 are addresses, DO ~ 15 are data, CLK and / CLK are 2-phase clocks. CKE is clock start, DML and DMU are data masks, / CS is chip selection, / RAS series bits Address strobe, / CAS is column address strobe, / WE is write enable, DQSL, DQSU are access control signals or command signals for data strobes. They are shown in VCCQ, VSSQ, VCC in Figure 6. VSS, VSS, and VSSQ are power terminals. Module instructions and address distribution wiring 19 and module clock distribution wiring 20 are orthogonal to those on the module substrate 10 The module data wiring 15 is wired. As can be clearly seen from FIG. 6, the respective signal wirings 19 and 20 and the corresponding terminals of the memory chip 11 are connected through a straight wiring path. If this is the case, the straight wiring path The module instruction and address allocation wiring 19 and the module clock allocation wiring 20 have no branches themselves. -Line. From the point of view of suppression by undesired signal reflections, from the standpoint of suppression of undesired signal reflections, the aforementioned linear path is the most appropriate, but it does not negate all wiring branches. Roughly if the following conditions are met, no unwanted signal reflection will occur. That is, the module data wiring 15 for DO, D 1 and the like is formed on the second wiring layer of the module substrate 10, and is connected to the memory data terminal Dm of the memory chip 11 through a hole (interlayer hole). At this time, the part of the hole forms a small branch. Therefore, although the module data wiring 15 becomes the first wiring path that can be aligned, the first wiring path is branched and the part connected to the hole of the memory data terminal Dm constitutes the second wiring path. At this time, the paper size of the aforementioned 2nd wiring paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 V. Description of the invention (M (please read the precautions on the back before filling this page) The length of the wiring path may be set to be shorter than the time required for the signal to reciprocate the second wiring path, for example, compared to the state transition time of the signal to ensure normal operation. In short, the signal path can be ignored at the point of signal reflection. The short branch part can be regarded as a part of the straight wiring path. As shown in DO and D 1 in Figure 6, if the aforementioned memory data terminals exist at least between adjacent terminals and the module data wiring, The orientation is staggered, and the contact between the memory data terminal Dm and the module data wiring 15 can be easily formed. Figure 7 is a longitudinal sectional view showing the data wiring part of the connectors 104A and 104B. The connector 1 04A is on one side. There is a horizontal groove on the side, and the connector terminal row 1 30 is formed on the upper and lower sides of the inner surface of the horizontal groove. The connector terminal row 1 30 is a connection through each connector terminal. The internal wiring 135 is connected to the corresponding wiring of the data signal wiring 112. The connector 104 B has one horizontal groove on each side, and the connector terminal rows 131 and 132 are formed on the upper and lower sides of the inner surface of the horizontal groove. The terminals of the connector terminal row 1 31 here and the terminals of the connector terminal row 1 32 are connected in series by the internal wiring 133 and 134 in the connector. Employee Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs The printed figure 8 is a longitudinal sectional view showing the power wiring part of the connector 104A and 104B. The power wiring 1 08 is installed on the motherboard 1 0 1 and is included in the connector terminal row 1 30 for the power connection. The connector terminals are connected to the power supply wiring 1 08 through the wiring in the connector, and the power connector terminals included in the connector terminal row 1 3 1 are connected through the wiring in the connector 1 3 8 to be included in the connector. The power connector terminals of terminal row 1 32 pass through the connector. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 539952 Α7 __ Β7 V. Description of the invention (1 (Please read the note on the back first) Please fill in this page again.) Wiring 1 39 is connected. Although the connection of Fig. 7 is also possible, the connection of Fig. 8 can be used to stabilize the power supply of the memory chip 11 and so on. Regarding the aforementioned instructions · The address wiring Η 3 can also be connected to the connector terminal rows 130, 131, and 132 of the connector 104A and 104B in the same manner as the power wiring 136. Fig. 9 shows the above-mentioned memory in the connector 104A and the connector 104B. An oblique view of the module 1. When the aforementioned memory module 1 is mounted on the connector 104A and the connector 104B, as shown in FIG. 9, the terminal row of the memory module 1 is inserted into the connector 104A and the connector. Insert the 104B terminal rows 130 and 131. At this time, the mark 140 of the connector indicates the direction and direction of the face of the memory module 1, so that the device direction indicator 28 of the memory module 1 and the mark 140 of the connector are closest to adjust the memory module. Face and direction of 1. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Fig. 10 is a cross-sectional view when the above-mentioned memory module 1 is installed at the connector 104A and the connector 104B. In FIG. 10, for convenience, a path of a memory chip connected to the upper side of the memory module 1 is taken as a signal path, and a path of a memory chip connected to the lower side of the memory module 1 is taken as a power path. The data signal path is a wiring path through which the connector 104A, the connector 104B, and the memory module 1 are not branched. In addition, the power supply wiring of each memory module 1 is also connected through the power supply wiring 108 of the main board 1 0 and the connectors 104A and 104B of the device, respectively, so that sufficient power supply can be realized, and power can be prevented. The voltage decreases. According to the first memory system, the following effects can be obtained. As can be clearly seen from Figure 1 and Figure 2, the module on the memory module 1-'Z \ ~ This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 V. Invention Explanation (1 (Please read the precautions on the back before filling in this page) Data wiring 1 5 and data signal wiring on the motherboard 1 〇 2 —they form the memory access data bus' In the memory system of each memory module 1, the module data wiring 15 of each memory module 1 is connected in series, and each module data wiring 15 does not constitute the motherboard 1 of the memory system. 〇1 The branch wiring of the data signal wiring 11 2 above. Therefore, no signal reflection due to the branch of the data signal wiring 1 1 2 on the motherboard 1001 of the system is recorded. For example, in the case of FIG. In the case of the memory system of the comparative example of the SSTL interface in FIG. 12, for the bus on the motherboard, the memory module is connected by branches. 'Stub resistors are arranged at each branch to correspond to undesired signal reflections. Therefore, in the comparative example, the main The delay component of the bus itself on the board becomes larger, preventing high-speed operation. In the memory system of Figures 1 and 2, the undesired load of the signal wiring on the motherboard does not increase, and the structure that prevents signal reflection does not increase. Obstructs high-speed operation. Furthermore, on each of the memory modules 1, the data terminal Dm of the memory chip 11 is directly connected to the module data wiring 15 described above. This is due to the module data wiring 1 5 The signal reflection of the branch will not be generated. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the memory module 1 is guaranteed to be accessed in parallel according to the number of bits of the bus width of the billion-byte access data bus. Therefore, it is possible to suppress the increase of the access time while suppressing the distortion of the signal waveform due to the signal reflection, which can improve the reliability of signal transmission. In the case of the comparative examples shown in FIG. 13 and FIG. The plurality of memory chips on the body module share the data bus in the module. The memory modules are serially connected to the serial bus. 'The memory module is not branched to the serial bus.' However, the paper size is not applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 — B7 V. Description of the invention (q will cause signal reflection due to the branch, but the bus becomes longer and the wiring load For reasons of increase, there is a limit in high-speed access. (Please read the precautions on the back before filling out this page.) Power supplies, etc. pass through the parallel paths formed by the wiring inside the connector 1 3 7, 1, 3 8, 1 3 9 Since the motherboard 1 101 is supplied in parallel to each memory module 1, the power supply or clock supply is stabilized. For example, if a power supply is supplied in series to the memory module, it is like a single memory module in the middle. If power noise is generated, its influence may spread in the later stage. In the case where the operation power is supplied in parallel from a parallel path, there is no such worry, and the memory operation can ensure high reliability. When the module data terminal pair 24L, 24R or module data wiring 15 is arranged in the aforementioned plurality of memory chips 11 along the length direction of the module substrate 10, the aforementioned module data terminal pair 24L, 24R is arranged One of the long side portions of the memory chip mounting surface of the module substrate 10 and the other long side portion. In other words, the module data wiring 15 is extended from one long side portion of the mounting surface of the memory chip of the module substrate 10 to the other long side portion. As a result, the wiring length of the module data wiring 15 must be shortened, and the parasitic capacitance or wiring resistance of the wiring becomes small. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to make the module data wiring 1 5 Straightly lay the module substrate 10 0 in the short direction of the module substrate, and lay out the cross-shaped module instructions. Location wiring 1 6 and 20 It is suitable for shortening the module data wiring and the module command and position wiring branch wiring length. In addition, the module command and position wiring of the module address terminal pair 25R and 25L are combined 1 6 through the command and the address buffer chip 1 2 Because it is separated from the command and address assignment wiring 19, it can also prevent the module command and position wiring -10- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 5 2. Description of the invention (16) Impedance mismatch points that cannot be ignored are formed. For the aforementioned module instructions and address allocation wiring 19, the wiring is terminated by the resistance elements 22 and 23 with its characteristic impedance, and the module instructions · The ends of the address allocation wiring 19 are matched and terminated. In this wiring 19, the distortion of the waveform due to signal reflection can be suppressed as much as possible. Here, the data signal waveforms of the memory system of FIGS. 1 and 2 will be described. simulation Results. First, as a comparative example, FIG. 15 shows the SSTL analog circuit of the memory system in the form of FIG. 11. FIG. 16A shows the simulation result of the SSTL signal waveform when the analog circuit of FIG. 15 is written. The result of simulation of SSTL signal waveform when reading the analog circuit of 15. In the SSTL of the circuit form as shown in Figure 11, in the case of high-speed operation or long branch wiring, the signal waveform of the receiving end may be disordered. 1 7 is an example of an analog circuit related to the data signal of the memory system described in FIG. 2. Here, when writing operation simulation, the driver 20 1 0 is set to the memory controller 102 and the reading operation simulation. It is set in the memory module. Driver 20 and 10 are assumed to be push-pull type output circuits with output resistance 2009. Here, the output resistance is set to 50 Ω. Also, the terminal resistance Rt is set to almost the effective characteristic impedance of the data signal wiring. The same. The terminal resistance 55 Ω on the side of the memory controller is the characteristic impedance of the transmission line between the memory controller and the near-end memory module is almost the same. Figure 1 A A Figure 17 The simulation result of the writing operation of the analog circuit (memory system illustrated in Fig. 2). For example, if the data signal bQRO ~ 3 (200 1 ~ 2004) of the inputted memory chip is viewed, it is shown in Fig. 16A of the comparative example. This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) ------ Meal · II (Please read the precautions on the back before filling out this page) · --- Line _ Ministry of Economy Printed by the Intellectual Property Bureau employee consumer cooperative 539952 A7 ___ —_ B7 V. Description of the invention (θ (Please read the precautions on the back before filling in this page) Write the simulation result of the data signal of the input billion chip chip bQRO Compared to ~ 3 (2101 ~ 2104), it is understood that the waveform distortion is smaller. Fig. 8B is a simulation result of the reading operation of the analog circuit of Fig. 17 (the memory system illustrated in Fig. 4). In the figure, DQRSIN1 ~ DQRSIN4 respectively output the data signals bQRO ~ 3 (200 1 ~ 2004) of the memory chip, and they are respectively input into the data signals of the memory controller 0 (^ 31 ~ 4 (2006). As shown in Figure 163 In the comparative example of the reading operation of the memory system, compared with the data signal DQRSIN 1 ~ 4 (2 106) input to the memory chip, it is understood that the waveform distortion is smaller. The output resistance is 1 5 In the Ω system, a good waveform can be obtained in the same way. In this case, although the power consumption is increased, it has the effect of increasing the logic amplitude. "Memory System 2 to 5" Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs consume The cooperative printed figure 19 is an equivalent circuit diagram of the data signal wiring system of the second memory system according to the present invention. In this memory system, as compared with the first memory system of FIG. 3, the first switch 230 is new A terminating resistor 1 05 is added to the memory controller 102 side, and a second switch 23 1 is newly added to the terminating resistor 1 06 on the opposite side of the memory controller 102. Among them, by reading in the memory Take (read) the first The switch 230 is turned on, and when the memory is written, it is turned off, and when the memory is read (read), the terminal impedance of the memory controller 102 side of the signal wiring 1 12 can be matched. In addition, the second switch 23 1 is turned on when writing to the memory, and turned off when reading (reading) from the memory. When writing to the memory, the memory controller 102 can be connected to The terminal impedance of the most remote signal wiring 135 is the same as the paper size of China National Standard (CNS) A4 (210 X 297 mm) 539952 A7 B7 V. Description of the invention (2 bows. (Please read the precautions on the back first) (Fill in this page again) The first switch 230 and the second switch 23 1 can be realized by, for example, a switching element formed of a MOS transistor, and the control can be controlled by the memory controller 102 in response to the access operation. The command / address buffer chip 12 has this switch control function. In the first memory system of FIG. 3 described above, two of the serial wiring paths formed by the signal wiring 1 12 and the connector wiring 1 3 5 etc. The end of the terminal is often terminated by a resistor, memory During the writing of the body and the reading (reading) of the memory, the current flows between the two resistors, and the power consumption increases. In the second memory system of FIG. 19, the signal wiring 1 1 2 and Among the terminals at both ends of the serial wiring path formed by the wiring in the connector, etc., only one side is terminated by a resistor in response to the writing of the memory and the reading (reading) of the memory. Compared with the first memory system, the current flowing through the terminating resistor can achieve lower power consumption. Furthermore, the logic amplitude can be increased, and the noise margin can be increased. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Figure 20 is an equivalent circuit diagram of the data signal wiring system of the third memory system according to the present invention. The memory system shown in the same figure is different from the memory system of FIG. 3 in that the termination resistor 1 105 on the memory controller 1 02 side adds the switch 230. The switch 230 and the memory are turned on when reading (reading), and are turned off when writing to the memory. When the memory is read (reading), the memory of the signal wiring 1 1 2 can be controlled. The impedance of the terminal on the side of device 1 〇2 is matched. The switch 230 may be implemented by a MOS transistor, and its control may be performed by a memory controller 102. In the above-mentioned first memory system, the terminals at both ends of the signal wiring 1 12 are often terminated by resistors. The paper size of the notebook applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 Λ7 V. Invention Explanation (21 (Please read the precautions on the back before filling out this page) During the writing and reading of the memory, the current flows through the resistance of both sides, and the power consumption increases. In contrast, in the third memory In the system, among the terminals at both ends of the signal wiring 1 12, only the terminal on the opposite side of the memory controller 102 is terminated by the resistor 10 when writing to the memory, and only one of the terminals flows a current. Therefore, compared with the first memory system, the power consumption can be reduced. Also, the noise margin at the time of writing can be increased. In the second memory system, the signal wiring 1 12 and Two switches are needed at both ends of the tandem path of wiring 1 33 and 1 35 in the connector, which increases the manufacturing cost. At this point, in the third memory system, the number of switches is one, which is the same as the second one. Compared with the system, the cost can be reduced. Employees 'intellectual property bureau of the Ministry of Economic Affairs' consumption cooperation Figure 2 is an equivalent circuit diagram of the data signal wiring system of the fourth memory system according to the present invention. In this memory system, compared with the first memory system of FIG. 3, the memory controller 102 The terminal resistor 105 on the side is removed, and as an output circuit of the memory chip 11, an open-drain type output transistor 2 3 3 is used. When the push-pull type output circuit is in operation, the output resistance of the transistor changes. In order to disturb the equivalent characteristic impedance of the serial wiring path for data formed by the signal wiring 1 1 2 and the like, it is easy to cause reflection. In contrast, if an open drain electrode composed of an open drain type output transistor 233 is used The output circuit can increase the output resistance during operation, which is almost constant. During operation, it does not disturb the effective characteristic impedance of the aforementioned serial wiring path for data. For this reason, in this memory system, Only the impedance of the resistor 106 is matched with the terminal on the opposite side of the memory controller 102. As a result, the terminal resistance is one, which can reduce cost and consume less power than the first memory system. -'1!-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 539952 Λ7 B7 V. Description of the invention (2 today (please read the precautions on the back before filling this page) Figure 2 2 is the equivalent circuit diagram of the instruction and address signal wiring of the fourth memory system. In the instruction and address signal wiring system, the memory controller 10 is directed to the instruction and address buffer chip 12. Only Because it is transmitted in one direction, as in the other examples, the termination resistor can be only the termination resistor 106 on the opposite side of the memory controller 102. Figure 2 3 is a data signal wiring system according to the fifth memory system of the present invention Equivalent circuit diagram. In the memory system that is not shown in the same figure, compared with the first memory system, the fourth memory system in FIG. 21 is the opposite, and the terminal resistance 1 06 on the opposite side of the memory controller 102 is Except, the output circuit of the memory controller 102 uses an open-drain output transistor 235 constituting an open-drain type output circuit. Therefore, for the same reason as the fourth memory system of FIG. 21, compared with the first memory system, it is possible to reduce the cost and power consumption. "Memory Controller" Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 24 is a circuit diagram of the memory controller 102 which is most suitable for the first memory system (refer to Figure 3) according to the present invention. The memory controller 1 02 shown in the same figure is built in with the information signal wiring 1 1 2 and the effective characteristic impedance matching resistance 1 05 A is connected to the data signal terminal 240 and the terminal power supply 1 09A inside the memory controller. . By using the memory controller 1 02 shown in the same figure in the first memory system, the memory controller 1 02 side of the motherboard 1 0 1 shown in FIG. 1 is added with a terminal resistor 1 05. No, the cost can be reduced. Figure 2 5 is the most suitable for the second memory system according to the present invention (refer to the paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 V. Description of the invention (2 today (please first Read the precautions on the back and fill out this page) Figure 19) Circuit diagram of the Keeyo controller 10 2. The memory controller shown in the same figure 1 〇 2 has a table 1 switch switch signal terminal 2 4 1 and The second switch switching signal terminal 242 is used to switch on and off the first switch 243 and the second switch 244 provided outside the memory controller 102. The output of these signal terminals 24 1, 242 is through The output circuit 246 outputs the input mode signal 245 of the memory controller 102 to the first switch switching signal terminal 241, and the inversion output circuit 247 reversely outputs the input mode signal 245 of the memory controller to the second switch switching The signal terminal 2 4 2 is output. Here, the input mode signal 245 of the memory controller 1 〇2 is set to the address "Η " when the data is input, and is set to the level" when the data is output. L " again The first switch 243 and the second switch 244 provided outside the memory controller 102 are made of, for example, a MOS transistor, and the gate level " Η " is set to ON, and the gate level "L "It is set to off. By using this memory controller 102 in the second memory system, as described above, it is possible to suppress the power consumption of unnecessary terminal resistors. The terminal resistor 105 is as shown in FIG. 24, It can also be built into the memory controller 1 0 2 0 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy Figure 26 is the memory controller 1 most suitable for the third memory system (refer to Figure 20) according to the present invention. The circuit diagram of 2. The memory controller shown in the same figure. 102 For the memory controller of the first memory system of FIG. 24, the switch 250 that controls the connection to the signal terminal 240 of the built-in terminating resistor 105A is built-in. The switch 250 is turned on and off with the input mode signal 2 4 5 of the memory controller 102. With this, the terminal resistance 105 is only when it becomes necessary (Urrnng), that is, the memory controller 102 Cost paper size applicable during input National Standard (CNS) A4 (210 X 297 mm) 539952 A. V. Description of the invention ((Please read the notes on the back before filling in this page) is valid. Therefore, because the third memory system uses the memory controller 102 shown in Figure 26, the terminal is not needed The power consumption of the resistor is suppressed, which can provide a memory system with low power consumption. There is no need to set a terminal resistor 105 on the motherboard 1 01 on the memory controller 102 side, which can reduce the cost. Figure 27 It is a circuit diagram showing the memory controller 100 which is most suitable for the third memory system (refer to FIG. 20) according to the present invention. The memory controller 102 shown in the same figure is the first one in FIG. 25 2 The inverting output circuit 247 of the memory controller of the memory system and the switch switching signal terminal 242 are removed. Because the memory controller 1 of the third memory system 1 〇 2 uses the structure of FIG. The power consumption of the resistor is suppressed, and a memory system with low power consumption can be provided. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, Figure 28 is the most suitable memory according to the fifth memory system of Figure 23 of the present invention. The circuit diagram of the controller. The memory controller 1 02 shown in the same figure is the memory controller 1 02 of the first memory system in Fig. 24. The output circuit of the memory controller 1 02 adopts an open-drain type output circuit. Transistor 25 1. By adopting this configuration as the memory controller 102 of the fifth memory system of the present invention, the termination resistor 105 on the memory controller side of the motherboard 1 01 is unnecessary, and the cost can be reduced. Of course, as shown in Figure 1, the termination resistor (1 05) can also be set outside the memory controller. "Examples of Other Memory Systems" Figure 29A, B, and C are different from those shown in Figure 4. The cross section of the second memory module of the structure. Figure 29A is a memory module in the form of a bank. This paper is applicable to this paper; the national standard (CNS) A4 specification (210 X 297 mm) _ 3U _ 539952 B7 __ V. Description of the invention (9 Please read the precautions on the back before filling out this page} A cross-sectional view of the data signal wiring. In the module 2 of this notebook, the module data terminal pair 24L and 24R are along One of the long sides of the group substrate 10 is arranged on both sides. Module data wiring 1 5 Connects the module data terminal pair 24R and 24L through the through hole 200. The module data wiring 15 is the same as the first memory module 1 and has a straight wiring path. Module data wiring 15 and memory Between the wafer data terminals Dm of the body wafer 1 1, a small branch that is substantially negligible due to the aforementioned holes (interlayer holes) is formed. This branch can be clearly understood from the foregoing and does not become an undesired signal The reason for the reflection. Figure 29B is a cross-sectional view of the signal wiring in the case of a memory module in the form of a 2 warehouse. Compared to the memory module 2 in Figure 29A, the data wiring 1 to 5 is compared to 1 Connected to the memory data terminal Dm of one memory chip 1 1 provided on one side of the module substrate 10, in the memory module of FIG. 29B, one module data wiring 15 is a straight line The memory data terminals D m and D m are connected to the memory chips 11 and 11 provided on both sides of the module substrate 10. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 29C is a sectional view of the power supply wiring of the memory module 2. Although the module power supply wiring 20 1 is wired to the chip power terminal Dp of the memory chip 11, it is not necessary to be connected by a straight wiring path, and the module power terminals 20 2L and 202R are respectively branched and extended. The module command / position wiring 16 or the module clock wiring 17 may be processed in the same manner as the module power wiring 20 1 or may be processed in the same manner as the module data wiring 15 as shown in FIG. 4. Fig. 30A shows the connector 2 1 0 for the second memory module 2 focusing on the signal wiring. The connector 2 1 0 has one vertical groove, and the connector terminals are listed in this paper. Applicable to China National Standard (CNS) A4 (210 X 297 mm) H " 539952 Λ7 B7 V. Description of the invention (q (please Read the precautions on the back before filling in this page) The front and back directions on the paper are formed on the left and right inner sides of the vertical grooves. The connector terminals 2 1 1 and 2 1 2 are shown in the figure as a representative. Data signal wiring on the motherboard 1 1 2 is connected to the connector terminals 2 1 1 and 2 1 2 and is separated here. Figure 30B shows the connector 2 1 0 for the second memory module 2 focusing on the power wiring. It is used as a power connector The terminals are represented by the connector terminals 2 1 3, 2 1 4 which are respectively connected to the branch wiring 2 1 5 and 2 1 6 which are branched by the power wiring 108, and the power wiring 108 is not electrically separated in the middle. Figure 3 1 is a cross-section of the memory system of the memory module 2 of the signal wiring display device. In the memory system shown in the same figure, if the memory module 2 is installed in the connector 2 1 0, Connector 2 1 0 Separate data signal wiring 1 1 2 Through memory module 2 Module data wiring 1 5 is connected. Figure 3 1 B is a cross-section of the memory system of the power wiring display device memory module 2. In this memory system, the memory module 2 is installed in the connector 2 1 0, the module power terminal of the memory module 2 passes through the connector 2 1 0 of the power connector terminal 2 1 3, 2 1 4 is connected to the power wiring 108 of the motherboard 1 0 1. Also, the aforementioned command and address signal Wiring 1 13 is the same as the power wiring 1 0 8 in FIG. 30B, which can be commanded by the motherboard 1 0 1. The address signal line 1 1 3 is connected to the memory module 2 through the connector 2 1 0. Of course, it can also be connected as shown in the printed 3 1 B by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. According to the second memory module 2, as in the above, the branch that does not cause undesired signal reflection is not made, and the increase of the wiring length can be avoided, and the electrical connection of the data signal wiring on the main board 1 101 can be continued. Body wafer. FIG. 32 is a plan view of a third billion-body module of the present invention. As shown in this paper, the size of the paper applies to the Chinese National Standard (CNS) A4 (210 X 297 public love) 539952
五、發明說明（3 (請先閱讀背面之注意事項再填寫本頁) 於同圖之記憶體模組3中，模組資料端子對24L、24R係在 模組基板1 0之相同面之相同邊相鄰地被配置，該端子對 24L、24R係藉由往復被敷設之模組資料配線1 5而被結合 ，在該模組資料配線1 5之中途，被一直線接續於1個之記 憶體晶片1 1之記憶體資料端子Dm。 圖33A、B係例示以連接器接續第3記憶體模組3之形 態。圖33A係假想在圖32之模組資料端子對24L之位置的 縱剖面，圖33B係假想在圖32之模組資料端子對24R之位 置的縱剖面。於圖33A中，資料信號配線1 12係由主機板 101透過連接器300之資料連接器端子30 1L以及模組資料端 子24L被接續於記憶體模組3之模組資料配線1 5。前述模 組資料配線1 5在模組基板1 0上路徑被折返，如例示於圖 33B般地，到達其之相鄰之模組資料端子24R，由連接器 3 00之資料連接器端子301R導通於主機板1〇1之資料信號配 線1 1 2。關於與主機板1 0 1上之電源配線1 〇8之接續，雖然 並無特別圖不，但是與圖3 1 B同樣地，由主機板1 〇丨之電源 配線1 08透過連接器接續於記憶體模組3之模組電源端子即 可° 經濟部智慧財產局員工消費合作社印製 藉由第3記憶體模組3，與上述同樣地，不製作分支 ，又不招致配線長之增加，可以於資料信號配線接續記憶 體晶片。 《僞記憶體模組》 說明可以置換構成記憶體系統之記憶體模組之一部份 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Λ7 B7 五、發明說明（ 之僞記憶體模組。 圖34係與在圖4說明之第1記憶體模組1 一齊利用， (請先閱讀背面之注意事項再填寫本頁) 可以構成記億體系統之僞記憶體模組1 A之平面圖，圖3 5係 顯示僞記憶體模組之側面圖。被顯示於同圖之僞記憶體模 組1 A對於圖4之記憶體模組1，係具備省略：記憶體晶片 11、指令·位址緩衝器晶片12、PLL晶片13、模組指令· 位址分配配線19、模組時脈分配配線20、終端電阻22、V. Description of the invention (3 (Please read the precautions on the back before filling this page) In the memory module 3 of the same figure, the module data terminal pairs 24L and 24R are the same on the same side of the module substrate 10 The terminal pairs 24L and 24R are connected by a module data wiring 15 that is laid back and forth. In the middle of the module data wiring 15, they are connected to one memory in a straight line. Memory data terminal Dm of chip 11 1. Figs. 33A and B are examples illustrating a form in which a connector is connected to the third memory module 3. Fig. 33A is a longitudinal cross section of the module data terminal pair 24L assumed in Fig. 32, Fig. 33B is a longitudinal cross section of the position of the module data terminal pair 24R in Fig. 32. In Fig. 33A, the data signal wiring 1 12 is the data connector terminal 30 1L of the motherboard 101 through the connector 300 and the module data The terminal 24L is connected to the module data wiring 15 of the memory module 3. The aforementioned module data wiring 15 is turned back on the module substrate 10, as shown in FIG. 33B, and reaches its adjacent one. Module data terminal 24R, data connector terminal 301R by connector 3 00 The data signal wiring 1 12 connected to the main board 110. The connection with the power wiring 1 0 8 on the main board 101 is not specifically illustrated, but it is the same as that shown in FIG. 3 1B. The power wiring 1 08 of the board 1 〇 丨 can be connected to the module power terminal of the memory module 3 through the connector. ° Printed by the third consumer module of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative, the same as the above Ground, without making branches, without incurring an increase in wiring length, you can connect the memory chip to the data signal wiring. "Pseudo-memory module" Explains that it can replace a part of the memory modules constituting the memory system. This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 539952 Λ7 B7 V. Description of the invention (the pseudo memory module. Figure 34 is used together with the first memory module 1 described in Figure 4. (Please read the precautions on the back before filling out this page) A plan view of the pseudo memory module 1 A that can constitute the billion memory system. Figure 3 5 shows the side view of the pseudo memory module. It is shown in the same figure Pseudo-memory module 1 A for Figure 4 The memory module 1 includes omissions: a memory chip 11, a command / address buffer chip 12, a PLL chip 13, a module command / address distribution wiring 19, a module clock distribution wiring 20, and a terminating resistor 22. ,
23之構成。換言之’僞記憶體模組1 A係於模組基板1 0具 備：以24L、25R所代表之模組端子對、模組資料配線15 、模組指令·位置配線16、以及模組時脈配線17。被顯示 於圖34之僞記憶體模組1 A如於圖1以及圖2說明之記憶體 系統中，代替記憶體模組1 ，裝置於連接器104A、104B 而利用，不於信號線1 1 2、1 1 3、1 1 7之路徑製作分支，又 不招致配線長之增加，可以變更記憶體系統之記憶體容纛 〇 雖然沒有圖示出，如於僞記憶體模組1 A上之配線1 5 ' 1 6、1 7設置再現晶片1 1、1 2、1 3之輸入電容之之僞電容 ，可以不弄亂實效之特性阻抗，更抑制波形之錯亂。 經濟部智慧財產局員工消費合作社印製 圖36A、B、C係顯示與第2記憶體模組2 —齊可以 利用之僞記憶體模組2A，圖36A係a-a剖面圖，圖36B係 放大表面圖，圖36C係放大裏面圖。圖36A之僞記憶體模 組2A對於被顯示於圖29A之記憶體模組2，具有沒有搭載 記憶體晶片1 1等之裝置之構成。總之，在記憶體晶片1 1 = 表裏藉由：以24L、25R爲代表之模組端子對、以15爲代 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（3弓 餐ί f請先閱讀背面之注咅？事項再填寫本頁} 表之模組資料配線、模組配線之貫穿孔200而構成。於圖 3 1之記憶體系統中，如代替記憶體模組2使用前述僞記憶 體模組2A，不製作分支，又不招致配線長之增加，可以變 更記憶體系統之記憶體容量。 圖37係顯示與第3記憶體模組3 —齊可以利用之僞記 憶體模組3A。被顯示於同圖之記憶體模組3A對於被顯示 於圖32之記憶體模組3，具有不搭載記憶體晶片11等之裝 置之構成。總之，在模組基板10之表面設置以24L、25R 爲代表之模組端子對、以1 5爲代表之模組資料配線而構成 。如代替第3記憶體模組3而使用僞記憶體模組3A，不製 作分支，又不招致配線長之增加，可以變更記憶體系統之 記憶體容量。 《終端用記憶體模組》 說明搭載被外加於記憶體系統之主機板之終端電阻之 終端用記憶體模組。 經濟部智慧財產局員工消費合作社印製 圖38A、B係顯示於第1記憶體模組1搭載終端電阻 而構成之終端用記憶體模組1 B，圖38A係部份平面圖，圖 3 8 B係側面圖。被顯示於圖3 8 A、B之記憶體模組1 B除掉 圖1之模組端子對24L、24R等之一方之模組端子24R等’ 於被接續於殘餘之模組端子24L等之模組資料配線1 5等接 續終端電阻106A，於此終端電阻106A接續終端電源端子 3 0而構成。如被顯示於圖3 8 B般地’模組基板1 0之裏面側 也同樣地構成。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（3弓 (請先閱讀背面之注意事項再填寫本頁) 圖39係顯示被對應於圖34之僞記憶體模組1 A之終端 用僞記憶體模組1 C。對於圖34之僞記憶體模組’除掉模組 端子對24L、24R等之一方之模組端子24R等，於被接續於 殘餘之模組端子24L等之模組資料配線1 5等接續終端電阻 106A，於此終端電阻106A接續終端電源端子30而構成。 於圖1之記憶體系統中，如代替前述記憶體模組1使 用被顯示於圖38之記憶體模組1 B或被顯示於圖39之記憶 體模組1 C，可以不使用主機板10 1上之終端電阻1 〇6 ’可 以在記憶體模組上終結主機板1 〇 1上之信號配線1 1 2、11 3 、117° 圖4 0 A、B、C係顯示於被顯示在圖2 9 A、B、C之記 憶體模組2搭載終端電阻而成之終端用記憶體模組2B，圖 40A係a-a剖面圖，圖40B係放大表面圖，圖40C係放大裏 面圖。被顯示於圖40A、B、C之記憶體模組2B除掉模組 端子對24L、24R等之一方之模組端子24R等，於被接續於 殘餘之模組端子24L等之模組資料配線1 5等接續終端電阻 106A，於此終端電阻106A接續終端電源端子30而構成。 經濟部智慧財產局員工消費合作社印制衣 於圖3 1 A、B之記憶體系統中，如代替記憶體模組2 使用前述終端用記憶體模組2B，可以不使用主機板101上 之終端電阻1 06，可以在記憶體模組上終端信號配線1 1 2。 關於別的信號配線1 Π、1 1 7也可以採用同樣之構成。 圖4 1係顯示於被顯示於圖32之記憶體模組3搭載終端 電阻而構成之終端用記憶體模組3B。被顯示於圖41之記憶 體模組3B除掉模組端子對24L、24R等之一方之模組端子 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Λ7The composition of 23. In other words, the 'pseudo-memory module 1 A' is on the module substrate 10 and includes: a module terminal pair represented by 24L and 25R, a module data wiring 15, a module command and position wiring 16, and a module clock wiring 17. The dummy memory module 1 A shown in FIG. 34 is used in the memory system described in FIGS. 1 and 2 instead of the memory module 1 and is used by the connectors 104A and 104B instead of the signal line 1 1 The path branch of 2, 1 3, 1 1 7 can be changed without incurring an increase in the wiring length. Although not shown in the figure, as in the pseudo memory module 1 A, The wiring 1 5 ′ 1 6 and 1 7 are set to reproduce the pseudo capacitance of the input capacitance of the chip 1 1, 1 2, 1 3 so as not to disturb the characteristic impedance of the actual effect, and further suppress the waveform disorder. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 36A, B, and C are pseudo-memory modules 2A that can be used together with the second memory module 2. Figure, Figure 36C is an enlarged inner view. The dummy memory module group 2A of FIG. 36A has a configuration in which the memory module 2 shown in FIG. 29A is not equipped with a memory chip 11 or the like. In short, in the memory chip 1 1 = in the table, the module terminal pairs represented by 24L, 25R and 15 are used as the paper size. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable. 539952 A7 B7 V. Description of the invention (3 bow meals f Please read the note on the back? Matters before filling out this page} The module data wiring and module wiring through-hole 200 are formed. The memory system in Figure 31 However, if the aforementioned pseudo memory module 2A is used instead of the memory module 2, the memory capacity of the memory system can be changed without making branches and without increasing the wiring length. Figure 37 shows the third memory module. Group 3 —Pseudo-memory module 3A that can be used together. The memory module 3A shown in the same figure has a structure in which the memory module 3 shown in FIG. 32 is not equipped with a memory chip 11 and the like. In short, the module substrate 10 is provided with a module terminal pair represented by 24L and 25R and a module data wiring represented by 15. For example, a pseudo memory is used instead of the third memory module 3. Module 3A, does not make branches, and does not cause wiring problems Increase, you can change the memory capacity of the memory system. "Terminal Memory Module" Describes a terminal memory module equipped with a terminal resistor that is added to the motherboard of the memory system. Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative 38A and B are printed. The first memory module 1 is equipped with a terminal memory module 1 B equipped with a terminating resistor. FIG. 38A is a partial plan view, and FIG. 3 8 B is a side view. 3 8 Memory modules of A and B 1 B Remove the module terminal 24R, 24R, etc. of one of the module terminal pairs 24L, 24R, etc. of FIG. 1, and connect the module data wiring to the remaining module terminals 24L, etc. The terminal resistor 106A is connected to terminal 15 and so on, and the terminal resistor 106A is connected to the terminal power terminal 30. As shown in FIG. 3B, the inside of the module substrate 10 is also configured in the same way. This paper standard applies China National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 V. Description of the invention (3 bows (please read the precautions on the back before filling this page) Figure 39 shows the pseudo memory corresponding to Figure 34 Pseudo-memory for terminal of body module 1 A Group 1 C. For the pseudo-memory module shown in FIG. 34, remove one of the module terminal pairs 24L, 24R, etc., and the module data wiring 1 connected to the remaining module terminals 24L, etc. The 5th grade is connected to the terminal resistor 106A, and the terminal resistor 106A is connected to the terminal power terminal 30. In the memory system of FIG. 1, if the memory module 1 shown in FIG. 38 is used instead of the aforementioned memory module 1, B Or the memory module 1 C shown in FIG. 39 can be terminated without using the terminating resistor 1 〇6 on the motherboard 101. The signal wiring on the motherboard 1 〇1 can be terminated on the memory module 1 1 2. 11 3, 117 ° Figure 4 0 A, B, and C are shown in Figure 2 9 A, B, and C are shown in Figure 2 9 A, B, and C are equipped with a termination resistor module 2B, Figure 40A series aa sectional view, FIG. 40B is an enlarged surface view, and FIG. 40C is an enlarged inner view. The memory module 2B shown in FIG. 40A, B, and C removes one of the module terminal pairs 24L, 24R, etc., and the module data wiring connected to the remaining module terminals 24L, etc. The terminal resistor 106A is connected to 15 and so on. Here, the terminal resistor 106A is connected to the terminal power terminal 30. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints clothes in the memory system of Figure 3 A and B. If the memory module 2B is used instead of the memory module 2, the terminal on the motherboard 101 can be omitted. The resistor 1 06 can terminate the signal wiring 1 1 2 on the memory module. The other signal wirings 1 Π and 1 1 7 can also have the same structure. Fig. 41 is a memory module for terminal 3B shown in Fig. 32, which is provided with a terminating resistor. The memory module 3B shown in Figure 41 removes the module terminals of one of the module terminal pairs 24L, 24R, etc. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 Λ7
五、發明說明（ (請先閱讀背面之注意事項再填寫本頁) 2 4 R等’於被接續於殘餘之模組端子2 4 L等之模組資料配線 1 5等接續終端電阻1 〇6A ’於此終端電阻1 〇6a接續終端電 源端子30而構成。如代替被顯示於圖32之記憶體模組3而 使用前述終端用記憶體模組3 B，可以使用主機板1 〇 1上之 終端電阻1 〇 6 ’可以在記憶體模組上終結信號配線丨1 2等。 《連接器之其它之形態》 說明構成記憶體系統之連接器之其它之形態。 圖42以及圖43係例示圖7以及圖8之前述連接器1〇4A 、1 04B之別的形態。圖42係以剖面顯示接續於資料信號線 1 1 2之部份，圖43係以剖面顯示接續於電源線丨08之部份。 接續於指令·位址信號線1 1 3、時脈信號線1 1 7之部份例如 如圖4 3般地構成。 總之，圖42、圖43之構成係以上下分開爲2可以裝置 、拆卸地構成圖7、圖8之連接器104A、104B，使記憶體 模組1、1 A、1 B之裝置變容易者。 經濟部智慧財產局員工消費合作社印製 即，將連接器104A 2分爲104Aa與104Ab，在分割片 1 04Aa之底面設置被形成爲凸條之1條的連接器端子部 1 04Ap，在分割片Ab之上面設置被形成爲凹條之1條的 連接器端子部l〇4Ag。同樣地，在分割片l〇4Ba之底面設骥 被形成爲凸條之2條的連接器端子部1〇4Bp 1、104Bp2 ’在 分割片1 04Bb之上面設置被形成爲凹條之2條的連接器端 子部 104Bbl、104Bg2。 於圖42中，在對應前述連接器端子部104AP、104Ag 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） 539952 A7 B7 五、發明說明（3弓 (請先閱讀背面之注意事項再填寫本頁) 之資料信號線1 1 2之部份中，藉由連接器內藏配線丨3 5 a、 135b，資料信號配線1 12可以與連接器端子列130之對應端 子導通。又，於圖43中，在對應前述連接器端子部l〇4Ap 、1 0 4 A g之電源配線1 0 8之部份，藉由連接器內藏配線1 3 7 a 、137b ’電源配線108與連接器端子列130之對應端子導 通。接續於指令·位址信號配線Π 3、時脈信號線1 1 7之連 接器104Aa、104Ab之部份也被設爲與圖43之情形相同。 經濟部智慧財產局員工消費合作社印製 進而，如圖42所示般地，對應連接器1〇4Β之分割片 104Ba之連接器端子列131與132之資料信號線1 12之對應 端子藉由連接器內藏配線133、134被相互導通，實質地與 圖7同樣地構成。又，於圖33中，在對應前述連接器端子 部104Bpl、104Bgl之電源配線108之部份中，藉由連接器 內藏配線1 3 8 a、1 3 8 b，電源配線1 0 8被設爲與連接器端子 列1 3 1之對應端子導通。同樣地，在對應前述連接器端子 部104Bp2、104Bg2之電源配線108之部份，藉由連接器內 藏配線139a、139b，電源配線108被設爲與連接器端子列 1 32之對應端子導通。接續於指令·位址信號配線Π 3、時 脈信號線117之連接器104Ba、104Bb之部份也被設爲與圖 43之情形相同。 於使用圖42以及圖43之連接器之記憶體系統裝置記憶 體模組之作業如下述。例如，在記憶體模組1之左右之模 組端子結合連接器分割片104Aa之連接器端子列130與連接 器分割片104Ba之連接器端子列131。接著’在下一記憶體 模組1之左右之模組端子接合連接器分割片l〇4Ba之連接器 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Λ7 B7 五、發明說明（3今 (請先閱讀背面之注意事項再填寫本頁) 端子列132與連接器分割片104Ba之連接器端子列131。如 此，將必要數目之記憶體模組橫向串列結合後，將被結合 於記憶體模組之連接器分割片104Aa之連接器端子104Ap結 合於對應之連接器分割片104Ab之連接器端子104Ag之同 時，將被結合於記憶體模組之連接器分割片l〇4Ba之連接 器端子1 0 4 B p 1、1 0 4 B p 2結合於對應之連接器分割片1 0 4 B b 之連接器端子104Bgl、104Bg2。藉由此，在記憶體模組之 設置作業所必要之空間成爲只有記憶體系統之上方空間之 故，可以在記憶體系統之周圍設置其它之裝置，在以壁面 包圍之場所設置記憶體系統。 經濟部智慧財產局員工消費合作社印製 圖44係顯示一部份具備連接器之機能之記憶體模組之 例。被顯示於同圖之記憶體模組1 C係在圖4之記憶體模組 附加：具有相當於圖43之連接器端子列1 32之機能之連接 器端子列132E與具有相當於前述連接器端子部104Bp2之機 能之連接器端子部104BpE而構成。連接器端子部132E係被 接續於模組資料配線1 5，連接器端子部1 04BpE係被接續於 模組電源配線、模組指令·位置配線16、以及模組時脈配 線17。對應前述連接器端子部104BpE，連接器104B被配 置於主機板1 〇 1。藉由採用圖44之構成，於記憶體模組設 置作業中，與圖42以及圖43之構成相比，可以降低將記憶 體模組接續於主機板之作業。進而也可以削減記憶體系統 之零件點數，被認爲可以有助於記憶體系統之低成本化。 圖45係以接續於資料信號線1 1 2之部份之剖面顯示可 以適用於記憶體模組1之別的形態之連接器。連接器1 54、 -39^ 本紙張尺度適用中國國家標準（CNS)A4規格（2忉x 297公釐） 539952 Λ7 B7 五、發明說明（3 (請先閱讀背面之注意事項再填寫本頁) 155、156分別具有被形成於向上之凹溝之連接器端子154A 、155A、156A，可以使記憶體模組1站立支持。連接器 157具有被形成於向下之凹溝之連接器端子157A、157B， 被插入站立之一對的記憶體模組1。主機板1 0 1上資料信號 配線112透過連接器內配線154a、154b與連接器端子154A 結合，透過連接器內配線155a、155b與連接器端子155A 結合，透過連接器內配線156a、156b與連接器端子156A 結合，透過連接器內配線157a、157b分別與連接器端子 157A、157B結合。因此，如於連接器154、155、157裝 置記憶體模組1，配線154a、157a、156a分別與資料信號 線112導通，配線154b、157b、156b分別與資料信號線 1 1 2導通。記憶體模組1不具有分支地，可以與資料信號線 112導通。 經濟部智慧財產局員工消費合作社印製 圖46係以接續於資料信號線1 1 2之部份的剖面顯示可 以適用於記憶體模組1之進而別的形態的連接器。連接器 164具有被形成於向上之凹溝之連接器端子164A，連接器 165具有被形成於向上之凹溝之連接器端子165A、165 B， 可以站立支持記憶體模組1。連接器1 66具有被形成於向下 之凹溝之連接器端子166A、166B，被插入站立之一對的 記憶體模組1。主機板1 0 1上之資料信號線1 1 2透過連接器 內配線164a、164b接續於連接器端子164A。連接器端子 165A與165B透過連接器內配線165a、165b相互結合。連 接器端子166A與166B透過連接器內配線166a、166b相互 結合。因此，如於連接器164、165、167裝置記憶體模組 -40 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（3弓 (請先閱讀背面之注意事項再填寫本頁) 1，配線164a、166a、165a分別與資料信號線112導通， 配線164b、166b、165b分別與資料信號線112導通。記憶 體模組1不具有分支地可以與資料信號線1 1 2導通。 圖47係顯示圖46之連接器之電源配線部份之剖面。主 機板1 0 1上之電源配線1 08在中途分支，透過連接器內配線 1 6 4 c、1 6 5 c接續於對應之連接器端子1 6 4 A、1 6 5 A之電源 用端子。 圖48係顯示在圖46以及圖47之連接器搭載記憶體模 組之狀態。如使用此連接器1 64〜1 66，不製作分支，又不 招致配線長之增加，可以在主機板上以小佔有面積形成於 資料信號配線接續記憶體元件之記憶體系統。使用圖45之 連接器1 54〜1 57也相同。又，指令·位址信號配線1 1 3、 時脈信號配線1 1 7之接續也可以使用圖45或圖46之連接器 《記憶體模組之其它之形態》 經濟部智慧財產局員工消費合作社印製 在圖4 9 A之斜視圖、圖4 9 B之側面圖顯示記憶體模組 之進而別的形感。被顯不於问圖之記憶體模組1 C對於則述 記憶體模組1，係以資料端子對24L、24R爲代表之模組端 子對170L、170R對於模組基板10被形成於正交方向之點 爲不同。 圖50係顯示搭載圖49A、B之記憶體模組之記憶體系 統之一例。主機板1 〇 1上之連接器雖爲特別限制，但是係 使用圖46之連接器164、165。也可以使用圖45之連接器 -41 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（q (請先閱讀背面之注意事項再填寫本頁) 154、155、156等。不使用圖46之連接器166、圖45之連 接器1 57等，又，記憶體模組之設置作業所必要之空間成 爲只有記憶體系統之上方之故，可以在記憶體系統之周圍 設置其它之裝置，在以壁面包圍之場所設置記憶體系統。 圖5 1係顯示不使用連接器、記憶體模組而在1個基板 260形成圖1之記憶體系統之例。藉由此，可以使記憶體系 統小型化，資料存取時間也可以縮短。零件數目被削減， 有助於低成本化。進而，如被例示於圖52般地，也可以在 同一基板260上之兩面形成記憶體系統。藉由此，小型化 之同時，也可以擴大記憶體容量。 又，也可以如被例示於圖53般地，將圖52之記憶體系 統261與CPU262 —齊地構裝於基板263，以封裝264密封 全體，構成MCM(多晶片模組）。前述CPU262被接續於記憶 體模組26 1之記憶體控制器1 02，透過此記憶體控制器1 02 存取記憶體晶片1 1。 經濟部智慧財產局員工消費合作社印製 圖54係作爲利用以上說明之記憶體系統之資料處理系 統之一例，以個人電腦裝置爲例而顯示。個人電腦裝置雖 無特別限制，但是具有：比較上動作速度快之處理器總線 BUS1與相對動作速度慢之周邊總線BUS2。資料處理器之 一例之微處理器280、L2快取記憶體28 1、以上說明之記 憶體系統282被結合於處理器總線BUS 1。記憶體系統282 不用說可以適用以上說明之種種形態之記憶體系統，但是 在圖54中，以具備記憶體控制器102與記憶體模組1之構 成爲代表圖示之。微處理器280內藏CPU、L1快取記憶體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） " " " "~ 539952 A7 B7 五、發明說明（, (請先閱讀背面之注意事項再填寫本頁) 等，將記憶體模組1內藏之記憶體晶片當成主記憶體存取 。處理器總線BUS1與周邊總線BUS2之介面控制係由橋接 電路 284 進行。IDE(Integrated Device Electronics :整合裝 置電子學）控制器287、圖形控制器2 8 5、以及其它介面控 制器2 8 8被接續於周邊總線BUS2。硬碟裝置等之補助記憶 裝置290被接續於IDE控制器287，進行磁碟存取控制。訊 框緩衝記憶體286以及顯示器291被接續於圖形控制器285 ，進行掃描控制或顯示控制。鍵盤、指向裝置等、其它之 周邊電路292被接續於其它介面控制器288。 於個人電腦系統如採用記憶體系統2 82，即使提升記 憶體系統之頻率，信號波形不會變亂，又，等待時間也可 以抑制，高速資料傳送成爲可能之故，有助於電腦系統之 資料處理速度之提升。 以上雖然依據實施形態具體說明由本發明者完成之發 明，但是本發明並不限定於此，在不脫離其之要旨之範圍 內，不用說可以有種種之變更可能。 經濟部智慧財產局員工消費合作社印製 例如，記憶體晶片不限定於同步DRAM，也可以爲其 它之記憶形式之記憶體。又，記憶體模組也可以利用以上 說明之連接器以外之構成的連接器以實現記憶體系統。 本發明之記憶體模組利用於個人電腦、工作站或伺服 器之需要大容量之電腦系統特別有效。 【發明之效果】 如簡單說明由本申請案所揭示之發明中代表性者所獲 -43 - 本紙張尺度適用中國國家標準（CNS)A4規格（2]0 X 297公釐） 539952 A7 B7 五、發明說明（ 得之效果，則如下述。 (請先閱讀背面之注意事項再填寫本頁) 即，可以提供：抑制由於信號反射之信號波形之錯亂 ，可以提升信號傳送之信賴性之同時’增加記憶體動作之 安定性，又，可以抑制存取時間之增加。 如使本發明之記憶體模組適用於電腦系統，即使提升 記憶體系統之頻率，信號波形不會錯亂’又，也可以抑制 等待時間（latency )，可以進行尚速資料傳送之故’能夠 提升藉由電腦系統之資料處理速度。 圖面之簡單說明 圖1係顯示本發明之記憶體系統之一例之正面圖。 圖2係圖1之記憶體系統之平面圖。 圖3係圖2之記憶體系統之槪略等效電路圖。 圖4係被適用於圖1之記憶體系統之第1記憶體模組 之平面圖。 圖5係圖4之記憶體模組之側面圖。 圖6係顯示圖4之記憶體模組之記憶體晶片之佈線之 例之說明圖。 經濟部智慧財產局員工消費合作社印製 圖7係可以適用於圖1之記憶體模組之連接器之資料 配線部份之槪略縱剖面圖。 圖8係可以適用於圖4之記憶體模組之連接器之電源配 線部份之槪略縱剖面圖。 圖9係在可以適用於圖4之記憶體模組之連接器裝置記 憶體模組之際之斜視圖。 -44 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 Α7 Β7 五、發明說明（3 圖1 0係在可以適用於圖4之記憶體模組之連接器裝置 記憶體模組之狀態之剖面圖。 (請先閱讀背面之注意事項再填寫本頁) 圖1 1係具有SSTL界面之比較例之記憶體系統之斜視 圖。 圖1 2係圖1 1之比較例之記憶體系統之等效電路圖。 圖1 3係將串列接續記憶體晶片之記憶體模組串列接續 之比較例之記憶體系統之斜視圖。 圖1 4係圖1 3之比較例之記憶體系統之等效電路圖。 圖1 5係圖1 1之形式之記憶體系統之SSTL之模擬電路 圖。 圖1 6 A、1 6 B係顯示圖1 5之模擬電路之寫入時與讀取 時之SSTL信號波形模擬結果之說明圖。 圖1 7係關於在圖2說明之記憶體系統之資料信號之模 擬電路圖。 圖18A、18B係顯示圖17之模擬電路之寫入動作與讀 取動作之模擬結果之說明圖。 圖1 9係依據本發明之第2記憶體系統之資料信號配線 系統之等效電路圖。 經濟部智慧財產局員工消費合作社印製 圖20係依據本發明之第3記憶體系統之資料信號配線 系統之等效電路圖。 圖2 1係依據本發明之第4記憶體系統之資料信號配線 系統之等效電路圖。 0 2 2係弟4記憶體系統之指令·位址fg號配線系統之 等效電路圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) Γ7^ ----- 539952 Λ7 ----B7 五、發明說明（4弓 圖23係依據本發明之第5記憶體系統之資料信號配線 系統之等效電路圖。 (請先閱讀背面之注意事項再填寫本頁) 圖24係最適於依據本發明之第χ記憶體系統之記憶體 控制器之電路圖。 圖25係最適於依據本發明之第2記憶體系統之記憶體 控制器之電路圖。 圖26係最適於依據本發明之第3記憶體系統之記憶體 控制器之電路圖。 圖27係最適於依據本發明之第3記憶體系統之記憶體 控制器之進而別的電路圖。 圖28係最適於依據本發明之第5記憶體系統之記憶體 控制器之電路圖。 圖29A、29B、29C係關於本發明之第2記憶體模組之 剖面圖。 圖30A、30B係可以適用於第2記憶體模組之連接器 之說明圖。 圖3 1 A、3 1 B係裝置第2記憶體模組之記憶體系統之 剖面圖。 經濟部智慧財產局員工消費合作社印製 圖32係本發明之第3記憶體模組之平面圖。 圖33A、33B係例示以連接器接續第3記憶體模組之 形態之剖面圖。 圖34係與第1記憶體模組一齊可以利用之僞記憶體模 組之平面圖。 圖35係圖34之僞記憶體模組之側面圖。 -40 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（41 圖36A、36B、36C係與第2記憶體模組一齊可以利用 之僞記憶體模組之說明圖。 (請先閱讀背面之注意事項再填寫本頁) 圖37係與第3記憶體模組一齊可以利用之僞記憶體模 組之平面圖。 圖38A、38B係於第1記憶體模組搭載終端電阻而形 成之終端用記憶體模組之說明圖。 圖39係被對應於圖34之僞記憶體模組之終端用僞記憶 體模組之說明圖。 圖40A、40B、40C係在圖29A所示之記憶體模組搭載 終端電阻而形成之終端用記憶體模組之說明圖。 圖4 1係在圖32所示之記憶體模組搭載終端電阻而形成 之終端用記憶體模組之說明圖。 圖42係著眼於資料信號配線而顯示關於圖7以及圖8 之連接器之別的形態之剖面圖。 圖43係著眼於電源配線部份而顯示關於圖7以及圖8 之連接器之別的形態之剖面圖。 圖44係例示一部份具備連接器之機能之記憶體模組之 剖面圖。 經濟部智慧財產局員工消費合作社印製 圖45係著眼於資料信號線部份而顯示可以適用於記億 體模組之別的形態之連接器之剖面圖。 圖46係著眼於資料信號線部份而顯示可以適用於記憶 體模組之進而別的形態之連接器之剖面圖。 圖47係著眼於圖46之連接器之電源配線部份之剖面圖 -4/ _ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 539952 A7 B7 五、發明說明（叫 圖48係顯示於圖46以及圖47之連接器搭載記憶體模 組之狀態之剖面圖。 圖49A、49B係顯示具備向下之模組端子對之記憶體 模組之進而別的形態之斜視圖。 圖5 0係顯示搭載圖4 9之記憶體模組之記憶體系統之一 例之剖面圖。 圖5 1係顯示不使用連接器、記憶體模組在1個之基板 形成圖1之記憶體系統之例之正面圖。 圖52係顯示在同一基板上之兩面形成記憶體系統之例 之正面圖。 圖53係顯示搭載記憶體系統與CPU，多晶片模組化之 例之平面圖。 圖54係使用記憶體系統之個人電腦裝置之方塊圖。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 主要元件對照表 1 A，1B，1C，1D,1E，1F 記 憶 體 模 組 2A，2B 記 憶 體 模 組 3A，3B 記 憶 體 模 組 10 模 組 基 板 11 記 憶 體 晶 片 12 指 令 位 址 緩 衝 器 曰 日日斤 13 PLL 晶 片 15 模 組 資 料 配 線 16 模 組 指 令 • 位 址 配 線 本紙張尺度適用中國國家(CNS)A4規格（210x 297公釐） 「此_ 539952 A7 _B7 五、發明說明（46) 17 模組時脈配線 19 模組指令·位址分配配線 20 模組時脈分配配線 22 、 23 終端電阻 -------------— (請先閱讀背面之注意事項再填寫本頁) 線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention ((Please read the precautions on the back before filling out this page) 2 4 R, etc. are connected to the remaining module terminals 2 4 L, etc. Module data wiring 1 5, etc. Connection terminal resistance 1 〇6A 'Herein, the terminating resistor 1 〇6a is connected to the terminal power terminal 30. If the terminal memory module 3 B is used instead of the memory module 3 shown in FIG. 32, the terminal board 10 may be used. Terminating resistor 1 〇6 'can terminate signal wiring on the memory module 丨 1 2 etc. "Other forms of connectors" Describes other forms of connectors constituting the memory system. Fig. 42 and Fig. 43 are exemplified diagrams 7 and the other forms of the aforementioned connectors 104A and 104B in Fig. 8. Fig. 42 shows a part connected to the data signal line 1 1 2 in a cross section, and Fig. 43 shows a part connected to the power line 8 in a cross section. The part connected to the command and address signal line 1 1 3 and the clock signal line 1 1 7 is structured as shown in Figure 43. In short, the structure of Figure 42 and Figure 43 can be divided into 2 above and below. Device, detachably constitute the connectors 104A and 104B of Figs. 7 and 8 to make the memory Modules 1, 1 A, and 1 B become easier. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, that is, the connector 104A 2 is divided into 104Aa and 104Ab, and the bottom surface of the split piece 104Aa is formed as a convex One connector terminal section 104Ap of one strip is provided on the divided piece Ab with a connector terminal portion 104A formed as one of the recessed strips. Similarly, a quilt is provided on the bottom face of the divided piece 104B. The two connector terminal portions 104Bp 1, 104Bp2 formed as two convex stripe are provided on the divided piece 104Bb with the connector terminal portions 104Bbl, 104Bg2 formed as two concave stripe. As shown in FIG. 42, Corresponds to the aforementioned connector terminal sections 104AP, 104Ag This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 public) 539952 A7 B7 V. Description of the invention (3 bows (please read the precautions on the back before filling this page) In the part of the data signal line 1 1 2, the data signal wiring 1 12 can be connected to the corresponding terminal of the connector terminal row 130 through the built-in wiring of the connector 3 5 a, 135 b. Also, in FIG. 43 , In the corresponding terminal portion of the connector 104Ap, 104A The part of the source wiring 108 is connected to the corresponding terminal of the connector wiring 130 by the built-in wiring 1 3 7 a and 137 b ′. It is connected to the command and address signal wiring Π 3 and clock The parts of the connectors 104Aa and 104Ab of the signal line 1 1 7 are also set to be the same as those shown in Fig. 43. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and as shown in Fig. 42, corresponding to the connector 1〇 Corresponding terminals of the data signal lines 112 of the connector terminal rows 131 and 132 of the 4B split piece 104Ba are electrically connected to each other by the built-in wiring 133 and 134 in the connector, and the configuration is substantially the same as that of FIG. 7. In FIG. 33, among the power supply wiring 108 corresponding to the connector terminal portions 104Bpl and 104Bgl, the power supply wiring 1 0 8 is provided by the built-in wiring 1 3 8 a and 1 3 8 b in the connector. It is connected to the corresponding terminal of the connector terminal row 1 31. Similarly, in the part of the power supply wiring 108 corresponding to the aforementioned connector terminal portions 104Bp2 and 104Bg2, the power supply wiring 108 is connected to the corresponding terminal of the connector terminal row 132 by the built-in wiring 139a and 139b of the connector. The parts of the connectors 104Ba and 104Bb connected to the command / address signal wiring Π 3 and the clock signal line 117 are also set to the same as those in FIG. 43. The operation of the memory module of the memory system device using the connector of Fig. 42 and Fig. 43 is as follows. For example, the module terminals on the left and right sides of the memory module 1 are combined with the connector terminal row 130 of the connector divided piece 104Aa and the connector terminal row 131 of the connector divided piece 104Ba. Then, 'the module terminal joint connector splitter of the next memory module 1 and the connector of the 104Ba connector. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 Λ7 B7 V. Description of the invention (3 today (please read the precautions on the back before filling this page) The terminal row 132 and the connector terminal row 131 of the connector split 104Ba. In this way, after combining the necessary number of memory modules in series, At the same time, the connector terminals 104Ap of the connector split piece 104Aa that is combined with the memory module are combined with the connector terminals 104Ag of the corresponding connector split piece 104Ab, and the connector split piece that is combined with the memory module l 〇4Ba connector terminals 1 0 4 B p 1, 1 0 4 B p 2 are combined with the connector terminals 104Bgl and 104Bg2 of the corresponding connector segment 1 0 4 B b. Therefore, in the memory module, The space necessary for the installation operation is only the space above the memory system. Other devices can be installed around the memory system and the memory system can be installed in a place surrounded by walls. Staff of the Intellectual Property Bureau, Ministry of Economic Affairs Figure 44 printed by the consumer cooperative shows an example of a part of a memory module with a connector function. The memory module 1 shown in the same figure is C. The memory module shown in Figure 4 is added: The connector terminal row 132E of FIG. 43 functions as a connector terminal row 132E and a connector terminal section 104BpE having a function equivalent to the aforementioned connector terminal section 104Bp2. The connector terminal section 132E is connected to the module data Wiring 15 and connector terminal 1 04BpE are connected to the module power wiring, module command and position wiring 16, and module clock wiring 17. Corresponding to the aforementioned connector terminal 104BpE, the connector 104B is arranged on the host Board 1 〇1. By adopting the configuration of FIG. 44, compared with the configuration of FIG. 42 and FIG. 43, the operation of connecting the memory module to the motherboard can be reduced in the memory module setting operation. It is thought that reducing the number of parts of the memory system can help reduce the cost of the memory system. Figure 45 shows the cross section of the part connected to the data signal line 1 1 2 and can be applied to the memory module 1 Difference Connectors in the form of connectors. Connectors 1, 54 and -39 ^ This paper size applies to China National Standard (CNS) A4 (2 忉 x 297 mm) 539952 Λ7 B7 V. Description of the invention (3 (Please read the precautions on the back first) (Fill in this page again.) 155 and 156 have connector terminals 154A, 155A, and 156A formed in the upward grooves, respectively, so that the memory module 1 can be stood and supported. The connector 157 has the grooves formed in the downward grooves. The connector terminals 157A and 157B are inserted into the standing memory module 1. The data signal wiring 112 on the motherboard 1 1 is connected to the connector terminal 154A through the internal wiring 154a, 154b, and is connected to the connector terminal 155A through the internal wiring 155a, 155b, and is connected to the connection through the internal wiring 156a, 156b. The connector terminals 156A are connected, and are connected to the connector terminals 157A and 157B through the wiring 157a and 157b in the connector, respectively. Therefore, as for the memory module 1 of the connectors 154, 155, and 157, the wirings 154a, 157a, and 156a are connected to the data signal line 112, respectively, and the wirings 154b, 157b, and 156b are connected to the data signal line 1 12 respectively. The memory module 1 has no branch ground and can be connected to the data signal line 112. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 46 is a cross-section of the part connected to the data signal line 1 12 to show the connector that can be applied to the memory module 1 and other forms. The connector 164 has the connector terminals 164A formed in the upward grooves, and the connector 165 has the connector terminals 165A and 165 B formed in the upward grooves, and can support the memory module 1 while standing. The connector 1 66 has connector terminals 166A and 166B formed in a downward groove, and is inserted into a pair of standing memory modules 1. The data signal lines 1 1 2 on the motherboard 1 0 1 are connected to the connector terminals 164A through the internal wiring 164a and 164b of the connector. The connector terminals 165A and 165B are connected to each other through the internal wiring 165a and 165b. The connector terminals 166A and 166B are connected to each other through the internal wiring 166a and 166b. Therefore, if the connector 164, 165, 167 device memory module -40-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 V. Description of the invention (3 bows (please Read the precautions on the back before filling this page) 1. Wirings 164a, 166a, and 165a are connected to data signal line 112, and wirings 164b, 166b, and 165b are connected to data signal line 112. Memory module 1 does not have a branch ground. It can be connected to the data signal line 1 1 2. Figure 47 shows the cross section of the power supply wiring part of the connector of Figure 46. The power supply wiring 1 08 on the motherboard 1 0 1 is branched in the middle, and the wiring through the connector 1 6 4 c, 1 6 5 c are connected to the corresponding power supply terminals 1 6 4 A and 16 5 A. Figure 48 shows the state of the memory module on the connector shown in Figure 46 and Figure 47. If used, This connector 1 64 to 1 66 does not make branches and does not cause an increase in wiring length, and can be formed on the motherboard with a small footprint on the data signal wiring connection memory element memory system. Use the connector of Figure 45 1 54 to 1 57 are the same. Also, the command · Address signal wiring 1 1 3, clock signal wiring 1 1 7 connection can also use the connector of Figure 45 or Figure 46 "Other Forms of Memory Module" Printed on Figure 4 9 A is a perspective view and Figure 4 9 B is a side view showing the memory module and other shapes. The memory module 1 C is not shown in the figure. The module terminal pairs 170L and 170R represented by the data terminal pair 24L and 24R are different from each other in that the module substrate 10 is formed in an orthogonal direction. Fig. 50 shows a memory equipped with the memory module of Figs. 49A and B. An example of a system. Although the connectors on motherboard 1 〇1 are particularly limited, they use the connectors 164 and 165 of Figure 46. You can also use the connectors of Figure 45 -41-This paper standard applies to the Chinese National Standard (CNS ) A4 specification (210 X 297 mm) 539952 A7 B7 V. Description of the invention (q (please read the precautions on the back before filling this page) 154, 155, 156, etc. Do not use the connector 166, Figure 45 of Figure 46 Connector 1 57, etc., and the space necessary for the installation of the memory module Since it is only above the memory system, other devices can be installed around the memory system, and the memory system can be installed in a place surrounded by a wall. Figure 5 1 shows the use of connectors and memory modules without One substrate 260 forms an example of the memory system shown in FIG. 1. With this, the memory system can be miniaturized and the data access time can be shortened. The number of parts is reduced, which contributes to cost reduction. Furthermore, as illustrated in FIG. 52, a memory system may be formed on both sides of the same substrate 260. As a result, the memory capacity can be increased while miniaturizing. Also, as illustrated in FIG. 53, the memory system 261 and CPU 262 of FIG. 52 may be mounted on the substrate 263 together, and the entire package may be sealed with a package 264 to form an MCM (multi-chip module). The aforementioned CPU262 is connected to the memory controller 102 of the memory module 261, and accesses the memory chip 11 through the memory controller 102. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 54 shows an example of a data processing system using the memory system described above, using a personal computer device as an example. Although the personal computer device is not particularly limited, it has a processor bus BUS1 which has a relatively fast operating speed and a peripheral bus BUS2 which has a relatively slow operating speed. An example of a data processor is a microprocessor 280, an L2 cache memory 28 1. The memory system 282 described above is integrated into the processor bus BUS1. It is needless to say that the memory system 282 can be applied to various types of memory systems described above, but in FIG. 54, a configuration including the memory controller 102 and the memory module 1 is shown as a representative diagram. The microprocessor 280 has a built-in CPU and L1 cache memory. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) " " " " ~ 539952 A7 B7 V. Description of the invention (, (Please read the precautions on the back before filling this page), etc., and access the memory chip in memory module 1 as the main memory. The interface between the processor bus BUS1 and the peripheral bus BUS2 is controlled by the bridge circuit 284 Yes. IDE (Integrated Device Electronics) controller 287, graphics controller 2 8 5 and other interface controllers 2 8 8 are connected to the peripheral bus BUS 2. Auxiliary memory devices 290 such as hard disk devices are connected. The IDE controller 287 performs disk access control. The frame buffer memory 286 and the display 291 are connected to the graphics controller 285 for scanning control or display control. The keyboard, pointing device, and other peripheral circuits 292 are connected. In other interface controllers 288. In the personal computer system, if the memory system 2 82 is used, even if the frequency of the memory system is increased, the signal waveform will not become chaotic, and when waiting It can also be suppressed that the high-speed data transmission becomes possible, which helps to improve the data processing speed of the computer system. Although the invention completed by the present inventors has been specifically described above according to the embodiment, the present invention is not limited to this, without departing from It is needless to say that various changes are possible within the scope of the gist. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, the memory chip is not limited to synchronous DRAM, and it can also be other types of memory. The memory module can also use a connector other than the connector described above to implement a memory system. The memory module of the present invention is particularly effective when used in a personal computer, a workstation, or a computer system requiring a large capacity. [Effects of the invention] As a brief description, obtained by the representative of the invention disclosed in this application -43-This paper size is applicable to China National Standard (CNS) A4 specifications (2) 0 X 297 mm) 539952 A7 B7 V. Description of the invention (The effect obtained is as follows. (Please read the precautions on the back before filling in this page) Provide: Suppression of signal waveform chaos due to signal reflection can improve the reliability of signal transmission while increasing the stability of memory operation, and can suppress the increase of access time. If the memory module of the present invention is applied In the computer system, even if the frequency of the memory system is increased, the signal waveform will not be disordered, and the latency can be suppressed, so that the data can be transmitted at high speed. It can improve the data processing speed by the computer system. Brief Description of the Drawings Fig. 1 is a front view showing an example of a memory system of the present invention. FIG. 2 is a plan view of the memory system of FIG. 1. FIG. FIG. 3 is a schematic equivalent circuit diagram of the memory system of FIG. 2. FIG. 4 is a plan view of a first memory module applied to the memory system of FIG. 1. FIG. FIG. 5 is a side view of the memory module of FIG. 4. FIG. 6 is an explanatory diagram showing an example of wiring of a memory chip of the memory module of FIG. 4. FIG. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 7 is a schematic longitudinal sectional view of the wiring part of the memory module connector applicable to Figure 1. FIG. 8 is a schematic longitudinal sectional view of a power supply wiring portion of a connector of the memory module applicable to FIG. 4. Fig. 9 is a perspective view of a memory module of a connector device applicable to the memory module of Fig. 4; -44-This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 539952 Α7 Β7 V. Description of the invention (3 Fig. 10 0 is a connector device that can be applied to the memory module of Fig. 4 A cross-sectional view of the state of the memory module. (Please read the precautions on the back before filling this page.) Figure 1 1 is a perspective view of a memory system with a comparative example with an SSTL interface. Figure 1 2 is a comparison of Figure 1 1 The equivalent circuit diagram of the memory system of the example. Figure 13 is a perspective view of a memory system of a comparative example in which a memory module serially connected to a memory chip is serially connected. Figure 14 is a comparative example of FIG. 13 The equivalent circuit diagram of the memory system is shown in Fig. 15. Fig. 15 is an analog circuit diagram of the SSTL of the memory system in the form of Fig. 11. Fig. 16 A and 16 B show the writing and reading of the analog circuit of Fig. 15 An explanatory diagram of the simulation result of the SSTL signal waveform at the time of taking. Fig. 17 is an analog circuit diagram of the data signal of the memory system described in Fig. 2. Figs. 18A and 18B show the writing operation and reading of the analog circuit of Fig. 17 An illustration of the simulation results of the action. Equivalent circuit diagram of the data signal wiring system of the second memory system. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, Figure 20 is an equivalent circuit diagram of the data signal wiring system of the third memory system according to the present invention. Figure 2 1 is the equivalent circuit diagram of the data signal wiring system of the fourth memory system according to the present invention. 0 2 2 is the equivalent circuit diagram of the instruction · address fg number wiring system of the 4th memory system. This paper standard is applicable to China Standard (CNS) A4 specification (210 X 297 public love) Γ7 ^ ----- 539952 Λ7 ---- B7 V. Description of the invention (4 bow Figure 23 is the data signal wiring of the fifth memory system according to the present invention Equivalent circuit diagram of the system. (Please read the precautions on the back before filling out this page.) Figure 24 is a circuit diagram of the memory controller most suitable for the xth memory system according to the present invention. Figure 25 is the most suitable circuit for the memory controller according to the present invention. Circuit diagram of the memory controller of the second memory system. Figure 26 is a circuit diagram of the memory controller most suitable for the third memory system according to the present invention. Figure 27 is a circuit diagram of the third memory most suitable for the present invention. The circuit diagram of the memory controller of the system. Fig. 28 is a circuit diagram of the memory controller most suitable for the fifth memory system according to the present invention. Figs. 29A, 29B, and 29C are the second memory model of the present invention. Sectional view of the group. Figures 30A and 30B are explanatory diagrams of a connector that can be applied to the second memory module. Figure 3 A, 3 1 B is a sectional view of the memory system of the second memory module of the device. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs, Figure 32 is a plan view of the third memory module of the present invention. 33A and 33B are cross-sectional views illustrating a form in which a third memory module is connected by a connector. Fig. 34 is a plan view of a pseudo memory module set which can be used together with the first memory module. FIG. 35 is a side view of the pseudo memory module of FIG. 34. -40-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 539952 A7 B7 V. Description of the invention (41 Fig. 36A, 36B, 36C is a fake that can be used together with the second memory module Memory module description. (Please read the precautions on the back before filling out this page.) Figure 37 is a plan view of a pseudo memory module that can be used together with the third memory module. Figures 38A and 38B are on the first 1 An explanatory diagram of a terminal memory module formed by a memory module equipped with a terminal resistor. Fig. 39 is an explanatory diagram of a terminal pseudo memory module corresponding to the pseudo memory module of Fig. 34. Fig. 40A, 40B and 40C are explanatory diagrams of a terminal memory module formed by mounting a terminal resistor in the memory module shown in FIG. 29A. FIG. 4 1 is formed by mounting a terminal resistor in the memory module shown in FIG. 32 An explanatory diagram of a memory module for a terminal. Fig. 42 is a cross-sectional view showing another form of the connector of Figs. 7 and 8 focusing on data signal wiring. Fig. 43 is a view showing a diagram focusing on power wiring. Section 7 and Figure 8 Fig. 44 is a cross-sectional view illustrating a part of a memory module having a connector function. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 45 is based on the data signal line and it can be used to record billions. A cross-sectional view of a connector of another form of the body module. Fig. 46 is a cross-sectional view of a connector that is applicable to a memory module and other forms by focusing on the data signal line. Fig. 47 is a view of The cross section of the power wiring part of the connector in Figure 46-4 / _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 539952 A7 B7 V. Description of the invention (called Figure 48 is shown in Figure 48) Fig. 46 and Fig. 47 are sectional views of a state in which a memory module is mounted on a connector. Figs. 49A and 49B are perspective views showing another form of the memory module having a downward module terminal pair. Fig. 5 0 Is a cross-sectional view showing an example of a memory system equipped with the memory module of Fig. 49. Fig. 5 is a diagram showing an example of the memory system of Fig. 1 formed on one substrate without using a connector and the memory module. Front view. Figure 52 shows Front view of an example where a memory system is formed on both sides of the same substrate. Fig. 53 is a plan view showing an example of a multi-chip module equipped with a memory system and a CPU. Fig. 54 is a block diagram of a personal computer device using the memory system. (Please read the precautions on the back before filling out this page) The main components printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1A, 1B, 1C, 1D, 1E, 1F Memory Module 2A, 2B Memory Module Group 3A, 3B Memory module 10 Module substrate 11 Memory chip 12 Command address buffer 13 PLL chip 15 Module data wiring 16 Module instruction • Address wiring This paper is applicable to China (CNS) ) A4 specification (210x 297 mm) "This _ 539952 A7 _B7 V. Description of the invention (46) 17 Module clock wiring 19 Module command and address assignment wiring 20 Module clock distribution wiring 22, 23 Termination resistor- ------------— (Please read the notes on the back before filling this page) This cooperative printed paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)