483159 五 A7 B7 發明說明（ί) (一）發明領域： 本發明係有關一種堆疊閘式快閃記憶體的製造方法，尤 指一種可提供窄間距隔離(narrow-pitch isolation)及高電容輕 合比例(capacitive coupling ratio)的堆疊閘式快閃記憶體製造 方法。 、 ㈡習用技術的說明： 快閃記憶體(flash memory)具有電性編程(electrical program)及電性抹除(electricalerasure)兩種操作。一般而言， 快閃記憶體是由記憶胞陣列(memory cell array)與週邊電路兩 大部分所組成，其中作為資料儲存的快閃記憶胞陣列是由許 多記憶胞排列整齊於陣列交錯的字元線(wor(j Une)與位元線 (bit line)中所構成。而週邊電路則是提供快閃記憶體操作時所 需的電源供應電路’及資料輸入、輸出相關電路。依據閘極 電極形狀分類，快閃記憶胞可區分為兩大類，一為堆疊閘式 (stack-gate)快閃記憶胞，另一為分離閘式(split_gate)快閃記憶 胞。 習知高密度堆疊閘式快閃記憶體的技術，如1997 IEDM 中K· Shimizu等人於論文 “A Novel High Density 5F2NAND STI Cell Technology Suitable for 256Mbit and 1Gbit Flash Memories”所述，可為一典型的代表。請參閱圖一a，提供 一半導體基板1，並於該半導體基板1形成淺渠溝隔離2，接著 形成一隧道氧化層3，再沈積一第一導電層4。如圖一B，再 沈積一第二導電層5。接著沈積一氮化矽層6，利用微影蝕刻 本紙張尺度適用中國國家標準（CNS)A4規格（21Q X 297公爱―483159 Five A7 B7 Description of Invention (ί) (I) Field of the Invention: The present invention relates to a method for manufacturing a stacked gate flash memory, especially a method capable of providing narrow-pitch isolation and high capacitance Capacitive coupling ratio manufacturing method of stacked gate flash memory. Explanation of conventional technology: Flash memory has two operations: electrical program and electrical erasure. Generally speaking, flash memory is composed of two parts: memory cell array and peripheral circuits. Among them, the flash memory array as data storage is composed of many memory cells arranged neatly in the array. Line (wor (j Une) and bit line). And the peripheral circuit is to provide the power supply circuit and data input and output related circuits required for flash memory operation. According to the gate electrode Shape classification, flash memory cells can be divided into two categories, one is a stack-gate flash memory cell, and the other is a split-gate flash memory cell. Flash memory technology, as described by K. Shimizu et al. In the paper "A Novel High Density 5F2NAND STI Cell Technology Suitable for 256Mbit and 1Gbit Flash Memories" in 1997 IEDM, can be a typical representative. Please refer to Figure 1a, A semiconductor substrate 1 is provided, and a shallow trench isolation 2 is formed on the semiconductor substrate 1. Then, a tunnel oxide layer 3 is formed, and a first conductive layer 4 is deposited. As shown in FIG. 1B, a second conductive layer is deposited. Layer 5. Next, a silicon nitride layer 6 is deposited and etched using lithography. The paper size is in accordance with China National Standard (CNS) A4 (21Q X 297).
請 先 閱 讀 背 面-之 注 意-事 項 S· f裝 本 . 頁 I 訂 # 五、發明說明（V) 圖案化氮化石夕層6後，再利用一次微影蝕刻技術以生成間隙壁 61 ’接著以IU匕石夕層6為遮罩(Mask)進行第三次钱刻，其中氮 化矽層6於第三次蝕刻時並不會被侵蝕，故第一導電層4及第 二導電層5被钱刻成如圖一c所示。接著如圖一d與圖一E，除 去氮化矽層6，再沈積一層氮化氧化層7(n〇)作為第一導電層 4和第二導電層5所組成之浮置閘(floating gate)與再沈積的第 二導電層8之間的介電層，最後圖案化完成堆疊閘（圖中未 示）。 ，很明顯地，使用習用技術製造堆疊閘式快閃記憶體，必 須制三次侧’因而增加製糊複雜度，使可靠度不佳而 降低良率’增加製造成本，影響其競爭力。而且制技術使 用的遮罩的魏’會使得絕緣間距無法再驗，以在積體電 路製程進入次微米或深次微米的技術時，將會嚴重影響其競 爭力。再者，習用技術無法更提高電容輕合比例(cap=ive C_mg加_增加_記麵的，在碰電路製程進 =次微米或深次微米的技術時，無法更提升_記憶體的電 :=質無法提升’—競爭優勢，落 經濟部智慧財產局員工消費合作社印製 (三）發明之簡要說明： 本發目的為提供—種堆疊閘式快閃記憶體的製造 增加而ΓίΓί影糊次數，降低製程的複雜度，使可靠度 本發明之再-目的為提供—種堆疊開式快閃記憶體的製 297公釐） A7 --~^_— 五、發明說明（g ) k方法，以達成更佳的窄間距隔離(narr〇w_pitch is〇iati〇n)的效 果。 止本發明之再一目的為提供一種堆疊閘式快閃記憶體的製 k方法，以製造出咼電容耗合比例(capacitive c〇Upli呢加⑹ 的快閃記憶體。 本發明為達上述目的，故提出一種堆疊閘式快閃記憶體 的製造方法，其較佳實施步驟係為：於一半導體基板上形成 淺渠溝隔離(STI)，再依序沈積一隧道氧化層、一第一導電層 及一第一介電層；圖案化該第一介電層，而停止於該第一導 電層上；再沈積一第二導電層，接著使用非等向性蝕刻該第 及第一導電層，以形成一浮置閘(floating gate)，以達成窄 間距隔離(narrow-pitch isolation)的效果，其中餘留之該第二導 電層在該第一介電層旁形成較小的間隙壁(spacer)，可提高電 容耦合比例(capacitive coupling ratio)，且為浮置閘的一部份， 接著去除該第一介電層；沈積一薄介電層，再沈積一第三導 電層再圖案化該苐二導電層，以形成一控制閘(con打〇ι gate);再使用傳統的後續製程，完成堆疊閘(stack-gate)。 為進一步對本發明有更深入的說明，乃藉由以下圖示、 經濟部智慧財產局員工消費合作社印製 圖號說明及發明詳細說明，冀能對貴審查委員於審查工作 時有所助益。 (四）圖g要說明： 圖上^習用技術快閃記憶體閘極的製程示意圖圖。 圖一A為本發明較佳實施例中，在一半導體基板上，形 本紙張尺度適用中國國家標準（CNs)A4規格（210 X 297公釐） 483159 A7 B7 五、發明說明（vf ) 成淺渠溝隔離後，再沈積隧道氧化層及第一導電 層之示意圖。 、 圖二B為本發明較佳實施例中，沈積第一介電層，並圖 案化第一介電層之示意圖。 圖二C為本發明較佳實施例中，沈積第二導電層之示意 圖。 圖二D為本發明較佳實施例中，蝕刻後之示意圖。 圖二E為本發明較佳實施例中，去除第一介電層，再沈 積薄介電層之示意圖。 圖二F為本發明較佳實施例中，沈積第三導電層之示意 圖0 (請先閱讀背面之注咅》事項再填寫本頁) 一裝---- 經濟部智慧財產局員工消費合作社印製 圖號說明： 卜10 半導體基板 2 > 20 淺渠溝隔離 3 ^ 30 隧道氧化層 4 > 40 第一導電層 5 " 60 第二導電層 6 氮化矽層 61 間隙壁 50 第一介電層 7 氮化氧化層 70 薄介電層 8、80 第三導電層 tr---------禮_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 483159 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（f ) 100 浮置閘 (五)本發明之詳細描述： 一種堆疊閘式快閃記憶體的製造方法，其步驟係用以下 圖式表示之：如圖二A所示，提供一半導體基板10，並形成 淺渠溝隔離20 (shallow trench isolation ; STI)，接著形成一 隧道氧化層30，再沈積一第一導電層40。其中第一導電層4〇 係為多晶矽（poly-silicon)、金屬矽化物（metalsilidde)或 非晶矽（amorphous silicon)其中一種，且其厚度在1〇〇〇a至 5000人間。 如圖一B所示，再沈積一第一介電層5〇，並利用微影餘 刻技術圖案化該第一介電層50，而停止於第一導電層上。 其中該第一介電層50係為氮化矽，且厚度在5〇〇人至4〇〇〇a 間。。 如圖二C所示，再沈積一第二導電層60，其形狀如圖所 示，係為一保角層（conformal layer)，以類似圖中型態沈積 覆蓋之。其中第一導電層60係為多晶石夕、金屬石夕化物或非晶 石夕其中一種，且厚度在500A至2500A間。又圖中第一介電^ 50加上第二導電層60的厚度A必須大於第一導電層4〇的厚^ B，以確保後續的微影餘刻動作可以有效的進行。 如圖二D所示，使用非等向性蝕刻第一導電層4〇及第二 導電層60，因為第-介電層5〇不會被麵，所以當第一導電 層40及第-導電層60性質接近時，兹刻後所形成的浮置閑 100(fl〇atmg gate)如圖所示，故可達成更佳窄間距隔離 私紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297&公爱 -----------^ --------^--------- (請先閱讀背茴之注务事項再填寫本頁) 483159 A7 _________~—_— B7 五、發明綱（t) ^ - -----------·*壯衣—— (請先閱讀t面之支音？事項再填寫本頁) (narrow-pitchisolation)的效果。且如圖二〇所示，當第—介 層50加上第二導電層60的厚度a大於第一導電層如的厚产b 時，在微影侧過後’第二導電層6〇在第一介電層5〇旁^ 像間隙壁(spacer)-般的殘留。而第二導電層6〇多出的殘留部 分’可使堆疊閘（stack-gate)的電容耦合比例（ca_4 coupling ratio)提升，進而增加快閃記憶體的電性。 如圖二E所示’去除第一介電層5〇後，再沈積一薄介電 層70作為中間層，其係為氮化氧化層仍〇)或氧化氣化氧化層 (0N0)其中一種，且厚度在100A至300A間。 如圖二(F)所示，再沈積一第三導電層8〇，接著圖案化該 第三導電層，以形成一控制閘(controlgate)(圖中未示），其係 為多晶石夕或金屬石夕化物或非晶石夕其中一種。 當然如業界所熟知，其再一實施例的步驟亦可改為，先 於半導體基板上依序沈積一隧道氧化層及第一導電層後，再 形成淺渠溝隔離（STI)，接著再沈積第二導電層，再來依照 上一實施例的後半步驟進行，便可得到相同的堆疊閘。 經濟部智慧財產局員工消費合作社印製 縱上所述，本發明至少有下列優點：用本發明的方法所 製得的浮置閘，只需使用兩次蝕刻，較習用技術必須使用三 次ϋ刻為少’可減少製程的複雜度，使可靠度上升進而提升 良率，降低製造成本，增加業界的競爭力。而且一次同時姓 刻兩導電層的方式，可達成更佳的窄間距隔離的效果，在積 體電路製程進入次微米或深次微米的技術時，將可更提升業 界的競爭力。再者，用本發明的方法所製得的浮置閘，因為 多出像間隙壁一般的部分，可更提高電容耦合比例，進而增 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 483159 A7 五、發明說明（？） 加快閃記憶體的電性，使產品品質更提升，而 爭優勢，不被時代所淘汰。 、 琢的只兄 本發明於習知技術領域上無相關之技術揭露，已具新賴 性；本發明之技術内容可確實解決該領域之問題，且^法原 理屬非根據習知技藝而易於完成者，其功效性業已經詳述’，、 實具進步性，又本發明採用之技術方法及所需設傷本身係屬 於本技術領域，亦具產業之可利用性。因此，基於鼓勵發明 目的，專利之惠准應根據專利法與專利審查基準之精神，相 信貴審纟委員秉持多年之審查實務、經驗，亦能認同本案符合 專利要件及專利精神，此種技術並非一般人士所易於能思^ 者，此點尚祈貴審查委員公正考量明鑒之，盼能早曰核准 專利，實為感禱。 本發明之圖式與描述以較佳實施例說明如上，僅用於藉 以幫助了解本發明之實施，翻赚定本發明之精神，而熟 悉此領域技藝者於領悟本發明之精神後，在不脫離本發明之 精神範圍内，當可作些許更動潤飾及同等之變化替換，其專 利保4範圍當視後附之申請專利範圍及其等同領域而定。 -----------··裝—— (請先閱讀背面之生意事項再填寫本頁) J^T· · 經濟部智慧財產局員工消費合作社印製 1 x 297公釐）Please read the back-attention-notes S · f first. Page I Order # V. Description of the Invention (V) After patterning the nitrided stone layer 6, a photolithographic etching technique is used to generate the spacer 61 '. The IU dagger stone layer 6 is used for masking for the third time. The silicon nitride layer 6 will not be eroded during the third etching. Therefore, the first conductive layer 4 and the second conductive layer 5 are The money is carved as shown in Figure 1c. Next, as shown in FIG. 1d and FIG. 1E, the silicon nitride layer 6 is removed, and a nitride oxide layer 7 (n0) is deposited as a floating gate composed of the first conductive layer 4 and the second conductive layer 5. ) And the re-deposited second conductive layer 8 are finally patterned to complete the stack gate (not shown). Obviously, the stack gate flash memory must be manufactured using conventional technology, so it must be made three times', which increases the complexity of making paste, reduces reliability and reduces yield, increases manufacturing costs, and affects its competitiveness. In addition, the shield used in the manufacturing technology will make the insulation pitch impossible to be tested again, so that when the integrated circuit process enters the sub-micron or deep sub-micron technology, it will seriously affect its competitiveness. In addition, conventional technology cannot further increase the ratio of capacitor light weight (cap = ive C_mg plus _ increase _ note, when the technology of the circuit process = sub-micron or deep sub-micron technology, can not improve _ memory electricity: = Quality cannot be improved'—Competitive advantage, printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (3) Brief description of the invention: The purpose of this development is to provide an increase in the number of stacked gate flash memories and the number of shadows. To reduce the complexity of the process and make it more reliable. The purpose of the present invention is to provide a system of stacked open flash memory of 297 mm. A7-~ ^ _— 5. Description of the invention (g) k method, In order to achieve a better narrow pitch isolation (narrww_pitch is〇iatiON) effect. Yet another object of the present invention is to provide a method for manufacturing a stacked gate flash memory, so as to produce a flash memory having a capacitive capacitance ratio (capacitive cOuppli). The present invention is to achieve the above object. Therefore, a method for manufacturing a stacked gate flash memory is proposed. The preferred implementation steps are: forming a shallow trench isolation (STI) on a semiconductor substrate, and sequentially depositing a tunnel oxide layer and a first conductive layer. Layer and a first dielectric layer; pattern the first dielectric layer and stop on the first conductive layer; deposit a second conductive layer, and then etch the first and first conductive layers using anisotropy To form a floating gate to achieve the effect of narrow-pitch isolation, in which the remaining second conductive layer forms a smaller gap wall beside the first dielectric layer ( spacer), which can increase the capacitive coupling ratio and is part of the floating gate, and then remove the first dielectric layer; deposit a thin dielectric layer, deposit a third conductive layer, and then pattern The second conductive layer to form a control (con 打 〇ι gate); and then use the traditional subsequent process to complete the stack-gate. In order to further explain the present invention, the following figure, printed by the Intellectual Property Bureau employee consumption cooperative of the Ministry of Economic Affairs The description of drawing number and detailed description of the invention are helpful to your review committee during the review work. (4) Figure g should explain: Figure ^ Schematic diagram of the conventional technology flash memory gate manufacturing process. Figure 1 A is a preferred embodiment of the present invention. On a semiconductor substrate, the size of the paper is adapted to Chinese National Standards (CNs) A4 (210 X 297 mm) 483159 A7 B7. 5. Description of the invention (vf) is a shallow trench. Schematic diagram of tunnel oxide layer and first conductive layer after isolation. Figure 2B is a schematic diagram of depositing a first dielectric layer and patterning the first dielectric layer in a preferred embodiment of the present invention. Figure 2C It is a schematic diagram of depositing a second conductive layer in a preferred embodiment of the present invention. Fig. 2D is a schematic diagram after etching in a preferred embodiment of the present invention. Fig. 2E is a preferred embodiment of the present invention in which the first dielectric is removed Electrical layer, redepositing thin dielectric Figure 2F is a schematic diagram of a third conductive layer deposited in the preferred embodiment of the present invention. 0 (Please read the note on the back first and then fill out this page). One pack ---- Intellectual Property Bureau of the Ministry of Economic Affairs Employee consumer cooperative printed drawing description: bu 10 semiconductor substrate 2 > 20 shallow trench isolation 3 ^ 30 tunnel oxide layer 4 > 40 first conductive layer 5 " 60 second conductive layer 6 silicon nitride layer 61 gap Wall 50 First dielectric layer 7 Nitrided oxide layer 70 Thin dielectric layer 8, 80 Third conductive layer tr --------- ceremony_ This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 483159 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (f) 100 Floating gate (5) Detailed description of the present invention: A method for manufacturing a stacked gate flash memory, The steps are represented by the following diagram: as shown in FIG. 2A, a semiconductor substrate 10 is provided, and a shallow trench isolation (STI) 20 is formed. Then, a tunnel oxide layer 30 is formed, and a first oxide layer 30 is deposited. A conductive layer 40. The first conductive layer 40 is one of poly-silicon, metal silidde, or amorphous silicon, and the thickness is between 1000a and 5000 people. As shown in FIG. 1B, a first dielectric layer 50 is further deposited, and the first dielectric layer 50 is patterned using a photolithography technique to stop on the first conductive layer. The first dielectric layer 50 is made of silicon nitride and has a thickness of 5,000 to 4,000 a. . As shown in FIG. 2C, a second conductive layer 60 is deposited. The shape of the second conductive layer 60 is a conformal layer, as shown in FIG. The first conductive layer 60 is one of polycrystalline stone, metallic stone or amorphous stone, and has a thickness between 500A and 2500A. In the figure, the thickness A of the first dielectric layer 50 plus the second conductive layer 60 must be greater than the thickness B of the first conductive layer 40, so as to ensure that the subsequent photolithography action can be performed effectively. As shown in FIG. 2D, the first conductive layer 40 and the second conductive layer 60 are anisotropically etched. Because the first dielectric layer 50 is not faced, when the first conductive layer 40 and the first conductive layer 40 are conductive, When the properties of the layer 60 are close, the floating 100 (floatmg gate) formed after the moment is shown in the figure, so it can achieve a better narrow-space isolation private paper. The standard is applicable to China National Standard (CNS) A4 (21 〇X 297 & Public Love ----------- ^ -------- ^ --------- (Please read the notes on the back of anise before filling out this page ) 483159 A7 _________ ~ —_— B7 V. Outline of Invention (t) ^------------ · * Zhuang Yi—— (Please read the note of t face first? Matters before filling out this page ) (narrow-pitchisolation). As shown in FIG. 20, when the thickness a of the first interlayer 50 plus the second conductive layer 60 is greater than the thickness b of the first conductive layer, after the lithography side passes, 'The second conductive layer 60 remains next to the first dielectric layer 50 like a spacer-like. The remaining part of the second conductive layer 60 is more than a stack-gate' The capacitance coupling ratio (ca_4 coupling ratio) is increased, thereby increasing the power of flash memory. As shown in FIG. 2E, after removing the first dielectric layer 50, a thin dielectric layer 70 is deposited as an intermediate layer, which is a nitrided oxide layer or an oxide gasified oxide layer (0N0). One of them, and the thickness is between 100A and 300A. As shown in FIG. 2 (F), a third conductive layer 80 is deposited, and then the third conductive layer is patterned to form a control gate (not shown), which is a polycrystalline stone. Or one of the metal stone or the amorphous stone. Of course, as is well known in the industry, the steps of another embodiment can also be changed. A tunnel oxide layer and a first conductive layer are sequentially deposited on the semiconductor substrate, and then a shallow trench isolation (STI) is formed, followed by deposition. The second conductive layer is performed in the second half of the previous embodiment to obtain the same stack gate. According to the above description, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the present invention has at least the following advantages: The floating gate produced by the method of the present invention only needs to use two etchings, and must use three engravings compared with conventional techniques For less, you can reduce the complexity of the process, increase reliability and improve yield, reduce manufacturing costs, and increase the competitiveness of the industry. In addition, the method of engraving two conductive layers at the same time can achieve a better narrow-pitch isolation effect. When the integrated circuit manufacturing process enters sub-micron or deep sub-micron technology, it will further enhance the competitiveness of the industry. In addition, the floating gate produced by the method of the present invention can increase the capacitance coupling ratio because there are more parts like gap walls, and the paper size can be increased to meet the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 483159 A7 V. Description of the invention (?) Speed up the flash memory's electrical properties, so as to improve the quality of the product, and strive for advantages, not to be eliminated by the times. The invention of this invention has no relevant technical disclosure in the field of known technology, and it is already new; the technical content of this invention can surely solve the problems in this field, and the principle of law is not based on the conventional technology and is easy to use. The finisher has been described in detail in terms of its effectiveness, and it is actually progressive, and the technical method and the wounds required by the present invention belong to the technical field and have industrial applicability. Therefore, for the purpose of encouraging inventions, the benefits of patents should be in accordance with the spirit of the Patent Law and Patent Examination Benchmarks. I believe that members of the Examiner's examination practice and experience for many years can also agree that this case is in line with the patent requirements and the spirit of patents. This technology is not It is easy for ordinary people to think about it, and I still hope that the examiners will consider the lessons from them fairly and hope that they can approve patents as soon as possible. The illustrations and descriptions of the present invention are described above in the preferred embodiments, and are only used to help understand the implementation of the present invention and determine the spirit of the present invention. Those skilled in the art will not depart from the spirit of the present invention after understanding the spirit of the present invention. Within the spirit of the present invention, when some modifications and equivalent changes can be made, the scope of its patent protection will depend on the scope of the attached patent application and its equivalent fields. ----------- · Installation—— (Please read the business matters on the back before filling in this page) J ^ T · · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 x 297 mm)