TW466764B - Manufacturing method of multi-segment circuit printing for multi-layered chip inductor - Google Patents

Manufacturing method of multi-segment circuit printing for multi-layered chip inductor Download PDF

Info

Publication number
TW466764B
TW466764B TW89125584A TW89125584A TW466764B TW 466764 B TW466764 B TW 466764B TW 89125584 A TW89125584 A TW 89125584A TW 89125584 A TW89125584 A TW 89125584A TW 466764 B TW466764 B TW 466764B
Authority
TW
Taiwan
Prior art keywords
printed
line
substrate
module
overlapped
Prior art date
Application number
TW89125584A
Other languages
Chinese (zh)
Inventor
Li-Chang Lin
Original Assignee
Tecstar Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tecstar Technology Co Ltd filed Critical Tecstar Technology Co Ltd
Priority to TW89125584A priority Critical patent/TW466764B/en
Application granted granted Critical
Publication of TW466764B publication Critical patent/TW466764B/en

Links

Landscapes

  • Coils Or Transformers For Communication (AREA)

Abstract

The present invention is related a kind of manufacturing method of multi-segment circuit printing for multi-chip inductor, in which the printing design of multi-segment loop coil circuit on the substrate is adopted to complete the multi-layered chip inductor that has multiple inductance coils and the same number of multi-layers. Thus, the inductive characteristic is greatly increased and higher inductive characteristic can be sustained in higher frequency environment.

Description

4 6 676 4 五、發明說明(〗) ~ ——— 尤指==::以::”感之多段線路製造方二 之線路印刷製造方法 作%境下能維持較高之電感特性 按習知積層線路製程方式,苴 再與另一層單圈迴路對、ς ς板上採印刷單圈迴路 ;單_路之積層線路然而,上 達到限疋尚頻工作範圍就會產生一錄^二電感.工作特性在 較高頻環境下工作得到穩农減效應,因此要在 如何提昇積層晶片電感之工作特二=疋無法達成的。要 要課題。 特生此乃本案所研究之主 本發明人基於籍思· , 研究,以累積多年從‘二感之工作特性需求,乃潛心 「積層晶片電感… 晶片電感之工作特性,法」,以提昇積層 本發明之主要目的匕產業上需求利用。 多段線路製造方法,Α p在於提供—種積層晶片電感之 之印刷設計,以使同^ 基板上採用多段迴路線圈線路 之效益’進而大幅之晶片電感具有倍數電感圈數 可維持較高之電i;::感特性’因此要在㈣ 幺幺依據本發日月卜j致 下: 揭目的所示|之製造方法詳加說明如 如第二:所示本發明主要方法為: 出從兩側邊緣向内延 之、,.罔板核組進行基板上印刷 n <伸之端點線路1〇。4 6 676 4 V. Description of the invention (〗) ~ ——— Especially == :::: ”The multi-segment line manufacturing method of the second line printing manufacturing method can maintain a high inductance characteristic under the circumstances. Know the manufacturing method of the multi-layer circuit, and then pair it with another layer of single-loop circuit, and use a printed single-loop circuit on the board. However, the single-circuit multi-layer circuit will reach the limit, and the high frequency working range will generate one record ^ two inductors. .Operating characteristics The stable agricultural reduction effect is obtained when working in a higher frequency environment. Therefore, how to improve the work of multilayer chip inductors can not be achieved. It is a major issue. This is the main inventor of this case. Based on thinking and research, to accumulate years of working characteristics from the "two senses," it is a "laminated chip inductor ... working characteristics of chip inductors" method to enhance the main purpose of the present invention. A method for manufacturing multi-segment circuits. A p is to provide a printed design of multilayer chip inductors, so that the benefits of using multi-segment loop coil circuits on the same substrate can be achieved. ; :: Feeling characteristics' Therefore, it is necessary to make the following according to the issue of the sun and the moon: According to the purpose of the disclosure | The manufacturing method is explained in detail as shown in the second: The main method of the present invention is as follows: The edge is extended inwardly, and the nuclei of the core plate are printed on the substrate with n < extended end lines 10.

第4頁 4 8 676 4 ;--- 五、發明說明(2) b. 以對基板左半面 田,各 留出一小段之端點線路1 〇仃覆蓋磁漿層2 0絕緣處理’ c. 以一第一對稱勒 路〗1印刷處理,以供輿/、’’路之網板模組進行第^對接,’ d·將基板右半面積^ =之端點線路1 〇對合搭接。 e. 以一第二斟骚姑是现磁漿層2〇絕緣處理。 A 路12印刷處理,以;::線路之網板模組進行第二 f. 同樣將基板左f接線路11對合搭接。 2以一第-4也面積再覆蓋磁漿層20絕緣處理0 g. 以 弟二組對稱舳时仏灿 線路i抑刷處理,以供2線f之網板模組進行第三對接 •續,右t面積覆蓋磁.漿層2 0絕緣處理。 以说H末端連接網板模組進行銜接線路1 4印刷處理 =與第三對接線路乂!對合搭接,而完成一具有4;二 圈數之積層晶片電感者。 攸電感 由上述得知,本案乃在基板上橡用多段迴路線 ”、印刷設計,以使在同樣積層數上具有倍數電感圈數之, 而大幅提高電感特性,因此要在較高頻環境下欢 、土較南之電感特性,極具進步性,為一合於實用之發日°維 法者。 %方Page 4 4 8 676 4; --- V. Description of the invention (2) b. To the left half of the substrate, leave a small segment of the end line 1 〇 仃 to cover the magnetic layer 2 0 insulation treatment 'c. A first symmetrical path is printed for the first ^ connection of the stencil module of the road, and d. The end line of the right half area of the substrate ^ = 1 is connected and overlapped. . e. A second consideration is that the current plasma layer 20 is insulated. A road 12 is printed and processed with ::: circuit board module for the second f. Similarly, the left f of the substrate is connected to the circuit 11 for overlapping. 2 Cover the magnetic slurry layer with a first -4 area. 20 Insulation treatment. 0 g. Two sets of symmetrical 舳 仏 仏 can circuit i brush suppression treatment for the second docking of the 2 wire f screen module. Continued , The right t area covers the magnetic and slurry layer with 20 insulation treatment. Let's say that the H-end connection stencil module is used for the connection line 1 4 printing processing = and the third butt-connection line 乂! Butt-lap, and complete a multilayer chip inductor with 4; two turns. You learned from the above, this case is to use a multi-section circuit line on the substrate "and print design so that the same number of layers has multiples of the number of inductance turns, and the inductance characteristics are greatly improved. Therefore, it must be used in a higher frequency environment. The inductance characteristics of Huan and Tujiaonan are highly progressive, and they are a practical and effective way to maintain the law.% 方

I 符號說明: 10 11 12 端點線路 • ·., 第 第一對接線路 第二對接線路 對接線'路.....1 3I Symbol description: 10 11 12 End-point line • ·., First first butt line Second butt line Butt line '..... 1 3

第5頁Page 5

Claims (1)

466764 六'申請專利範圍 一種積層晶片電感夕 〜~~ 丨包括: ' 夕又線路印刷製造方法,其+ 以:端點對稱轨跡線路之 ”步‘驟 丨從兩:=内延伸之端點線路板模組進行基板上印刷出 、土板左半面積進行 —小段之端點線路; 盍磁漿層絕緣處理,各, 未以—第一對稱執跡線路之 邊出 將基板右半線路對合搭接;對接線印 以-第二:=Γ聚層絕緣處理; 接線路 I印刷處理,以供與第一 ,,罔板模組進行第二 同樣將基板左半面積對合搭接; 對接線 以一第三組對稱勤紘覆盍磁漿層絕緣處理 |路印刷處理,以供J :對::網板模組進行第 丨用—末端連接網板模組進“彖處理,以及 與第三對接線路對合搭接,以二線路印刷處理,以供 广積層晶片電感,進而大:層數具有倍數電感 雄境下可維持較高之電感特性^“電感特性,在較高頻466764 Six 'patent application scope A multilayer chip inductor ~~~ 丨 Including:' Xiyou circuit printing manufacturing method, which + + :: the step of the terminal symmetrical trajectory line 丨 from the end of the extension of two: = The circuit board module is printed on the substrate, and the left half of the soil plate is carried out-a small segment of the end line; 盍 magnetic slurry layer insulation treatment, each, not with-the edge of the first symmetrical track line to the right half of the substrate Bonding and bonding; the wiring is printed with-the second: = Γ poly-layer insulation treatment; the wiring I is printed for processing with the first and second module modules and the second half of the substrate is also overlapped and overlapped; The butt wiring is covered with a third group of symmetrically covered magnetic plasma insulation treatment | road printing processing for J: Pair :: the stencil module is used for the first time—the end is connected to the stencil module for "彖 processing, and It is overlapped with the third butt-connected line, and printed with two lines for wide-stacked chip inductors, so as to be large: the number of layers has multiples of the inductance, and it can maintain a higher inductance characteristic under the circumstance of ^ "inductance characteristics, at higher frequencies 第8胃8th stomach
TW89125584A 2000-12-01 2000-12-01 Manufacturing method of multi-segment circuit printing for multi-layered chip inductor TW466764B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW89125584A TW466764B (en) 2000-12-01 2000-12-01 Manufacturing method of multi-segment circuit printing for multi-layered chip inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW89125584A TW466764B (en) 2000-12-01 2000-12-01 Manufacturing method of multi-segment circuit printing for multi-layered chip inductor

Publications (1)

Publication Number Publication Date
TW466764B true TW466764B (en) 2001-12-01

Family

ID=21662167

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89125584A TW466764B (en) 2000-12-01 2000-12-01 Manufacturing method of multi-segment circuit printing for multi-layered chip inductor

Country Status (1)

Country Link
TW (1) TW466764B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same

Similar Documents

Publication Publication Date Title
JP6371309B2 (en) Parasitic inductance reduction circuit board layout design for multilayered semiconductor devices
CN106030730B (en) Like the inductor of 8 shapes
JP5779213B2 (en) Magnetic field cancellation in switching regulators
TWI406306B (en) Highly coupled inductor
TW541548B (en) Laminated impedance device
JP2004235556A (en) Laminated capacitor, wiring board, decoupling circuit, and high-frequency circuit
JP2001085248A (en) Transformer
TW591996B (en) Split inductor with fractional turn of each winding and PCB including same
JP6533342B2 (en) Composite smoothing inductor and smoothing circuit
JP3753928B2 (en) Printed circuit board and power supply using the same
US9064628B2 (en) Inductor with stacked conductors
CN105932001A (en) Packaged Integrated Circuit Including Switch-mode Regulator And Method Of Forming The Same
TW579627B (en) RF circuit and an integrated inductor therewith
CN105051841B (en) magnetic device
JPH1140438A (en) Planar magnetic element
TW466764B (en) Manufacturing method of multi-segment circuit printing for multi-layered chip inductor
JP2009038297A (en) Semiconductor device
CN108770186A (en) Voltage isolation circuit and electronic device
JP5644298B2 (en) DC-DC converter module
WO2018229978A1 (en) Printed circuit board
JP2010062409A (en) Inductor component
TW200834914A (en) Structure of inductor
JP2005116666A (en) Magnetic element
JP4227985B2 (en) Power supply using printed circuit board
JP5920392B2 (en) DC-DC converter module

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent