TW444370B - Flip-chip packaging substrate - Google Patents

Flip-chip packaging substrate Download PDF

Info

Publication number
TW444370B
TW444370B TW089110023A TW89110023A TW444370B TW 444370 B TW444370 B TW 444370B TW 089110023 A TW089110023 A TW 089110023A TW 89110023 A TW89110023 A TW 89110023A TW 444370 B TW444370 B TW 444370B
Authority
TW
Taiwan
Prior art keywords
patternized
flip
surface
layout layers
layout
Prior art date
Application number
TW089110023A
Inventor
Ying-Jou Tsai
Shr-Guan Chiou
Han-Ping Pu
Original Assignee
Siliconware Prec Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Prec Ind Co Ltd filed Critical Siliconware Prec Ind Co Ltd
Priority to TW089110023A priority Critical patent/TW444370B/en
Application granted granted Critical
Publication of TW444370B publication Critical patent/TW444370B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

A flip-chip packaging substrate comprises: multi-layer patternized layout layers and at least one insulation layer; the insulation layer is configured between the patternized layout layers for isolating the patternized layout layers and overlapped with the patternized layout layers; the patternized layout layers are electrically connected with each other in which one of the patternized layout layer is located on the surface of the flip-chip package substrate and at least comprising a plurality of the first mounting pads and a plurality of the second mounting pads; the solder mask layer, covering the patternized layout layers on the surface of the flip-chip package substrate to expose part of the surface of the first mounting pad; and, covering part of the surface at the outer edge of the first mounting pad to completely expose the surface of the second mounting pad.
TW089110023A 2000-05-24 2000-05-24 Flip-chip packaging substrate TW444370B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW089110023A TW444370B (en) 2000-05-24 2000-05-24 Flip-chip packaging substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW089110023A TW444370B (en) 2000-05-24 2000-05-24 Flip-chip packaging substrate

Publications (1)

Publication Number Publication Date
TW444370B true TW444370B (en) 2001-07-01

Family

ID=21659841

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089110023A TW444370B (en) 2000-05-24 2000-05-24 Flip-chip packaging substrate

Country Status (1)

Country Link
TW (1) TW444370B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977763B2 (en) 2002-01-19 2011-07-12 Megica Corporation Chip package with die and substrate
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136246B2 (en) 2001-12-31 2015-09-15 Qualcomm Incorporated Integrated chip package structure using silicon substrate and method of manufacturing the same
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers
US7977763B2 (en) 2002-01-19 2011-07-12 Megica Corporation Chip package with die and substrate

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Legal Events

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees