4443 5 7 A7 B7 五、發明説明（） 發明領斑： 本發明係關於一種高密度垂直罩幕式唯讀記憶胞的 製成方法’亦即關於一種遮罩式准讀記憶胞的製成方法； 並且本發明更關於一種利用溝渠元件來作為遮罩式唯讀 記憶胞的製程方法。 發明眢景： 近年來由於半導體技術的迅速提升，更複雜、效能更 好的積技電路（1C)被製造出來，然而相對上用來製造它 們所需的製程步驟也更為複雜》以1970年代有關16百萬 位元（16 mega bits)之超大型積體電路元件（ultra large-scale integration circiuts device; ULSI)的 記憶Λ ( memory )而言’至少就需要超過20個以上的罩 幕電路位準（mask levels)。對於一個一百萬級的記憶 體而言’其位元線的密度只要平面結構的電容及電晶體即 可組成。 其次’所謂的唯讀記憶It (ReadOnly Memory)的定 義乃是此類元件在電路上只允許資料的讀出，而不許其寫 入之電路元件。一般唯讀記憶艘的種類，依其資料存入方 式可分為下列數種：最簡單之罩幕式唯讀記憶體（Mask ROM)，以及可租式之唯讀記憶艘（ProgrammableROM)、 第2頁 私纸張尺度逋用中》國家橾率{〇邮）八4規展（210父297公釐） 1锖先聞讀背面之注意_項存碘寫本貫) ^装- -" 經濟部智慧財產局負工消費合作社印製 4443 5 7 A7 A7 B7 五、發明説明（） 可抹除且可程式之唯讀記愧體（Erasable Programmable ROM)、可電性抹除且可程式之唯讀記億體（Electrically Erasable Programmable ROM)等；而依資料在記憶體内 的處理方式又可分為：靜態隨機存取記憶體（SRAM )和動 態隨機存取記憶體（DRAM)等。 以下第1 a圖至第le圖所示係一平面構造罩幕式唯 讀記憶艘的製程步驟。 如第la田所示：提供一具有輕微摻雜有p導電型之 捧雜物的基材100。並在基材1〇〇之表面的兩側並具有場 氡化區域（f ield-oxide ) 106;而一光阻層104後蓋在此 基材100的表面上，此光阻層104係用以定義複數個捧雜 區域102的形成區域。此複數個摻雜區域1〇2係利用離子 佈植製程所形成’其中此複數個換雜區域1〇2所掺雜的離 子為η導電型之離子，例如：砷或磷。此外，在複數推雜 區域102形成後，移去光限層104。 經濟部智恶財產局員工消费合作社印製 之後，如第lb圈所示：利用離子佈椬法揸入蝴離子， 在該基材100上形成隔離區（isolation regions) 1Q8» 此隔離區域108係用來防止元件與元件之間的漏電情形。 接著’在基材100以及摻雜區域1〇2上方形成—開氧 化層110’諳參考第lc圈所示。並且在此閘氧化層u 4443 5 7 A7 B7 五、發明説明（） 經濟部智慧財產局負工消費合作社印製 上方形成一複晶矽層11 2。 然後’如第Id圖所示·在閘氧化層112之上覆蓋一 光阻層114，此光阻層Π4係在硼離子佈植的步驟中遮蔽 部分區域’而暴露出欲植入雜質的區域，用來定義一罩幕 式之唯讀記憶胞的程式編碼（coding cell of R〇M)。 最後，如第le圖所示：傳統之罩幕式唯讀記億體包 含複數個摻雜區域102，且兩個彼此相鄰之摻雜區域1〇2 具一固定之臨界電壓（threshold voltage)。由於此摻 雜區域102摻有η型導電雜質，而摻雜區域116則摻有硼 離子，故位於硼離子摻雜區域116兩側相鄰之摻雜區域 102之間的臨界電壓將被提高。亦即，高臨界電壓值對應 至邏輯高準位；相反的，其它臨界電壓值較低的區域118 則對應至邏輯低準位。 然而，當元件的組成密度越來越高，而單一晶片的元 件大量增加時，元件與元件之間由於距離越來越近將會造 成嚴重的漏電情成*而上述之平面結構的摹幕式唯讀記憶 艘無法有效的提供防止元件與元件之間漏電情形’且其單 位面積所能容納的元件數目有限；故一個可以有效抑制元 件與元件之間漏電情形*且在單位面積内可容納較大量元 件的製程方法，乃是記憶體製租技術上所里欲解決的問 題。有16於此，本發明即針對此技術瓶頭提供一解決的方 (請先閲讀背面之注意事項再填寫本頁) .^. 订 J— 第4頁 本紙張尺度逍用中國國家榣率（CNS ) Α4規格（2丨0X297公釐） 4443 5 7 A 7 B7 經濟部智慧財產局員工消費合作钍印製 五、發明説明（） 法。 發明目的及概： 本發明之目的在提供一高密度垂直革幕式唯讀記憶 胞的製造方法；亦即，溝渠結構之罩幕式唯讀記憶體的製 程方法。此溝渠結構之罩幕式唯讀記愧體可以達到加大積 效電路的容量、降低電流漏電的情形，以及縮小元件大 小。 本發明所提供此溝渠結構之革幕式唯讀記憶體的主 要製程步驊如下所述•其中，本發明的第一個實施例的製 程步驟包含··在一具有輕微摻雜Ρ導電性摻雜物的基材 上，先覆蓋一層墊氡化層，並在墊氧化層之上繼續覆蓋一 層氮化矽層*接著，利用蝕刻技術蝕刻此基材以形成複數 個溝渠*然後，利用時沈積法或熱氡化法在各個溝渠之表 面上形成一閘氡化層。之後，移去位於基材上方的氮化矽 層5接著，利用離子佈植技術在溝渠之間的基材上方之墊 氧化層下方形成一摻雜區；且其中之η導電型離子包含砷 離子或磷離子；此摻雜區與下面步驟所形成之掺雜區為 本發明之位元線（bit line)。然後，一複晶矽層在上 述完成之元件上方上形成；其中此複晶矽層並進行圓案 蝕刻以形成本發明之字語線（word 1 i ne )。最後，再利 用一光阻復蓋部分溝渠，亦即暴露部分的溝渠·，然後，mss. (锖先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用t國«家韓準（CNS ) A4规格（210X297公釐> • 4 443 5 7 A7 _ B7 五、發明說明（） 最這些暴露之溝渠的底部植入n導電型之離子。這些植 入區域用以定義此罩幕式唯讀記愫體的程式編碼。 本發明之另一實施例為將上述之製程方法中，選擇先 進行η導電性離子佈椬，然後再進行蝕刻定義複數個溝渠 構造。亦即，在一具有輕微摻雜〇導電型摻雜物的基材上 方覆蓋一墊氧化層，並且接著利用離子佈植植導電型 之離子；之後，後蓋一氮化矽層。並利用蝕刻技術蝕刻此 基材以形成複數個溝渠。接下去的步驟則與上一實施例相 同。利用此方法亦可得到相同之罩幕式唯讀記憶體。 利用本發所得到的溝渠構造之罩幕式唯讀記憶體具 有增加積體電珞容量、降低電流漏電，以及縮小元件的效 果。這樣的結果可以滿足現今半導體製程的發展趨勢，因 應未來半導逋製程技術的需要β 圖式ffi JL .明: . '^裝--------訂---------峻'Y (請先閱讀背，面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 記 讀 唯 式 幕 箪 之 式 面 平 關 有 知 為 圖 Θ TA 第称 am程 1 製 第的 體 憶 方 上 材 基 至 質 雜 導 型 η 入 植 法 方 植 佈 子 離 用 利 0 a 12 第 圖 意 示 面 剖 的 域 區 。絕 明隔 意- 示 面 剖 的 域 區 分 部 的 b 第 成 形 子 離 硼 入 植 為 圈 本紙張尺度適用中國g家標準（CNS)A4規袼（210 x 297公鏟） #443 5 74443 5 7 A7 B7 5. Description of the invention () The invention spot: The present invention relates to a method for making a high-density vertical mask-type read-only memory cell, that is, a method for making a mask-type quasi-reading memory cell And the present invention is more about a manufacturing method using a trench element as a mask-type read-only memory cell. Invention: In recent years, due to the rapid advancement of semiconductor technology, more complex and more efficient integrated circuit (1C) has been manufactured, but the process steps required to manufacture them are also more complicated. Regarding the memory Λ (memory) of an ultra large-scale integration circiuts device (ULSI) with 16 mega bits (16 mega bits), at least more than 20 mask circuit bits are required. (Mask levels). For a one-million-level memory, the density of its bit lines can be composed of a planar capacitor and a transistor. Secondly, the definition of the so-called read-only memory It (ReadOnly Memory) is a circuit element that allows only data to be read out of the circuit, but not written to it. The types of general read-only memory ships can be divided into the following types according to their data storage methods: the simplest mask-type read-only memory (Mask ROM), and the rentable read-only memory ship (ProgrammableROM). 2 pages of private paper in use "National rate {0 Posts" 8 4 exhibitions (210 fathers 297 mm) 1 first read the attention on the back _ Xiangcun iodine writing this book) ^ 装--" Economy Printed by the Ministry of Intellectual Property Office, Consumer Cooperatives 4443 5 7 A7 A7 B7 V. Description of the invention () Erasable Programmable ROM, erasable and programmable Reading Erasable Programmable ROM, etc .; and according to the data processing method in the memory can be divided into: static random access memory (SRAM) and dynamic random access memory (DRAM). Figures 1a to 1e below show the process steps of a planar structured curtain-type read-only memory ship. As shown in Section 1a, a substrate 100 having a dopant doped with a p conductivity type is provided. And on both sides of the surface of the substrate 100, there are field-oxide regions 106; and a photoresist layer 104 is covered on the surface of the substrate 100. The photoresist layer 104 is used for In order to define the formation region of the plurality of miscellaneous regions 102. The plurality of doped regions 102 are formed by an ion implantation process, wherein the ions doped in the plurality of doped regions 102 are n-type ions, such as arsenic or phosphorus. In addition, after the complex doping region 102 is formed, the optical confinement layer 104 is removed. After printing by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs, as shown in circle lb: Ion cloth is used to insert butterfly ions to form isolation regions 1Q8 on the substrate 100. This isolation region 108 is Used to prevent leakage between components. Next, 'on the substrate 100 and the doped region 102 are formed-the open oxide layer 110' is shown with reference to circle lc. And on this gate oxide layer u 4443 5 7 A7 B7 V. Description of the invention () Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a polycrystalline silicon layer 11 2 is formed above. Then “as shown in FIG. Id. • A photoresist layer 114 is covered on the gate oxide layer 112, and this photoresist layer Π4 is used to mask a part of the area during the boron ion implantation step” to expose the area where the impurities are to be implanted. , Used to define a coding cell of ROM for a curtain-style read-only memory cell. Finally, as shown in Fig. Le, the traditional mask-type read-only memory includes a plurality of doped regions 102, and two adjacent doped regions 102 have a fixed threshold voltage. . Since the doped region 102 is doped with n-type conductive impurities, and the doped region 116 is doped with boron ions, the threshold voltage between the doped regions 102 adjacent to both sides of the boron ion doped region 116 will be increased. That is, a high threshold voltage value corresponds to a logic high level; conversely, other regions 118 with a lower threshold voltage value correspond to a logic low level. However, when the composition density of components is getting higher and higher, and the number of components on a single chip is increasing, the distance between the components is getting closer and closer, which will cause serious leakage. The read-only memory boat cannot effectively prevent the leakage situation between components and its number of components per unit area is limited; therefore, one can effectively suppress the leakage situation between components and components * and can accommodate more The manufacturing method of a large number of components is a problem to be solved in the memory system rent technology. There are 16 here, the present invention is to provide a solution for the bottle head of this technology (please read the precautions on the back before filling this page). CNS) Α4 specification (2 丨 0X297 mm) 4443 5 7 A 7 B7 Consumption cooperation for employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. OBJECTS AND SUMMARY OF THE INVENTION The object of the present invention is to provide a method for manufacturing a high-density vertical leather-type read-only memory cell; that is, a method for manufacturing a curtain-type read-only memory with a trench structure. The hood-style read-only shame of this trench structure can increase the capacity of integrated circuits, reduce current leakage, and reduce component size. The main process steps of the leather screen read-only memory of the trench structure provided by the present invention are as follows. Among them, the process steps of the first embodiment of the present invention include: On the substrate of the debris, firstly cover a padding layer, and then continue to cover a layer of silicon nitride layer on the pad oxide layer. Then, the substrate is etched using an etching technique to form a plurality of trenches. Then, it is deposited during use. The method or thermal curing method forms a gated layer on the surface of each trench. After that, the silicon nitride layer 5 above the substrate is removed, and then an ion implantation technique is used to form a doped region under the pad oxide layer above the substrate between the trenches; wherein the η conductive ions include arsenic ions Or phosphorus ions; this doped region and the doped region formed in the following steps are bit lines of the present invention. Then, a polycrystalline silicon layer is formed over the completed device; the polycrystalline silicon layer is subjected to circular etching to form the word line of the present invention. Finally, a photoresist is used to cover part of the ditch, that is, the exposed part of the ditch. Then, mss. (锖 Please read the precautions on the back before filling this page) This paper is applicable to country «家 韩 准 （CNS） A4 specifications (210X297 mm > • 4 443 5 7 A7 _ B7 V. Description of the invention () The bottom of these exposed trenches is implanted with n-conducting ions. These implanted areas are used to define this mask-only read-only Record the program code of the body. Another embodiment of the present invention is to select the η conductive ion cloth in the above process method, and then perform etching to define a plurality of trench structures. The substrate of the doped conductive dopant is covered with a pad oxide layer, and then conductive ions are implanted with ion implantation; after that, a silicon nitride layer is back-covered, and the substrate is etched using an etching technique to form a plurality of layers. A trench. The next steps are the same as the previous embodiment. The same mask-type read-only memory can also be obtained using this method. The mask-type read-only memory using the trench structure obtained by the present invention has an increased product. body Capacitive capacity, reducing current leakage, and reducing the effect of components. This result can meet the current development trend of semiconductor processes, in response to the needs of future semiconductor process technology β pattern ffi JL. Ming:. '^ 装 --- ----- Order --------- Jun'Y (Please read the back, the precautions above, and then fill out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives The surface level is known as the figure Θ TA, which is the first procedure of the am process 1 system, the upper material base to the heterogeneous conductive type η. Enormous Separation-The section b of the domain division of the surface section is implanted in a circle. The paper size applies the Chinese Standard (CNS) A4 (210 x 297 male shovel) # 443 5 7
五、發明說明（） lc圖為依序在基材上復蓋一層氧化層和複晶矽層的别 面示意圖。 第Id圖為利用一遮革定義程式蝙％，並植入硼離子形成 疋之罩幕式唯讀記愧體的剖面示意圖。 第le圖為一罩幕式唯讀記愧體的截面示意圖。 第2a圖至第26圈為本發明之一實施例的罩幕式唯讀 記憶艘的製程步驟： 第2a圖為本發明之實施例中提供一具有輕微摻雜之半導 體基材，且此基材上並覆蓋一層氧化層、一氮化 層，以及一用以定義溝渠形成位置的光阻之剖面示 意圖4 第2b圈為本發明之實施例中利用蝕刻技術形成複數個溝 渠的剖面示意圈。 經濟部智慧財產局員工消費合作社印製 t請先閱讀背面之法意事項再填寫本頁) 第2c圖為本發明之實施例中在溝渠蝕刻後1於各個溝渠 的表面上形成閘氡化層的剖面示意圖β 第2d圖為為本發明之實施例中在介電層之上形成一複晶 梦層並利用離子佈植法在各個溝渠之間的基材上 方之墊氡化層底部植入η導電型之離子以形成一摻 雜區的剖面示意圖。 第2e «為本發明之實施例中利用_箪幕定義程式編碼以 形成溝渠結搆之罩幕式唯讀記憶想的剖面示意 圖。 第7頁 本紙張尺度適用中國困家標準（CNS)A4规格（210x 297公釐 4443 5 7 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 第3明為本發明溝渠構造之罩幕式唯讀記憶體的剖面圖。 第4a圊至第4f围為本發明之另一實施例的溝渠構造 之罩幕式唯讀記憶體的製程步驟： 第4a圖本發明之另一實施例中在一復蓋一墊氧化層的基 材上利用離子佈植法對此基材植入η導電型離子的 剖面示意圈。 第4b圓本發明之另一實施例中在墊氡化層上形成一層氮 化梦層的剖面示意圖。 第4c Μ本發明之另—實施例中對基材蝕刻以形成複數個 溝渠的刮面示意圖。 第4d圖本發明之另一實施例中在各個法渠的表面上形成 一閘氡化層的剖面示意圖β 第4e圈為本發明之另—實施例中在閉氧化層之形成_複 晶矽層的剖面示意圖。 第4f圖為本發明之另一實施例中利用一光阻來定義裡式 編蜗以形成溝渠結構之笨幕式唯讀記憶想的則面 示意圖· 發明祥細说aq _ ： 本發明的目的在捤供 社徙併高密度垂直革幕式唯讀記憶 胞的製造方法；亦即，一種新细沾，妓· 種新型的溝渠結構之遮覃式唯讀 -------.--—丨-f裝---I--丨丨訂·丨丨丨— — — —4V (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention () The lc diagram is a schematic diagram of another surface in which an oxide layer and a polycrystalline silicon layer are sequentially covered on the substrate. Figure Id is a schematic cross-sectional view of a mask-only read-only shame body using a mask to define the formula bat% and implanting boron ions to form a mask. Figure le is a schematic cross-sectional view of a read-only shame body in a curtain ceremony. Figures 2a to 26 are process steps of a mask-type read-only memory ship according to an embodiment of the present invention: Figure 2a is a semiconductor substrate with a slight doping provided in the embodiment of the present invention, and this base The material is covered with an oxide layer, a nitride layer, and a photoresistive cross-sectional view for defining a trench formation position. The second circle 2b is a schematic cross-sectional circle of a plurality of trenches formed by an etching technique in an embodiment of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, please read the legal notices on the back before filling out this page) Figure 2c is an example of the present invention. After the trenches are etched, a gate layer is formed on the surface of each trench Figure 2d is a cross-sectional view of the embodiment of the present invention. A polycrystalline dream layer is formed on the dielectric layer and implanted at the bottom of the padding layer over the substrate between the trenches using an ion implantation method. Schematic cross-sectional view of n-type ions to form a doped region. Section 2e «is a schematic cross-sectional view of a mask-only read-only memory that uses the _ 箪 screen definition program code to form a trench structure in the embodiment of the present invention. Page 7 This paper size is in accordance with China Standard for Household Standards (CNS) A4 (210x 297 mm 4443 5 7 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy A cross-sectional view of a mask-type read-only memory. Sections 4a to 4f are process steps of a mask-type read-only memory in a trench structure according to another embodiment of the present invention: FIG. 4a illustrates another implementation of the present invention. In the example, a cross-sectional schematic circle of implanting η-conducting type ions on this substrate using an ion implantation method on a substrate covered with an oxide layer is provided. In the fourth embodiment of the present invention, a spacer layer is formed on the substrate. A schematic cross-sectional view of a nitrided dream layer is formed on the top. FIG. 4c Schematic illustration of a scraped surface of a substrate etched to form a plurality of trenches in another embodiment of the present invention. FIG. 4d FIG. Sectional schematic diagram of a gated layer formed on the surface of the channel β The 4e circle is another section of the present invention—the formation of a closed oxide layer in the embodiment_the cross-sectional schematic diagram of the polycrystalline silicon layer. FIG. 4f is another section of the present invention. In the embodiment, a photoresist is used to define the Chinese style. A schematic diagram of a stupid screen-only read-only memory that forms a trench structure. · Invention details: aq _: The purpose of the present invention is to manufacture a high-density vertical leather-screen type read-only memory cell that migrates to the community; that is, A new type of fine dip, prostitute · A new type of trench structure covering Qin-style read-only ------------.---------------------- —4V (Please read the notes on the back before filling this page)
4443 5 7 經濟部智慧財產局員工消费合作杜印製 Λ7 _B7___ 五、發明說明（） 記憶體的製裎方法。以下將配合圖示說明，利用一典型的 實施例詳細說明之。 本發明之一實施例如以下配合圖式說明第2a圖至第 2e®。首先，如第2a圖所示··在一基材200上形成一墊 氧化層202a。並且此基材輕微摻雜有p導電型離子。其 中’此墊氡化層202a可以是利用熱氧化法或沈積法等方 法形成。於本實施例中之墊氧化層202a的厚度約在300 至600埃之間。接著，一氩化矽層204形成在墊氧化層202a 之上。此氣化梦層204係用以在下面的姓刻步棘中保護整 氧化層202a的，且其厚度約在1〇〇〇至2〇〇〇埃之間。然 後’ 一光阻206形成在氮化梦層204之上，且光阻206係 用以定義溝渠（trenches)形成的位置。 接著’在墊氧化層202a和氮化矽層204形成之後， 利用傳統的微影罩幕和蝕刻製程在此基材2〇〇之上形成圖 案化的光阻層206，再利用此圊案化光阻層206蝕刻底層 之氣化ί夕層204。如第2b圖所示：剝除光阻層206之後， 以姓刻後之氮化矽層204作為蝕刻罩幕而往下蝕刻墊氧化 層202a及基材200，在基材200 4»型成溝渠208。其中， 在本步驟中不同的配方可以得到深度不同的溝渠2〇8。而 不同深度的溝渠208會造成在以下形成相鄰之摻雜區域具 有不同的臨界電壓，其中的關係將在下文中做較詳盡的說 明。 第9頁 本紙張尺度適用中國國家標準（CNS>A4规格<21〇 χ 2g7公釐 ---I----— — W裝·！-----訂 *----— I !嫂'^ (請先閱讀背面之注意事項再填寫本頁) 4443.5(修正 Α7 Β7 經濟部智慧財產局員工消费合作社印製 五、發明說明（） 如第2c圖所示，利用熱氧化的方法在這些溝渠208 之底部和側壁的表面上形成一層閘氡化層2〇2b，再形成一 光阻層201於溝渠中•之後，如第2(1圖所示’先移去位 於基材200頂層之氮化矽層204。其中，氮化矽層204， 了以在約1 50到200 C的溫度下以Ji：iP〇4溶液來去除·»並且 在移除氣化矽層204之後’利用離子佈植法形成多個摻雜 區域°因為溝渠208内部位置有殘餘之光阻層阻礙，所以 在各個溝渠208之間的基材200中植入^導電型離子以形 成複數個摻雜區域210;其中此複數個摻雜區域2IQ並位 於整·氧化層202b下方。其中，植入之^導電型離子可以 是51離子或磷離子；而砷離子植入的能量（亦即佈植時之 的離子加速能量）約在40至lOOKeV之間，如此可以在塾 氧化層2 0 2a得到厚度約在1 5 0 0至3 0 0 〇埃左右的摻雜區 域210;此外’若植入的離子為磷離子，則其植入能量約 在30至80KeV之間；且其離子的濃度約在5χ1〇"至5xl〇i5 之間《之後移除其餘剩下在溝渠中之光阻層20丨，並且利 用化學氣相沈積CCVD)的方式在基材200的表面形成一 複晶碎層212或#雜η導電型離子的複晶麥。以一較佳實 施例為例，以LPVCD在溫度450-6 50以同步摻雜的方式沈 積，摻雜一濃度約5又1019至5；£1021/^1]13的11導電型離子' 該複晶碎層212可予以闽案.化以作為定義字語線（w〇rd line) β 如第2e®所示：在上述步秘完成之後，在此基材goo 第10頁 本紙張尺度適用中a 0家棵準（CNS>A4規·格/210 * 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝 • n 1 _ 線4443 5 7 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs DU7 _B7___ V. Description of the invention () Method of making memory. In the following, it will be described in detail with a typical embodiment in conjunction with the illustration. An embodiment of the present invention is described below with reference to the drawings 2a to 2e®. First, as shown in FIG. 2a, a pad oxide layer 202a is formed on a substrate 200. And this substrate is slightly doped with p-conducting ions. Among these, the pad-forming layer 202a may be formed by a method such as a thermal oxidation method or a deposition method. The thickness of the pad oxide layer 202a in this embodiment is about 300 to 600 angstroms. Next, a silicon argon layer 204 is formed on the pad oxide layer 202a. The gasification dream layer 204 is used to protect the entire oxide layer 202a in the next step, and has a thickness of about 1000 to 2000 Angstroms. Then, a photoresist 206 is formed on the nitride nitride layer 204, and the photoresist 206 is used to define the positions where trenches are formed. Next, after the pad oxide layer 202a and the silicon nitride layer 204 are formed, a patterned photoresist layer 206 is formed on the substrate 200 by using a conventional lithography mask and an etching process, and then patterned. The photoresist layer 206 etches the underlying gasification layer 204. As shown in FIG. 2b, after the photoresist layer 206 is stripped, the silicon oxide layer 204 after the last name is used as an etching mask, and the pad oxide layer 202a and the substrate 200 are etched downward, and the substrate 200 4 is formed into a shape. Ditch 208. Wherein, different formulas in this step can obtain trenches 208 with different depths. The trenches 208 of different depths will cause different threshold voltages to form adjacent doped regions below. The relationship among them will be described in more detail below. Page 9 This paper size applies to Chinese National Standards (CNS > A4 Specifications < 21〇χ 2g7mm --- I -------W Pack ·! ----- Order * ----- I ! 嫂 '^ (Please read the notes on the back before filling this page) 4443.5 (Amendment Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () As shown in Figure 2c, using thermal oxidation method A gated layer 202b is formed on the bottom and sidewall surfaces of these trenches 208, and a photoresist layer 201 is formed in the trench. After that, as shown in Figure 2 (1), the substrate 200 is first removed. The top silicon nitride layer 204. Among them, the silicon nitride layer 204 was removed with a Ji: iP04 solution at a temperature of about 150 to 200 ° C and after removing the vaporized silicon layer 204 ' Ion implantation method is used to form multiple doped regions. Because of the residual photoresist layer inside the trenches 208, conductive ions are implanted in the substrate 200 between the trenches 208 to form a plurality of doped regions. 210; wherein the plurality of doped regions 2IQ are located under the oxide layer 202b. Among them, the implanted ions can be 51 Ions or phosphorus ions; and the energy of arsenic ion implantation (that is, the acceleration energy of ions at the time of implantation) is between 40 and 10 OKeV, so that the thickness of the hafnium oxide layer 2 0 2a is about 15 0 0 to The doped region 210 is about 300 angstroms; in addition, if the implanted ions are phosphorus ions, the implantation energy is about 30 to 80 KeV; and the concentration of the ions is about 5 × 10 to 5 × 10. Between i5, "the remaining photoresist layer 20 in the trench is removed, and a chemical vapor deposition (CCVD) method is used to form a multicrystalline fragment 212 or #heteroconductive ion on the surface of the substrate 200. Compound crystal wheat. Taking a preferred embodiment as an example, LPVCD is deposited by simultaneous doping at a temperature of 450-6 50, and a doping concentration of about 5 and 1019 to 5; £ 1021 / ^ 1] 13 of 11 Conductive ions' The complex crystal layer 212 can be mined. It can be used as a definition word line (β) as shown in Section 2e®: After the above steps are completed, The paper size of this page is applicable to a 0 family standards (CNS > A4 rules / grid / 210 * 297 mm) (Please read the precautions on the back before filling this page) Installation • n 1 _ line
X 444_ 444_ Α7 Β7 修正( 五、發明說明（） 之表面上形成一遮革214用以復蓋部分溝渠2〇8α其目的 即是使得在下面的離子佈植令’只讓部分溝渠2〇8的底部 被施以離子佈植，以降低部分區域的臨界電壓。亦即，本 遮革214的目的即是用以定義本發明之溝渠構造之罩幕式 唯讀記憶娌的程式編碼（cod i ng )。利用此遮單2丨4復蓋 在複晶梦層212的上方’然後植入^導電型離子；植入之 離子如神離子或填離子必須有足夠的錐子及動能才能穿 透複晶矽層212在機材200中形成離子植入區。其中，砰 離子植入的能量約在150至IOOOKeV之間，若使用峨離子 其植入能量則在90至lOOOKeV ;它們的濃度範圍則在 5x1 0H至5x10ls之問·此植入離子步驟的條件與複晶矽層 •a 212的厚度以及位元線的阻值有關·»最後，移去該定義程 式編碼之遮罩214，則本發明之溝渠構造之罩幕式唯讀記 憶體即形成。 參照第3圖，本發明之溝渠構造之罩幕式唯讀記憶體 包含一些邏輯低準位302和一些邏輯高準位304的區域。 並且，這些邏輯低準位302對應的區域為具有較低臨界電 壓的區域·相反的，其中之逢輯高準位304則對應至具 有較高臨界電壓的區域。而兩相鄰之堆堊構造間的臨界 電壓與溝渠的深度以及溝渠的.導電性有關：當位於兩堆 晏之間的溝渠深度增办/時，則兩堆要之間的臨界電壓跟 著升高；而位於兩堆要之間的溝渠若植入與堆壘導電性 相同的摻雜物，則將會降低兩堆要之問的臨界電壓；如 -^第11頁 _ 本紙張尺度適用中a a家楳準（CNS)A4规格（210 X 297公釐〉 (請先閱讀背面之注意事項再填寫本頁) ••裝 l·---訂*-------綠 經濟部智慧財產局員工消费合作社印製 年 nr 斗 44 3-5 修正 補充 A7 B7 五、發明說明（ 第3囷之3 0 2區域《當然，高臨界電壓的區域對應至關 (〇 F F )的狀態；而低臨界電壓的區域則對應至開（Ο N ) 的狀態。因此，本發明之溝渠構造的罩幕式唯讀記愧體 即可因此建構完成。邏輯低準位302相當於一個具有低 臨界電壓為VI的元件，即是開（ON)的狀態；而邏輯 高準位304則相當於一個具有高臨界電壓為Vh，即是關 (off )的狀態》而其中本罩幕式唯讀記憶體具有位元 線（bit line) 306，以及字語線（word 丨ine) 308a 本發明之另一實施例，如第4a圖至第4f囷為其製 程的示意圖：其中與上述之實施例最大的不同處在於， 本貧施例的蝕刻複數個溝渠構造的步驊和在各個溝渠之 間之基材的上之墊氧化層之下部植入π導電型離子的步 驟作對調；此兩實施例最後可以得相同的溝渠構造之罩 幕式唯讀記憶體。 如第4a ®所示：一基材40 0用於本發明之溝渠構造 之革幕式唯讀記憶體的製程》如上述之實施例一樣此基材 400可以是具有輕微摻雜之p導電型摻雜物。且本基材400 並且預先形成_墊氧化層404a在其上方，而此墊氧化層 404a之形成方式，及其厚度與上述實施例相同.接著，利 用離子佈植的方式植入n導電型離子，如砷離子或磷離 子，由於離子的物理作用，會在墊氧化層404a的下方形 成一離子佈植層402。離子佈植層40 2的厚度由砷離子的 第12頁 良紙張尺度適用中a國:家禰準（CNS)A4规格（210 X 297公« > (請先閱績背面之注意事項再填窝本頁) -1 * ---I----訂.！-- 經濟部智慧財產局貝工消费合作社印製 4443 5 y-/y 經濟部智慧財產局貝工消费合作社印製 修正 A7 B7 五、明() 加速動能約在40至100£eV間的離子轟擊形成厚度約丨5〇〇 至3000埃之間的薄層，或以磷離子以動能約30至8〇KeV 之間的能量來植入亦可。 接著，如第4b圖所示：在墊氧化層40 4a上方形成一 氮化矽層 406，用以在下面的蝕刻步驟中保護墊氣化層 404a β其次，如第4c圖所示：接著，如第2b圈所示·在 墊氧化層404a和氮化矽層406形成之後，利用傳統的微 彩革幕和飪刻製程在此基材400之上形成圖案化的光阻層 408，再利用此圖案化光阻層.408蝕刻底層之氮化矽層 406。剝除光阻層4(34之後，以蝕刻後之氮化矽層40^作 為蝕刻覃幕而往下蝕刻墊氧化層404a及基材400，在基材 400中形成溝渠410。 接著，如第4d®所示：f先，在溝渠410内之底部 和側邊的表面上形成一閘氧化層404b。故在各個溝渠410 之間之基材40Q的上表面之墊氧化層404a下方保留有複 數個具有η導電性摻雜物的區域402。 然後，如第4e圖所示：在閘氧化層404b和墊氧化層 4 0 4a上形成一複晶矽層412，並圈案化以當成字語線β其 形成方式可以利用LPCVD ;亦可在沈積的過程中同步加入 η導電性離子摻雜物，以增加其導電性。 第13頁 本紙張尺度適用ψ a a家棵爷（cns>a4規格moχ 297公* > * - _丨·' (請先閱讀背面之注意事項再填寫本頁) W裝 l·---訂---------線 \ 绥濟部智慧財產局員工消費合作社印製 五、發明說明（） 最後，如第4f圖所示：在上述步驟完成之後，在此 基材100之表面上形成一遮革414用以復蓋部分溝渠。其 目的即是使得在下面的離子佈植_ 410,只讓部分溝渠410 的底部被施以離子佈植，以降低部分區域的臨界電壓。亦 即，本遮幕414的目的即是用以定義本發明之溝渠構造之 革幕式嘴讀記憶艘的程式编瑪（c〇ding)*利用此遮罩414 復蓋在複晶矽層412的上方，然後植入n導·電型離子；植 入之離子如砷離子或磷離子必須有足夠的離子及動能才 能穿透複晶έ夕層412在機材400 _形成離子植入區。其 中，砷離子植入的能量約在150至lOOOKeV之間，若使用 磷離子其植入能量則在90至lOOOKeV;它們的濃度範面則 在5xl014至5xl0u之間•此植入離子步驟的條件與複晶矽 層4丨2的厚度以及位元線的阻值有關。最後，移去該定義 程式编碼之遮罩414，則本發明之溝渠構造之罩幕式唯讀 記憶體即形成* 此外，本發明並非僅限於在p導電性的基材中植入η 導電性離子；相反的，本發明亦可利用在η導電性的基材 中植入ρ導電性的離子來形成罩幕式唯讀記憶體。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範面；凡其它未脫離本發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請專利 範圍内。 本紙張尺度適用令困國家棵準（CNS)A4规格<21〇 χ 297公釐） ----— ml---.wjgl^ . I ! I — I 訂---------.#v (靖先閱讀背面之注意事項再填寫本頁} 炉年（月π |lf'· Ίχ~補充 Α7 Β7 五、發明說明（） 經濟部智慧財產局員工消f合作社印製 圖式 標 號 說 明： 104 光 阻 層 106 場 氧 化 層 103 隔 雄 區 域 110 閘 及 氧 化 層 1 12 複 晶 矽 層 1 14 光 阻 層 116 摻 雜 區 域 1 1 8 無 摻 雜 區 域 200 基 材 202a 墊 氧 化 層 202b 墊 氧 化 層 204 氮 化 矽 層 206 光 阻 層 203 溝 渠 210 摻 雜 區 域 212 複 晶 矽 層 302 邏輯 準位 304 邏輯 低 準 位 306 位 元 線 308 宇 語 線 400 基 材 402 離 子 佈 植 層 404a 墊 氧 化 層 404b 墊 氧 化 層 406 氮 化 矽 層 408 光 阻 層 4 10 溝 渠 412 複 晶 矽 層 414 遮 革 201 光 阻 層 (請先閱讀背面之注意事項再填寫本頁) -------訂--------綠 筑1馆 本紙張尺度適用中困國家標準（CNS>A4規格（210 X 297公* )X 444_ 444_ Α7 Β7 Correction (V. Description of the invention) A cover leather 214 is formed on the surface to cover part of the trenches 208α. The purpose is to make the following ion implantation order 'let only part of the trenches 208 The bottom of the substrate is implanted with ions to reduce the critical voltage in some areas. That is, the purpose of this cover 214 is to program code (cod i ng). Use this cover sheet 2 丨 4 to cover the compound crystal layer 212 'and implant ^ conductive ions; implanted ions such as god ions or filled ions must have sufficient awl and kinetic energy to penetrate the compound The crystalline silicon layer 212 forms an ion implantation region in the machine 200. Among them, the energy of the implantation of the ping ion is between 150 and 100 OKeV, and the implantation energy of the ion implantation is 90 to 100 OKeV; their concentration range is between 5x1 0H to 5x10ls · The conditions for this ion implantation step are related to the thickness of the polycrystalline silicon layer · a 212 and the resistance of the bit line · »Finally, the mask 214 encoded by the definition program is removed, and the present invention The veil of the trench structure is read-only memory With reference to FIG. 3, the veil-type read-only memory of the trench structure of the present invention includes some areas of the logic low level 302 and some areas of the logic high level 304. In addition, the areas corresponding to these logic low levels 302 have relatively high levels. Regions with low critical voltages. Conversely, the high level 304 corresponds to regions with higher critical voltages. The critical voltage between two adjacent chalk structures and the depth of the trench and the conductivity of the trench. Relevant: When the trench depth between the two stacks is increased, the critical voltage between the two stacks increases; and if the trench between the two stacks is implanted with the same conductivity as the stack barrier, Debris, it will reduce the critical voltage of the two piles; eg-^ 第 11 页 _ This paper size is applicable to the aa home standard (CNS) A4 specification (210 X 297 mm) (Please read the back Please fill in this page again for the matters needing attention) •• Install l · --- Order * ------- Printed by the Intellectual Property Bureau of the Ministry of Green Economy Employee Consumer Cooperative Year nr Dou 44 3-5 Amend and supplement A7 B7 V. Description of the invention (Section 3 of No. 3 0 2 "Of course, the region of high threshold voltage corresponds to (〇FF) state; and the region of low critical voltage corresponds to the state of ON (0 N). Therefore, the mask type of the trench structure of the present invention can be constructed only by reading the shame body. The logic low level 302 is equivalent to a component with a low threshold voltage of VI, which is the ON state; and a logic high level 304 is equivalent to a state with a high threshold voltage of Vh, which is the off state. This mask-type read-only memory has a bit line 306 and a word line 308a. Another embodiment of the present invention, as shown in FIG. 4a to FIG. 4f, is a schematic diagram of its process: The biggest difference from the above-mentioned embodiment lies in the steps of etching a plurality of trench structures and the step of implanting π-conducting ions in the lower portion of the pad oxide layer on the substrate between the trenches in the lean embodiment. The two embodiments can finally obtain the mask-type read-only memory of the same trench structure. As shown in Section 4a ®: A substrate 400 is used in the manufacturing process of the leather curtain read-only memory of the trench structure of the present invention. As in the above embodiment, the substrate 400 may be a p-conductive type with slight doping. Dopant. And the substrate 400 has a pad oxide layer 404a formed thereon in advance, and the formation method and thickness of the pad oxide layer 404a are the same as those in the above embodiment. Next, an n-conducting ion is implanted by ion implantation. Due to the physical action of ions, such as arsenic ions or phosphorus ions, an ion implantation layer 402 is formed under the pad oxide layer 404a. The thickness of the ion implant layer 40 2 is based on arsenic ions on page 12. Good paper size Applicable in country A: Furniture Standard (CNS) A4 (210 X 297) «> (Please read the notes on the back of the results before filling (This page) -1 * --- I ---- Order.!-Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4443 5 y- / y Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Amendment A7 B7 V. Ming () Accelerated kinetic bombardment of ions between 40 and 100 £ eV to form a thin layer with a thickness of about 500 to 3000 angstroms, or phosphorus ions with a kinetic energy of about 30 to 80 KeV. Energy can also be implanted. Next, as shown in FIG. 4b: a silicon nitride layer 406 is formed over the pad oxide layer 40 4a to protect the pad gasification layer 404a β in the next etching step, as shown in FIG. Figure 4c: Next, as shown in circle 2b, after the pad oxide layer 404a and the silicon nitride layer 406 are formed, a patterned pattern is formed on the substrate 400 by using a conventional micro-colored leather curtain and cooking process. Photoresist layer 408, and then use this patterned photoresist layer. 408 to etch the underlying silicon nitride layer 406. After stripping the photoresist layer 4 (34, use the etched silicon nitride layer 40 ^) To etch the screen, the pad oxide layer 404a and the substrate 400 are etched down to form a trench 410 in the substrate 400. Next, as shown in 4d®: f, first, on the bottom and side surfaces in the trench 410 A gate oxide layer 404b is formed. Therefore, a plurality of regions 402 having n conductive dopants remain under the pad oxide layer 404a on the upper surface of the substrate 40Q between each trench 410. Then, as shown in FIG. 4e : Form a polycrystalline silicon layer 412 on the gate oxide layer 404b and the pad oxide layer 4 0 4a, and circle it as a word line β. The formation method can use LPCVD; η conductivity can also be added simultaneously during the deposition process Ionic dopants to increase its conductivity. Page 13 This paper size applies to ψ aa family tree master (cns > a4 size moχ 297 male * > *-_ 丨 · '(Please read the precautions on the back first) (Fill in this page) W installed l ------ Order --------- line \ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Suiji V. Invention Description () Finally, as shown in Figure 4f: After the above steps are completed, a covering leather 414 is formed on the surface of the substrate 100 to cover part of the trench. The purpose is Is to make the ion implantation _ 410 below, so that only the bottom of part of the trench 410 is implanted with ion implantation to reduce the critical voltage in some areas. That is, the purpose of this mask 414 is to define the invention Coding of the ditch structure with a leather curtain mouth reading memory vessel * Using this mask 414 to cover over the polycrystalline silicon layer 412, and then implanting n-conductance and electric ions; implanted ions For example, arsenic ions or phosphorus ions must have sufficient ions and kinetic energy to penetrate the polycrystalline layer 412 to form an ion implantation region in the machine 400. Among them, the energy of arsenic ion implantation is between 150 and 100OKeV, and if phosphorus ions are used, the implantation energy is between 90 and 100OKeV; their concentration range is between 5xl014 and 5xl0u. Conditions of this implantation ion step It is related to the thickness of the polycrystalline silicon layer 4 and 2 and the resistance of the bit line. Finally, removing the mask 414 that defines the program code, the mask-type read-only memory of the trench structure of the present invention is formed. * Furthermore, the present invention is not limited to implanting n-conductivity in a p-conductive substrate. Conversely, the present invention can also use a p-conductive ions implanted in the η-conductive substrate to form a mask-type read-only memory. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included below Within the scope of the patent application. The size of this paper is applicable to the A4 specification of CNS (<21〇χ 297 mm) ----— ml ---. Wjgl ^. I! I — I order -------- -. # v (Jing first read the precautions on the back before filling out this page) Year of the furnace (month π | lf '· Ίχ ~ Supplement A7 Β7 V. Description of the invention () Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed cooperative drawings DESCRIPTION OF SYMBOLS: 104 photoresist layer 106 field oxide layer 103 gate region 110 gate and oxide layer 1 12 polycrystalline silicon layer 1 14 photoresist layer 116 doped region 1 1 8 undoped region 200 substrate 202a pad oxide layer 202b Pad oxide layer 204 silicon nitride layer 206 photoresist layer 203 trench 210 doped region 212 polycrystalline silicon layer 302 logic level 304 logic low level 306 bit line 308 Yuyu line 400 substrate 402 ion implantation layer 404a pad Oxide layer 404b, pad oxide layer 406, silicon nitride layer 408, photoresist layer 4 10 trench 412, polycrystalline silicon layer 414, cover 201, photoresist layer (please read the precautions on the back before filling this page) ------- Order -------- Green Hall 1 in the present paper trapped scale applicable national standards (CNS > A4 size (210 X 297 well *)