經濟部智慧財產局員工消費合作社印製 4.4 1 0 3 4 A 4 ^93〇v^d^/〇〇6 A7 B7 五、發明說明（/) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種咼品質因子(high quality factor)電感的製造方 法。 在積體電路中，電感是一種重要的元件，一般爲圓形 或方形的螺旋狀金屬線圈，應用十分廣。對高頻應用領域 來說，是十分需要局品質因子(亦即高Q値)電感的。例如 在無線通訊的應用上，要求電感元件之Q値要高達60左 右。上述Q値的定義如下： Q = 〇)0L/R (1) 其中ω。爲電感之共振角頻率（resonant angular frequency)，R爲電感之電阻，而L爲金屬線圈之電感値。 由第（1)式可知，在L固定下，Q値會隨著共振角頻率 的增加與/或電阻下降而提升。其中電阻又和電流密度的平 方成正比，所以要提升Q値的方法之一爲增加金屬線圈之 截面積來降低金屬線圈電流密度，以此方式來降低金屬線 圈的電阻，達成提升Q値的目的。 在半導體積體電路製程中最關鍵的步驟爲微影製程， 微影製程包括塗佈光阻、曝光與顯影等步驟。受限於特定 光源波長之聚焦深度的影響，在基底上所塗佈之光阻厚度 不能無限制增加。光阻厚度受到限制，則利用光阻爲蝕刻 罩幕時1其所能承受的蝕刻時間有限，因此位於其下之材 料層的厚度也跟著受到了限制。 3 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裳i丨丨！丨丨訂i -----線 經濟部智慧財產局貝工消費合作社印製 3 s .: ^ 5p9^w^doc/006 五、發明說明（2 ) 如上所述，因此在半導體製程中若要以增加金屬導線 截面積來製造高Q値電感，因金屬層之厚度受到限制’只 能以加粗金屬導線寬度的方式來完成。但是若金屬導線的 寬度太大時，又會因爲電荷傾向集中分佈於金屬導線之轉 角處，而使得金屬導線所增加的截面積無法達成降低金屬 導線電流密度的效果，也就無法提升由金屬導線所組成之 電感元件的Q値。所以一般以半導體製程所能製造出之電 感，其Q値最多只能到10左右。 有些解決方法爲將上下兩層之金屬導線之間以金屬插 塞陣列來連接之，企圖以如此的方式來形成一等效之具有 大截面積的金屬導線，再以此等效之大截面積的金屬導線 來形成電感元件。此解決方式之問題爲用來連接上下兩層 金屬導線之金屬插塞，爲了考慮沈積時之溝塡(gap fiU)能 力，其材質多爲金屬鎢，和上下兩層金屬導線的材質根本 不同，且金屬鎢的電阻也較高，所以整體電感兀件之Q値 的提升程度將十分有限。即使金屬插塞的材質和上T兩層 金屬導線的材質相同，其和大截面積金屬導線之間的等效 性也是有待商確的。 有鑑於此，本發明提烘一種高品質因子電感的製造方 法，包括提供一基底，此基底上已形成有若千元件’且此 基底與元件之上形成有平坦化之介電層。接下來’形成^ 案化之金屬導線層於介電層上。再形成平坦化之絕，緣層於 基底上，圖案化最上層之絕緣層，以暴露出最上層之部分 金屬導線層。然後形成圖案化之另一金屬導線層於基底 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐〉 ---1---------^--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 4 41 〇84 ^ ^ ^8〇}§vf§〇c/006 經濟部智慧財產局員工消費合作社印製 五、發明說明（i) 上，覆蓋在部分之前金屬導線層之上。 然後可依所需’重複上述形成平坦化之絕緣層於基底 上'圖案化最上層之絕緣層、形成圖案化之另一金屬導線 層於基底上以覆盖在則金屬導線層上等之步驟數次，以_ 得所需厚度之金屬導線層。金屬導線的材質例如可爲銘金 屬或銅金屬，絕緣層的材料例如可爲氧化砂或可流動氧化 物（Floatable Oxide ; FOX)。 因此應用本發明具有可依不同應用上之需求，製造出 所需厚度之金屬導線’以達成該應用所要求之高Q値電感 元件的優點。而且整個金屬導線皆爲相同之低電阻材質， 可以更容易製造出高Q値之電感元件。而且本發明所用之 技術都是成熟的技術，也不需要用到特別材料，所以應用 起來十分經濟有效。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A至1D圖是依照本發明一較佳實施例之一種高品 質因子電感的製造流程剖面圖。 圖式之標記說明： 10(P基底 110 :介電層 120、125、150 :金屬導線層 130、130a :絕緣層 5 (請先閱讀背面之注$項再填寫本頁) 裝 ----1 I I 訂---11 I I-- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） 4 4 10 8 4 4 4· oc/006 A7 B7 經濟部智慧財產局貝工消費合作社印製 五、發明說明（¥ ) 14Q :開口 實施例 請參照第1A至1D圖，其係依照本發明一較佳實施例 之一種高品質因子電感的製造流程剖面圖。 請參照第1A圖，先提供基底100，基底1〇〇上已形成 有若干元件(圖上未示出）。接著形成平坦化之介電層110， 其材質例如可爲氧化矽，其形成方法例如可爲化學氣相沈 積法。 然後形成圖案化之金屬導線層120,其材質例如可爲 金屬鋁或金屬銅。而金屬導線層120的形成方法例如可先 用物理氣相沈積法或電鍍法形成一層金屬鋁或金屬銅之 後，再利用一般所熟知之微影蝕刻製程來完成之。 請參照第1B圖，在基底100上形成平坦化之絕緣層 130。絕緣層130的厚度只比金屬導線層120的厚度要稍微 大一些，例如金屬導線層120的厚度爲2微米時，絕緣層 130的厚度可以比金屬導線層120的厚度多0.1至0.2微米 左右。 絕緣層130的材質例如可爲氧化矽、可流動氧化物或 其他低介電係數材料。絕緣層130的形成方法，例如可先 利用化學氣相沈積法沈積一層氧化矽層於基底丨〇〇上，再 利用化學機械硏磨法將其平坦之。或者至少先利用旋塗法 (spin-coating)將溶解在溶劑中之介電材料起始物塗佈在基 底100上，再利用烘烤、固化步驟將多餘的溶劑蒸發掉， 並使介電材料起始物進行分子間鍵結反應’形成所需之介 6 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Α7 Β7 ' .Π 03 Λ dt)c/006 五、發明說明（ί) 電材料。 請參照第1C圖，對絕緣層130進行例如微影蝕刻步 驟，使其成爲圖案化之絕緣層130a，並於其中形成開口 140 暴露出金屬導線層120的表面。 請參照第1D圖，再沈積一層金屬層於基底上’ 然後例如利用微影蝕刻製程將金屬層圖案化’形成另一層 的金屬導線層125，覆蓋在前一層的金屬導線層120上。 如此金屬導線120與125,即合倂成厚度爲原來兩倍之金 屬導線150。 如此再重複上述第圖至第1D圖之步驟若干次’即 可依不同應用之需求來獲得不同Q値的電感。而且其中在 上述第1D圖的步驟中，金屬導線層125不一定要覆蓋在 所有的金屬導線層120上，可以依照實際需求’只覆蓋在 部分的金屬導線層120上’則在基底上之不同區域可以獲 得不同厚度之金屬導線，以滿足不同應用之需求。 另外一般要用來做電感之金屬導線其寬度都比較大， 以使其Q値較高，例如約數微米左右。而上下兩層金屬導 線要對準時，以目前的微影技術已經可以精準到〇·ΐ微米 以下，所以上下兩層金屬導線可以說是完全對準的。 由上述本發明較佳實施例可知，應用本發明具有可依 不同應用上之需求’製造出所需厚度之金屬導線’以達成 該應用所要求之高Q値電感元件的優點。而且整個金屬導 線皆舄相同之低電阻材質’可以更容易製造出高Q値之電 感元件。而且本發明所用之技術都是成熟的技術，也不需 . I--------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局具Η消費合作社印製 本紙張尺度適用中圈國家標準（CNS)A4規格（210 X 297公釐） 4 4108 4 ^ ^ 3s8twf.^〇c/006 A7 B7 五、發明說明（4 ) 要用到特別材料，所以應用起來十分經濟有效。 ^然本發明已以一較佳實施例揭露如上’然其並非用 以限^本發日月’任㈣習此技藝者，在不麵本發明之精 神和，當口7作各種之更動與潤飾’因此本發明之保 護_画視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------線 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4.4 1 0 3 4 A 4 ^ 93〇v ^ d ^ / 〇〇6 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a semiconductor device, and In particular, it relates to a method for manufacturing a high quality factor inductor. In integrated circuits, inductance is an important component. Generally, it is a circular or square spiral metal coil, which is widely used. For high frequency applications, local quality factor (ie high Q 値) inductors are highly needed. For example, in the application of wireless communication, the Q of the inductive element is required to be as high as about 60. The above Q 値 is defined as follows: Q = 0) 0L / R (1) where ω. Is the resonant angular frequency of the inductor, R is the resistance of the inductor, and L is the inductance of the metal coil. From equation (1), it can be known that under the fixed L, Q 値 will increase as the resonance angular frequency increases and / or the resistance decreases. The resistance is directly proportional to the square of the current density, so one of the ways to improve Q 値 is to increase the cross-sectional area of the metal coil to reduce the current density of the metal coil. In this way, the resistance of the metal coil is reduced to achieve the goal of increasing Q 値. . The most critical step in the semiconductor integrated circuit manufacturing process is the lithography process. The lithography process includes steps such as coating photoresist, exposure, and development. Affected by the depth of focus of a specific light source wavelength, the thickness of the photoresist applied on the substrate cannot be increased indefinitely. The thickness of the photoresist is limited, so when using the photoresist to etch the mask, 1 the etching time that it can withstand is limited, so the thickness of the material layer below it is also limited. 3 This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page).丨 丨 Order i ----- Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 s .: ^ 5p9 ^ w ^ doc / 006 V. Description of the Invention (2) As mentioned above, if the semiconductor process To increase the cross-sectional area of a metal wire to make a high Q 値 inductor, the thickness of the metal layer is limited, and it can only be done by thickening the width of the metal wire. However, if the width of the metal wire is too large, the charge tends to be concentrated at the corners of the metal wire, so that the increased cross-sectional area of the metal wire cannot achieve the effect of reducing the current density of the metal wire, nor can it improve the metal wire. The Q 値 of the composed inductive element. Therefore, the Q 値 of an inductor which can be manufactured by a semiconductor process is generally only about 10 at most. Some solutions are to connect the metal wires of the upper and lower layers with a metal plug array, in an attempt to form an equivalent metal wire with a large cross-sectional area in this way, and then use this equivalent to a large cross-sectional area. Metal wires to form an inductive element. The problem with this solution is the metal plug used to connect the upper and lower layers of metal wires. In order to consider the gap fiU ability during deposition, the material is mostly metal tungsten, which is fundamentally different from the material of the upper and lower layers of metal wires. And the resistance of metal tungsten is also high, so the improvement of Q 値 of the overall inductor element will be very limited. Even if the material of the metal plug is the same as that of the upper T metal wires, the equivalence between the metal plug and the large cross-section metal wire remains to be determined. In view of this, the present invention provides a method for manufacturing a high-quality factor inductor, which includes providing a substrate on which there are thousands of elements' and a planarized dielectric layer is formed on the substrate and the elements. Next, a patterned metal wire layer is formed on the dielectric layer. A planarization layer is then formed, and the edge layer is on the substrate, and the uppermost insulating layer is patterned to expose the uppermost metal wire layer. Then form another patterned metal wire layer on the substrate. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) --- 1 --------- ^ ---- ---- Order --------- line (please read the notes on the back before filling this page) 4 41 〇84 ^ ^ ^ 8〇} §vf§〇c / 006 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative V. Description of the invention (i), covering part of the previous metal wire layer. Then you can repeat the formation of a flattened insulating layer on the substrate as needed to pattern the topmost insulating layer, The step of forming a patterned another metal wire layer on the substrate to cover the metal wire layer is performed several times to obtain a metal wire layer of a desired thickness. The material of the metal wire may be, for example, a metal or a copper metal. The material of the insulating layer may be, for example, oxidized sand or flowable oxide (FOX). Therefore, the application of the present invention has the capability of manufacturing metal wires of a desired thickness according to the requirements of different applications to achieve the requirements of the application. Advantages of high Q 値 inductive components. And the entire metal wire has the same low resistance Material, it is easier to manufacture high Q 値 inductive elements. Moreover, the technology used in the present invention is mature technology and does not require special materials, so it is very economical and effective to apply. In order to make the above and other purposes of the present invention , Features, and advantages can be more clearly understood, a preferred embodiment is given below, in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: Figures 1A to 1D are a preferred embodiment according to the present invention. A cross-sectional view of the manufacturing process of a high-quality factor inductor according to the embodiment. Marking description of the drawing: 10 (P substrate 110: dielectric layer 120, 125, 150: metal wire layer 130, 130a: insulating layer 5 (please read the back first) (Note the $ items, then fill out this page) Packing ---- 1 Order II --- 11 I I-- This paper size applies to China National Standard (CNS) A4 (210 χ 297 mm) 4 4 10 8 4 4 4. · oc / 006 A7 B7 Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (¥) 14Q: For opening examples, please refer to Figures 1A to 1D, which is one of the preferred embodiments according to the present invention. A cross-sectional view of the manufacturing process for high quality factor inductors. Referring to FIG. 1A, a substrate 100 is first provided, and a number of elements (not shown in the figure) have been formed on the substrate 100. Then, a planarized dielectric layer 110 is formed. The material may be, for example, silicon oxide. It can be a chemical vapor deposition method. Then, a patterned metal wire layer 120 is formed, and the material thereof can be, for example, metal aluminum or metal copper. The method for forming the metal wire layer 120 can be formed by physical vapor deposition or electroplating, for example. After a layer of metal aluminum or metal copper, it is completed by a commonly known lithography etching process. Referring to FIG. 1B, a planarized insulating layer 130 is formed on the substrate 100. The thickness of the insulating layer 130 is only slightly larger than the thickness of the metal wire layer 120. For example, when the thickness of the metal wire layer 120 is 2 micrometers, the thickness of the insulating layer 130 may be about 0.1 to 0.2 micrometers greater than the thickness of the metal wire layer 120. The material of the insulating layer 130 may be, for example, silicon oxide, flowable oxide, or other low-dielectric-constant material. For the method of forming the insulating layer 130, for example, a silicon oxide layer is deposited on the substrate by a chemical vapor deposition method, and then planarized by a chemical mechanical honing method. Or at least firstly spin-coating the dielectric material starting material dissolved in the solvent on the substrate 100, and then use the baking and curing steps to evaporate the excess solvent and make the dielectric material The media needed for the formation of the intermolecular bonding reaction of the starting materials 6 (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Α7 Β7 '.Π 03 Λ dt) c / 006 V. Description of the Invention (ί) Electrical materials. Referring to FIG. 1C, the insulating layer 130 is subjected to, for example, a photolithography etching step to be a patterned insulating layer 130a, and an opening 140 is formed in the insulating layer 130 to expose the surface of the metal wire layer 120. Referring to FIG. 1D, another metal layer is deposited on the substrate ', and then the metal layer is patterned using a photolithographic etching process to form another metal wire layer 125 covering the previous metal wire layer 120. In this way, the metal wires 120 and 125 are combined into a metal wire 150 having a thickness that is twice the original thickness. In this way, the steps of the above diagrams to 1D are repeated several times' to obtain different Q 値 inductances according to the requirements of different applications. Moreover, in the step of the above-mentioned FIG. 1D, the metal wire layer 125 does not necessarily cover all the metal wire layers 120, and according to the actual requirements, 'covering only part of the metal wire layers 120' is different on the substrate Areas can be obtained with different thickness metal wires to meet the needs of different applications. In addition, the width of metal wires that are generally used as inductors is relatively large to make their Q 値 higher, such as about a few microns. When the upper and lower layers of metal wires are to be aligned, the current lithography technology can already be accurate to less than 0 · ΐ microns, so the upper and lower layers of metal wires can be said to be completely aligned. As can be seen from the above-mentioned preferred embodiments of the present invention, the application of the present invention has the advantage of being able to 'make metal wires of desired thickness' according to the needs of different applications to achieve the high Q 値 inductance element required for the application. In addition, the entire metal wire is made of the same low-resistance material ’, which makes it easier to manufacture high-Q inductors. And the technology used in the present invention is mature technology, no need. I -------- Order --------- line (Please read the precautions on the back before filling this page) Economy The Ministry of Intellectual Property Bureau has printed the paper size of the consumer cooperative to apply the Central Circle National Standard (CNS) A4 specification (210 X 297 mm) 4 4108 4 ^ ^ 3s8twf. ^ 〇c / 006 A7 B7 V. Description of the invention (4 ) Special materials are used, so it is very cost-effective to apply. ^ However, the present invention has been disclosed in a preferred embodiment as described above, but it is not intended to be limited to ^ this issue of the sun and the moon. Anyone who learns this skill, but does not face the spirit of the present invention, when making changes and retouching 'Therefore, the protection of the present invention is determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Packing -------- Order --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 Standard (CNS) A4 specification (210 X 297 male