TW437051B - Electrostatic discharge protection component with silicon controlled rectifier - Google Patents

Abstract

An electrostatic discharge protection component for composite voltage application system which employs a silicon controlled rectifier as the basic bypass component; and, stacking at least two MOSFETs in cascade configuration so as to reduce the trigger voltage of protection component. The voltage between the gate to the drain, the gate to the source, or the source to the drain of each transistor will not exceed the low supply voltage so that all of the dielectric layers will not be challenged by the hot carrier reliability.

Description

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 '437U5 1

5. Description of the invention () 5-1 Field of the invention ... The present invention relates to an electrostatic discharge protection circuit for preventing the integrated circuit from being damaged by electrostatic discharge (Electrostatic Discharge), and more particularly to an application circuit for combining voltages. Electrostatic discharge protection circuit using Silicon Controlled Rectifier (SCR). 5-2 Background of the Invention: The electrostatic discharge (ESD) phenomenon often occurs when integrated circuits come into contact with the human body or mechanical devices with static charges. This phenomenon is increasingly occupied in the electronic circuit and semiconductor industries. Important position. Because the electrostatic discharge phenomenon can cause extremely high-energy radio wave pulses, general integrated circuits are easily damaged by high-energy shocks. As the development of semiconductor process technology tends to reduce the area of components to increase the integration integration of integrated circuits, the possible destructive power of electrostatic discharge phenomena on integrated circuits will become more and more serious. In order to avoid the failure of integrated circuits due to unexpected damage, the electrostatic discharge effect must be suppressed. Therefore, in addition to antistatic coating, electrostatic discharge protection circuits are also often used to protect the main circuits in integrated circuit chips. Circuit components. —General ESD protection circuit is always placed on the circuit of the protected circuit. This paper standard is suitable for home care (CNSM4 specification ⑵Q χ 297). (Please read the idea on the back before filling this page)

4370 5 1 5. Description of the invention () Pin (Pm) or I / O pad. Each electrostatic discharge protection circuit forms a bypass of the king circuit. When the terminal voltage of the protection circuit reaches the trigger voltage, a critical junction in the circuit will cause a charge breakdown (ava 〖anChe breakd0Wn) effect, the protective circuit is turned on, and a large amount of current flows to the ground potential through the bypass. When the protection circuit is triggered, it enters a negative impedance operation mode, so that the bypass current can flow through the protection circuit under a sustain voltage that is much lower than the trigger voltage, without causing high impedance. The generation of excessive thermal energy can protect the protected main circuit from being damaged by high-energy electrostatic discharge. ^ In common electrostatic discharge protection circuits, SiHcOn Comrolled Rectifier (SCR) is an important and effective protection element. The first figure shows a cross-sectional view of a typical Lateral Silicon Controlled Rectifier (LSCR). For the fabrication of a traditional lateral silicon controlled rectifier (LSCR), an N-type well region 20 is formed in the P-type substrate 10, and a heavily doped p-type conductive region 30 is formed in the N-well region 20 as an anode. In the p-type substrate, a heavily doped N-type conductive region 40 is formed as a cathode. It is also possible to selectively form heavily doped P-type and N-type contact regions 50 and 60 in the p-type substrate 10 and the N-type well region 20, respectively. In this structure, the N-type conductive region 20 is disposed between the P-type conductive regions 10 and 30. The p-type conductive region is disposed between the N-type conductive regions 20 and 40. This paper size applies to the Chinese National Standard (CNS) ^ grid (210 x 297 issued f, please read the urgent matter on the back before filling out this page). ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 43TU 5 1 A7 B7 5. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed on the invention description (when an external voltage is applied to make the anode potential-controlled rectifier (LSCR) function as 1. When the jade potential is removed, when the lateral silicon pressure is within the normal operating voltage range, because ρ: the interface 15 between the substrate 7 and the well area 20 is subjected to the reverse bias by the soil substrate 10 and π 7 and only A very small leakage current can pass through this — the code delays the interface, at this time the horizontal stone evening softening · 'cloud device (LSCR) can be regarded as the "off" state. To control the trigger voltage of the mailer At the time,…: terminal; = the charge collapse phenomenon will occur at the interface during voltage-controlled rectification, which will result in a… effect, which will make the quantity t two large, and the hole pair will eventually reach 9%. Through interface 15 and the entire lateral 5 rectifier (LSCR). When less β is connected, the J SCR can be switched In the "on" state, make the helmet + 乂 +} shape. The energy of electrostatic discharge flows in high currents' through the protective circuit under the maintenance voltage far lower than the trigger voltage to avoid the main circuit. Components are protected from damage. θ The biggest problem encountered in the application of the traditional lateral silicon controlled rectifier mentioned above is that the gas is generally around tens of volts. This is because the lateral silicon controlled rectifier must be triggered below the breakdown voltage of junction 15. . However, there are many integrated circuit structures that require electrostatic discharge protection but cannot withstand such high voltages. These circuits are often damaged below the trigger voltage mentioned above. In order to improve this situation, the development of the low-triggered stone-controlled rectifier (10w VQItage triggering LVTSCR) has effectively reduced the trigger voltage of the silicon-controlled rectifier and expanded the scope of protection. This paper size is applicable to the Chinese solid standard (CNS) Al specification (210x7 ^ · ^) I-1 * i --- 1 — — — — order ------ — Μ (read the urgent matters on the back first (Fill in this page again)! '4370 5 1 at

5. Description of the invention () Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The second figure shows a cross-sectional view of a low-triggered silicon controlled rectifier (LVTSCR). A typical low-triggered silicon-controlled rectifier retains all the components of a lateral silicon-controlled rectifier (LSCR) and its structural relationship, and adds three components to it: a heavily doped N-type conductive region 70 is formed on a p-type substrate 1 On the boundary with the N-well region 20; the gate oxide layer 80 and the gate electrode 90 are stacked on the substrate 10 at a position between N [type conductive doped regions 40 and 70 'to form N-type gold An oxygen half field effect transistor (N_type Metal_ Oxide-Semiconductor transistor; NM〇S) is 100 on the substrate; wherein the N-type conductive doped region and 70 are used as the source and ytterbium and pole β, respectively. It is learned that the low-halogen silicon-controlled rectifier (TLVTSCR) is composed of a lateral silicon-controlled rectifier and a Mi-mute field-effect transistor (NMOS). The n-type conductive doped region 40 is used as a common region. Form a coupling. In this low-triggered silicon controlled rectifier (LVTSCR) configuration, the gate 90 of the field effect transistor 100 is connected to the N-type conductive and electrically doped region 40 (source), so that the transistor 100 does not conduct under normal conditions. . When the anode-to-cathode bias voltage continues to increase, the field-effect transistor 100 will enter a charge collapse state earlier than the junction 15. The low-triggered silicon-controlled rectifier (LVTSCR) is the breakdown current of the field-effect transistor 100. Triggered and turned on. Since the breakdown voltage of the field effect transistor 100 is far lower than the breakdown voltage of the junction 15 under the advanced semiconductor technology, the trigger voltage of the silicon controlled rectifier can be effectively reduced. This paper size is applicable to + national national standard (CNS) A4 specification (2) 0 × 297 mm. Ί Jingxian read the note on the back? Please fill in this page again} -------- Order ----- 一, 4 437 U 5 1 Λ7 B7 V. Description of the invention () Although it has a lower trigger voltage, this low-triggered silicon control Rectifiers (LVTSCRs) still face the problem that they are difficult to apply to mixed voltage applications. Because in the application design of integrated circuit and computer system, 5 volts was used as the standard supply voltage to drive the system operation. Under the demands of application fields and market development, in conjunction with the advancement of electronics and semiconductor process technology, it is an inevitable trend to achieve more efficient performance with lower power consumption. Therefore, lower voltage supply standards have been cited and adopted The 3.3 volt supply voltage became the new system standard. However, the old system still exists, and the new low-voltage standard cannot be immediately adopted. The components designed and manufactured with the new low-voltage standard must often be used in conjunction with the old system. Therefore, the new and old components with different voltage standards are adopted. Sometimes it is necessary to connect the circuit. For this combined voltage circuit system, it must be guaranteed that the components designed and manufactured under the new low voltage standard will not be damaged under the old high voltage supply. "But in this case, the silicon trigger with the above low trigger Rectifier (LVTSCR), as the electrostatic discharge protection circuit of low voltage components, will make the oxide layer of the field effect transistor in the protection circuit encounter a high standard supply voltage across both sides. Since the low-triggered silicon controlled rectifier (LVTSCR) at this time is used as an electrostatic discharge protection circuit for low-voltage components, generally, the protected main circuit components are manufactured in the same process at the same time. Therefore, the specifications of the gate oxide layer are the same as those of the main circuit components, and they generally do not have the ability to withstand high standard voltages. The high standard voltage across the gate oxide layer will generate a strong electric field, which will cause thermionic effect. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back first) (Fill in this page) "" ----------- Order! -'Printed from the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-Λ

Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, "纠" 437u b 1 V. Description of the invention (: Reliability is lowered' shortens the life of the oxide layer. Therefore, in order to prevent electrostatic discharge in the group 2 = application circuit It is necessary to find a more effective electrostatic discharge protection circuit that can adapt to:-voltage mixed state. 5-3 Purpose and Summary of the Invention: In the background of the above invention, the traditional electrostatic discharge protection circuit will encounter in the combined voltage application system. The problem of reliability and reliability. The present invention therefore provides two pieces of electrostatic discharge protection suitable for combined voltage application systems, using silicon controlled rectifier (SCR) as the basic bypass element in the protection circuit, and a lateral silicon controlled rectifier ( LSCR), or silicon-controlled rectification in the suspension well area! 4ii ^ ating-well SCR) as this basic element. In addition, it can be formed using the Genshangjing area seven! ^ -Type heavily doped binding region band), and coupled to expand the limit of silicon-controlled rectifier element latch-uj); you can also use the p-type substrate to form a p-type heavy doped region , Ground it with one foot (Han Hezhi vss), to achieve a similar effect. The present invention also uses a metal-oxide half field effect transistor (MOS) to reduce the trigger voltage of the protection element. ^ Among them, at least two of them are combined in series (cascode configurgi ^ ji ^ iiu ^ L ^,窨 In this configuration, the voltage between the 閛 and the drain, the gate and the source, or the source and the drain of any transistor will not exceed the low supply voltage of 3'3 volts, so All mediator layers will not be challenged by hot carriers + reliability. This paper size applies CNS A4 size ⑵G X 297. (Please read the precautions on the back before filling this page)

Seal of Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 437U 5 1 A7 __B7_ V. Description of the invention () It can be applied to the combined voltage application system. 5-4 Schematic illustration: The preferred embodiment of the present invention will be explained in more detail in the following explanatory text t with the following figures: The first figure is a typical lateral silicon controlled rectifier (LSCR) in traditional technology A cross-sectional view of a semiconductor wafer of a low-triggered silicon controlled rectifier (LVTSCR) in a conventional technique, and a third graph of a semiconductor wafer of an electrostatic discharge protection element according to the first embodiment of the present invention. A circular cross-sectional view; FIG. 3B is a plan view of a semiconductor wafer of the ESD protection element according to the first embodiment of the present invention; FIG. 3C is an equivalent circuit diagram of the ESD protection element according to the first embodiment of the present invention; FIG. 4A is a cross-sectional view of a semiconductor wafer of an electrostatic discharge protection element according to a second embodiment of the present invention; FIG. 4B is a plan view of a semiconductor wafer of a 7C component of electrostatic discharge protection according to the second embodiment of the present invention; FIG. Is an equivalent circuit diagram of an electrostatic discharge protection element according to a second embodiment of the present invention; FIG. 5A is a semiconductor diagram of an electrostatic discharge protection element according to a third embodiment of the present invention Circular cross-section diagram; This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (谙 Read the business matters on the back before filling this page). ------ 'A7 l · 4 3 7 ϋ 5 1 _B7_ V. Description of the invention (5) Figure B is the equivalent circuit diagram of the electrostatic discharge protection element according to the third embodiment of the present invention; Figure 6A Sectional view of a semiconductor wafer of an electrostatic discharge protection element according to a fourth embodiment of the present invention; FIG. 6B is an equivalent circuit diagram of an electrostatic discharge protection element according to a fourth embodiment of the present invention; and FIG. 7A is a diagram according to the present invention Cross-sectional view of a semiconductor wafer of an electrostatic discharge protection element according to a fifth embodiment; 'FIG. 7B is a cross-sectional view of a semiconductor wafer of an electrostatic discharge protection element according to a sixth embodiment of the present invention; FIG. A cross-sectional view of a semiconductor wafer of the electrostatic discharge protection element of the seventh embodiment; and a seventh D view is a cross-sectional view of a semi-conductor wafer of the electrostatic discharge protection element according to the eighth embodiment of the present invention. (谙 Please read the note on the back before filling in this page), ---- order --------; printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs, this paper applies the national standard (CNS) ) A4 size (210 X 297 mm) Γ '4370 5 1 Α7 Β7 V. Description of the invention (5-5 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Detailed description of the invention: The present invention provides an electrostatic discharge protection element that can be applied In a combined voltage application system, the electrostatic discharge protection element of the present invention uses a Silicon Controlled Rectifier (SCR) as a basic element for forming a current bypass in a protection circuit, and an N-type metal-oxide-semiconductor field-effect transistor ( NMOS) to reduce the trigger voltage of the protection element. In addition, at least two metal-oxide half field effect transistors are stacked in series (cascod) to suit the combined voltage application system. A sectional view of the ESD protection element according to the first embodiment of the present invention is formed. This ESD protection element is formed in a p-type substrate 310-an n-type well region 320, and a heavy doping can be selectively formed. The P-type contact region 315 is formed in the P-type substrate 310, and a heavily doped N-type contact region 325 may also be formed in the N-type well region 3 20. In the N 丼 region 320, a heavily doped p is formed. The type conductive region 33 is used as an anode, and a heavily doped n-type conductive region 340 is formed in the P-type substrate 31 as a cathode. In this structure, the 'configuration of the anode 33 and the cathode 340' makes the K-type conductive region 320 It is located between the P-type conductive areas 310 and 330, and the p-type conductive area 31 is set between the N-type conductive areas 320 and 340, thereby forming a lateral silicon controlled rectifier (LSCR) structure. This paper standard applies Chinese National Standard KNSM4 Specification JlO x 297 Public Love ')' (谞 Please read the dignity matters on the back before filling this page)-^ 装 ------- · Order -------- Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives' 4370 5 1 a? B7 V. Description of the invention () On the substrate 310, at least two N-type metal-oxide-semiconductor field-effect transistors (NMOS) are connected in series (cascode configuration) Set to form a field effect transistor stack structure. Both field effect transistors 350 and 370 are set on the same active Region (activearea) and share a heavily doped N-type conductive region 360 as the source of the first field effect transistor 350 and the source of the second field effect transistor 370; The transistor 3 50 uses a heavily doped N-type conductive region 3 4 0 as a source, and the heavily doped N-type conductive region 380 is formed on the boundary between the p-type substrate and the N well region 320 as a first The drain of two field-effect transistors 37 °. The dielectric layer 352 is stacked with the conductive layer 354; the position on the substrate 310 between the N-type conductive doped regions 340 and 360 to form the gate dielectric layer and the gate electrode of the first field effect transistor 350 . The dielectric layer 372 and the conductive layer 374 are stacked on the substrate 310, and are located between the N-type conductive doped regions 360 and 380 'to form a gate dielectric layer and a gate electrode of the second field effect transistor 370. The second diagram B shows a top view of the above-mentioned electrostatic discharge protection element of the first embodiment of the present invention, in which the relationship position and reference number of each element are the same as those shown in the third diagram A. The closed dielectric layers 352 and are not shown because they are located directly below the free electrodes 354 and 374, respectively. The equivalent circuit diagram of the first embodiment is shown in the third C diagram. ^ ^ ^ The network silicon rectifier is composed of a PNP bipolar transistor 3.35 and an npn bipolar transistor 345 in a positive feedback configuration. Make up. The P-type substrate 310, the N-well region 32 and the heavily doped P-type anode 330 are respectively used as PNP bipolar transistor 11 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)- ----- *-; --- 'Install! 1 --- Order! —-^ / 1 (Please read the unintentional matter on the back before filling in this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4370 5 1 A7 ---- B7__ V. Collector of the Invention Description () ), Base, and einitter. The same 'N-well region 320, the P-type substrate 31o, and the heavily doped N-type cathode 34o serve as the chirp, base, and emitter of the NPN bipolar transistor 345, respectively. The resistor 313 is generated by the junction between the P-type substrate 31o and the heavily doped p-type contact region 315; the resistor 323 is formed by the N 丼 region 32o and

The interface between the heavily doped N-type contact regions 325 is created. Two N-type metal-oxide-semiconductor field-effect transistors (NM0S) 35 and 37 are set in a cascade configuration, so that the source of the _field Ling crystal mo is reduced to .NPN double The emitter of the carrier transistor 345; the non-pole of the second field-effect transistor 370 is coupled to the base of the PNP bipolar transistor 335 320 = the structure of the first embodiment of the present invention is arranged in an integrated circuit When used as an electrostatic discharge protection element, this protection circuit can be ballasted to the main circuit in the following manner. In the protection circuit, the emitter 330 of the 'PNP bipolar transistor 335 and the N-well contact area 325 serve as anodes, and are connected to the input / output port 399 of the main circuit. The P-type substrate contact area 315 and the N-type common area of the lateral transmitter-control rectifier and transistor stacked structure; 340 is used as the p-pole 'and grounded. The gate 354 of the first field effect crystal ceremony 350 is simultaneously grounded. The gate 374 of the second field-effect transistor 370 can be directly coupled to the low-voltage panel supply terminal Vdd, or coupled to the low-voltage supply terminal Vdd via a network of a series of transistors. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the unintentional matter on the back before filling this page) ---,-437051 A7 B7 V. Description of the invention (Electrical protection ^ The static electricity shown in Figures A, B, and C of the present invention is used to protect the electrostatic discharge phenomenon. The main emperor road 9 is effective, and can still meet the dielectric requirements under high standard supply voltage 'will not be damaged by the hot carrier effect. Under static electricity ...', when the anode is seeded with the electrostatic discharge voltage of the cathode When the trigger voltage is reached, the transistor stacking structure enters the effect of the double-carrier transistor at the 38th-370th of the drain electrode 370, and the source of the field-effect transistor 350 becomes dual-load. The "electron transistor": the effective pole of the ... becomes the collector, a breakdown current at = this one will trigger the lateral silicon controlled rectifier (lscr) structure, so that: to the wonderful control rectifier to form a bypass Circuit, the electrostatic discharge effect; the same energy generated in the form of current is guided by this bypass to the ground potential. The king circuit that is loaded with f can be protected from the high-energy current generated by the electrostatic discharge effect. As for the collapse of the anode structure, the breakdown voltage and the trigger voltage of the entire electrostatic discharge protection element can be changed by changing the electricity. The length of the total channel of the crystal stack structure is adjusted. (Jing first read the notes on the back before filling in this page) n ϋ 1 ϋ t— n tr --------, o 'Employees of Zhiming Property Bureau, Ministry of Economic Affairs The effect printed by the consumer cooperative τ 'When a high standard H voltage of about 5 volts appears between the anode and the cathode of the electrostatic discharge protection element, the second field-effect transistor will be slightly less than 5 Voltage of volts. Since the idler and source of the first field effect transistor 35 are grounded, the idle plant of the second field effect transistor 370 will reach a low supply voltage of about 3.3 volts. The consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economy Printed 437051 Λ7 ----- B7__ 5. Description of the invention () vdd, at this time, the common area between the first and second field effect transistors will be limited to the low supply voltage Vdd (second field effect transistor) 37〇gate voltage) minus the second field effect transistor The level of the starting voltage (thresh0M v〇itage) of 37. Below this-the voltage distribution, between the gate to the drain, the gate to the source, or the source to the drain of the transistor. The supply voltage does not exceed the low supply voltage of 3.3 volts, so all dielectric layers will not be challenged by the reliability of the hot carriers. 'Figure A shows the electrostatic discharge protection element of the second embodiment of the present invention. Sectional view of this electrostatic discharge protection element) An N-type well region 420 is formed in a p-type substrate 410, and a heavily doped P-type contact region 415 can be selectively formed on the p-type substrate 41. Among them, a heavily doped N-type contact region 425 may also be formed in the N-type rhenium region 420. A heavily doped p-type conductive region 43o is formed in the N-well region 420 as a shouting pole, and a heavily-doped n-type conductive region 440 is formed in the P-type substrate 410 as a cathode. In this structure, the anode 43 and the cathode 440 are arranged so that the N-type conductive region 420 is disposed between the P-type conductive regions 410 and 430 'and the p-type conductive region 410 is disposed between the N-type conductive regions 420 and 440. This results in the formation of a lateral silicon controlled rectifier (LSCR) structure. Above the substrate 410, at least two N-type metal-oxide-semiconductor field-effect transistors (NMOS) are arranged in a case gd e configuration to form a transistor stack structure. Two field-effect transistors 450 and 470 are set. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the business matters on the back before filling in this page). 'I · Α7 Β7 437〇5 1 V. Description of the invention () In a king moving region, and sharing a heavily doped N-type conductive region 4 6 0 as the drain of the first field effect transistor 4 5 0 and the second The source of the field-effect transistor 470; the first field-effect transistor 450 uses a heavily doped N-type conductive region 440 as the source, and the second field-effect transistor 47 (is formed on a P-type substrate The heavily doped N-type conductive region 48C in 41 ° is used as the drain, and the orientation of the heavily doped N-type conductive region 48C is such that the first field effect transistor 450 is located in the N-well region 42 and is heavily doped. Between the N-type conductive regions 480, a dielectric layer 452 and a conductive layer 454 are stacked on the substrate 410, and are located between the N-type conductive doped regions 44 and 46 to form a first field-effect transistor. 45 °. The gate dielectric layer and the gate electrode. The dielectric layer 472 and the conductive layer 474 are stacked on the substrate 41 °, which is between N-type conductive doping. And a gate dielectric layer and a gate electrode of the first field-effect transistor 47◦. The fourth B diagram shows the above-mentioned electrostatic discharge protection element of the second embodiment of the present invention. In the top view, the relationship positions and numbers of the components are the same as those shown in the fourth A. The gate dielectric layers 452 and 472 are not shown because they are directly under the gate electrodes 454 and 474, respectively. Second The equivalent circuit diagram of the embodiment is shown in Figure 4c. Among them, the lateral silicon controlled rectifier is composed of a PNP bipolar transistor 435 and an NPN bipolar transistor in a positive feedback configuration. P-type substrate 41. The N-well region 42 and the heavily doped P-type anode 430 serve as the forbidden, base, and emitter electrodes of the PNP bipolar transistor 435. Similarly, the N-well region 42 and p-type plate 410 are heavily doped. Miscellaneous N-type cathode 440 is used as npn double carrier ^ crystal 15 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) {Please read the precautions on the back before filling this page) \ Installation ------ 11 Order --- 1 ---- Γ > Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4370 5 A7 B7 Printed clothing by the Consumer Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China. 5. Description of the invention (collector, base, and emitter of body 445. The resistor 413 is formed between the P-type substrate 410 and the heavily doped p-type contact region 415. Produced by the interface. Two n-type metal-oxide-semiconductor field-effect transistors (NMOS) 450 and 470 are arranged in series (cascode c〇nfigurati〇n), so that the source of the first field-effect transistor 450 is coupled to the NPN The emitter of the double-carrier transistor 445; the drain 48 of the second field-effect transistor 470 (which is coupled to the emitter 430 of the PNP double-carrier transistor It 435. When the structure of the second embodiment of the present invention is configured to be engraved in a integrated circuit as a static discharge protection device, this protection circuit can be coupled to the main circuit β protection circuit in the following manner, a PNP bipolar transistor 43ί's emitter 430, N-well contact area 425, and second field-effect transistor 47 ('; and pole 480 as anodes, which are connected to the input and output of the main circuit 499. I-type substrate contact area 415 and transverse rectifier rectifier The N-type common area 44o, which is stacked with the transistor, serves as the cathode and is grounded. The closed electrode 454 of the first field effect transistor ft 450 is simultaneously grounded. The open electrode 474 of the second field effect transistor 470 can be directly connected. It is coupled to the low-voltage supply terminal vm, and the bit is coupled to the low-voltage supply terminal: dd through a network of transistors. The transistor stack structure in this second embodiment is used as an output buffer. In the electrostatic discharge effect, a breakdown current can be provided, and the silicon controlled rectifier is brought into a conducting state. Using the electrostatic discharge protection elements shown in the fourth A, fourth B, and fourth C of the present invention, the discharge phenomenon can still occur. It plays the role of protecting the main circuit when it is born, and is able to apply the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) at * 16 paper sizes. --Please read the sobbing items on the back before filling this page) ------- Order --------- ^ ί '4 3 7 0 5 1 Α7 Β7 V. Description of the invention (The standard supply voltage still meets the reliability requirements of the dielectric layer and will not be affected by Damaged by the hot carrier effect. In addition to the standard horizontal silicon controlled rectifier structure suitable for the upper loop, the present invention can also adopt a poorly controlled silicon controlled rectifier. The fifth embodiment of the present invention does not show the second embodiment Example of a cross-sectional view of an electrostatic discharge protection element 'uses a floating-weld SCR (floating_welI SCR) as a basic defense element. This-the electrostatic discharge protection element forms an N-type in a p-type substrate 510 A well region 52 is formed, and a heavily-doped p-type contact region 515 may be selectively formed in the p-type substrate 5i0. In the N-type well region 520, a heavily-doped p-type conductive region is formed. 53 ° is used as an anode without forming a contact area, and is formed in a p-type substrate 51 ° The heavily doped N-type conductive region 54o serves as the cathode. In this structure, the anode 530 and the cathode 540 are arranged such that the N-type conductive region 52o is disposed between the P-type conductive regions 510 and 530, and the p-type conductive region The region 510 is located between the N-type conductive regions 520 and 540, thereby forming a lateral silicon controlled rectifier (LSCR) structure. (Jing first read the vii-t matters on the back before filling in this page) ^ il ----— Order ----- I f- — ^ s .. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is printed on the substrate 510. At least two n-type metal-oxide-semiconductor field-effect transistors (NMOS) are connected in series (cascode configuration ) To form a transistor stack structure. The two field-effect transistors 550 and 570 are both disposed at the same active region t, and share a heavily doped N-type conductive region 560 as the drain of the first field-effect transistor 550 and the second field-effect transistor. The source of crystal 570; of which, the first field-effect transistor 550 applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to the original paper size

Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ '437U 5 1 a; _ B7 V. Description of the invention () Doped N-type conductive region 540 is used as the source, and heavily doped N-type conductive region 580 is formed at On the boundary between the p-type substrate 51o and the N-well region 520, as the second field effect transistor 57o; and the pole. The dielectric layer 552 and the conductive layer 554 are stacked on the substrate 510 at a position between the N-type conductive doped regions 540 and 560 to form a gate dielectric layer and a gate electrode of the first field effect transistor ho. The dielectric layer 572 and the conductive layer 574 are stacked on the substrate 510, and the gate dielectric between the N-type conductive doped regions 56 and 580 is formed to form a second field effect transistor 57. Between thunder poles. The equivalent circuit diagram of the second embodiment is shown in Fig. B. Among them, the lateral silicon controlled rectifier is composed of a PNP bipolar transistor 535 and an NPN bipolar transistor 545 in a positive feedback configuration to form a Dp-type substrate 51, an N-well region 520, and a heterogeneous P-type anode 530, respectively. As the pnp bipolar chirped body 535, the base, emitter, and emitter. Similarly, the n 丼 region 520, the P-type substrate 510, and the heavily doped N-type cathode 540 are used as the prohibition, base, and emitter of the NPN bipolar transistor 545, respectively. The resistance 513 is generated by a junction between the P-type substrate 510 and the heavily doped p-type contact region 515. Two n-type metal-oxide-semiconductor field-effect transistors (NMOS) 550 and 570 are set in a cascode configuration so that the source of the first field-effect transistor 550 is light-coupled to the emission of the NPN bipolar transistor 545 The drain of the second field-effect transistor 570 is combined to the base 520 of the PNP bipolar transistor 535. The structure of the third embodiment of the present invention is configured into an integrated circuit as an electrostatic discharge protection component. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the note on the back first) Please fill in this page again for details) nn · 1 · lOJT unnn A)-, A7 B7 4370 5 1 5. When the invention is explained (), this -protection circuit can be drafted into the main circuit in the following way. In the protection circuit, the emitter 530 of the bipolar transistor 535 is used as the anode, and is connected to the I / O port 599 of the king circuit. ΗThe substrate contact area 515 and the N-type common area 540 of the horizontal dream-control rectifier and transistor stack structure are used as cathodes, and are grounded. The closed-electrode 554 of the first field-effect transistor 55 is simultaneously grounded. The gate 574 of the second field effect transistor 57 can be directly consumed to the low-voltage supply terminal Vdd, or coupled to the low-voltage supply terminal Vdd through a network of a series of transistors. By adopting the electrostatic discharge protection element shown in the fifth A and fifth B diagrams of the present invention, the function of protecting the main circuit can be exerted when the phenomenon of electrostatic discharge occurs, and it can still conform to the dielectric layer at a standard supply voltage of $. Reliability requirements do not suffer from thermal carrier effects. Fig. 6A shows a cross-sectional view of the electrostatic discharge protection element of the fourth embodiment of the present invention, and a silicon controlled rectifier (fiocating well SCR) in the suspension well area is used as a basic protection element. Such an ESD protection element forms an N-type well region 62 in a P-type substrate 610, and can optionally form a heavily doped P-type contact region 615 in the p-type substrate 6m 'in an N-type A well-doped p-type conductive region 630 is formed in the well region 620 as an anode without forming a contact region, and a heavily doped N-type conductive region 640 is formed on the p-type substrate 610 as a cathode. In this structure, the arrangement of the 'anode 630 and the cathode 640 is such that the N-type conductive region 620 is disposed between the P-type conductive regions 61 and 63, and the p-type conductive region 610 is disposed between the N-type conductive region 620 and Between 640, this paper size applies _ National Standard (CNS) A4 specification (210 X 297 mm) J--j-^ --- ', · crack -------- order ·- ----- ΓΛ, ν (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 437U 5 1 --------- B7_____ V. Description of Invention () Thus, a lateral silicon controlled rectifier (LScR) structure is formed. (Please read the precautions on the back before filling this page) On the substrate 610, at least two n-type metal-oxide-semiconductor field-effect transistors (NlVtOS) are arranged in a cascode configuration to form a transistor stack structure . The two field-effect transistors 650 and 670 are both disposed in the same active region, and share a heavily doped N-type conductive region 660 'as the drain of the first field-effect transistor 650 and the second field-effect transistor. The source of the crystal 670; among them, the first field-effect transistor 650 uses the doped N-type conductive region 640 as the source, and the second field-effect transistor 670 is re-doped in the P-type substrate 610. The miscellaneous & type conductive region 680 is used as a drain, and the heavily doped N-type conductive region 680 is arranged so that the first field effect transistor 650 is located between the N well region 620 and the re-doped N. type conductive region 680. between,. A dielectric layer 652 and a conductive layer 654 are stacked on the substrate 610 at a position between the N-type conductive doped regions 640 and 660 to form a gate dielectric layer and a gate electrode of the first field effect transistor 65. . The dielectric layer 672 and the conductive layer 674 are stacked on the substrate 610 and are located between the N-type conductive doped regions 660 and 680 to form a gate dielectric layer and a gate of the second field effect transistor 670. electrode. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The equivalent circuit diagram of the fourth embodiment is shown in FIG. 6B. Among them, the lateral silicon controlled rectifier is composed of a PNP bipolar transistor 635 and an NPN bipolar transistor 645 in a positive feedback configuration. The p-type substrate 610, the N-well region 620, and the heavily doped P-type anode 630 serve as the stopper, base, and emitter of the PNP bipolar transistor 635, respectively. Similarly, the paper size of the n-well area is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 V. Description of the invention () 620, P-type substrate 610 and heavily doped N-type cathode 64 °, respectively As the forbidden, base, and emitter of the NPN bipolar transistor 645. (Please read the precautions on the back before filling this page.) The resistor 613 is generated by the junction between the P-type substrate 610 and the heavily doped p-type contact region 615. Two N-type metal-oxide-semiconductor field-effect transistors (NMOS) 650 and 670 are printed in series (casc〇de c〇nfigUrati〇n) in the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The source of the effect transistor 65 is light-coupled to the emitter of the npn bipolar transistor 645; the drain 68 of the second field effect transistor 67 is coupled to the emitter 63 of the PNP bipolar transistor 635 〇. When the structure of the fourth embodiment of the present invention is arranged in an integrated circuit as an electrostatic discharge protection element, this protection circuit can be coupled to the main circuit in the following manner. In the protection circuit, the emitter 63 of the PNP bipolar transistor 635 and the drain 68 of the second field effect transistor 670 are used as anodes, and are connected to the input / output port 699 of the main circuit. The P-type substrate contact area 615 and the N-type common area 64o of the lateral silicon controlled rectifier and transistor stack structure are used as cathodes, and are grounded. The first field effect. The gate 654 of the crystal 65 is simultaneously grounded. The gate 674 of the second field effect transistor 670 can be directly coupled to the low voltage supply 4 Vdd 'or through a network coupling port formed by a series of transistors to the low voltage supply terminal Vdd. The transistor stack f structure in this fourth embodiment is used as an output buffer, and can provide a breakdown current in the electrostatic discharge effect, triggering the lateral silicon controlled rectifier to enter a conducting state. By adopting the electrostatic discharge protection elements shown in the sixth A and sixth B diagrams of the present invention, the Xia can play the role of protecting the main circuit when the phenomenon of electrostatic discharge occurs, and it can still meet the dielectric requirements under a high standard supply voltage. Reliability of this paper is suitable for this paper size_National Standard (CNS) A4 Specification (210 X 297 Gongchu) 4370 5 1 A7 B7 5 Printed and Invention Description of Employee Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs Damaged by the carrier effect. In addition to the above embodiments, the present invention can also be applied in the case of higher trigger current. At this time, a N-type heavily doped guard band (guard band) can be formed in the N-well region. ) And couple it to a low supply voltage vdd; it is also possible to form a p-type heavily doped binding region in the p-type substrate and ground it (coupled to V ss).… The seventh figure shows the invention A cross-sectional view of the electrostatic discharge protection element of the fifth embodiment. In this embodiment, the components used in the first embodiment described above and shown in the third A, three B, and three c are opposite to each other. Relationship Retained and marked with the same number. In addition, an N-type heavily doped binding region 71 is formed in the n-well region 32, and the medium, 13¾ heavily doped anode 330 and the N-type field-effect transistor are N-type. And the position between the pole 380. With the setting of this bounding area 71, the limit of the latch-up of the silicon-controlled rectifier element will be greatly expanded. The structure of the fifth embodiment of the present invention is arranged to a spit. When it is an electrostatic discharge protection element, this protection circuit can be electrically coupled to the main circuit. In the protection circuit, PNp uses the following square emitter 330 as the anode, and the sub-transistor connected to the main circuit is moved. The board contact area is $ 315, and the lateral silicon controlled rectifier and the second input port. The N-type common area 340 of the P-type base is used as the cathode, and the binding area 710 that is coupled with the crystal stack structure of Xiao Yu and the contact area of the N well h 4 is required. The type weight b can be directly coupled to 22 paper sizes that are applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 public love) (read the back of the paper first; i will fill in this page before filling in) ^-n tl n f " · * nn I say f 437U 5 1 A7 B7 V. Description of the invention (combined with low voltage supply The application terminal V dd, or coupled to the low voltage supply terminal Vdd via a network composed of a series of transistors. Figure 7B shows a cross-sectional view of the ESD protection element of the sixth embodiment of the present invention. Here_ In the embodiment, all the elements used in the second embodiment described above and shown in the fourth A, fourth b, and fourth C diagrams and their relative structural relationships are substantially retained, and are labeled with the same number. In addition, an N The heavily doped binding region 72 is formed in the n-well region 420 between the P-spaced heavily doped anode 430 and the N-type heavily doped cathode 440. The limit of the blocking of the rectifier element will be greatly expanded by the setting of this east-bound region 720. In order to keep the structure of the sixth embodiment, it is arranged in a -integrated circuit for electricity: when Γ pieces, this is a defense ... The following method can be used to couple S to Wang Lu. In the protection circuit, the emitter 430 of the PNP is used as the anode, and is connected to the wheel of the main circuit: the transistor 435 board contact area 415 and the horizontal stone evening rectifier. The P-type N-type common area 44o is used as the cathode, so the electric body stack structure is doped in the binding region $ 72〇 # ΝWELL contact area: ground. The N type is superposed to the low-voltage supply terminal Vdd, or it can be directly coupled to the M voltage for the MV transistor through a network that can be directly coupled. The seventh C figure shows that the seventh embodiment of the present invention ^ ^ Sectional view of a discharge prevention element. In this embodiment, the vibration reduction is used for the aforementioned second 23 paper sizes. The Chinese National Standard (CNS) A4 specification (21〇χ297 mm) is applied (please read the unintentional matter on the back before filling in the clothing page)- ----- Order ------! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 437 u 5 V. Description of the invention (A7 B7 real examples and shown in the fourth relative structural relationship, are roughly 1 ,… [The components in the picture are identical to those of a p-type heavy hybrid beam ^ and marked with the same number. In addition, 'between 73 ° formed in the p-type substrate 410, by this-the binding region m cathode 440 The position of (1 cent-up) will be greater than 4 = set, and the rectifier element is locked to configure the seventh embodiment of the present invention as a static electricity protection device _ _ & i, ... Coupling to the main Leiba—the anti-knock circuit can use the following square-knot circuit, the emitter 430 of the PNP dual 'carrier electric s _ 435 as the anode Λ electric 435 board contact area 415 and ground ^ I / O port. P-type N-type common area 44. Department: Principle of stacked rectifier and transistor structure From straight to to: ground. The transistor of the heavily doped N-well contact region is formed by a transistor; the circuit is: 1 volt supply terminal V dd ′ or coupled to the low voltage supply terminal Vdd via a -system network. The figure shows the correction view of the electrostatic discharge protection element of the eighth embodiment of the present invention. In this embodiment, all of the foregoing are used in the second embodiment, and are shown in the fourth, fourth, fourth, and fourth ( : The components in the figure and their relative structural relationships are generally retained, and are labeled with the same number. In addition, —p-type heavily doped binding regions 75 ◦ are formed in the mouthpiece substrate 40, between the N 丼 region 420 and Position between N-type heavily doped cathode 44o;-N-type heavily doped binding region 74o is formed in n-well zone 42o, 24 paper sizes are applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the unintentional matter on the back before filling in this page)

«— — — — — — — —I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 437U 5 A7 B7 V. Description of the invention (for P-type heavily doped anode 330 blood

Location. With this-East sister, Γ + soil cone's bound area 75C knows that this east bound area 740 passes 7t; n the limit of the latch-up of the rectifier element will be greatly expanded to 0, Shi Xikong will When the structure of the eighth embodiment of the invention is deployed as an electrostatic discharge prevention element in a integrated circuit, this protection circuit is lightly closed to the main circuit. In the protection circuit, p uses the following 10,000 emitters 430 as anodes, and is connected to the 435 input / output ports of the transistor. The P-type base two contact area ... and the horizontal N-type common area 440 of the horizontally-controlled rectifier and transistor stack structure are used as cathodes, and the grounded j-type is used to support the miscellaneous binding area, which is also grounded to the dN s miscellaneous binding area 740. The contact area 325 with N 丼 can be directly coupled to the low voltage supply terminal.

Vdd is also coupled to the low-voltage supply Vdd via a network of transistors. By adopting the electrostatic discharge protection element 'proposed by the present invention, the main circuit in the integrated circuit wafer can be protected from the damage of the electrostatic discharge effect' and the voltage tolerance of the protection element can be greatly improved. The silicon-controlled rectifier structure used in the protection element provides a solid bypass protection channel; and the Jinye half field effect transistor provides _ trigger current to achieve a lower trigger voltage. The structure of the transistor stack in series can prevent the protective element itself from being damaged by high supply voltage. It ensures the reliability of the dielectric layer in the element in the combined voltage application system. 25 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (please read the business matters on the back before filling this page). -------- Order ------- -j -r, · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs! '4 3 7 u 5 1 A7 _B7__ V. Description of the invention () In addition, the voltage tolerance improved by the protective element of the present invention can be used The manufacturing process is the same as that of the main circuit in the integrated circuit, and the production process is performed at the same time without any additional steps. Any component in the electrostatic discharge protection circuit is applicable to the same design specifications (designru 1e) as the main circuit component, and does not need to use an additional high-dose ion implantation process to form ultra-high concentration conductive doped regions; also It does not require long-term oxidation or deposition to make a thicker gate oxide layer. Therefore, the electrostatic discharge protection element provided by the present invention can achieve application reliability in a combined voltage system under economical and effective conditions. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications are made without departing from the spirit disclosed by the present invention, such as the use of multiple In the series connection structure of two (three or more) field effect transistors, or the area of the P-type conductive type and the area of the N-type conductive type are interchanged, all of which should be included in the scope of the patent application described below. . (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 7 υ 5 彳 Storage C8 DS VI. Application for patent scope 1. An electrostatic discharge protection element used in a combined voltage system, the protection element contains at least: a silicon controlled rectifier , Including a common area; and a field effect transistor stack structure, the field effect transistor stack structure includes at least two field effect transistors, stacked in a cascade configuration (casc ode configuration), the field effect transistor stack The structure also includes the common area. When the field effect transistor stacked structure produces a charge collapse effect, its collapse current will trigger the silicon controlled rectifier. 2. The protection element of item 1 of the scope of patent application, wherein the above-mentioned field effect transistor stacked structure is formed in an active area. 3. For the protection element according to item 1 of the patent application scope, wherein the silicon-controlled rectifier is formed in a semiconductor layer with a first conductivity type, the silicon-controlled rectifier includes at least: a conductive well region is formed in the semiconductor layer The conductive puppet region is a second conductive type; a first conductive region is formed in the conductive well region; the first conductive region is the first conductive type; and a second conductive region is formed in the semiconductor layer In a position outside the conductive well region, the second conductive region is the second conductive type. 4. For the protection element in the scope of patent application No. 3, among which the above silicon control 27 paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 111 · ---- l I .--- Pack ----- II Order ------- 1 '-^' h. (Please read the precautions on the back before filling this page) Scope of patent application The rectifier further includes a substrate contact area formed in the semiconductor layer, and the side substrate contact area is the first conductive type. 5. The protection element according to item 3 of the Shenyang Patent Fanyuan, wherein the above-mentioned Shixi controlled rectifier further includes a conductive well contact area formed in the conductive well area. 'The conductive well contact area is the second conductive type. state. 6 'The protective element as described in item 3 of the patent application' wherein the silicon controlled rectifier described above further includes a substrate guard band formed in the semiconductor layer, interposed between the conductive well region and the first conductive region. It is said that the substrate binding region is the first conductive type. 1 The protection element according to item 3 of the scope of patent application, wherein the silicon-controlled rectifier further includes a conductive guard band formed in the conductive well region between the first conductive region and the second Between the conductive regions t, the conductive well restraint region is the second conductive type. (Please read the precautions on the back before filling out this page) nnnnn ti nn 1- n 1- nnn) δϋt I Bi Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Cooperative, printed well guidance, semi-electric second field Described in the upper shape of AW1 or middle body: 1 crystal containing the electrical cladding of the electric cladding, the effect of the body is small, three protective fields to the first crystal, the first crystal, the first crystal, and the third crystal. The second field of the field is the shape of the domain. The domain conducts the electric conductance of the electric conductance stack. The second conductor should be stacked on the second and third body layers. The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 specifications (210 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 ′ 437〇5 1 jaw C3 D8 VI. Patent application scope-the first gate area is formed in The semiconductor layer is interposed between the second conductive region and the third conductive region; and a first gate dielectric layer is formed between the semiconductor layer and the first gate region. Protection element of scope item 8 in which the field effect transistor described above The stacked structure further includes a second field-effect transistor formed on the semiconductor layer, between the conductive pallium region and the first field-effect transistor. 1. Such as the protection element of the scope of the patent application No. 9 ' The second field-effect transistor includes at least a fourth conductive region formed in the semiconductor layer and partially overlaps the conductive well region, and the fourth conductive region is the second conductive type. 1 1 · For example, the protection element of item 9 of the patent application scope, wherein the second field effect transistor described above includes the third conductive region. 12. The protection element of item 3 of the patent application scope, wherein the above field effect transistor stack structure Furthermore, a first field effect transistor is formed on the semiconductor layer, and the first field effect transistor includes at least: the second conductive region; a third conductive region is formed in the semiconductor layer, so that the second conductive region Between the conductive well area and the third conductive area, the third conductive area is the second conductive type; this paper size is applicable to China National Standard (CNS) A4 (210 * 297 cm) (please Read first Note to fill out the back of this page) P 4370 5 1 滢 D8 Sixth, the scope of the patent application shall be the layer and body on the interface, and the half of the region shall be formed into a region-shaped electric region. The first and second layer guides should be in the domain of the forming layer's dielectric gates, the first and the second, and the second and the second. Including the second and more detailed structure of the structure. # Specially piled, please ask Shen Jingrudian. Effect 3 ί 1 field should be described In the shape of the body, the crystals of the electric element are protected by the second element of the electric field. The second part is 11 = 11. The electric field effect of the intermediate body crystal is two and a half. Guidance of the fieldware element protection and anti-electricity 3, 3, 1 and 1 of the enclosing fan and special body crystal, please call to apply for the effect. 2 4-Domain (谙 Please read the precautions on the back before filling this page) The above-mentioned middle element piezoelectric combination of the element to protect against static discharge is used in the application ^-° ^ Type 1 5 The middle is the layered body guide half of the layer: one containing the package, the shape " Watch area to body well parts conductive element semiconducting protection one by one state The conductance is the zone well conductance. The conductance is the first. The conductance in the area is the conductance in the forming area. The state is the first conductance. The employee ’s consumer cooperation in the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the conductance in the well. The above-mentioned, the conductive state of the electric field in the shape of the domain is second, the first is the effective field of the electric field in the first state, the second half of the electric field conductor of the type, and the second half of the electric field of the electric field conductor. Jing Erdian: The first effect contains the field package, a little extra crystalline extra-terrestrial electricity 30 This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) '437051 Jaw C8 D8 A second conductive region; a third conductive region formed in the semiconductor layer between the conductive well region and the second conductive region, the third conductive region being the second conductive type; a first gate A pole region is formed on the semiconductor layer between the second conductive / drain region and the third conductive region; and a first gate is formed on the semiconductor layer and the first gate A second field-effect transistor is formed on the conductor layer between the regions, between the conductive well region and the first field-effect transistor. The second 'effect transistor and the first field-effect transistor are connected in series. The connection form (cascode configuration) is formed in an active area. 16. The protection element according to item 15 of the patent application scope, wherein the silicon-controlled rectifier further includes a substrate contact area formed in the half-percent body layer, and the substrate contact area is the first conductive type. 17. The protection element according to item 15 of the scope of patent application, wherein the silicon-controlled rectifier further includes a conductive well contact area formed in the conductive well area, and the conductive well contact area is the second conductive type. 18. The protection element according to item 15 of the scope of patent application, wherein the silicon controlled rectifier further includes a substrate guard band formed in the semiconductor layer, interposed between the conductive well region and the first conductive region. No. 31 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Read the business matters on the back before filling out this page) ~ r 、 Packing -------- Order-- ----- 117 ^ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4370 51 A8 B8 C8 D8 The scope of patent application for this substrate is the first conductive type. 19. The protection element according to item 15 of the scope of patent application, wherein the silicon-controlled rectifier further includes a conductive well guard band formed in the conductive well region, interposed between the first conductive region and the first conductive region. Between the two conductive areas, the area bounded to the east of the conductive well is the second conductive type. 20. If the protection element according to item 15 of the scope of patent application, wherein the second field-effect transistor includes at least a fourth conductive region formed in the semiconductor layer and partially overlaps the conductive well region, 'The first The four conductive regions are the second conductive type. 2 1. The protection element according to item 15 of the scope of patent application. The two field effect transistors include the third conductive region. Among them the above (please read the unintentional matter on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 2. An electrostatic discharge protection element used in a combined voltage system. : A semiconductor layer, the semiconductor layer having a first conductivity type; a conductive well region is formed in the semiconductor layer, the conductive well region is a second conductivity type; a first conductive region is formed in the conductive well region Wherein the first conductive region is the first conductive type; and a second conductive region is formed in the semiconductor layer outside the conductive well region, and the second conductive region is the second conductive type 32 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) -------- Order -------! 437051 A8 B8 C8 D8 An effect transistor is formed on the semiconductor layer, and the first field effect transistor includes at least: the second conductive region and a third conductive region formed in the semiconductor layer so that the second conductive region is interposed between the conductive well region With that third Between the conductive regions 5 The second conductive region is the second conductive type, a first gate region is formed on the semiconductor layer, and is interposed between the second conductive region and the third conductive region; and First gate-gate region Formed on the semiconductor layer and the second field-effect transistor are formed on the bulk layer, so that the first field-effect transistor is interposed between the conductive well region and the X-th effected transistor, the second field-effect transistor The transistor and the first field effect transistor are formed in an active area in a cascode configuration. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 3 · If the patent protection scope item 22, the above silicon controlled rectifier includes a substrate contact area formation In the semiconductor layer, the substrate contact area is the first conductive type. 24. The protection element according to item 22 of the patent application park, wherein the silicon-controlled rectifier further includes a conductive radon contact area formed in the conductive well area, and the conductive well contact area is the second conductive type. 33 The size of this paper is applicable to the national standard (CNS) A4 specification (2〗 0 X 297 mm) AS 437051 g DS VI. Application scope of patent 2 5. If the protection element of the scope of patent application No. 22, the above silicon The rectifier further includes a substrate guardband formed in the semiconductor layer, interposed between the conductive well region and the first conductive region. The substrate bound region is the first conductive type. 26. The protection element according to item 22 of the scope of patent application, wherein the above-mentioned stone evening rectifier further comprises a conductive well guard band formed in the conductive well region, interposed between the first conductive region and the Between the second conductive areas, the area bounded by the conductive wells is in the second conductive type. 27. The protection element according to item 15 of the scope of patent application, wherein the second field-effect transistor and the third conductive region are included. (Please read the precautions on the back before filling this page) Μ / 1 It n I n ϋ rn I n Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The paper size is applicable to China National Standard (CNS) A4 (210 X 297 Mm)