TW436795B - Memory system - Google Patents

Abstract

A memory system (10) comprising a non-volatile memory (18) having memory locations (38), and a controller (16) for writing data structures to and reading data structures from the memory. The system (10) is architecturally configured so that the locations (38) can be written to individually but are erasable only in blocks. The controller (16) forms one or more erasable units (39) which are each subdivided into cells (50) each consisting of a group of locations (38). The controller (16) writes data structures to and reads data structures from each cell (50) on a per cell basis. The system (10) may comprise a controller (16) may be embedded in, or implemented in, a host system such as a personal computer (PC).

Description

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs p Λ36795 at _____B7___ V. Description of the Invention (I) The present invention relates to a non-volatile memory system for storing and retrieving data. The memory system includes a memory with a memory location. Memory, and its memory locations can be written individually, but can only be erased by the location of the entire block, and its system also includes a controller for controlling access to these memory locations; the invention also relates to a non- Volatile memory is used in such a non-volatile memory system and relates to a controller for controlling non-volatile memory. In particular, the present invention relates to a flash memory system having a defective memory location, and to a controller for a flash memory. Flash EPROM (programmable read-only memory) can be used to store non-volatile data in the electronics industry. The architecture of flash memory devices has locations that can be individually written but can only be erased collectively, which is called erasable blocks. Because the transistor clusters in flash memory are connected by a common erasure circuit, such a structure is produced. Therefore, the size of the erasable block (the number of storage locations) is determined by the structure of the device, and it has been formulated at the time of design and manufacture, and cannot be modified by the user. One application of data storage is to store data structures generated by, for example, a personal computer (PC). If flash memory with invalid memory locations is used to store data structures, a problem arises because these invalid memory locations cannot be reliably used for data storage. • One way to solve the problem of having invalid locations in memory is to avoid the use of any erasable blocks that contain invalid locations by the flash controller. However, if the erasable block containing the location of failure is never used (marked by the controller __-_ 4___, this paper size applies the Chinese National Standard (CNS) A4 specification (2I0X297 mm) -------- --- ^ ------ ΐτ ------ ii (Please read the precautions on the back before vik this page) Printed by the Consumer Cooperatives of the Yttrium Evil Property Bureau of the Ministry of Economic Affairs ′ '4367 9 5 at _______ Β7 5 , The description of the invention (>) is marked as unusable), it may greatly waste the available memory storage space (depending on the size of the erasable block and the number of usable memory locations), This results in low memory usage (low ratio of available memory locations to total memory location). It is an object of the present invention to provide a non-volatile memory system which removes or alleviates the above disadvantages. It is an object of the present invention to provide a non-volatile memory system including a memory having a location where data cannot be stored, but the memory can be used for efficient storage and retrieval of data structures. According to a first aspect of the present invention, a memory system connected to a host system is provided. The memory system includes: a non-volatile memory having a memory location, and a controller for writing a data structure into the memory. And remove the data from the memory, and construct its system so that the location can be written individually, but can only be eliminated by the collective block of the location; its progress is: the controller sets at least one Each erasable unit includes at least one erasable block, and the controller subdivides each erasable unit into a location group (each group is referred to herein as a cell), and based on each A cell, the controller writes the data structure into each cell and reads the data structure from each cell. With the advantages of the present invention, the memory is reconstructed as a cell, so that the controller can avoid the use of Failure of individual cells' without having to avoid the use of erasable erasable blocks β This effectively increases memory ----------- S _ Use Chinese National Standard (CNS > Α4 Specification (210 ×: 297 mm) --------- ^ --- t .------ ΐτ ------ 0 (Please read first Note on the back f .. this page) · \ A7 B7 Π367 9 5 An invention description (today) The usage rate of Lin. An erasable unit may only contain one erasable block. Instead, An erasable unit may contain a plurality of erasable blocks; it is jointly declared that the erasable block is a multiple of a binary. It will be understood that one erasable block is typically more than one cell. Before connecting to the main system, test the hundreds of millions of positions in each cell, and if the failure occurs even in only one cell, the controller treats the entire cell as unusable In addition to the data structure, the entire cell is considered to be used to store the data structure. It will be understood that the proper noun memory location can refer to a single bit stored in the billion body; however, Proper noun cells refer to most bits stored in memory. A typical cell can Stores 256 bytes or 512 bytes. It will be understood that the locations that can be individually written can be composed of a plurality of physical memory locations, such as a row of physical memory, so that in such an example An entire row is the smallest unit of memory that can be individually written. Non-volatile memory can include multiple memory devices or only a single memory device. Preferably, the controller In the form of the main controller of the auxiliary controller, the auxiliary controller is incorporated into its memory device or each memory device. Alternatively, the controller is in the form of a single controller, and the single controller controls Its memory pack ----------- This paper wave standard is applicable to China National Standard (CNS) 8-4 specifications (21〇 > < 297mm) (Please read the precautions on the back before you copy this Page) Binding and ordering-Printed by the Ministry of Economic Affairs, Smart Money, J. Bureau Employee Cooperative Cooperative, printed r 436795 5. Invention Description (+) or each memory device. Preferably, the controller specifies that at least one of the available cells in each of the erasable units is reserved to have invalid cells that are invalidated, and the cells are reserved for the control information, and the available cells. To store data received from the main system. Preferably, the reserved cells are used to store the address translation information, and the address translation information is used to convert the address from the host system into an address suitable for storing memory. Preferably, since there are a plurality of reserved cells linked together, the address conversion is realized. Preferably, each reserved cell is used to store pointer information, and the pointer information is used to point to the next reserved cell until the last reserved cell is reached, and the pointer information is to point to An address in memory, which stores an address suitable for accessing memory. Preferably, the reserved cell is constructed so as to have a plurality of entries, wherein the entry stores a plurality of fields, and the fields stored in one entry are used To point to a field stored in another registry element, and only treat fields that were recently written in one registry field as valid. According to a second aspect of the present invention, a controller is provided for a non-volatile memory with a position, which can be individually written, but can only be erased by a position block. In use, the controller Set at least one erasable unit, each of which contains at least one erasable unit _________2______ Reference paper size Applies to China National Standard (CNS) A4 (2 丨 0X297 mm) (Please read the back Note again J > i this page)-Pack. Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the bone-eliminating cooperative of the Ministry of Economic Affairs, printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative of the Ministry of Economic Affairs, 4367 9 5 5. Description of invention (ζ :) Furthermore, the controller subdivides each erasable cell into a cell ', and reads the data structure from the cell and writes the data structure into the cell based on each cell'. The proper data structure (data struture) is used to cover all the data stored in memory. Therefore, the proper noun data structure covers read / write biock (that is, a block of data transmitted between a PC and memory) and control information (that is, for example, Information generated by the memory controller). According to the third aspect of the present invention, a non-volatile memory for the controller is provided. The memory with a position can be individually written, but it can only be erased by the position block to construct a non-volatile memory. The memory is provided with at least one erasable unit, and each erasable unit contains at least one erasable block, and each erasable unit is subdivided into a memory called a cell. Groups of locations so that on each basic cell, the controller reads the data structure in the cell and writes the data structure into the cell. Because each cell in each of the erasable units tested has been constructed, non-volatile memory is constructed, and the test results of each unit are written into a set of locations to form in its unit A header in each unit, so that each unit has a header containing header information. Alternatively, in a deletable unit containing a plurality of blocks, in each deletable area Each cell in the block can be tested, and the test results of each erasable block are written into a header in its block. Control ____ «—___ This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) '— I ----.---„ -------------, 玎- ---- Μ (Please read the precautions on the back before making this page again.} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4367 95 at B7 V. Description of the invention (); Read header information in each of the blocks, and link header information 'and store the linked header information in a single header in an erasable unit, and its erasable unit is Contains most of the read blocks. Preferably, at least one cell is designated to be reserved in each erasable unit for storing control information. Preferably, a plurality of reserved (control) cells are stored Linked together 'to form a cell system' to achieve address translation. And 'and to indicate the various levels in the cell system by the individual bits in the logical address that the main system responds to, The lowest cell in the cell system either provides the actual specific address required, or Provides indicator information to point to another cell system. These and other aspects of the invention will be apparent from the following explicit description of the given example 'and with reference to the drawings' in the drawings: Figure 1 according to An embodiment of the present invention shows a block diagram of a memory system with flash memory. FIG. 2 shows various failure structures that may occur in one of the erasable blocks of the flash memory of FIG. 1. Fig. 3A shows the erasable block of Fig. 2 subdivided into cells to form an erasable unit; Fig. 3B shows an erasable unit including eight erasable blocks of Fig. 2; Fig. 4 shows The erasable unit in FIG. 3A has five storages in the data structure; The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2S0X297 mm) n Hi H--I- --1 I t-- -i lil I 111-_______-n I —____ _ i: I (please read the precautions on the back .'-, this page) Γ 4367 9 5 Α7 Β7 5. Description of the invention (1) Figure 5 illustrates How a part of a cell pattern is structured as Deletion unit; FIG. 6A shows the format of a typical cell pattern; FIG. 6B illustrates a part of a cell pattern in FIG. 6A resulting from FIG. 5; FIG. 7 shows a physical address used to access the memory of FIG. Figure 8 shows a part of Figure 7 in more detail; Figure 9 shows the addressing system used to convert the logical address of the system of Figure 1 into a physical address; Figure 10 shows a part of Figure 9 in more detail; 11 shows the chain structure of the addressing system of FIG. 9 in the form of an address table of the second block; FIG. 12 illustrates the table of FIG. 11 when stored in a control cell, and FIG. After that, the configuration of the control cell in its unit; Figure 14 shows the format of a unit address that can be removed; Figure 15 shows a unit that can be added with a billion-dollar device; and Figure 16 shows the The hierarchical system is an embodiment of the present invention, in which the controller implements a software hierarchy. FIG. 1 shows a memory system 10 connected to a personal computer 12 through a standard PC interface M. The system 10 has a controller 16 connected to a flash memory 18, and the flash memory 18 is used to store data structures-10 ____ ___ This paper size is applicable to China National Standards (CNS) A4 specifications (210X297) Li) I ----------- Meal ------ 1T ------ ^ (Please read the notes on the back before 'yi? 7 pages) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Consumption Cooperative. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed by the Consumer Consumption Cooperative at 436795 at ____137. 5. Description of the invention (none). These data structures can be generated by PC I2 (read / write block) or by controller 16 (control information). The controller 16 manages the transmission of the data structure between the pc 12 and the flash memory 1δ. The controller 16 has a PC interface hardware 20 connected to the PC interface 14. The PC interface hardware 20 is connected to the memory interface hardware 22 via a data bus 24 and also via a control bus 26. A buffer memory 28 is also connected to the data bus 24 to provide temporary storage of data to be written to the flash memory. A microprocessor 29 is provided in the controller 16. The microprocessor 29 uses the volatile memory 33 via the control bus 26 to communicate with the PC interface firmware in the non-volatile memory 30 and the controller management firmware also in the non-volatile memory 32. The memory interface hardware 22 is connected to the flash memory 18 via a second data bus 34. The flash memory 18 is typically a 16-megabit memory, constructed with thirty-two erasable blocks (one of which is shown in Pass 2 by the example block 36), Each erasable block 36 has a memory location for storing 64 kilobytes. Some or all of the erasable blocks 36 here are bit-addressed ' and have a memory location 38 ' of 65535 bytes wide, some of which are typically invalid. By way of example, FIG. 2 shows a group of non-failure locations 38 that are not close to ten in the upper left corner of block 36, and shows structures with different failure locations, such as point 40 (that is, a simple single failure location), magnetic cluster 42, Repeated magnetic clusters 44 'column 46 and row 48 fail. Specifically, the size of the position M has been increased relative to the erasable block 36 '. (Please read the precautions on the back # / k this page first). Binding. The Chinese national (CNS) eight-view grid _ (21. X 291? 1 thin) Α7 Β7 Γ 436795 V. Description of the invention (f) A physical address is always needed to access memory 18 (which addresses an actual memory location); therefore, a logical address (such as that received by the controller from PC 12) must be converted to a physical address To store the data structure, as if stored in a physical device (memory 18). All read / write blocks are transcribed and read in memory 18, as if having a byte (eight bits A block conversion algorithm for a string size of a block size according to the present invention. The controller 16 is provided with an erasable unit 39 which includes one or more erasable blocks 36. In one embodiment, such as As shown in Fig. 3A, the erasable unit 39 is composed of one erasable block 36. In another embodiment, one erasable unit 39 may include a plurality of erasable blocks 36, for example, two Carryable multiple erasable blocks 36 are finally placed in the memory 18, as shown in FIG. 3B The erasable unit 39 includes eight erasable blocks 36. The controller 16 confirms that the data structure stored in one erasable unit 39 does not overlap with the other erasable unit 39, and Make sure that each erasable unit 39 is irrelevant to all other erasable units 39. Before the flash memory 18 is not inserted into the memory system 10 ', test the memory location 38 and replace all entities in the invalid location The address is stored in a header near the beginning (lowest physical address) of each erasable unit 39. The header is a series of m memory locations, and the first location is near a erasable unit Beginning. Therefore, each erasable unit 39 contains the physical addresses of all invalid locations, such as 40, 44, 46_, and occupies in its erasable unit 39. This means that the storage pc 12 is transmitted ------12 This paper size applies to China National Standards (CNS) A4 specification (210 X 297 mm) ---------.------------------ '玎 ------ 0 (please read the precautions on the back before Γ'., 'This page) " Cooperative printed M 4367 9 5 V. Description of the invention () The m (non-invalid) memory locations are invalid, and because the energy t_ is used to arrange these locations in rows, in a deletable block, The physical address of the first m (or even a series) of these m locations is not required. Referring to Figure 3A and Figure 2, the controller 16 subdivides each erasable area. Block 36 is divided into adjacent memories The clusters of body positions 38 constitute an eradicable unit 39: these clusters of adjacent memory positions 38 are referred to herein as cell 50. The physical division of memory ’has not actually happened. The controller 16 considers each erasable unit 39 as a combination of certain cells, where each cell is a group of adjacent memory locations. To minimize the required storage space, the cell sizes are preferably the same. Cells of variable size can be used but they will be more complex. Each cell 50 contains 512 addressable memory locations 38 'and each memory location 38 is one byte wide. Its position is arranged in a cell according to 16 rows and 32 columns. 'The controller 16 sets a cell map for each erasable unit 39, wherein the cell map stores the failed cells in the unit 39 (that is, cells with at least one failed position) Location (physical address). Controller designed for a special memory structure (the size of the block can be deleted to eliminate the size of the unit). 16 'so that its cell chart corresponds to the position of the position in the erasable unit 39状 Array. The controller 16 stores its cell chart to serve as header information in the corresponding erasable unit 39 header 52. • Cell chart is generated by a test unit (not shown) '——._____________ 1_3 .._______ This paper size applies to China National Standard (CNS) A4 (210X297 mm) I ----- -Γ--Seed coat ------ tT ------ ^ (Please read the precautions on the back first and then the first page) Printed by K Consumer Cooperative, Member of Intellectual Property Bureau, Ministry of Economic Affairs ^ rv Λ367 9 5 V. The description of the invention (\ () (please read the precautions on the back and then the "text page") and write it into the header 52 during the manufacturing test process of the flash memory 18, but if it is during the valid period of the device operation If an error occurs, the cell diagram can be updated by the controller 16. The controller 16 controls the erasure of the erasable unit 39, and writes the corresponding cell diagram to the erasable block before erasing. In the buffer memory 28, and after erasing is completed, 'the corresponding cell chart is written back to the erasable unit 39. For precautionary purposes, a backup copy of the cell chart is likewise written. Enter the next Division * Divide the unit 39. If a cell 50 contains one or If there are multiple invalid memory locations, the cell is marked as invalid (in the cell chart) as described in more detail below. Each consumer unit of the Intellectual Property Bureau of the Ministry of Economic Affairs ’s consumer cooperative can print each deletable unit 39. Data is stored in cell 50, which is useful for storing data, but not in invalid cell 54 'or in the cell (control cell) where the control information is configured (retained) , Such as header 52. Therefore, the logical capacity of each erasable unit 39 (the number of addressable locations effective for data storage) will be less than the physical capacity of each erasable unit 39 (the addressable memory location 38 Total). Since the relationship between the stale cell 54 and the control cell 56 (which are both ignored when reading or writing its read / write block) has the same logical length (ie, Read / write blocks of the same number of data bits) may occupy different amounts of physical memory space (different number of memory locations 38). This is illustrated in Figure 4. In Figure 4, five reads Fetch / write block 60a, b, c, d, and q, the paper size of this paper is applicable to China National Standards (CNS) A4 specification (21〇X 297 mm) A7 4 3 6 7 9 5 V. Description of invention (p " ·) is stored in Erasable unit 39. Read / write blocks are usually stored contiguously in one or more rows of erasable unit 39, for example, the first read / write block may terminate when available Column 51, row 4 of cell 51, and the next read / write block usually starts at column 1, row 5 of the same available cell 51. Before the next column is used, read / The write block is full on an entire column in the erasable unit 39 (the number of available cells 51 is often extended). The read / write block thus connects the entire column of the erasable unit 39 and is independent of the cell 50. This is how 60a, 60b, 6c and 60d are stored. The address of the start position of 60b is immediately after the address of the last position of 60a, and the address of the start position of 60c is immediately after the address of the last position of 60b, and so on. However, in order to illustrate the utility of having many adjacent cells, the read / write block 60q shown is located near the bottom of the erasable unit 39 (because it is near the bottom of the unit 39 in FIG. 4, it has a more invalid (Cells) 〇 If there is no invalid cell 54 and control cell 56, 'in a single erasable unit 39' will be based on adjacent consecutive addresses 'and based on the row after row full' configuration reading Fetch / write block. The read / write blocks 60b, 60d, and 60q have the same logical length. As can be seen in Figure 4, the read / write block 60 can start at any position of any row in the cell; and 'samely' can end any of any row in the cell 50 The position of a line. It does not need to start in a particular column or row, or end in a particular column or row. Each read / write block 60 has a header portion 62 and ~ qualifications applicable to China National Standard (CNS) A4 specifications (210X 297 public ϋ " —— " 装 、 STii (Please read the back first Please note again ^^ this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 436795 A7 B7___ 5. Description of the invention () Material part 64. The header part 62 typically occupies 18 twelve of the memory Bytes, and contains: a flag 'used to indicate whether the data in the data part is valid; a logical block address to read / write the block; an error correction code (ECC)' used To protect the data in the header section 62; a digital 'indicating' the type of the stored data; its type such as compressed, uncompressed, protected, and the like (similar); and the next read / Write the physical address of block 60. The data part 64 contains the stored data. The length of the data part 64 is determined by the system 10. An error correction code can be appended to it by the controller 16. On the data. Read the fetch / write block 60 received from PC I2 has It is a fixed size, and its size is determined by the PC interface firmware 30. It will be appreciated that the logical capacity of each erasable unit 39 is not fixed, which is caused by the failure storage The number of cells 54 and the number of control cells are determined. When the read / write block 60 is to be written to the flash memory 18, the controller 16 determines the block 60-a suitable starting address. The selection of the starting address is determined by the specific algorithm performed by the controller. For example, the controller 16 may fill a whole column before adding to the next column: Similarly, the controller 16 may add before adding to the next column. A full row. The algorithm used depends on the structure and characteristics of the billion-body device 18. • In this embodiment, the entire column is filled first. That is, the lowest available column address is used to As the starting address, and before the column address is increased, fill the entire column (by adding the row address). Therefore, the controller 16 searches for the Zhang scale and applies the Chinese National Standard (CNS) Λ4 specification (210X29) ? Mm) --------- „---; ^ ------ Order ------. ^ ( Please read the note on the back of the page before reading. This page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs.

l · ·: 4367 9 5 A A7 B7-丨 I '1' " V. Description of the invention (\ 屮) The cell chart with the lowest available column address. The controller judges the number of available cells used to store the read / write block 60 before reaching the first invalid cell. From the number of available cell 51 and the position of each cell 51 with sixteen rows 'the number of valid memory positions can be easily determined' so the number of valid memory positions equals the available memory before the first invalid cell Multiply the number of cells by sixteen. If it is possible to store the entire block 60 'without conflicting with the stale cell 54 (or the control cell 56)', the example of storing the block 60 ° is block 60a and 6c in FIG. If, in any case, before reaching the invalid cell 54 (or control cell 56), only a part of the block 60 can be stored 'then this part can be transferred to memory and stored' after 'when the controller 16 judges the next When the position of available cell 51 is', its transmission is suspended. The controller 16 then determines how much data can be stored between the next available cell 51 and the stale cell 54 (or control cell 56) immediately after the next available cell 51. The controller 16 then increases the address to be written so that the address to be written is equal to the first available address, and starts the transmission of data, and so on. Alternatively, if the characteristics of the flash memory device do not easily allow setting a new address for data transmission, for example, because the device is constructed for continuous data transmission, the controller 16 can be used A data transmission clock is generated and supplied to the memory device without actually transmitting the data. When the internal access in the memory device (driven by the clock signal)-__17__ one-one "in the paper store standard (CNS> A4 specification (2HTX297 mm)-" ^ ~ --- iw --- ^ --- Lily clothes ------ 1T ------ 0 (Please read the note on the back and then jealous nine pages) 4367 95 V. Description of the invention (丨 <) When the indicator reaches the next available address, its data transmission is restarted by the controller 16. Therefore, the data transmission between the PC 12 and the flash memory 18 is split: each segment is stored in A set of consecutive memory locations. The length of each segment is equal to the number of consecutively available memory locations. A segment terminates at the last address before reaching the invalid cell 54 (or control cell 56), and When the next available cell 51 is reached, it restarts (at the lowest available address in the cell). Therefore, the 'controller 16 determines the size of the segment to be transmitted. When many invalid cells appear in memory 18 The utility of this segment transfer is explained by reading / writing the block 60q. , You must skip the invalid cell (and control cell), when the data will be read from the flash memory, a similar process will be performed. The controller 16 skips the cell in the following way. When a section When the last address in the segment is read, the controller 16 is in the first available cell 51 immediately after the failed cell 54 or the control cell 56 (, increasing its address to be the first available When the read / write block 60 is read, and there is an error in any of the data reads indicated by the ECC corresponding to its read / write block 60+, the controller 16 Then identify specific invalid bits, and mark the available cells or cells 51 containing those bits as invalid, and update the corresponding cell chart. Alternatively, the controller 16 may read all The available cell or cell SI of the writer block 60 is marked as invalid. In this way, the controller 16 confirms in each time data each integer Γ-Τ -------__ 1 £ _ sheet Standards apply to China National Standards (CMS> M specifications (2 〖0 × 297mm ) '436 7 9 5 A7 B7 V. Description of the invention (available in the available cell 51 of the volume (α). Therefore, the controller 16 can identify a new failure that appears in the available cell 51. In another embodiment, A self-test procedure can be used. At the beginning of the self-test, the controller 16 writes data and then reads out each available cell 51 to determine whether any available cell has a failure. The controller 16 uses a write Input indicator (as explained in GB 2 291 911) to indicate the next memory location to be written, and use an erasure indicator to indicate the next erasable unit 39 to be erased. The controller 16 also confirms that at least one of the erased and written indicators has been deleted between the write indicator and the erase indicator by the instruction of the write indicator and the read / write block is written to the indicated position. Annihilation unit 39. The controller also uses a separate control cell write pointer to indicate the memory location where control information will be written. Its control cell write indicator only indicates the position in the control cell 56. Figure 5 shows a eliminable unit with a mark to illustrate how to construct a part of a cell chart, where the row numbers of the cells are 0 to 15 and the column numbers are 0 to 7. FIG. 6A shows the format of a typical cell chart 70. FIG. Each cell chart 70 contains the address h of the erasable unit 39 related to the chart 70; the number of controllable cells 56 that are effective in the erasable unit 39 72; in the erasable unit 39 The number 73 of available cell 51; and-a set of bits 74, which represents the available cell 51 in block 36. FIG. 6B illustrates how a set of bits 74 are generated from FIG. 5. In FIG. 6B, a set of state-like financial standards (CNS) A4 (21Qx297) is displayed in a grid pattern corresponding to the cell pattern of FIG. 5 (please read the precautions on the back before reading this.) Page) --5 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by Hammer Property Agency X Printed by the Consumer Cooperatives, 436795 A7 B7 5. Bit 74 of the invention description (j). In Figure 6B 'for the sake of clarity' And an extra first row 75 and first column 76 'are not actually stored. A cell chart of eight by sixteen arrays containing-and zero (set of bit 74) is stored in each In the header 52 of each erasable unit 39. In an embodiment of the erasable unit 39 including a plurality of erasable blocks 36, a cell chart may be stored only in the first erasable unit of the erasable unit 39. There are several erasable blocks. Alternatively, a cell chart is overlapped with several erasable blocks, and the cell map is used for erasable units with a large number of erasable blocks, especially Is the memory location in each erasable block if it contains one or a few rows The first Drow 75 refers to the column editor of the cell, and the younger column 76 indicates the row number of the cell (as each labeling method in Figure 5). Row 75 and column 76 are not stored in In header 52. If a cell is available, insert the number 0 into the relevant column and row; however, if a cell is unavailable (for example, because it is a stale cell, or To control the cell), insert the number 1 into the relevant column and row. For added protection, 'a backup of cell chart 70 for clearable unit 39' can be stored in the next erasable In the header of cell 39. This is to guarantee that if one of the positions in header 52 of cell 39 can be deleted, the next header 52 can be used to store the cell in header 52. Figure 70 is restored. The information in cell chart 70 is protected by an ECC, and the ECC is inserted into the information stored in the header 52. The header 52 contains a storage for the relevant erasable unit 39 Grid chart 70, one divisible for the previous Cell chart 70 in unit 39 (please read the precautions on the reverse side before going to this page)-binding and binding

J2 £ L scale is applicable to Chinese national standard (CNS> A4 specification (2 丨 0 X 297mm) Α7 Γ '4367 9 5 V. Description of invention (丨 name), a unique identification method, so that the controller can identify Header 52, a write start flag 'a write end flag, a control cell start flag, a control cell end flag', and either the control cell header information or the control cell Index information. Initial time after erasable unit 39 is cleared 'When a read / write block is written into erasable unit 39, the write start flag is declared (set to a non-erasable state). When the read / write block is full of erasable unit 39, the write termination flag is declared. After erasable unit 39 is cleared, when the control cell (except the control memory containing the header) is written for the first time. Cell), the control cell start flag is declared. When all control cells are written, 'the control cell end flag is declared. If in a single control cell for the entire header information Out of space, you just need to control # 存 格 Header indicator 'in the example' The control cell header information is stored in another control cell indicated by the control cell indicator. Figure 7 shows for access (ie, from its Read and write to) the format of a physical address 80 of the flash memory 18. The physical address 80 has a first field 82, which indicates a removable unit 39. In this embodiment, one The size of the erasable unit 39 is equal to one erasable block 36. The physical address 80 also has a second field 84, which contains an address of the erasable unit 39. In the second field 84 The address in is about the total physical address space of the erasable unit 39. The second field 84 is used to define the position of any data structure in the erasable unit 39. This paper scale applies Chinese national standards (CNS) Α4 specification (210 X 297 mm) ----- ^ ----- Xiang ------ IT ------ ^ (Please read the precautions on the back before ^^: (This page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 6 7 9 5 at ____B7____ Description of the Invention (lf) Figure 8 shows a more detailed second field 84. The second field 84 contains a cell row 92, a row 94, a cell f96, and an fT 98. The cell Column 92 is a special column of the cells in the erasable unit 39 to be accessed. Column 94 is the physical address of the specific column of the location (in cell column 92) to be accessed. The address of this column is Is the first column in the cell. Similarly, cell row 96 is a specific row of cell in division unit 39 to be accessed, and row 98 is the location to be accessed (cell (Line 96) The physical address of a particular line. The address of this row is the first row in the relevant cell. The order of the data structures stored in the physical address space is completely independent of the logical block address (LBA) of each data structure. The data structure corresponding to any specific logical block can be allocated in the space of any physical address. The data structure entity address (PBA) of each LBA is specified in a set of tables, such as the known block address table (BAT), which can be accessed through a tree structure of an index table (PT) BAT, as illustrated in Figures 9 and 10. A shoelace structure 100 is stored in a control cell 56 in the first erasable unit 39 of the memory 18. For the purpose of protection, a backup of the boot strap structure 100 is also stored in the second and last erasable unit 39 of the memory 18. The control cell 56 for storing the shoelace structure 100 is selected by the controller 16 and its position is the first one immediately after the control cell including the header 52 Controls the location of the cell. The shoelace structure 100 is the first data structure, which is the controller 16 _______ _22_____ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I -------- ^ --- --- ΐτ ------ ^ (Please read the notes of Ι & before r'-private page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs f '4 3 6 7 9 5 A7 B7 5 Description of the invention (necessary for each system initialization (that is, each time the system is restarted after being shut down). The reason why the bootstrap structure 100 must be configured first is that it contains two very important indicators: A header index 52 and a block address index 104. The header index 52 is used to point to a header address table (HAT) to determine the position of each header 52 in each erasable unit 39 HAT refers to the HAT at the highest level (or root segment). The block address indicator 104 is used to point to a block address table (BAT) to convert the logical address received from PC I2. Become a physical address suitable for accessing flash memory 18. BAT refers to the highest-level (or root) BAT. Bootstrap structure 100 The following information is stored: 1. A unique mark to assist the identification of the controller 16; 2. An indicator pointing to the removable header with the structure 10 configured; 3. The highest available memory in the memory 18 Clear the number of cells 39; 4. The total number of rows in cell 50; 5. The total number of rows in one cell 50; 6. The total number of rows in a removable cell (e.g. 16 in Figure 3) ); 7. The total number of columns of cells in a divisible cell (for example, 8 in Figure 3); 8. The logical address of a control block (to be described below); 9. Generally used in the system The length of the read / write block in 10; 10. the length of any ECC used to read / write the block; 11. the block address index 104; and the gutter {please read the back (Notes on this page again) This paper size applies Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Ministry of Economic Affairs, M? Property Bureau, Consumer Consumption Cooperation |% 4367 9 5 Λ7 Β7 V. Description of the invention (> /) 12. Header address indicator 102. The block address index 104 defines the physical address of the control cell, and the control cell is configured with a block address table of the highest level (also known as the root segment). Similarly, the header address indicator 102 defines the physical address of the control cell, and the control cell is configured with the header address table of the highest level (also known as the root segment). FIG. 10 shows a logical address 11 ′ of the read / write block 60, whose address contains n + 1 fields (representing the hierarchy), and the nth field (representing the highest hierarchy, or the root of the tree) Segment) 112 is the most significant bit of address 110, and the zeroth field (indicating the lowest level, or the leaf of the tree) 114 is the least significant bit of address 110. For each header address index 102 and block address index 104, the shoelaced structure '100 contains an address that points to the (physical) starting position of the index table 116 of a single n-th level address table site. The controller 16 uses the number of the n-th field Π2 to indicate a single entry element in the n-th index table 116. The single sign-on element pointing to the n-th index table 116 is one of the index tables 118 for indicating the n-1th level of the address table. The specific entry element in the n-1th level table 118 pointed to is determined by the n-1th field of the logical address. This multi-level index processing is continued until the zeroth field 114 points to a registration element in the address table U0, where the address table 120 contains the actual physical address to be accessed. ‘The number of levels required is determined by the number of entries in each table 116, US, 120, and the total logical capacity of memory 18. It will be known that the same form of multi-level tree structure can be applied to Chinese National Fragmentation (CNS) using the I scale of this paper ------: „^ r-- 办 本 ------ ΪΤ- ----- 0 (Please read the precautions on the back before f-this page). 436795 V. Description of the invention (> ^)-to determine the physical address of the header 52, so as to determine the read / write area The physical address of block 60. FIG. 9 illustrates a tree structure configuration for the header 52 and the read / write block 60. A header address tree 130 is used to determine the physical address of the header 52, and a block address tree 132 is used to determine the physical address of the read / write block 60. The zero field table (corresponding to 12 in FIG. 10) pointed by the block address tree Π2 is the block address table (BAT) 136. Similarly, the header address tree 130 points to the header address table 138. The block address table 136 has two forms: primary BATs (PBATs) and secondary BATs (SBATs). A PBAT can be paired with a specific SBAT. PBATs and SBATs can be placed in any location in the physical address space, and they always store their control cell 56 no matter what. Each erasable unit 39 has at least one header control cell for maintaining the addresses of PBATs and SBATs in the erasable unit 39 (to control the format of the cell header). Depending on the size of the control cell 56 to be used, this header control cell may also include a header 52. Each PBAT contains a registry element used to predict the number of read / write blocks 60. A registry element in the PBAT may contain the physical address of the memory to be accessed, or it may contain an indicator pointing to a registry element of the corresponding SBAT. Similarly, the SBAT can contain the physical address of the memory to be accessed 'or it can contain an indicator that points to the same SBAT as another registrar. Therefore, an indirect addressing chain can be constructed to track the movement of a read / write block. In this way, it provides an indirect standard for this paper, which is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back first and then this page). Printed ^ 435 795 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention The addressing mechanism allows updating of BAT 136 when a read / write block is rewritten to a different location in memory 18. FIG. 11 shows a chain structure of a sub-block address table (SBAT) 139. Each SBAT login element H0 has three SBAT fields H2. Each field 142 can be written continuously and independently. In the examples shown in Figures 11 and 12, before the SBAT needs to be erased, a read / write block 60 can be written (reconfigured) three times (the maximum key lock length (key lock in Figure 11) Each connection is one. One SBAT field 142) Four fields H2 〇 One SBAT (Sector 1) is required for the first time, and the new read / write block address is written to field 142a The next write (reconfiguration) of its read / write block 60, which corresponds to sector two, and writes a new address into field 142b, and points to its new one through field 142c Address; therefore, two fields (142b and 142c) must be written at this time. The next write (reconfiguration) of its read / write block 60, a new address is written to field 142d , And point to its new address by field 142e; again, two fields (142d and 142e) must be written. Therefore, for each entry element 140, only the most recently written The field is only valid. Repeat this process until all the blocks are written. In the figure, it happens when the section three ^ *-is written. Another example is When its read / write block is written seventeen times (in section 17 in Figure 11), fields 142f and 142g are written. When all fields are written, before they can be used , You need to eliminate the entire SBAT 139. It will be known that, for such an architecture, _______2fi_____ This paper size applies to the Chinese National Standard (CNS) M specification (2H) X297 mm) ---- ^-„ --- install ------ order-^ ---- line (please read the precautions on the back before ylh this page) 4367 9 5 a? B7 V. Description of the invention When writing to block 60, up to two fields must be updated each time. The advantage of a SBAT 139 chain structure is that it allows easy reconstruction of its chain, as the controller writes and rewrites data Block without processing the lengthy chain link that would hinder the operating speed of the memory system 10. Figure 13 shows a removable unit 39 with the same invalid cell 54 as shown in Figures 3 to 5, which adds one Invalid cells are in the first row of the second column. Each control cell 56 is placed in the first available cell in each column Each time the erasable unit 39 is cleared, according to some predetermined algorithms, it must be initialized by rewriting the available cell 51 so that the available cell 51 can be used as the control cell. It can be used as each The number of available cell 51 in control cell 56 in erasable unit 39 is determined by a parameter stored in cell chart 70. The number of this parameter cannot be less than that used to configure the shoelace The number of control cells 56 required by the formula structure 100 and the header 52. In this embodiment, the control cell 56 is arranged in the first available cell 51 in each incomplete failure column of the erasable unit 39 . Since some flash memories cannot eliminate the perturbation effect caused by multiple individual write operations in the same column of the memory device, there is a limit on the maximum number of usable control bank 56. To eliminate such a result, the number of control cells 56 that may be arranged in the same column is limited. In this embodiment, since each erasable unit% has sixteen rows of cells and is limited to only one cell in each column, its maximum parameter is equal to the total number of available cells divided by ten. six. When writing to control cell 56, only one column is written, and then the paper size is increased to apply the Chinese National Standard (CNS) A4 specification (2! 0 X 297 mm> (Please read the precautions on the back before continuing) (This page): -'5 Printed A7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 436795 V. Invention Description (> <) (Please read the notes on the back before #minus this page) Add it and write Enter the next column in the control cell 'and so on. In contrast, when writing available cell 51, before writing its entire row,' write an entire column of unit 39. Control data mainly includes each independent Short field for transcribing data. Therefore, the number of control cells limited by the row used to store the control data is used to provide a limit on the number of individual transcribing operations in the same row of the memory device, instead of using similarly available A data structure of a read / write block in a cell to limit the number of separate write operations in the same row of the memory device. These control cells 56 are used to store the block address table (BAT) 136 Index table PT) 116 and 118, Header Address Table (HAT) 138, Header 52, and Bootstrap Structure 100. Each control cell 56 has a header 'with a unique code for Identifies whether it stores information related to BAT 136, PT 116, HAT 138, header 52, or bootstrap structure 100. The control cell header also has an obsolete flag to indicate storage in the control storage Whether the information in the header of the grid is valid or invalid. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as described above, the header for all control cells 56 in one erasable unit 39 is common. Stored in a single header control cell in unit 39, the header of which can also cover header 52 for unit 39. Each PBAT 136 has a plurality of login elements, and each login element has a specific The logical address of the read / write block. Each PBAT 136 is related to a set of consecutive logical addresses. The existence of independent PBAT is isolated to provide sufficient capacity for all logical read / write blocks in the device. Example __2S -----__ _______ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 436795 A7 B7 V. Description of the invention For example, each PBAT login element has three address fields. After the deletion, when one is written for the first time When the PBAT is registered, the physical address of the read / write block is written in the first field. At a later time, when the same logical block is rewritten, a new physical address is entered. In the second address field, the first field is no longer valid. At a later time, when the same logical block is rewritten again, the third field is used Provide an indirect address (the address of a SBAT login element 140). The controller 16 automatically considers the highest field (most recently transcribed) of the three address fields to be valid and ignores all addresses in the lower field. Certain control information must be retained in the memory 18 so as to provide the system 100 with proper initialization when the PC 12 begins to detect the system 10. For easy configuration, this information must be stored in a predetermined location. In any case, this information is periodically updated during the normal operation of the memory system 10. Therefore, the durability of the memory is caused by the repeated erasure of its predetermined position. To avoid this problem, its control information is stored as a control block with a predetermined logical address, rather than a control block with a predetermined physical address. Therefore, with each update, the control block is rewritten in a different area of the memory, but is always accessed through the same logical address. The logical address of the control block is close to the top of the logical address space of the memory 18 and cannot be accessed by the PC 12. The highest logical address available for PC I2 is immediately below the control block address. Use the block address table to determine the location of the control block in physical memory. The header address table 138 is stored in the control cell 56 using the following format. HATs 138 has one _; __ _ _ 29 — _ _ for each deletable unit 39 of the record body 18. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 0¾ (please first ^ Notes on the back of the book are different.) &Quot; 'Printed by A7 436795 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (registration element. There is only one HAT table configured in the control cell 56. For each HAT registration element The length is 16 bytes, so consecutive HAT login elements are arranged in a control cell% with a limit of 16 bytes. Therefore, one control cell 56 can accommodate 32 login elements. Controller 16 Convert a logical address into a physical address in the following manner (where the logical block address format of the read / write block to be read / written is the format of the logical address Π0). Control The device 16 uses the block address index 104 to configure the highest (nth) level block address index table 116, and by using the read / write logic bit address of the nth field 112, , Access the correct login element in table 116 The entry points to the next (n-1th level) block address index table 118. After that, it accesses the entry point pointed to by the read / write address n-1 field. Table 118 all This process is repeated for all η levels of the block until it points to a registry element in the block address table. If the registry element of this block address table is an index directly pointing to an address in the memory 18, then control The processor 16 reads the erasable unit header 52 of the erasable unit 39, and the read / write block therein is configured in its erasable unit. The controller 16 then reads the cell chart 70 In addition, the controller 16 reads its read / write block header portion 62 to confirm the logical block address field of the read / write block header portion 62, and The logical address 11 of the read / write block 60 matches. Before the data transfer operation between the PC 12 or the buffer memory 28 and the memory 18 is initialized, the controller 16 removes the erasable unit 39 to be accessed. _____________3J3________. The paper size is applicable to China National Standards (CNS) A4 specification (210 × 29? Mm)

----- ： ----- ^ ------ 'Order ------ ^ (Please read the notes on the back before f. This page) C Employees' Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Print A7 B7 5. In the description of the invention (5 and), read the cell chart 70 to determine the available / unavailable status of all cells 50, and the cell 50 is read / written to block 60. Stretched out. During the data transmission ', the controller 16 monitors the transmission of data to detect the boundary between the available cell 51 and the control cell 56, or the failed cell 54. When a boundary is encountered, its transmission is suspended to allow the allocation of a new (continued) address. Where possible, the write index address may be lost due to power failure. By scanning the data structure of the memory 18 until it is found that a partially erasable unit 39 has been written, it can be obtained again. The correct address of the write index, some of which can be written into the erasable unit 39, have a write start flag that has been declared, and a write end flag that has not been declared. This is performed by reading the flag state of the continued erasable unit header 52. When the correct erasable unit 39 is found, the unit 39 is scanned until the first erasable unit is found. Up to one location (in the available cells). This is where the indicator is written. According to the specific erasing table algorithm implemented ', the erasing index is found by scanning the erasing unit 36 from the position where the index is written until the first erasing unit that should be erasing is found. Each erasable unit 39 is confirmed by reading the data structure header 'immediately after the erasable unit header 52. FIG. 14 shows a modified format of the erasable unit physical address 84b, which is used in a flash memory architecture with an external memory device. Figure 15 shows the removable unit 39 of a flash memory, and the flash memory is ^ ___ ^ ___ u_ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (Please Read the precautions on the back first, and then go to this page). Printed by the Ministry of Economic Affairs, Intellectual Property Bureau, the Consumer Cooperative of the Property Bureau, and printed by the Ministry of Economic Affairs, the Intellectual Property Bureau, the Employee Consumer Cooperative, and printed by the employee ’s cooperative. Γ '4367 9 5 Α7 Β7 5. Description of the invention f) It has a main storage device 150 and an additional single-row byte storage device U2. The eliminable unit physical address 84b (Figure H) has an additional address bit (xcell bit) 154, which is used to indicate that its address represents the primary (bit 154 is set to zero) memory space, or Yes means extra (bit 154 is set to one) memory space. When the xcell bit is set to zero, bit 84b is used in the same way as address field 84 described above. When the xcell bit is set to 1, the xcell having a column address corresponding to rows 92 and 94 is accessed anyway. When the additional storage device 152 is used, the cell chart 70 covers an additional row to indicate whether the xcell of each column is invalid or valid. If most rows of xcell are used, rows 96 and 98 can be used to access the correct row of the external storage device. In use, the controller 16 writes all data structures into the memory 18 by providing a physical address of the starting position of the data and by providing the length of the data segment to be written. In an example of a read / write block with one or more invalid or controlled cells, or an example of a read / write block that overlaps from one physical memory row to another, follow some Individual data segments to describe their data structure. In an example of the control data structure in the control cell 56, its data is written according to one or more data segments, each of which occupies part of a row or a row of the control cell 56. The physical address of a control data structure is either calculated by the controller 16 or obtained by reading another control data structure. The above embodiment is related to the controller 16 ', the controller 16 of which has a processor set in a flash memory card and the required firmware __ _12_______ This paper standard is applicable to China Garden Home Standard ( CNS) A4 specification (210X297mm) i I line (please read the precautions on the back before ^ Γ this page) A7 B7: 436795 V. Description of the invention (now 0). In any case, the controller 16 may be provided in a host system, such as PC I2, and alternatively, in accordance with a software level (using a control algorithm) in the host system using linear memory cards, Implement the controller 16. FIG. 16 illustrates the hierarchy 160 system in the host system and a linear flash memory 162 connected to the host system. In the system of FIG. 16, a cell chart can be generated by a main software driver. 70 ° It will be seen that the present invention has a P advantage: by using cells to store either control information or reading / Write block, a erasable block can store both control information and read / write block. In addition, by using the pointer in the cell to point to other cells, it is easy to store control information that needs to be updated frequently, and it is easy to continuously track the control information that needs to be updated frequently. Since any valid control cell can be easily identified and reconfigured, erasing blocks is easy. From the viewpoint of the present invention, various modifications can be constructed into the embodiments described above. For example, an erasable block 36 may be larger or smaller than 64 kilobytes; similarly, a cell may be larger or smaller than 512 bytes. As an example, 256 bytes may be more than Good. The size of the selectable unit of the particular number will depend on the manufacturer's choice, but is generally related to the architecture, technology, and form of the memory cells of the memory device 18. The size of the selected number of cells will depend on the required memory capacity: if you use a smaller cell size, the available capacity will be larger, but as more cells are used, it will make Each ___-____ U____ This paper wave scale is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 丨 installed, ^ 1 line (please read the precautions on the back before ^ _ this page) Economy Member of the Ministry of Intellectual Property Bureau 4 Printed by the Consumer Cooperative Cooperative Member of the Ministry of Economic Affairs Intellectual Property Bureau X-Consumer Cooperative Printed 436 7 9 5 1_ml i_ V. Description of the Invention () Cancellable units require larger cell charts. Error correction codes can be implemented in the above data structure to minimize the possibility of losing important data. It will be appreciated in other embodiments that the size of the data structure can be different from what is illustrated, for example, if a larger or smaller memory is used. In other embodiments, the flash memory 18 may be composed of a memory device including a large number of erasable blocks, and each erasable block may be a row (section) of the memory device, or It is typically a small number of consecutive columns of sixteen. In this example, the erasable unit 39 managed by the controller 16 may be composed of a plurality of erasable blocks. In other embodiments, the size of the block may be larger or smaller than eight bits, for example, sixteen bits or sixty-four bits. In other embodiments, a chain length greater than four may be used. In such an embodiment, the long chain lock of the SBAT login element can be expanded due to the reconfiguration of a majority of a read / write block 60. In such an example, the chain lock can be interrupted by updating the PBAT registry element pointing to the beginning of the SBAT chain lock so that it points to the new SBAT. In other embodiments, the control cell 56 can be configured in different ways. For example, the control cell can be configured in the last available cell 51 in each column of the erasable unit 39 and in each of the second columns. More than one control cell 56 can be arranged in the first cell or each row. In other embodiments, the cell chart 70 can be constructed by the controller 6 without using a separate device (test unit). [Explanation of Component Symbols] 10 Memory System 12 Personal Computer ___ 34 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) ------------- installation- ------ Order · 一 ----- 1 * line (please read the notes on the back before filling in this education) 89.12. 0 month and month supplement 436795 A7 B7 V. Description of Invention (Intellectual Property of the Ministry of Economic Affairs Printed by Bureau Consumer Cooperatives 14 PC interface 16 Controller 18 Flash memory 20 PC interface hardware 22 Memory interface hardware 24 Data bus 26 Control bus 28 Buffer memory 29 Microprocessor 30 Non-volatile memory 32 non-volatile memory 33 non-volatile memory 34 data bus 36 block 38 memory location 39 erasable unit 40 1 occupant 42 magnetic plexus 44 magnetic plexus 46 rows 48 rows 50 cell 51 cell 52 header 35 (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)

436195 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) V. Invention Description (54 56 60a 60b 60c 60d 60q 62 64 70 71 72 73 74 75 76 80 82 84 92 94 96 98 100 cell read / write block like / write block read / write block read / write block read / write block header part data department The number of copies of the chart address is a group of bits and rows. The physical address block field, the storage cell, the storage cell, the row, and the boot strap structure. The paper dimensions are applicable to China National Standard (CNS) A4 (210 X 297 mm). Year, month and year 4367 9 5 Supplement without A7 ------ ------ installation------ --- order -------- line (please read the precautions on the back before (Fill in this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (102 104 110 112 114 116 118 120 130 132 136 138 139 140 142 142a 142b 142c 142d 142e 142f 142g 150 152) Header Block Address Index Address Field 'Field Index Table Index Table Address Table Header Address Tree Block Address Tree Block Address Table Icon Block address table entry table address field blocking element bit Fields field Fields field Fields field storage location the storage device of the present paper is suitable China National Standard Scale (CNS > A4 size (210 X 297 mm)

436795 A7 B7 V. Description of the invention (154 address bit 160 level 162 flash memory — — — — — — — — — — It '— — — III — · 11 {1 * 1111 (Please read the back Please fill in this page again if you are concerned about the matter) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 38 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

Positive charge repair GJ ο I 5 9 7 6 3 Λα U0 8 8 8 ABCD Ministry of Economic Affairs, Ministry of Economic Affairs, Finance and Economic Chaos Bureau: ^ Industry and Metallurgy ^ Printed by the cooperative 6. Application scope 1. A memory system connected to the main system, the system Includes: a non-volatile memory with a memory location, and a controller 'for writing and reading data structures to and from the memory, and constructing the system so that the location can be individually Write, but can only be erased by the position of the entire block; its improvement is: the controller constitutes at least one erasable unit, where 'each erasable unit contains at least one erasable block, and the control The device subdivides each eliminable unit into groups of locations (where each group is called a cell), and the controller writes a data structure to and reads from each cell based on each cell Take the data structure. The memory system according to item 1 of the scope of the patent application, in which the memory location in each cell is tested, and if a failure occurs in the cell, the entire cell cannot be considered to store the data structure, otherwise, It is considered that the cell can be used for storing data structures. 3. According to the memory system of the first or second patent application scope, the non-volatile memory includes a plurality of memory devices. 4. A memory system according to item 1 or 2 of the scope of patent application, wherein the non-volatile memory is only a single memory device. 5- The memory system according to item 3 of the scope of patent application, wherein the controller controls the attached controller integrated in each of its memory devices. 6. The memory system according to item 3 of the scope of patent application, wherein the controller controls each memory device in the form of a single controller. 7. Memory system according to item 1 of the scope of patent application, in which the specified paper scale is applicable to the Chinese national standard {CMS Α4 specification (210X Μ7 mm) --------- 1¾ clothing ---- ---- ΪΤ ------- ^ [(Please read the notes on the back before filling this page) 4367 9 D8 VI. Patent Application Park Each cell of at least one of the erasable units is reserved to store control information. 8. The memory system according to item 2 of the scope of the patent application, wherein the controller designates to retain at least one of the available cells in each of the erasable units so that it has reserved unusable cells and storage control information. 'Cells' and available cells for storing data received from the host system. 9. According to the memory system of the 7th patent application, some of the reserved cells are used to store the address translation information, and the address translation information is used to convert an address from the main system into a An address suitable for accessing memory. 10. The memory system according to item 7 of the scope of the patent application, wherein each reserved cell is used to store index information pointing to the next reserved cell until the last reserved cell is reached, which points to storage suitable for access The address in memory. 11. The memory system according to item 1 of the scope of the patent application, in which a plurality of cells connected together to form a cell system realize address conversion, in which a logical address supplied from the main system is used Different bits to address different levels of the cell system 'so that the lowest cell provides either the actual physical address required or the index information pointing to another cell system. I2. The memory system according to item 11 of the patent application, where the cell system is composed of cells reserved to store control information. Π. The memory system according to item 7 of the scope of the patent application, which constructs a 2 -δ sentence-'(Please read the precautions on the back before filling in this f) 夂 地 * 乂 Applicable to China National Standard (CNS) A4 grid (210X297) 436795 A8 B8 C8 D8 1% This material is modified L supplement, and the cell reserved by the scope of patent application has a large number of registered elements, and among them Each registry element stores multiple fields 'hence-a field stored in a registry element is used to point to a field stored in another registry element' and it is considered that only the most recent script stored in one registry element is written The fields are valid. 14. A controller for non-volatile memory with a position, where the position can be individually written, but can only be erased by the position of the entire block, so that in use, the controller is provided with at least one Erasable units, where each erasable unit contains at least one erasable block, the controller subdivides each erasable unit into a memory location group called a cell, and the controller is based on each storage Read the data structure from the cell and write the data structure to the cell. 15. A type of non-volatile memory used in the controller. The memory can be individually written, but can only be erased by the entire block position. This non-volatile memory is constructed so that At least one erasable unit is provided, wherein each erasable unit contains at least one erasable block 'and each erasable block is subdivided into a memory location group called a cell' so that the controller is based on each Cell, and read the data structure from the cell and write the data structure to the cell. 16. According to the non-volatile memory of item 15 of the patent application, at least one cell in each erasable unit is designated to be reserved for storing control information. 17. According to the non-volatile memory of item 16 of the patent application, most of the reserved cells are connected together to form a cell system, which is used for address conversion, and provided by the host system. , —Binding τ 线-^ (Please read the precautions on the back before filling out this page) Printed by AM Ministry of Economic Affairs AM Industrial Consumer Cooperative Co., Ltd.% This paper is applicable to Chinese national standards (CNS > A4 now (2! Ο X 297 mm) 43679¾ C8 D8 々 Different bits of a logical address should be applied for patent application to address different levels of the cell system, so that the lowest cell provides either the actual physical address required or a pointer to another Metric information for the cell system. ---------- ^ _ Install-^ ----- Order 1 -----: line (please read the precautions on the back before filling out this page) Poetry Consumers Cooperative Co., Ltd. produced rolled paper with long-term use and Chinese National Standard (CNS) A4 (210X 297 mm)