TW425769B - Mapping register structure of codec controller and powering down and suspending method using the same - Google Patents

Mapping register structure of codec controller and powering down and suspending method using the same Download PDF

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Publication number
TW425769B
TW425769B TW088111570A TW88111570A TW425769B TW 425769 B TW425769 B TW 425769B TW 088111570 A TW088111570 A TW 088111570A TW 88111570 A TW88111570 A TW 88111570A TW 425769 B TW425769 B TW 425769B
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Taiwan
Prior art keywords
register
decoder
controllers
controller
control device
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TW088111570A
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Chinese (zh)
Inventor
Ya-Ming Pan
Yung-Huei Chen
Jia-Huei Han
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Via Tech Inc
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Priority to TW088111570A priority Critical patent/TW425769B/en
Priority to US09/434,862 priority patent/US6480908B1/en
Priority to DE19959685.9A priority patent/DE19959685B4/en
Application granted granted Critical
Publication of TW425769B publication Critical patent/TW425769B/en
Priority to US10/154,218 priority patent/US6584570B2/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M11/00Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/30Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/16Sound input; Sound output
    • G06F3/162Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/40Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection

Abstract

There is provided a mapping register structure for a codec controller, which comprises: a first and a second codec controllers, each having a first register block and a second register block, wherein the first register blocks of the first and second codec controllers are used to store the status data of the first and second codec-controller, respectively, and the second register blocks of the first and second codec controllers are used to store the status data of the first register blocks of the mapped second and the first codec controllers, respectively; and a first codec and a second codec coupled to the codec controllers. Therefore, each of the first and second codec controllers can directly read the status data of the other one from the mapping register.

Description

經濟部智慧財產局員工消f合作社印製 4 2 5 7 6 9 5022twf,doc/006 A7 _____B7 五、發明説明(/ ) 本發明是有關於一種解編器控制器的結構,且特別是 有關於解編器控制器中具有影射暫存器之架構,而仍從其 直接讀取其他解編器控制器之狀態資料的架構。 一般的解編器控制器(codec controller)與解編器(codec) 之間的訊號傳輸,例如第1A圖所繪示之AC 97規格,其 包括由控制器10傳至解編器12的重置訊號RESET#、同 步訊號SYNC,由解編器12傳送至控制器10之位元時脈 訊號BIT_CLK,以及將資料由控制器1〇傳送至解編器12 的訊號SDATA_0UT與將資料由解編器12傳送至控制器10 的訊號SDATA_IN。 第1B圖係繪示解編器控制器與解編器之間的控制時 脈訊號的時序圖。例如,在時序T0時,同步訊號SYNC 由低準位開始轉換爲高準位,同時對應於此訊號SYNC之 上升緣,由解編器同步送出位元時脈訊號BIT_CLK。在時 序T1之上升緣開始送出音訊資料訊號SDATA_0UT的有 效訊框(vahd frame) F,而在時序T1週期期間對其取樣, 輸出至解編器12。以上述之協定(protocol)方式,滿足AC 97 規格便稱爲解編器控制器爲一ACLINK控制器或ACLINK 協定。 以目前的語音與通訊的發展來看,在一電腦系統中整 合有ACLINK控制器20,其包含語音(audio)解編器控制器 與數據機(modem)解編器控制器,來分別控制語音解編器22 與數據機解編器24,如第2圖所示。再者,語音解編器控 制器與數據機解編器控制器則分別由與之對應而掛在作業 3 ------------------,玎------^ (請先閲讀背面之注項再填寫本頁) 本紙浪尺度適用中國國家揉率(CNS ) A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 5022twf.d〇c/006 Λ/ __ _ B7 五、發明説明(2) 系統上的驅動程式(dnver)來加以驅動。在此情況下,前述 之訊號BIT_CLK通常由codecO,如語音解編器22來驅動。 而由ACUNK控制器20傳送到各解編器之資料則共用一 個訊號線SDATA_0UT,從各解編器22、24傳送資料到 ACLINK控制器20中的各解編器控制器則分別使用訊號線 SDATA_IN 0 與 SDATA_IN 卜 各個軟體的驅動程式,如用以驅動語音音效與數據機 之解編器,可能由不同的軟體程式設計者所設計。其可能 彼此均不知彼此的狀態。或者,其中之一解編器必須透過 ACLINK控制器來獲得彼此的狀態。假如,當在系統(如電 腦)要進入關機/暫停模式(power down/suspend mode)時, codec 0驅動解編器之BIT_CLK訊號使之關掉,此時若另 一個解編器卻還在工作時,由於解編器之間很難得知彼此 之間的狀態。因此,在系統即將進入關機/暫停模式時,可 能,如前述之語音驅動解編器22 (codecO),在關掉BIT_CLK 時脈訊號時,數據機驅動解編器24 (codec 1)之還在工作, 便造成系統當機。 綜上,在目前整合性的晶片組越來越發達的情況之 下,將語音' 數據機、通訊、繪圖等功能整合於一晶片組 中。若語音與數據機功能以前述方式來達成,由於彼此無 法得知彼此的狀態,很容易在系統即將進入關機/暫停模式 時造成系統當機。 因此本發明係提出一種解編器控制裝置之影射暫存器 架構與運用此架構之關機/暫停方法,其利用影射(shadow) 4 (請先閲婧背面之注意事項再填寫本頁) -訂 本紙張尺度適用中國國家標準(CNS > A4規格(2丨0><297公釐) 5 022twf . doc / 006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(彡) ' 暫存器的方式,使各酸㉜間可以_彼此的狀態。 本發明係提出-種解編器控制裝置之影射暫存器架構 與運用此架構之關機/暫停方法,其利用影射暫存器的方 式使系統在彳寸進入關機/暫停模式時,會讀取影射暫存器 .中所記存之對方裝置的狀態,而不會貿然把時脈控制訊號 關閉。 本發明係提出一 _解編器控制裝置之影射暫存器架構 與運用此架構之關機/暫停方法,其利用影射暫存器的方 式’使系統在將進入關機/暫停模式時’會讀取影射暫存器 中所記存之對方裝置的狀態’待所有裝置結束工作後,再 進入關機/暫停模式。 本發明所揭露之解編器控制裝置之影射暫存器架構與 運用此架構之關機/暫停方法’其簡述如下: 一種解編器控制裝»之影射暫存器架構,包括解編器 控制裝置,其具有第一與第二解編器控制器(codec controller),第一與第二解編器控制器各包含第一暫存器區 塊與第二暫存器區塊,其中第一與第二解編器控制器之第 一暫存器區塊係分別記存第一與第二解編器控制器之狀態 資料,而第一與第二解編器控制器之第二暫存器區塊係分 別記存影射之第二與該第一解編器控制器之第一暫存器區 塊狀態資料。以及。第一與第二解編器’耦接至該解編器 控制裝置。 上述之第一與第二解編器可特別針對使用ACLINK規 格之協定的語音解編器(audio codec)與數據機解編器 本紙張尺度適用中國國家榡準(CNS ) A4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) -5 Γ 經濟部智慧財產局員工消費合作社印製 tes 5〇22twf . do c/〇 〇 β A 7 ______B7____ 五、發明説明(y) (modem codec)。藉由此影射暫存器(shadow register)之架構’ 語音解編器控制器可以由影射的暫存器區塊中直接讀取到 數據機解編器控制器的狀態與控制等資料,反之亦然’而 不必如同習知技術一般須再透過ACLINK協定之控制器來 5買取對方的狀態資料。 一種_用解編器控制裝置之影射暫存器架構之關機/暫 停方法’該解編器控制器包含複數個控制器,包括 首先,將各控制器起始化,並將對應各控制器之的狀 態資料記存於暫存器中,且將其餘該些控制器之狀態資料 以影射方式記存於該暫存器中。對應各控制器之暫存器中 的主動位元設定爲第一狀態(如“1”)。在進入關機/暫停模 式之前’將各個控制器中用以驅動時脈控制訊號之控制訊 號所對應的主動位元設定爲第二狀態(如。接著,檢查 各個控制器所對應的主動位元是否均爲“〇”,亦即均停止 工作。當各個控制器所對應的主動位元均爲“0”時’便進 入進入關機/暫停模式。 藉此,由於驅動時脈訊號的解編器在關閉時脈訊號之 前’會在對應的控制器中的影射暫存器中檢查對應其他控 制器的解編器是否仍在進行工作。只有所有的解編器停止 工作,才將時脈訊號關閉·,反之則等到所有的解編器結束 工作才關閉時脈訊號。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂, 下文特舉較佳實施例,並配合所附圖式,作詳細說明如下: 圖式之簡單說明: 6 11 1 n 訂 線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家樣準(CNS )八4规格(210X297公釐) 425769 5022twf.doc/006 A7 B7 五、發明説明(夂) 第1A圖繪示解編器控制器與解編器之間的訊號傳輸 不意圖 第1 B圖繪7|\解編器控制器與解編器之間的控制時脈 訊號的時序圖 第2圖繪示具有兩個解編器時,其與ACLINK控制器 之間的訊號連接關係圖; 第3圖繪示依據本發明之連接架構關係示意圖; 第4圖繪示依據本發明,解編器控制器中之影射暫存 器之間的關係示意圖;以及 第5圖繪示具有影射暫存器之解編器控制器之關機/暫 停方法的流程布意圖。 標號說明: 10解編器控制器(ACLINK) 12解編器 20 ACLINK控制器 24 解編器(codec 1) 3 0晶片組 32a第一解編器控制器 34第一解編器(codec ◦) 22 解編器(codec 0) 32 ACLINK控制器 32b第二解編器控制器 36第 (codec 1) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 44第一驅動程式 42作業系統(0S) 46第二驅動程式 50、50’暫存器 50a/b,50’a/b,52a/b、52’a/b 組態暫存器 實施例 本發明之特徵係在具有多個解編器之架構下,其解編 52、52’影射暫存器 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 5022twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(έ) 器控制器中對應到各個解編器的控制器均可以從暫存器中 來存取自己的狀態資料《並且從影射暫存器中來直接讀取 其他解編器控制器的狀態資料,而不必透過如ACLiNK規 格協定來獲取其他解編器控制器的狀態資料。 請參照第3圖,其繪示一種具有多個解編器之架構的 方塊示意圖。第4圖則繪示第3圖中之解編器控制器中的 暫存器與影射暫存器的示意圖。 如第3圖所示,在本實施例其以語音解編器34與數 據機解編器36爲例子,而其控制器則以ACLINK規格之 ACLINK控制器32爲例子。在此,僅做爲方便說明之用, 解編器的數目非以兩組爲限,控制器也非以ACLINK協定 規格爲限。 在此實施例中,ACLINK控制器32具有對應語音解編 器34與數據機解編器36之語音與數據機解編器重器32a、 32b。語音解編器34與數據機解編器36以ACLINK協定耦 接至ACLINK控制器32。其包括由解編器送至控制器32 的時脈訊號BIT_CLK、與分別由語音解編器34與數據機 解編器36傳送至控制器32之訊號SDATAJN,以及由控 制器32送至各個解編器34 ' 36之訊號SDATA_OUT,其 爲同一訊號線。語音與數據機解編器重器32a ' 32b則分別 由掛在作業系統42下的語音驅動程式44與數據機驅動程 式46所驅動。 由第4圖之示意圖可以看出.語音與數據機解編器重器 32a、32b包含第一暫存器區塊50、50’與第二暫存器區塊 8 (請先閲讀背面之注意事項再填寫本頁) 線 本紙張尺度適用中國國家橾準(CNS > A4规格(210X297公着) 經 濟 部 智 慧 財 A 局 消 費 合 作 社 印 製 425769 5 Q 2 2 tw f . doc / 0 0 6 A7 B7 五、發明説明(7) 52、52’,其中語音與數據機解編器控制器之第一暫存器區 塊50、50’係分別記存語音與數據機解編器控制器之狀態 資料’而語音與數據機解編器控制器之第二暫存器區塊 52、52’係分別記存影射之數據機與語音解編器控制器32b、 32a之第一暫存器區塊50’、50狀態資料。 亦即’在對應語音解編控制器32a部分之暫存器區塊 50係記錄著與語音解編控制器32a相關的狀態與控制等的 資料;在對應數據機解編控制器32b部分之暫存器區塊50, 係記錄著與數據機解編控制器32b相關的狀態與控制等的 資料。記錄著與數據機解編控制器32b相關的狀態與控制 等資料的暫存器區塊50’則以影射的方式記存至影射暫存 器52 ’其對語音解編控制器32a爲唯讀的屬性;記錄著與 數據機解編控制器32a相關的狀態與控制等資料的暫存器 區塊50則以影射的方式記存至影射暫存器52,,其對數 據機解編控制器32b爲唯讀的屬性。 藉此’語音解編控制器32a便可以直接從影射暫存器 52中讀取到數據機解編控制器32b相關的狀態與控制等的 資料;而數據機解編控制器32a便可以直接從影射暫存器 52’中讀取到語音解編控制器32a相關的狀態與控制等的資 料。 此外,在暫存器區塊50中所記存的資料可以包括兩 11 : 一爲控制器32a之所有狀態的資料的組態暫存器50a, 另〜可爲輸出入基準(如1〇 base.0)之組態暫存器50b。同 f里暫存器區塊50’中也包含前述兩層組態暫存器50’a與 (請先閱讀背面之注意事項再填寫本頁) 訂' 0阳)八4規格(210乂297公釐> 經濟部智慧財產局員工消費合作社印製 425769 5022twf.doc/006 A7 B7 五、發明説明(p) 5(Tb。此外,影射暫存器52、52’中也分別包括兩層組態暫 存器(52a、52b)與(52,a、52,b)。 暫存器(50、52)與(50,、52’)可以實體方式分別在語音 與數據機解編器控制器32a ' 32b中設置。亦或,在同一暫 存器硬體上’ ill語音與數據機解編器控制器32a、32b把上 述之狀態資料編碼成不同的位址。 因此當電腦系統要進入關機/暫停模式時,在c〇dec0, 如g吾首解編器34關掉時脈訊號前,可以由語音解編器控 制器34中的影射暫存器52’ ’讀取到數據機解編器36目 前的工作狀態。如果數據機解編器36仍然在工作,便可 以暫停關掉時脈訊號,以避免系統當機。此架構,對近來 將語音與數據通訊整合於一晶片組中的趨勢十分有其功 效。 缕考第5圖,其繪示依據本發明之具有影射暫存器之 解編器控制裝置之關機/暫停方法。 解編器控制裝置可包含複數個控制器,分別對應外接 的複數個解編器。具體而言,可以語音解編器控制器與數 據機解編器控制器爲例。 於步驟100,將每個解編器控制器起始化,並將對應 各控制裝置之狀態資料記存於一暫存器中,且將其餘控制 裝置之狀態資料以影射方式記存於暫存器中。接著,在步 驟[02,將對應各解編器控制器之暫存器中的主動位元 (active bh)設定爲第一狀態,例如”1”。接著,在步驟1〇4, 判斷是否進入關機/暫停模式。 (請先閱讀背面之注項再填寫本頁)Printed by the Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2 5 7 6 9 5022twf, doc / 006 A7 _____B7 V. Description of the Invention (/) The present invention is related to the structure of a decompiler controller, and in particular it is related to The decoder controller has a structure that maps the register, but still reads the structure data of other decoder controllers directly from it. The signal transmission between a general codec controller and codec, such as the AC 97 specification shown in FIG. 1A, includes the signal transmitted from the controller 10 to the codec 12. Set signal RESET #, synchronization signal SYNC, the bit clock signal BIT_CLK transmitted from the decoder 12 to the controller 10, and the signal SDATA_0UT that transmits data from the controller 10 to the decoder 12 and the data from the decompiler The signal SDATA_IN sent from the controller 12 to the controller 10. Figure 1B is a timing diagram showing the control clock signals between the decoder controller and the decoder. For example, at timing T0, the synchronization signal SYNC is converted from a low level to a high level, and at the same time, the bit clock signal BIT_CLK is sent out by the decoder in response to the rising edge of this signal SYNC. The vahd frame F of the audio data signal SDATA_0UT starts to be sent at the rising edge of the timing T1, and it is sampled during the timing T1 cycle and output to the decompiler 12. In the above protocol mode, meeting the AC 97 specification is called a decompiler controller as an ACLINK controller or ACLINK protocol. Judging from the current development of voice and communication, an ACLINK controller 20 is integrated in a computer system, which includes an audio decoder controller and a modem decoder controller to control the voice separately. The demodulator 22 and the modem demodulator 24 are shown in FIG. 2. In addition, the voice decoder controller and the modem decoder controller are correspondingly assigned to the task 3 ------------------, 玎- ---- ^ (Please read the note on the back before filling in this page) The paper scale is applicable to the Chinese National Kneading Rate (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5022twf. d〇c / 006 Λ / __ _ B7 V. Description of the Invention (2) The driver (dnver) on the system is used to drive. In this case, the aforementioned signal BIT_CLK is usually driven by a codecO, such as a speech decoder 22. The data transmitted by the ACUNK controller 20 to the decoders share a signal line SDATA_0UT, and the data transmitted from the decoders 22 and 24 to the ACLINK controller 20 each use the signal line SDATA_IN. 0 and SDATA_IN The driver of each software, such as the decompiler used to drive the voice effects and modem, may be designed by different software programmers. They may not know each other's status. Alternatively, one of the decompilers must obtain each other's status via the ACLINK controller. For example, when the system (such as a computer) is going to enter power down / suspend mode, codec 0 drives the BIT_CLK signal of the decoder to turn it off. At this time, if another decoder is still working At this time, it is difficult to know the status of each other between the decompilers. Therefore, when the system is about to enter the shutdown / pause mode, it is possible that, as in the aforementioned voice-driven decoder 22 (codecO), when the BIT_CLK clock signal is turned off, the modem-driven decoder 24 (codec 1) is still there. Work, the system crashed. In summary, under the situation that the integrated chipset is more and more developed, the functions of voice modem, communication, and graphics are integrated into one chipset. If the voice and modem functions are achieved in the aforementioned manner, it is easy to cause the system to crash when the system is about to enter the shutdown / pause mode because the status of each other cannot be known to each other. Therefore, the present invention proposes a shadow register structure of a decompiler control device and a shutdown / pause method using this structure, which uses shadow 4 (please read the precautions on the back of Jing before filling this page)-Order This paper size applies to Chinese National Standards (CNS > A4 specifications (2 丨 0 > < 297 mm) 5 022twf .doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (彡) '' The method of the register makes the states of each acid can be _ each other. The present invention proposes a mapping register structure of a decoder control device and a shutdown / pause method using this structure, which uses the mapping register When the system enters the shutdown / pause mode, the system reads the status of the counterpart device recorded in the shadow register. It does not rashly turn off the clock control signal. The present invention proposes a solution The mapping register structure of the editor control device and the shutdown / pause method using this architecture, which uses the mapping register to 'make the system enter the shutdown / pause mode' will read the records in the mapping register Save The state of the other device 'after all devices have finished working, then enter the shutdown / pause mode. The mapping register structure of the decompiler control device disclosed by the present invention and the shutdown / pause method using this structure' are briefly described below : A mapper register structure of a decoder control device »comprising a decoder control device, which has a first and a second decoder controller (codec controller), each of the first and the second decoder controller Including a first register block and a second register block, wherein the first register block of the first and second decoder controllers respectively record the first and second decoder controllers State data, and the second register block of the first and second decoder controllers respectively record the state data of the mapped second register and the first register of the first decoder controller. ... and the first and second decoders are coupled to the decoder control device. The above-mentioned first and second decoders can be specifically targeted to the audio codec and audio codec using the ACLINK specification agreement. Modem decompiler This paper size is applicable to Chinese national standards CNS) A4 size (210X 297mm) (Please read the precautions on the back before filling out this page) -5 Γ Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs tes 5〇22twf. Do c / 〇〇β A 7 ______B7____ V. Description of the invention (y) (modem codec). By using the structure of the shadow register, the voice decoder controller can be directly read from the data register decoding by the shadow register block. Controller controller status and control data, and vice versa 'instead of having to buy the other party ’s status data through the controller of the ACLINK protocol as in the conventional technology. A kind of _shutdown / pause method of a shadow register structure using a decoder control device 'The decoder controller includes a plurality of controllers, including first, initializing each controller and corresponding to each controller's The status data of the controller are stored in the register, and the status data of the remaining controllers are stored in the register in a shadowing manner. The active bit in the register corresponding to each controller is set to the first state (such as "1"). Before entering the shutdown / pause mode, set the active bit corresponding to the control signal used to drive the clock control signal in each controller to the second state (eg. Next, check if the active bit corresponding to each controller is Both are "0", that is, they all stop working. When the active bit corresponding to each controller is "0", it enters the shutdown / pause mode. As a result, the decoder for driving the clock signal is in Before the clock signal is turned off, it will be checked in the mapping register in the corresponding controller whether the decoders of other controllers are still working. Only when all decoders stop working, will the clock signal be closed. On the other hand, the clock signal will not be turned off until all the decompilers have finished their work. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are given below in conjunction with the accompanying drawings, The detailed description is as follows: Brief description of the diagram: 6 11 1 n Thread (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) 8 4 specifications (2 10X297 mm) 425769 5022twf.doc / 006 A7 B7 V. Description of the invention (夂) Figure 1A shows the signal transmission between the decoder controller and the decoder not intended. Figure 1 B drawing 7 | \ Decompilation The timing diagram of the control clock signal between the controller and the decompiler. Figure 2 shows the signal connection relationship between the two decoders and the ACLINK controller; Figure 3 shows Schematic diagram of the relationship of the connection architecture of the invention; FIG. 4 illustrates the relationship between the mapping registers in the decomposer controller according to the present invention; and FIG. 5 illustrates the decomposer controller with mapping registers The flow layout of the shutdown / pause method is as follows. Symbol description: 10 Decoder Controller (ACLINK) 12 Decoder 20 ACLINK Controller 24 Decoder (codec 1) 3 0 Chipset 32a First Decoder Controller 34 The first decoder (codec ◦) 22 The decoder (codec 0) 32 ACLINK controller 32b The second decoder controller 36 (codec 1) (Please read the precautions on the back before filling this page) Economy Ministry of Intellectual Property Bureau Employee Cooperatives Printed 44 First Driver 42 Operating System (0S) 46 Second driver 50, 50 'register 50a / b, 50'a / b, 52a / b, 52'a / b Configuration register embodiment The feature of the present invention is that it has multiple decompilers Under the framework of the framework, its decoupling 52, 52 'mapping register is based on the Chinese National Standard (CNS) A4 specification (210X297 mm) 5022twf.doc / 006 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. Description of the invention The controllers corresponding to each decoder in the controller can access their own status data from the register, and directly read other decoder controls from the shadow register. Status data of the device without having to obtain the status data of other decompiler controllers through the ACLiNK specification protocol. Please refer to FIG. 3, which illustrates a block diagram of an architecture with multiple decompilers. Figure 4 is a schematic diagram of the register and mapping register in the decompiler controller in Figure 3. As shown in Fig. 3, in this embodiment, the voice decoder 34 and the data decoder 36 are taken as examples, and the controller is an ACLINK controller 32 of the ACLINK standard as an example. Here, it is only for the convenience of explanation. The number of decompilers is not limited to two groups, and the controller is not limited to the ACLINK protocol specifications. In this embodiment, the ACLINK controller 32 has voice and modem decoders 32a, 32b corresponding to the voice decoder 34 and the modem decoder 36. The voice decomposer 34 and the modem decomposer 36 are coupled to the ACLINK controller 32 using the ACLINK protocol. It includes the clock signal BIT_CLK sent from the decoder to the controller 32, and the signal SDATAJN transmitted from the speech decoder 34 and the modem decoder 36 to the controller 32, and the controller 32 sends to each decoder The signal SDATA_OUT of the editor 34 '36 is the same signal line. The voice and modem decompiler repeaters 32a'32b are driven by a voice driver 44 and a modem driver 46, respectively, which are hung under the operating system 42. It can be seen from the diagram in Figure 4. The voice and modem decompiler repeaters 32a, 32b include the first register block 50, 50 'and the second register block 8 (please read the precautions on the back first) Please fill in this page again) The paper size of the paper is applicable to China National Standards (CNS > A4 size (210X297)) Printed by Consumer Cooperative of Bureau of Smart Finance A, Ministry of Economic Affairs 425769 5 Q 2 2 tw f .doc / 0 0 6 A7 B7 V. Description of the invention (7) 52, 52 ', in which the first register blocks 50 and 50' of the voice and modem decompiler controller record state data of the voice and modem decomposer controller, respectively 'And the second register blocks 52 and 52 of the voice and modem decoder controller are the first register blocks 50 of the mapped modem and the voice decoder controller 32b, 32a, respectively. ', 50 state data. That is,' in the register block 50 of the corresponding speech decoding controller 32a, the state and control data related to the speech decoding controller 32a are recorded; the data is decomposed in the corresponding data machine. The register block 50 of the controller 32b part records the decompilation control with the modem The state and control data related to the register 32b. The register block 50 'which records the state and control related data of the modem decompiler controller 32b is recorded in a map manner to the map register 52' The speech decoding controller 32a is a read-only attribute; the register block 50, which records the status and control data related to the modem decoding controller 32a, is mapped to the mapping register in a mapping manner. 52, which is a read-only attribute for the modem decomposing controller 32b. This allows the 'voice decomposing controller 32a to directly read from the mapping register 52 to the state of the modem decomposing controller 32b. Data related to control and so on; and the modem decompression controller 32a can directly read the state and control data related to the voice decompression controller 32a from the mapping register 52 '. In addition, in the register area The data stored in block 50 may include two 11: one is a configuration register 50a for all the status data of the controller 32a, and the other is a configuration temporarily for the input and output reference (such as 10base.0). Register 50b. Register 50 'in the same f also contains the aforementioned two Configuration register 50'a and (Please read the precautions on the back before filling this page) Order '0 Yang' 8 specifications (210 乂 297 mm > Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 425769 5022twf .doc / 006 A7 B7 V. Description of the invention (p) 5 (Tb. In addition, the mapping registers 52 and 52 'also include two-layer configuration registers (52a, 52b) and (52, a, 52). , B). The registers (50, 52) and (50, 52 ') can be physically set in the voice and modem decompiler controller 32a' 32b, respectively. Or, on the same register hardware, the 'ill voice and modem decompiler controllers 32a, 32b encode the above state data into different addresses. Therefore, when the computer system is to enter the shutdown / pause mode, before co-dec0, such as the clock decoder 34, the mapping register 52 'in the voice decoder controller 34 can be used. The current working state of the modem decompiler 36 is read. If the modem demodulator 36 is still working, the clock signal can be suspended to avoid system crashes. This architecture is very useful for the recent trend of integrating voice and data communications into one chipset. Fig. 5 shows a shutdown / pause method of a decoder control device having a mapping register according to the present invention. The decomposer control device may include a plurality of controllers corresponding to the external decomposers. Specifically, the voice decoder controller and the data machine decoder controller can be taken as examples. In step 100, initialize each decompiler controller, and store the state data corresponding to each control device in a temporary register, and record the state data of the remaining control devices in the temporary storage by mapping. Device. Next, in step [02, the active bit (active bh) in the register corresponding to each decoder controller is set to the first state, for example, "1". Next, in step 104, it is determined whether or not the shutdown / pause mode is entered. (Please read the note on the back before filling this page)

本紙張尺度通用中國圏家樣準(〇'!^)/'14規^(210'乂297公釐) 5022twf.d〇c/006 A7 5022twf.d〇c/006 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明説明(7 ) 在步驟106,當系統要進入關機/暫停模式時,之前, 將解編器控制器中用以驅動時脈控制訊號之控制訊號所對 應的主動位元設定爲第二狀態,例如”〇”。此通常爲codecO 之解編器,在此實施例爲語音解編器。 之後,於步驟108,檢查在影射暫存器中所記存的各 控制器所對應的主動位元是否均爲”〇,’。當其餘各控制器 所對應的主動位元均爲”0”時,便執行步驟110 »進入進入 關機/暫停模式。 由上所述可以得知,由於驅動時脈訊號的解編器在關 閉時脈訊號之前,會在對應的控制器中的影射暫存器中檢 查對應其他控制器的解編器是否仍在進行工作。只有所有 的解編器停止工作,才將時脈訊號關閉;反之則等到所有 的解編器結束工作才關閉時脈訊號。 因此’藉由本發明之架構與方法,確實可以防止在其 餘解編器上在工作時,便停掉時脈訊號,而造成當機 綜上所述’本發明之解編器控制裝置之影射暫存器架 構與運用此架構之關機/暫停方法,與習知技術相較之下至 少具有下列之優點與功效: 依據本發明之解編器控制裝置之影射暫存器架構與運 用此架構之關機/暫停方法,其利用影射(shadow)暫存器的 方式’使各個裝置之間可以知道彼此的狀態。 依據本發明之解編器控制裝置之影射暫存器架構與運 用此架構之關機/暫停方法,其利用影射暫存器的方式,使 系統在將進入關機/暫停模式時,會讀取影射暫存器中所記 (請先閱讀背面之注^^項再填寫本頁)The size of this paper is in accordance with Chinese standards (〇 '! ^) /' 14 ^ (210 '乂 297mm) 5022twf.d〇c / 006 A7 5022twf.d〇c / 006 A7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperative B7 V. Description of Invention (7) In step 106, when the system is going to enter the shutdown / pause mode, the active bit corresponding to the control signal used to drive the clock control signal in the decoder controller was previously The element is set to the second state, such as "〇". This is usually a codecO decoder, in this embodiment a speech decoder. Then, in step 108, it is checked whether the active bit corresponding to each controller stored in the mapping register is “0,”. When the active bits corresponding to the remaining controllers are “0”, Step 110 »Enter the shutdown / pause mode. It can be known from the above that the decoder that drives the clock signal will map the register in the corresponding controller before the clock signal is turned off. Check whether the decoders corresponding to other controllers are still working. Only when all decoders stop working, the clock signal will be closed; otherwise, the clock signals will be closed when all decoders are finished. Therefore, ' With the structure and method of the present invention, it is indeed possible to prevent the clock signal from being stopped when the rest of the decoders are working, causing the shadow register of the decoder control device of the present invention described in the crash summary. The architecture and the shutdown / pause method using the architecture have at least the following advantages and effects compared with the conventional technology: The mapping register structure of the decompiler control device according to the present invention and the use of the framework The shutdown / pause method uses a shadow register to make each device know the status of each other. According to the present invention, the destructor control device has a shadow register structure and a shutdown using this structure. / Pause method, which uses the mapping register method, so that when the system will enter the shutdown / pause mode, it will read the records in the mapping register (please read the note ^^ on the back before filling this page)

、1T 線 ~~~~) MMM- ( 210X297^ ) 經濟部智慧財產局員工消費合作社印製 425769 5022twf.d〇c/006 A7 B7 五、發明説明(^) 存之對方裝置的狀態,而不會貿然把時脈控制訊號關閉, 防止系統當機。 依據本發明之解編器控制裝置之影射暫存器架構與運 用此架構之關機/暫停方法,其利用影射暫存器的方式,使 系統在將進入關機/暫停模式時,會讀取影射暫存器中所記 存之對方裝置的狀態,待所有裝置結束工作後,再進入關 機/暫停模式。 依據本發明之本發明之解編器控制裝置之影射暫存器 架構與運用此架構之關機/暫停方法,其解編器控制器,特 別是ACLINK控制器可支援複數個解編器,故其對整合性 多功能晶片組特別具有功效。 綜上所述 '雖然本發明已以較佳實施例揭露如上,然 其並非用以限定本發明,任何熟習此技藝者,在不脫離本 發明之精神和範圍內,當可作各種之更動與潤飾,因此本 發明之保護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁)、 1T line ~~~~) MMM- (210X297 ^) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 425769 5022twf.d〇c / 006 A7 B7 V. Description of the invention (^) The state of the counterpart device, but not Will rashly turn off the clock control signal to prevent the system from crashing. The mapping register structure of the decompiler control device and the shutdown / pause method using the architecture according to the present invention utilize the mapping register to make the system read the mapping register when the system will enter the shutdown / pause mode. The state of the other device recorded in the memory, after all devices finish working, then enter the shutdown / pause mode. According to the present invention, the mapping register structure of the decoder control device of the present invention and the shutdown / pause method using the architecture, the decoder controller, especially the ACLINK controller can support a plurality of decoders, so its Especially effective for integrated multi-function chipsets. To sum up, 'Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling this page)

11T 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公嫠)11T This paper size applies to China National Standard (CNS) A4 specification (210 × 297 cm)

Claims (1)

A8 B8 C8 D8 修正I r R 期 89/7 /3 一第一與 42576 9 5 02 2 twf1/0 0 2 苹A fi Ί Ί Ί 5 7 Π號專利鞞|H條Tf太 :、申請專利範圍 1.一種解編器控制裝置之影射暫存器架構,包括: 一解編器控制裝置,具有一第一與一第二解編器控制 器,該第一與該第二解編器控制器各包含一第一暫存器區 塊與一第二暫存器區塊,其中該第一與該第二解編器控制 器之該第一暫存器區塊係分別記存該第一與該第二解編器 控制器之狀態資料,而該第一與該第二解編器控制器之該 第二暫存器區塊係分別記存影射之該第二與該第一解編器 控制器之該第一暫存器區塊狀態資料;以及 解編器,耦接至該解編器控制裝置 2, 如申請專利範圍第1項所述之解編器控制裝置之影 射暫存器架構,其中該第一與該第二解編器分別爲語音解 編器與數據機解編器。 3, 如申請專利範圍第2項所述之解編器控制裝置之影 射暫存器架構,其中該第一與該第二解編器控制器分別爲 語音與數據機解編器控制器。 4, 如申請專利範圍第1項所述之解編器控制裝置之影 射暫存器架構,其中該解編器控制裝置係包括ACLINK規 格之控制器。 5, 如申請專利範圍第1項所述之解編器控制裝置之影 射暫存器架構,其中該第一與該第二解編器控制器之該第 一與該第二暫存器區塊分別均爲各自獨立實體暫存器》 6, 如申請專利範圍第1項所述之解編器控制裝置之影 射暫存器架構,其中該第一與該第二解編器控制器之該第 一與該第二暫存器區塊係在同一暫存器上,以不同的編碼 13 I . ----Ί — ·』^---I--訂---I---f I I L (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 方式來配置。 7. 如申請專利範圍第1項所述之解編器控制裝置之影 射暫存器架構,其中該第一與該第二解編器控制器之該第 一暫存器區塊係包含第一層組態暫存器與第二層組態暫存 器,分別對應該第一與該第二解編器控制器之所有狀態的 資料,以及對應輸出入基準(10 base 0)之組態暫存器。 8. 如申請專利範圍第7項所述之解編器控制裝置之影 射暫存器架構,其中該第一與該第二解編器控制器之該第 二暫存器區塊係包含第一層組態暫存器與第二層組態暫存 器,分別對應該第二與該第一解編器控制器之所有狀態的 資料,以及對應輸出入基準(I〇 base 0)之組態暫存器。 9. 一種具有影射暫存器之解編器控制裝置,包括一具 有一第一與一第二解編器控制器,該第一與該第二解編器 控制器各包含一第一暫存器區塊與一第二暫存器區塊,其 中該第一與該第二解編器控制器之該第一暫存器區塊係分 別記存該第一與該第二解編器控制器之狀態資料,而該第 一與該第二解編器控制器之該第二暫存器區塊係分別記存 影射之該第二與該第一解編器控制器之該第一暫存器區塊 狀態資料。 10. 如申請專利範圍第9項所述之具有影射暫存器之解 編器控制裝置,其中該第一與該第二解編器控制器分別爲 語音與數據機解編器控制器。 11. 如申請專利範圍第9項所述之具有影射暫存器之解 編器控制裝置,其中該解編器控制裝置係包括ACUNK規 ----.--------- ------JI — 訂--------線—. {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 425769 5022twfl/002 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 申請專利範圍 格之控制器。 12. 如申請專利範圍第9項所述之具有影射暫存器之解 編器控制裝置\其中該第一與該第二解編器控制器之該第 一與該第二暫存器區塊分別均爲各自獨立實體暫存器。 13. 如申請專利範圍第9項所述之具有影射暫存器之解 編器控制裝置,其中該第一與該第二解編器控制器之該第 一與該第二暫存器區塊係在同一暫存器上,以不同的編碼 方式來配置。 14. 如申請專利範圍第9項所述之具有影射暫存器之解 編器控制裝置,其中該第一與該第二解編器控制器之該第 一暫存器區塊係包含第一層組態暫存器與第二層組態暫存 器,分別對應該第一與該第二解編器控制器之所有狀態的 資料,以及對應輸出入基準(10 base 0)之組態暫存器。 15. 如申請專利範圍第14項所述之具有影射暫存器之 解編器控制裝置,其中該第一與該第二解編器控制器之該 第二暫存器區塊係包含第一層組態暫存器與第二層組態暫 存器,分別對應該第二與該第一解編器控制器之所有狀態 的資料,以及對應輸出入基準(I〇 base 0)之組態暫存器。 16. —種具有影射暫存器之解編器控制裝置,包括一具 有複數個解編器控制器,該些解編器控制器各包含一第一 暫存器區塊與一第二暫存器區塊,其中該些解編器控制器 之該第一暫存器區塊係分別記存該些解編器控制器之狀態 資料,而該些解編器控制器之該第二暫存器區塊係分別記 存影射之該些解編器控制器之該第一暫存器區塊狀態資 1 5 0^---------- 訂·------I I F (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 9 6 7 一0 2 4 8888 ABCD 經濟部智慧財產局員工消費合作社印製 夂、申請專利範圍 料。 17.如申請專利範圍第16項所述之具有影射暫存器之 解編器控制裝S,其中該第一與該第二解編器控制器之該 第一與該第二暫存器區塊分別均爲各自獨立實體暫存器^ 18_如申請專利範圍第16項所述之具有影射暫存器之 解編器控制裝置,其中該第一與該第二解編器控制器之該 第一與該第二暫存器區塊係在同一暫存器上,以不同的編 碼方式來配置。 19. 如申請專利範圍第16項所述之具有影射暫存器之 解編器控制裝置,其中該第一與該第二解編器控制器之該 第一暫存器區塊係包含第一層組態暫存器與第二層組態暫 存器,分別對應該第一與該第二解編器控制器之所有狀態 的資料,以及對應輸出入基準(10 base 0)之組態暫存器。 20. 如申請專利範圍第19項所述之具有影射暫存器之 解編器控制裝置,其中該第一與該第二解編器控制器之該 第二暫存器區塊係包含第一層組態暫存器與第二層組態暫 存器,分別對應該第二與該第一解編器控制器之所有狀態 的資料,以及對應輸出入基準(10 base 0)之組態暫存器。 21. —種具有影射暫存器之解編器控制器之關機/暫停 方法,該解編器控制器包含複數個控制器,該方法包括: 將各該些控制器起始化,並將對應該些控制器之一的 狀態資料記存於一暫存器中,且將其餘該些控制器之狀態 資料以影射方式記存於該暫存器中; 對應各該些控制器之該暫存器中的一主動位元設定爲 16 — — If-----— — IJ4-----——訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 卜-…… 1 - 」 A8 B8 5022twfl/002 C8 D8 六、申請專利範圍 一第一狀態; 在該進入關機/暫停模式之前,將該些控制器中用以驅 動時脈控制訊號之該控制訊號所對應的該主動位元設定爲 一第二狀態; 檢查該些控制器所對應的主動位元是否均爲該第二狀 態; 當該些控制器所對應的主動位元均爲該第二狀態時, 進入該進入關機/暫停模式。 衣-------訂---------線-· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐)A8 B8 C8 D8 amended I r R period 89/7 / 3-first and 42576 9 5 02 2 twf1 / 0 0 2 Ping A fi Ί Ί Ί 5 7 Π patent 鞞 | Article Tf too :, scope of patent application 1. A mapping register structure of a decoder control device, comprising: a decoder control device having a first and a second decoder controller, the first and the second decoder controller Each includes a first register block and a second register block, wherein the first register blocks of the first and second decoder controllers respectively record the first and second register blocks. State data of the second decompiler controller, and the second register block of the first and the second decompiler controller respectively record the mapped second and the first decompiler The first register block state data of the controller; and a decompiler, coupled to the decomposer control device 2, a mapping register of the decomposer control device as described in the first patent application scope Architecture, wherein the first and second decoders are a speech decoder and a modem decoder, respectively. 3. The shadow register architecture of the decoder control device as described in item 2 of the scope of the patent application, wherein the first and second decoder controllers are voice and modem decoder controllers, respectively. 4. The shadow register architecture of the decoder control device as described in item 1 of the scope of patent application, wherein the decoder control device includes an ACLINK-compliant controller. 5. The mapping register structure of the decoder control device described in item 1 of the scope of the patent application, wherein the first and second register blocks of the first and second decoder controllers Each is an independent entity temporary register "6, the shadow register structure of the decoder control device as described in item 1 of the scope of patent application, wherein the first and second decoder controllers A block with the second register is on the same register, with a different code 13 I. ---- Ί — · 』^ --- I--Order --- I --- f IIL (Please read the notes on the back before filling out this page) Printed on the paper by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs The Chinese paper standard (CNS) A4 (210 X 297 mm) is applicable Print 6. Configure the scope of patent application. 7. The mapping register structure of the decoder control device according to item 1 in the scope of the patent application, wherein the first register blocks of the first and second decoder controllers include the first The layer configuration register and the second layer configuration register respectively correspond to the data of all the states of the first and the second decompiler controllers, and the configuration registers corresponding to the input / output reference (10 base 0). Memory. 8. The mapping register structure of the decoder control device according to item 7 of the scope of the patent application, wherein the second register block of the first and the second decoder controller includes the first The layer configuration register and the second layer configuration register respectively correspond to the data of all the states of the second and the first decompiler controllers, and the corresponding input / output base (I0base 0) configuration Register. 9. A decoder control device with a shadow register, comprising a first and a second decoder controller, each of the first and the second decoder controller includes a first register Register block and a second register block, wherein the first register block of the first and second decompiler controllers respectively record the first and second decompiler control State data of the device, and the second register block of the first and the second decompiler controller respectively record the first temporary register of the second and the first decompiler controller. Register block status data. 10. The decoder control device with a shadow register as described in item 9 of the scope of the patent application, wherein the first and second decoder controllers are voice and modem decoder controllers, respectively. 11. As described in item 9 of the scope of the patent application, a decoder control device with a shadow register, wherein the decoder control device includes ACUNK regulations ----.---------- ----- JI — Order -------- Line —. {Please read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ) 425769 5022twfl / 002 A8 B8 C8 D8 The Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs has printed a controller with a patent scope. 12. Decoder control device with mapping register as described in item 9 of the scope of patent application, wherein the first and second register blocks of the first and second decoder controllers Each is a separate entity register. 13. The decompiler control device with a shadow register as described in item 9 of the scope of the patent application, wherein the first and the second register block of the first and the second decomposer controller It is configured on the same register with different encoding methods. 14. The decomposer control device having a shadow register as described in item 9 of the scope of the patent application, wherein the first register blocks of the first and second decomposer controllers include the first The layer configuration register and the second layer configuration register respectively correspond to the data of all the states of the first and the second decompiler controllers, and the configuration registers corresponding to the input / output reference (10 base 0). Memory. 15. The decomposer control device with a shadow register as described in item 14 of the scope of the patent application, wherein the second register block of the first and the second decomposer controller includes the first The layer configuration register and the second layer configuration register respectively correspond to the data of all the states of the second and the first decompiler controllers, and the configuration corresponding to the input / output base (IObase 0). Register. 16. A decoder control device with a shadow register, including a decoder controller, each of which includes a first register block and a second register Device blocks, wherein the first register blocks of the decomposer controllers respectively record the state data of the decomposer controllers, and the second temporary registers of the decomposer controllers The register block is used to record the first register block status data of the decompiler controllers. (Please read the precautions on the back before filling out this page) This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) 9 6 7 1 0 2 4 8888 ABCD Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs夂, patent application scope materials. 17. The decompiler control device S with a shadow register as described in item 16 of the scope of the patent application, wherein the first and the second register areas of the first and the second decomposer controllers The blocks are independent registers of their respective entities. ^ 18_ The decoder control device with a shadow register as described in item 16 of the scope of patent application, wherein the first and second decoder controllers are The first and the second register blocks are on the same register and are configured in different encoding methods. 19. The decomposer control device having a shadow register as described in item 16 of the scope of patent application, wherein the first register blocks of the first and second decomposer controllers include a first The layer configuration register and the second layer configuration register respectively correspond to the data of all the states of the first and the second decompiler controllers, and the configuration registers corresponding to the input / output reference (10 base 0). Memory. 20. The decomposer control device having a shadow register as described in item 19 of the scope of patent application, wherein the second register block of the first and the second decomposer controller includes a first The layer configuration register and the second layer configuration register respectively correspond to the data of all states of the second and the first decompiler controllers, and the configuration registers corresponding to the input / output reference (10 base 0). Memory. 21. —A shutdown / pause method of a decompiler controller with a shadow register, the decompiler controller including a plurality of controllers, the method comprising: initializing each of the controllers, and The status data of one of the controllers should be stored in a register, and the status data of the remaining controllers should be stored in the register in a shadowing manner; the temporary storage corresponding to each of the controllers An active bit in the device is set to 16 — — If -----— — IJ4 -----—— Order --------- (Please read the precautions on the back before filling this page ) This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) Bu -... 1-"A8 B8 5022twfl / 002 C8 D8 VI. First scope of patent application; enter shutdown / pause at this time Before the mode, the active bit corresponding to the control signal for driving the clock control signal in the controllers is set to a second state; check whether the active bit corresponding to the controllers are the first Two states; when the active bits corresponding to the controllers are the second state Enter this into shutdown / suspend mode. Clothing ------- Order --------- Line- · (Please read the notes on the back before filling in this page) Employees ’cooperation with the Intellectual Property Bureau of the Ministry of Economic Affairs National Standard (CNS) A4 (210 x 297 mm)
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US09/434,862 US6480908B1 (en) 1999-07-08 1999-11-04 Codec system with shadow buffers and method of performing a power down/suspend operation on this codec system
DE19959685.9A DE19959685B4 (en) 1999-07-08 1999-12-10 Duplicate memory coded-decoding system and method of performing a power-off / interrupt mode in this coding-decoding system
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108352161A (en) * 2015-12-21 2018-07-31 英特尔公司 Dynamic audio frequency codec is enumerated

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004038213A1 (en) * 2004-08-05 2006-03-16 Robert Bosch Gmbh Method and device for accessing data of a message memory of a communication module
US7937606B1 (en) * 2006-05-18 2011-05-03 Nvidia Corporation Shadow unit for shadowing circuit status
US8171312B2 (en) * 2006-07-05 2012-05-01 Canon Kabushiki Kaisha Recording apparatus and method for controlling the recording apparatus
US20090150697A1 (en) * 2007-12-06 2009-06-11 Yang Su-Young Media file reproduction apparatus and method

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0616617B2 (en) * 1987-12-07 1994-03-02 富士通株式会社 Initial condition setting method
JP2920942B2 (en) * 1989-07-20 1999-07-19 富士通株式会社 Video phone
AU629019B2 (en) * 1989-09-08 1992-09-24 Apple Computer, Inc. Power management for a laptop computer
DE4417924C2 (en) * 1993-05-24 1995-09-28 Reszl Karl Michael Interface for an uninterruptible power supply
US5526503A (en) * 1993-10-06 1996-06-11 Ast Research, Inc. Virtual addressing buffer circuit
CA2126903C (en) * 1994-06-28 1996-12-24 Stephen Hon Digital surround sound method and apparatus
US5646621A (en) * 1994-11-02 1997-07-08 Advanced Micro Devices, Inc. Delta-sigma ADC with multi-stage decimation filter and gain compensation filter
KR100202538B1 (en) * 1994-12-23 1999-06-15 구자홍 Mpeg video codec
US5883670A (en) * 1996-08-02 1999-03-16 Avid Technology, Inc. Motion video processing circuit for capture playback and manipulation of digital motion video information on a computer
US5983299A (en) * 1996-10-18 1999-11-09 Samsung Electronics Co., Ltd. Priority request and bypass bus
KR19980044990A (en) * 1996-12-09 1998-09-15 양승택 Structure of Portable Multimedia Data Input / Output Processor and Its Driving Method
US6259957B1 (en) * 1997-04-04 2001-07-10 Cirrus Logic, Inc. Circuits and methods for implementing audio Codecs and systems using the same
US6418203B1 (en) * 1997-06-06 2002-07-09 Data Race, Inc. System and method for communicating audio information between a computer and a duplex speakerphone modem
US6240166B1 (en) * 1998-12-08 2001-05-29 Conexant Systems, Inc. LAN connection using analog modems via telephone wiring
US6389033B1 (en) * 1999-01-25 2002-05-14 Conexant Systems, Inc. System and method for performing signal acceleration on an AC link bus
US6195766B1 (en) * 1999-05-10 2001-02-27 Conexant Systems, Inc. System and method for providing soft audio and soft modem copy protection for hardware interfaces and software code

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108352161A (en) * 2015-12-21 2018-07-31 英特尔公司 Dynamic audio frequency codec is enumerated

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