TW411566B - Process of forming the SAC Plug for self-aligned contact hole - Google Patents

Abstract

A process of forming the SAC Plug for self-aligned contact hole comprises steps of providing a substrate with semiconductor devices; forming a insulation layer on the substrate and defining an automatically self-aligned contact hole; proceeding the first impurity implantation procedure to allow the impurity penetrating into the substrate through the self-aligned contact hole and further forming a diffusion area; forming a high temperature doped polysilicon to adequately cover the surface of the insulation layer and the inner wall and bottom of the self-aligned contact hole; proceeding the second impurity implantation procedure to allow the impurity penetrating into the diffusion layer via the polysilicon layer as interlayer so as to further adjust the impurity concentration in the diffusion area; applying a dry etching procedure to partially remove the high temperature doped polysilicon layer; forming a low temperature doped polysilicon layer on the high temperature doped polysilicon layer and filling the self-aligned contact hole; and applying a planarization treatment and forming a SAC Plug inside the self-aligned contact hole to connect with the semiconductor devices.

Description

sjf. MM J The present invention relates to a plug process for automatically aligning a contact window ', and more particularly to a plug inspection process for an automatic quasi-contact window of an embedded dynamic random access memory. The conventional process for automatically aligning contact plugs (SAC pUg), which is mainly covered with an insulating layer after the semiconductor element is formed, and uses an lithography process and etching technology to define automatic alignment at predetermined positions. The "quasi-contact opening" is then filled with a conductive material groove to automatically align the contact opening to form a conductive plug, which can be used as an electrode plate or a bit line under the capacitor. In order to make this plugging process more visible, it will be explained in detail in Figures U ~ 1D. First, referring to FIG. 1A, a semiconductor substrate 100 is provided, on which are formed electrical circuits composed of gate electrodes 110, 120 and insulating sidewalls 125, and source / drain diffusion regions 130a, 130b, and 130c. Crystal. Secondly, please refer to FIG. 1B. First, an insulating layer 140 is formed on the surface of the substrate 100 as shown in FIG. 1A, and then an auto-alignment contact is defined at a predetermined position by a lithography process and an etching technique. Opening 150. Then "Please refer to the iC chart, in a furnace with a temperature of about 540 ~ 600 ° C" to form a polycrystalline silicon layer 16 doped with impurities on the insulating layer 14 and fill the groove with the automatic alignment contact opening] 5 〇. Among them, the impurities in the polycrystalline silicon layer may be N-type impurities such as phosphorus or arsenic, or p-type impurities such as boron. In addition, before forming the polycrystalline silicon layer 160, an impurity implantation treatment step may be applied to allow the impurities to enter the substrate through the automatic alignment of the contact openings to form an impurity diffusion region (not shown) for adjusting the contact openings. The interface impurity concentration. The types of impurities used, as well as the energy and dosage at the time of planting, can be selected as required.

411566 ___Case No. 87119087__Year Month Day __ ^ Five Description of the Invention (2) Finally, please refer to Figure 1 D, and use the etch-back method or chemical mechanical polishing method to remove the excess polycrystalline silicon layer 160 until the insulating layer Up to 140, an insertion test 180 'is formed in the auto-alignment contact opening 150, which can be used as a lower electrode of a capacitor or a bit line. In addition, 'Because the logic of the conventional dynamic random access memory and the memory device are formed on different chips, and then set on the same board', but because of the structure of the memory device and logic device formed on different chips, To ensure its high speed, a memory that faithfully sets the memory element and the logic element on the same chip has been proposed, which is the so-called embedded s-memory 'such as a funnel-type dynamic random access memory ( embedded

Random Access Memory). Figures 2A to 2D show part of the process using the plug-in process described in Figures 1A to 1D to produce embedded dynamic random access memory. First, referring to FIG. 2A, a semiconductor substrate 200 is provided, which can be divided into a cell area where a memory element is to be formed and a peripheral circuit area including a logic element. Among them, the cell region is formed with a transistor composed of gates 2 10, 2 2 0, insulating sidewalls 225, and source / drain diffusion regions 230a, 230b, and 230c. A diffusion region is formed in the peripheral circuit region. 23〇d, and a shallow trench isolation area for isolation. Its-human, β green Refer to Figure 2 B Figure 'First to form an insulating layer 1 4 0 in the cell area and peripheral circuit area shown in Figure 2 A On the surface of the substrate 20, an aligning contact opening 255 and 260 is defined at a predetermined position of the cell area and the peripheral circuit area by lithography and silver engraving technology. Then, please refer to FIG. 2C The temperature is about 5 4 0 ~ 6 0 0 X: stove

Page 5 ± _η Revision 5. In the description of the invention (3), a polycrystalline silicon layer 270 doped with impurities is formed on the insulating layer 140 ', and the trench fill is automatically aligned with the contact openings 2 5 5 and 2 60. The impurities in the polycrystalline silicon layer 27 0 · may be N-type impurities such as phosphorus or arsenic or P-type impurities such as boron. In addition, before the formation of the polycrystalline silicon layer, an impurity implantation treatment step can be applied to allow the impurities to enter the substrate through the automatic alignment of the contact openings, and an impurity diffusion region (not shown) is formed to adjust the contact openings. The interface impurity concentration. Among them, the type of impurities used, and the energy and dose at the time of planting can be selected according to need. Finally, referring to FIG. 2D, the excess polycrystalline silicon layer 16 ′ is removed by the etch-back method or chemical mechanical polishing method until the insulating layer 140, and a plug 280 and 280 are formed in the automatic alignment contact openings 255 and 260, respectively. 290. Prepare a lower electrode serving as a capacitor in a cell area or a bit line in a peripheral circuit area. However, the contact resistance value (rc) and junction leakage phenomenon of the 'polymorphite layer formed in the furnace' can no longer meet the current requirements of deep sub-micron components, so a groove filling property is developed and low contact can be provided. The plug process of resistance value and interface leakage is an urgent task. The feature of the present invention is to disclose an insertion inspection process for forming an automatic alignment contact window, the steps comprising: providing a substrate formed with a semiconductor element; forming an insulating layer on the substrate 'and defining a self-aligned contact window. The first impurity doping step is performed so that the impurities can enter the substrate through the self-alignment = touch window and form a diffusion region: forming a high-temperature doped polycrystalline silicon layer to cover the surface of the insulating layer smoothly. , And the inner wall and bottom of the self-aligned contact window 0; perform a second impurity doping step to make the impurities

Years and Months_Modification 4115 Paper 87119087 Five 'Invention Description (4) The quality can use the temperature-doped polycrystalline silicon layer as a slow-weighing layer to enter the diffusion region, and adjust the impurity concentration in the diffusion region; Shi Yigan Etching, removing part of the local temperature doped polycrystalline silicon layer; forming a low temperature doped polycrystalline silicon layer on the high temperature doped polycrystalline silicon layer, and trench filling the self-aligned contact. A planarization process sequentially removes the excess low temperature doped polycrystalline silicon layer and the high temperature doped polycrystalline silicon layer to the insulating layer, and a plug connecting the semiconductor element is formed in the automatic alignment contact opening. . The plugging process as described above, wherein the insulating layer can be an oxide layer commonly used in general semiconductor processes, such as a silicon oxide layer; a high-temperature doped polycrystalline silicon layer is formed by a chemical vapor deposition method, and the formation temperature is about 6 2 0 ~ 6 8 ° C, thickness is about 350 ~ 750 angstrom 'and impurity-type phosphorus mixed in the high-temperature-doped polycrystalline silicon layer, and the impurity concentration in the high-temperature-doped polycrystalline silicon layer is about ^ OMatoms / cni3; The low-temperature doped polycrystalline silicon layer is formed in a furnace at a temperature of about 54 ° to t, and the thickness is about 350,000 to 450,000 angstroms. In addition, the low-temperature doped polycrystalline silicon layer contains impurities as phosphorous. , Its impurity concentration is about / 102 ° at0ms / cm3. In addition, in the first impurity doping step, the type of material used may be selected from N-type impurities such as phosphorus or arsenic, or p-type impurities such as boron. The energy of the implant is 40keV, and the implant dose is 5 xl 〇Uat〇ms / cm2 [, and the type of material used in the second impurity implantation treatment step may be selected from N-type impurities such as arsenic or p-type impurities such as boron, and the energy of its implantation is 40keV, The implantation dose is 5 × 1014 at 0 ms / cm2; in the dry etching step, the etching gas used is hexafluoroethane and krypton (the ratio is 15/1), and the processing time is about 120 seconds; The planarization process can be performed by a chemical mechanical polishing method or a retro-etching method.

Page 7

-No. 87U9〇87 V. Description of the invention (5) Another feature of the present invention is that the auto-aligned contact window includes a cell area and an insulating layer defining an impurity that can touch the window to enter the polycrystalline hair layer to contact Window impurities can be removed, and some layers are removed in the high-peripheral circuit sequence. Multiple layers are removed to the periphery of the plug revealed by the insulation system and f * »enter the cell area and are formed in the insulation area. On the heterocrystalline layer layer, the contact window heteroplex is an embedded dynamic process, in which the semiconductor in the step region is in the cell region and the first-time impurity and the peripheral circuit region-diffusion region; the surface of the edge layer is formed in a row. The second impurity is slowly weighed on the substrate, and self-aligned contacts respectively pass through the inner wall of the thin substrate and cover it comfortably, and the bottom is adjusted with the high temperature doping to adjust the two-temperature doping and re-temperature of the diffusion region. The self-alignment of the polycrystalline spar area is pushed to the low temperature doped edge layer. Layer as a mass concentration, applying a layer; forming a low temperature and filling the grooves separately; and applying a flat silicon layer and the high-recovery access note include: providing a substrate; forming-the peripheral circuit region is doped with a step to self-align Joining-high temperature doping and the self-aligned doping step to dry-etch into the diffusion region, select the complex polycrystalline silicon cell region and the frankening process, and dope the polycrystalline silicon according to temperature as described above. In the plug process, the insulating layer can be an oxide layer commonly used in general semiconductor processes, such as a silicon oxide layer; a high-temperature doped polycrystalline silicon layer is formed by a chemical vapor deposition method, and the formation temperature is about 62 ° to 68 °. 0 ° C, thickness is about 350 ~ 750 angstroms, and the impurity-based phosphorus is mixed in the high-temperature-doped polycrystalline silicon layer. The impurity concentration in the high-temperature-doped polycrystalline silicon layer is about 1 (Patoms / cm3; low temperature). The doped polycrystalline silicon layer is formed in a furnace at a temperature of about ° C and has a thickness of about 3500 to 4500 angstroms. In addition, the impurity concentration of the doped polycrystalline silicon layer in the low temperature is about 3500 to 4500 angstroms. The impurity concentration is about

411566 ___ Case No. 87119087 * I Description of the invention (6) '---------- 1 〇atoms / cm3. In addition, You Chu, ^ Sizhe + a, in the first impurity-doping step, the type of material used may be selected from N-type impurities such as odor or bang. The energy for implantation is technical eV 'and its dose is 5 x i. Two = quality: in the second impurity implantation treatment step, the type of material used can be selected from N-type impurities such as dishes or chips' or p-type impurities such as butterflies, ^ from 40keV, and its implantation dose is 5 y · | ni4 +, g is in this position. Half of the time is determined by Putian atoms / cm; at the dry etching point, the S, ν Λ Λ body is six gas ethane, and oxygen (the ratio is about It is 120 seconds; and the planarization process can be completed by chemical mechanical polishing method or etch-back method. The advantages and characteristics of the clarification can be made clearer. I will take the present invention to better examples, sub-matching related drawings, and detailed drawings. The simple description of the formula: The circles 1A to 10 show a conventional self-plugging process. The 2A to 2D diagrams of Gou Yanhan's contact opening show an automatic alignment contact opening of a conventional embedded memory. The plug process of σ ... Random Access § Figures 3A to 3E show the plug process according to the present invention. " Figures 4A to 4E of the half-contact opening show the plug-in process of automatically aligning the contact opening in accordance with the present invention for inserting and taking out memory. J Heart Tongcun [Symbol Description] 100 ~ semiconductor substrate U10, 120 ~ gate; 125 ~ Insulating sidewalls, 130a, 130b, 13 0c ~ Source / drain diffusion; 14 ~~ insulation; 150 ~ auto-aligned contact opening; 160 ~ polycrystalline silicon layer; 18 ~~ plug

L Μ Μ 411 566 _ Case No. 87119087 _ year, month, and year _ V. Description of the invention (7) plug; 2 0 ~ semiconductor substrate; 2 1 0, 2 2 0 ~ gate; 2 2 5 ~ insulating sidewall; 230a, 230b, 230c ~ source / drain diffusion; 230d ~ diffusion; 240 ~ shallow trench isolation; 2 55, 2 60 ~ automatically aligned contact openings; 270 ~ high temperature doped complex Shi Xi layer; 280, 290 ~ plug; 3 0 0 ~ semiconductor substrate; 3 1 0, 3 2 0 ~ gate; 3 3 0 ~ insulating sidewall; 34 0a, 340b, 340c ~ source / drain diffusion Region; 350 ~ insulating layer; 360 ~ self-aligned contact opening; 365 ~ impurity diffusion region; 370 ~ high temperature doped polycrystalline silicon layer; 370 ~~ high temperature doped polycrystalline silicon layer with defective surface, 375 ~ diffusion region, 380 ~ 1¾ temperature push compound crystal dream layer; 385 ~ crystal layer; 390 ~ plug; 400 ~ semiconductor substrate; 410, 420 ~ gate; 425 ~ insulating sidewall; 430a, 430b 430c ~ source / drain diffusion area; 430d ~ diffusion area; 440 ~ shallow trench isolation; 450 ~ insulation layer; 455, 4 6 0 ~ automatic alignment Contact openings; 465a, 465b ~ impurity diffusion region; 470 ~ high temperature doped polycrystalline silicon layer; 470 '~ surface defect South temperature doped complex crystal breaking layer, 475a, 475b ~ diffusion region, 480 ~ high temperature doped Miscellaneous polycrystalline silicon layer; 4 8 5 ~ polycrystalline silicon layer doped with impurities; 490, 500 ~ insertion inspection. Embodiment 1: First, referring to FIG. 3A, a semiconductor substrate 300 is provided, and is formed with gate electrodes 310, 320, insulating sidewalls 330 ', and source / drain diffusion regions 340a, 340b, and 340c. The transistor.

Page 10 411566 Amended case number '87〗 1Q087 V. Description of the invention (8) Secondly, referring to FIG. 3B, an insulating layer 35 is formed on the substrate 300. The insulating layer 3 50 may be, for example, ordinary An oxide layer commonly used in semiconductor processes, such as a silicon oxide layer. Then, the lithography process and the etching technique are used to define the insulating layer 350 'and define a self that exposes the source / drain diffusion region 34ob at the place where a capacitor or a bit line or a plug for connecting an interconnect is intended to be formed'. Align the contact opening 360. Then, the first impurity implantation step is performed so that impurities can enter the substrate 300 through the automatic alignment contact opening 360 and an impurity diffusion region 365 is formed in the source / drain diffusion region 340b to adjust the contact opening contact. Miscellaneous and difficult. The type of impurities used to adjust the impurity impurity content of the contact opening 360 and the energy and dosage during blending can be selected as required. For example, the impurities can be selected from N-type impurities such as cans or gods or P-type impurities such as boron. The implanted impurity used in this embodiment is phosphorus, its implantation energy is 40kev, and its implantation dose is 5 x 1014 a toms / cm2 c. Then, the chemical vapor deposition method is used again at a temperature of about 6 2 〇 ~ 6 § 〇 A polycrystalline silicon layer 370 with a thickness of about 350 ~ 750 angstroms and mixed with impurities is formed in the reaction chamber to cover the insulating layer 3 50 and the inner wall and bottom of the self-aligned contact opening 36 (). Among them, the impurities in the polycrystalline silicon layer 370 can be selected from N-type impurities such as ytterbium and phosphorus or p-type impurities such as boron, and the doped concentration is about 1020 atoms / cm3 °. Then 'Please refer to FIG. 3C' A second impurity doping step is performed, so that the impurities can use the high-temperature doped polycrystalline silicon layer 370 as a slow-weighing layer to enter the diffusion region 365 'and adjust the impurity concentration in the diffusion region 365 to form a junction impurity concentration Better diffusion region 375. As the second impurity cloth

1 side p. 11 411566

-Chamber slurry 87ligns? V. Description of the invention (9), or boron, etc. Its implantation energy In addition, because of the hawthorn processing step, impurities may be selected from N-type impurities such as phosphorus or arsenic, which are used in this embodiment The implantation impurity is 40keV phosphorus, and the implantation dose is 5 xi〇15at〇ms / cm2 ^ field. The quality is doped into the diffusion region 3 6 5 through the high temperature doped polycrystalline silicon layer 37. The surface of the polycrystalline silicon layer 37 ° will be hit by implanted impurities and generate a few defects, and become a high-temperature doped polycrystalline silicon layer 37 ° with a defective surface. Furthermore, referring to FIG. 3D ', using an etching gas composed of hexafluoroethane / oxygen (ratio about 15/1), the substrate surface obtained in the process of FIG. 3C is subjected to a -drying treatment for about 12G seconds. In order to remove the defects on the surface of high temperature doped polycrystalline sand 2 ^ 0 ', it becomes a thinner layer of high temperature doped polycrystalline silicon. Then, in a furnace at a temperature of 540 to 600 t, another compound doped with impurities is formed. The crystalline silicon layer 385 is on the polycrystalline silicon layer 380, and the trench fills the self-aligned contact opening 360 with a thickness of about 350,000 to 4500 angstroms. The impurity in the polycrystalline silicon layer 385 may be selected from n-type impurities such as arsenic and saucer or p-type impurities such as boron, and the planting concentration thereof is about 10 Gatoms / cm3. Finally, referring to FIG. 3E, the excess polycrystalline silicon layer 385 and 380 to the insulating layer 350 are sequentially removed by using an etch-back method or a chemical mechanical polishing method, and a self-aligned contact opening 36 is formed. A polycrystalline silicon layer 385 and a plug 390 composed of 380. The plug 390 has excellent step coverage and trench filling characteristics. In addition to overcoming the shortcomings of poor plug filling characteristics of the current plug material, the plug 390 can provide lower contact resistance (rc) and Leakage characteristics' improve the shortcomings of the current sub-micron or deep sub-micron semiconductor plugging process

P. 2 411566 month

—---- 8711Qn «7 V. Description of the invention (10) Second embodiment: This embodiment is based on the process of the random access memory as described above, and the plug-in process of the embedded dynamics with the opening according to the present invention. The plug process is applied to embedded dynamics and will be automatically aligned with the access memory of the reader in Figures 4A to 4D.-First, please refer to Figure 4A to provide a semiconductor substrate 400, which can be It is divided into a cell area ready to form a memory and a peripheral circuit area connecting the cell areas. Among them, the cell region is formed with a transistor composed of gates 41 and 42, insulating sidewalls 425, and source / drain diffusion regions 43a, 43b, and 43c; peripheral circuit regions Formed with a diffusion region 43 d and a shallow trench isolation for isolation "0. Second, referring to Fig. 4B, an insulating layer 4 5 0 is first formed in the cell shown in Fig. 4A Area and the peripheral circuit area of the substrate 40 surface, wherein the insulating layer can be, for example, an oxide layer commonly used in general semiconductor manufacturing processes, such as a silicon oxide layer. Then, the insulating layer 450 is defined by a lithography process and an etching technique, and is used in the cell area and peripheral circuits. Predetermined positions of the regions define an auto-alignment contact opening 455 and 460, respectively. Then, a first impurity implantation step is performed, so that impurities can enter the substrate 400 through the auto-alignment contact openings 455 and 460, and the source / drain An impurity diffusion region 465a and 465b are formed in the electrode diffusion regions 430b and 430d, respectively, for adjusting the impurity concentration at the interface of the contact opening. Among them, the type of impurity used to adjust the impurity concentration at the interface of the contact opening and the type of impurity during implantation. And the amount of dosage needed to select visual doped implanted impurities used in the examples in this embodiment is phosphorus, and the implantation energy is 40 keV, the implantation dose of 5 X 1 014 atoms / cm2.

Page 13 411566 _ Case No. 8711 卯 87_ Year and Month 傣 ___ Five. Description of the invention (11) Next, a chemical vapor deposition method is used to form a thickness of about 350 ~ in the reaction chamber at a temperature of about 620 ~ 680 ° c. The polycrystalline silicon layer 470 mixed with impurities at 750 angstroms comfortably covers the inner wall and bottom of the insulating layer 450 and the self-aligned contact openings 455 and 460. The impurities in the polycrystalline silicon layer 470 may be selected from N-type impurities such as divine and -phosphorus or P-type impurities such as boron. The impurity used in this embodiment is a dish, and its doped concentration is about 102Q a toms / cm3. Next, referring to FIG. 4C, a second impurity doping step is performed, so that the miscellaneous shells can use the south temperature seeding polycrystalite layer 4 70 as a gentle scale to enter the diffusion regions 465a and 465b, and adjust The impurity concentration ′ in the diffusion regions 465 a and 465 b forms a diffusion region 475 a and 475 b with better impurity concentration at the interface. Among them, the impurities enter the diffusion regions 465a and 465b through the high-temperature doped polycrystalline silicon layer 470. Therefore, the surface of the doped complex polycrystalline layer 470 will be impacted by the implanted impurities toward the temperature and generate some defects. Defective high temperature doped polycrystalline silicon layer 470 '. Furthermore, please refer to FIG. 4D, and apply a dry etching treatment to the surface of the substrate obtained by the process of FIG. 4C using an etching gas composed of hexafluoroethane / oxygen (the ratio is about 15/1). In order to remove the defects on the surface of the high-temperature-doped polycrystalline silicon layer 47 ° in seconds, it becomes a thinner high-temperature-doped multicrystalline fragment layer 480 °. Then, in the furnace, the temperature is 5 4 0 ~ 60 0 ° C. At temperature, another layer of polycrystalline silicon layer 485 mixed with impurities is pushed onto the polycrystalline silicon layer 480, and the trenches are self-aligned with the contact openings 455 and 460, and the thickness is about 3500 to 4500 angstroms. The impurity in the polycrystalline silicon layer 485 may be selected from N-type impurities such as arsenic and phosphorus or P-type impurities such as boron. The impurity used in this embodiment is a dish, and its doped concentration

Page 14 411566-^-87119081 ___ month day Article V. Description of the invention (12) One ----- about l02Qat〇Bis / cin3. Finally, please refer to FIG. 4E, and use the etch-back method or chemical mechanical polishing method to sequentially remove the excess polycrystalline silicon layer 485 and 480 to the insulating layer, and within the self-aligned contact openings 455 and 46 °, respectively. Formation—Plugs 49 and 500 consisting of polycrystalline silicon layers 485 and 480. Among them, the plugs 49 and 0 have excellent step coverage and trench filling characteristics. In addition to overcoming the current shortcomings of poor plug material trench filling characteristics, the plugs 49 and 500 can be inserted separately. -Type dynamic random access memory prepares capacitor lower electrodes and bit lines with lower contact resistance and leakage characteristics, which improves the disadvantages of the current submicron or deep submicron semiconductor plug manufacturing process. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. "Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention." Uchida 5 = The scope of patent protection in this month

Claims (1)

411566 • MM 87Π9087 6. Scope of patent application J: __S Including—a plug process for forming an automatic alignment contact window, the steps of which include providing a contact window—a substrate with a semiconductor element formed; forming an insulating layer on the substrate, and defining the first impurity doping of the alignment interface The implantation step allows impurities to enter the substrate through the self-contact window, and forms a diffusion region; I aim to form a high-temperature doped polycrystalline silicon layer to cover the surface of the insulating layer and distant self-aligned contacts. The inner wall and bottom of the window; a second impurity doping step is performed, so that impurities can use the high-temperature doped silicon layer as a slow-weighing layer to enter the diffusion region, and adjust the impurity concentration in the diffusion region; Shi Yigan A lithography process to remove a portion of the high temperature doped polycrystalline silicon layer; forming a low temperature doped polycrystalline silicon layer on the high temperature doped polycrystalline silicon layer; and trench filling the self-aligned contact window; and applying a flat surface Chemical treatment, sequentially removing the excess of the low-temperature doped polycrystalline stone layer and the sulphur-doped polycrystalline silicon layer to the insulating layer, and a connection is formed in the automatic alignment contact opening. Plugs for semiconductor components. 2 _ The process as described in item 1 of the scope of patent application, wherein the insulating layer is an oxide layer. The insulating layer, the high-temperature doped 3 ′, and the process described in item 2 of the scope of the patent application is an oxide dream layer. 4_ The process as described in item 1 of the scope of the patent application. The hetero-multicrystalline layer is formed by chemical vapor deposition. Page 16 Amendment 5. The process as described in item 4 of the scope of patent application, wherein the formation temperature of the high-temperature-doped polycrystalline hair layer is about 620 to 68 ° C. 6. The process as described in item 5 of the scope of the patent application. The impurities in the heteromulticrystalline silicon layer are phosphorus. 7 · The impurity concentration in the heteromulticrystalline hard layer according to the process described in item 6 of the patent application range is about 102 Datoms / Cm3, where the high temperature is mixed therein and the high temperature is mixed 8. The process described in item 7 of the patent application range The thickness of the hetero-multicrystalline silicon layer is about 350 ~ 750 angstroms. 9 · According to the process described in item 1 of the scope of patent application, a hetero-multicrystalline silicon layer is formed in a furnace. 10. The process described in item 9 of the scope of patent application for forming a hetero-multicrystalline silicon layer has a temperature of about 540 to 600 ° C. 11. The process described in item 10 of the scope of patent application is doped with impurities in the polycrystalline silicon layer based on phosphorus. 12. The impurity concentration in the doped polycrystalline silicon layer is about 1 (Patoms / cm3) in the process described in item 11 of the scope of patent application. 13. The process described in item 12 of the scope of patent application, wherein the low temperature doping The thickness of the polycrystalline silicon layer is about 3,500 to 4,500 angstroms. 14. The impurity implantation process used in the process described in item 1 of the scope of the patent application, the impurity is phosphorus 15. As described in the scope of patent application 14 The implantation energy of the process is 40 keV, and the implantation dose is 5 × 1014 atoms / cin2. 16. The process described in item 1 of the scope of patent application, wherein in the second impurity implantation treatment step, Impurity is phosphorus. The high temperature is mixed with the low temperature and the low temperature is pushed. The low temperature is the low temperature. Page 17 Correction 411566 _ Case No. 87119087 6. Scope of patent application 1 7. The process described in the 16th paragraph of the scope of application for patent application, wherein the implantation energy of the impurity is 40 keV, and the implantation dose thereof is 5 X 10 μatoms / cm2. 1 8. The process described in item 丨 of the scope of patent application 'wherein in the dry etching process step, the etching gas used is hexafluoroethane / oxygen (ratio is about 15/1) and the processing time is about It was 120 seconds. 1 9. The process according to item 1 of the scope of patent application, wherein the planarization treatment is performed by a chemical mechanical polishing method. 2 0. The process as described in item 1 of the scope of patent application, wherein the planarization process uses a back-cut method. 21. A plug-in process for automatically aligning a contact window of an embedded dynamic random access memory, the steps include: providing a semiconductor substrate including a cell area and a peripheral circuit area; and forming an insulating layer on the A contact window is defined on the substrate and in the cell area and the side circuit area respectively; the cell area undergoes the first impurity doping step so that impurities can pass through the fine and: and peripheral circuit areas respectively. The self-aligned contact window enters the substrate and) forms a diffusion region; the surface and 20% of a high-temperature doped polycrystalline silicon layer comfortably cover the surface of the insulating layer, and the inner wall and bottom of the self-aligned contact window D ; The second step of doping f is doped with polycrystalline osmium 3, so that the impurity f can use the high-temperature doped impurity t as a slow-weighing layer to enter the diffusion region, and adjust the concentration of the diffusion region and Jia, and Shi Yigan Etching process' removes part of this high temperature doped polycrystalline silicon layer Page 411 566 On the correction, the touch window forms a low-temperature-doped polycrystalline silicon layer on the high-temperature-doped polycrystalline silicon layer and fills the self-aligned connection of the cell region and the peripheral circuit region, respectively, and applies a planarization treatment, The excess low temperature doped polycrystalline stone layer and the high temperature doped polycrystalline silicon layer are sequentially removed until the insulating layer. 2 2. The process as described in item 2 丨 of the scope of patent application, wherein the insulating layer is an oxide layer. 23. The process as described in claim 22, wherein the insulating layer is a silicon oxide layer. 24. The process as described in item 2 of the patent application scope, wherein the high-temperature doped polycrystalline silicon layer is formed by a chemical vapor deposition method. 25. The process according to item 24 of the scope of the patent application, wherein the formation temperature of the high-temperature-doped polycrystalline silicon layer is about 620-1680. (:. 2 6. The process as described in item 25 of the scope of patent application, wherein the impurities in the high temperature doped polycrystalline spar layer are lin. 27. The process as described in item 26 of the scope of patent application, wherein the The impurity concentration in the high-temperature doped polycrystalline spar layer is about 10 2 Datoms / cm3. 28. The process described in item 27 of the scope of application for patents, wherein the thickness of the high-temperature-doped polycrystalline silicon layer is about 35 ° ~ 75 0 angstroms. 2 9. The process according to item 21 of the scope of the patent application, wherein the low-temperature doped multicrystalline fragment is formed in a furnace. 30, the process according to item 29 of the scope of patent application. Where the low temperature Page 19 ----- _ ___________ Days, amendments_ 6. Application scope of patents Impurities in doped polycrystalline stone cans. 32. The process as described in item 31 of the scope of the patent application, wherein the impurity concentration in the high-temperature doped polycrystalline silicon layer is about 102 G a toms / cm3. 3 3. The process according to item 32 of the scope of patent application, wherein the thickness of the low-temperature-doped polycrystalline silicon layer is about 350,000 to 4500 Angstroms. 34. The process as described in claim 21, wherein the impurity used in the first impurity implantation treatment step is phosphorus. 3 5. The process as described in item 34 of the scope of patent application, wherein the implantation energy of the impurity is 40 keV, and the implantation dose thereof is 5 x 1014 atoms / cm2. 36. The process as described in item 21 of the scope of patent application, wherein the impurity used in the second impurity cloth haw treatment step is phosphorus. 37. The process as described in item 36 of the scope of patent application, wherein the implantation energy of the impurity is 40 keV, and the implantation dose thereof is 5xi0i4atoms / cm2. 38. The process as described in item 21 of the scope of patent application, wherein the last-name gas used in the dry neodymium-etching process step is hexafluoroethane / oxygen (ratio is about 15/1) and the processing time is about丨 2 seconds. 3 9. The process according to item 21 of the scope of patent application, wherein the Hiragaki chemical treatment is completed by chemical mechanical polishing ° 40. The process according to item 21 of the scope of patent application, wherein the Hiragaki chemical treatment is performed by using back Last name carved. ___