TW405223B - Method for avoiding the poisoning at the trench of the dual damascene structure and the dielectric hole - Google Patents

Method for avoiding the poisoning at the trench of the dual damascene structure and the dielectric hole Download PDF

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TW405223B
TW405223B TW087112287A TW87112287A TW405223B TW 405223 B TW405223 B TW 405223B TW 087112287 A TW087112287 A TW 087112287A TW 87112287 A TW87112287 A TW 87112287A TW 405223 B TW405223 B TW 405223B
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Taiwan
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metal
layer
patent application
dielectric layer
scope
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TW087112287A
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Kuen-Lin Wu
Hung-Bo Lu
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United Microelectronics Corp
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Priority to TW087112287A priority Critical patent/TW405223B/zh
Priority to US09/166,821 priority patent/US6013581A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0384Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09Treatments involving charged particles
    • H05K2203/095Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/002Etching of the substrate by chemical or physical means by liquid chemical etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

A7 B7 3241twf.doc./005 405223 五、發明説明(丨) - 本發明是有關於一種半導體元件多重內連線 (Multilevel Interconnects)的製造方法,且特別是有關於 一種避免雙重金屬鑲嵌(Dual Damascene)結構之溝渠與介 層窗毒化(Poison)的方法。 雙重金屬鑲嵌製程是一種將金屬內連線巧妙地嵌入於 絕緣層的技術。其作法係在基底上先形成一層絕緣層,並 將其平坦化後,再依照所需之金屬導線的圖案以及介層窗 的位置,蝕刻絕緣層,以形成溝渠以及—介層窗口(Hole)。 然後’再於基底上沈積一層金屬層,使其塡滿溝渠與介層 窗口’以同時形成金屬導線與介層窗。最後,再以化學機 械硏磨法(Chemical-Mechanical Polishing,CMP)將元件 的表面平坦化,即完成雙重金屬鑲嵌的製作。由於採用雙 重金屬鑲嵌的方式,可以避免典型先形成介層窗再形成金 屬導線的方法在微影製程中所面臨疊對誤差(Overlay Error)與製程偏差(process Bias)的問題,而使元件的可 靠度增加,並且使製程能力提昇,因此,在元件高度積集 化之後,雙重金屬鑲嵌已逐漸成爲半導體工業所採用的一 種技術。 第1A圖至第1D圖爲習知一種雙重金屬鑲嵌結構的製 造流程剖面圖。首先,請參照第1A圖,在已形成有金屬層 102的基底1〇〇上依序形成一層蝕刻終止層104與介電層 106,並將介電層1〇6平坦化,以使介電層1〇6的厚度與所 需之介層窗的深度相當。接著,再於介電層1〇6上依序覆 蓋一層蝕刻終止層108與介電層110 ’並進行平坦化’以使 3 本紙張尺度適用中囷國家榡準(CNS ) A4規格(210X297公嫠) —.J----------裝--^---i--訂------線 (請先閲讀背面之注意事項再填寫本頁) A7 B7 3241twf.doc./0054 05223 五、發明説明(>) · 介電層110的厚度與預定形成之雙重金屬鑲嵌結構中金屬 層(金屬線)所需之厚度相同。其中,典型的介電層106 與介電層110之材質包括氧化矽,形成的方法例如爲化學 氣相沈積法;蝕刻終止層104之材質包括氮化矽,形成的 方法例如爲化學氣相沈積法;蝕刻終止層108之材質包括 氮氧化矽,形成的方法例如爲化學氣相沈積法。 然後,請參照第1B圖,定義介電層110,以在介電層 11〇中形成開口 112,此開口 112即爲預定形成之介層窗所 在的位置,其對應於金屬層102的上方。典型的方法係在 介電層110上形成一層具有開口圖案的光阻層,接著,以 光阻層爲蝕刻罩幕,蝕刻終止層108爲蝕刻終點,蝕刻介 電層110,其後再將光阻層剝除,以在介電層110中形成開 □ 112。 其後,請參照第1C圖,去除開口 112所裸露之蝕刻終 止層108,以使開口 112的圖案轉移至蝕刻終止層108。然 後,再去除部份的介電層110、介電層106與蝕刻終止層 104,以使介電層110的開口 112面積更廣而形成溝渠114, 並使開口 112的圖案繼續往下轉移至介電層106與蝕刻終 止層104而形成介層窗開口 II6,裸露出金屬層1〇2,使溝 渠114與介層窗開口 116共同組成雙重金屬相嵌開口 118。 習知的方法係在介電層110上形成一層圖案化的光阻層(未 繪示於圖中),並以光阻層與蝕刻終止層108爲蝕刻罩幕, 蝕刻終止層104爲蝕刻終點,蝕刻介電層11〇與介電層 106,其後,再以蝕刻終止層108爲蝕刻罩幕,蝕刻去除蝕 (請先閱讀背面之注項再填寫本頁) -* 鳑逆部中头枝準^h-T消合作初印來 4
3241twf.doc./00540 5 2 2 Ο A7 _________—~~___ B7 五、發明説明(今)" ;- 刻終止層104,以使介電層11〇中開口 114的面積更廣,而 形成溝渠114,並使開口 112的圖案往下轉移至介電層1〇6 與蝕刻終止層104,而形成介層窗開口 1]6,然後,再將光 阻層剝除’以形成雙重金屬相嵌開口 118。 之後,請參照第1D圖,在基底100上覆蓋一層導體材 料,使其塡滿雙重金屬鑲嵌開口 Π8,並進行平坦化,以形 成雙重金屬鑲嵌結構126。典型的導體材料例如爲具有鈦/ 氮化鈦作爲阻障層/黏著層122的金屬層124,例如金屬銘、 金屬鎢或金屬銅。其作法係在基底100上先形成一層與雙 重金屬鑲嵌開口 U8共形的阻障層/黏著層122,然後,再 於基底100上形成一層金屬層124使其塡滿雙重金屬鑲嵌 開口 118。其後,再進行平坦化以去除覆蓋於介電層11〇 上的阻障層/黏著層122與金屬層124,而形成與金屬層ι〇2 電性藕接的雙重金屬相嵌結構126。 隨者兀件的局度積集化,位於兩金屬層之間的金屬層 間介電層(Inter-Metal Dielectric) 110與1〇6所造成的寄生 電容(Parasitic Capacitance)問題愈形嚴重。因此,在深 次微米以下的製程中’多採用低介電常數的材料來做爲金 屬層間介電層110與’以減少寄生電容所衍生的電阻 電容時間的延遲(Resistance-Capacitance Time Delay) 應。一般常用之低介電常數的材料包括無機類的材料,例 如HSQ、FSG等’以及有機類的材料,例如旋塗式高分子 (Spin on Polymer ’ SOP) ' Flare、SILK、Parylene 等 於這一些低介電常數的介電材料易吸附水氣,因此,将ζ 5 本紙張尺度適用中國國家標率(CNS ) Α4规格(21〇Χ297公釐)—- ---- 1/---------裝--"------訂------線 (請先閲讀背面之注意事項再填寫本頁) 3241twf.doc./005 405223 A7 B7 五、發明説明(</ ) · 一些材質應用於上述的製程中時,在導體材料塡入於雙重 金屬相嵌開口 118時,易造成介電層的出氣(0utgassing), 而導致雙重金屬相嵌結構126之金屬溝渠與介層窗的毒 化,影響元件的電性與良率。 因此’本發明的目的就是在提供一種雙重金屬鑲嵌結 構的製造方法,以避免使用低介電常數之介電材料而造成 雙重金屬相嵌結構中之溝渠與介層窗的毒化現象。 根據本發明的目的,提出一種避免雙重金屬鑲嵌結構之 溝渠與介層窗毒化的方法,其作法係在雙重金屬鑲嵌開口 形成之後,以電漿處理雙重金屬鑲嵌開口所暴露的介電層 表面’使介電層的表面結構更爲緻密,以避免介電層在導 體材料塡入雙重金屬鑲嵌開口之後造成出氣現象,而導致 雙重金屬鑲嵌結構之溝渠與介層窗的毒化。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂,下文特舉一較佳實施例,並配合所附圖式,作詳細 說明如下: 圖式之簡單說明: 第1A圖至第1D圖爲習知一種雙重金屬鑲嵌結構的製 造流程剖面圖;以及 第2A圖至第2E圖爲依照本發明實施例一種雙重金屬 鑲嵌結構的製造流程剖面圖。 圖式標記說明: 100, 200 :基底 102, 202 :導體層 (讀先閲讀背面之注意事項再填寫本頁) •秦 -β Γ
I 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) 好逆部中戎«·準^h-T消费合竹相印衆 405323 Α7 3241twf.doc./005 五、發明説明(π ' 104, 108, 204, 208 :蝕刻終止層 106, 1 10, 206, 206a, 210, 210a :介電層 112, 212 :開口 Π4, 214 :溝渠 116, 216 :介層窗開口 118, 218 :雙重金屬鑲嵌開口 122, 222 :阻障層/黏著層 124, 224 :金屬層 126, 226 :雙重金屬鑲嵌結構 220 :電漿 實施例 第2A圖至第2E圖爲依照本發明實施例一種雙重金屬 鑲嵌結構的製造流程剖面圖。首先,請參照第2A圖,在已 形成有導體層202的基底200上依序形成一層蝕刻終止層 204與介電層206,並將介電層206平坦化,以使介電層206 的厚度與所需之介層窗的深度相當。接著,再於介電層206 上依序覆蓋一層蝕刻終止層208與介電層210,並進行平坦 化’以使介電層210的厚度與預定形成之雙重金屬鑲嵌結 構中金屬層(金屬線)所需之厚度相同。其中,典型的介 電層206與介電層210之材質包括氧化矽、氟摻雜氧化矽 (F Doped Silicon Oxide,FSG)、磷矽玻璃(PSG)與低 介電常數之介電材質,例如爲芳香環(Aromatic Ring)高 分子、膠體物質(Gel)、甲基矽氧烷(Methylsiloxane)化 合物、氫化砂倍半氧化物(Hydrogen Silsesquioxane,HSQ) 7 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨0 X 297公釐) (請先閲讀背面之注意事項再填寫本頁) t 丁 405223 3241twf.doc./005 五、發明说明(A) ' 等旋塗式高分子(Spin on Polymer ’ SOP);蝕刻終止層204 之材質包括氮化矽,形成的方法例如爲化學氣相沈積法; 蝕刻終止層208之材質包括氮氧化矽,形成的方法例如爲 化學氣相沈積法。 然後,請參照第2B圖,定義介電層210,以在介電層 210中形成開口 212,此開口 212即爲預定形成之介層窗所 在的位置,其對應於導體層202的上方。典型的方法係在 介電層210上形成一層具有開口圖案的光阻層,接著,以 光阻層爲蝕刻罩幕,蝕刻終止層208爲蝕刻終點,蝕刻介 電層210,其後再將光阻層剝除,以在介電層210中形成開 □ 212。 其後,請參照第2C圖,去除開口 212所裸露之蝕刻終 止層208,以使開口 212的圖案轉移至蝕刻終止層208。然 後’再以蝕刻終止層204爲蝕刻終點,去除部份的介電層 21〇以使開口 212面積更廣而形成溝渠214,並在同時去除 部份的介電層206使開口 212的圖案往下轉移至介電層 2〇6,然後再去除部份的終止層204使開口 212的圖案繼續 往下轉移至終止層204,以形成介層窗開口 216,裸露出導 體層202,使溝渠214與介層窗開口 216共同組成雙重金屬 相嵌開口 218。習知的方法係在介電層210上形成一層圖案 化的光阻層(未繪示於圖中),並以光阻層與蝕刻終止層 208爲蝕刻罩幕,蝕刻終止層204爲蝕刻終點,蝕刻介電層 210與介電層206,其後,再以蝕刻終止層208爲蝕刻罩幕, 飽刻去除蝕刻終止層204,以使介電層210中開口 214的面 8 (讀先閲讀背面之注意事項再填寫本頁) 裝· 本紙張尺度通用中國固家樣牟(CNS )八4胁(21GX297公釐) 405223 3241twf.doc./005 A7 B7 好米部中λ*.Γ2?-^Μ工消費合竹=fi印策 五、發明説明(7 ) * 積更廣,而形成溝渠214,並使開口 212的圖案往下轉移至 介電層206與蝕刻終止層204,而形成介層窗開口 216,然 後,再將光阻層剝除的方式,以形成雙重金屬相嵌開口 218。由於介電層206與基底200之間形成有一層餓刻終止 層204,因此,在微影時對準失誤(Misalign)而造成開口 212偏移時,此蝕刻終止層204可以在介電層210與介電層 206的蝕刻製程中作爲蝕刻的終點,以避免過度蝕刻介電層 206,而使後續所形成之雙重金屬相嵌結構與基底中200的 其他導體層造成短路的現象。 之後,請參照第2D圓,本發明的關鍵步驟係雙重金屬 相嵌開口 218形成之後,以電漿220處理雙重金屬相嵌開 口 218所暴露之介電層206與介電層210的表面,以使介 電層206與210的表面固化(Curing)而形成表面結構更爲 緻密的介電層206a與介電層210a。其中,電漿的種類係選 自由氫氣、氮氣、一氧化二氮與氨氣所組成之族群,其能 量約爲100瓦〜1000瓦左右。 其後,請參照第2E圖,在基底200上覆蓋一層導體材 料,使其塡滿雙重金屬鑲嵌開口 218,並進行平坦化,以形 成雙重金屬鑲嵌結構226。典型的導體材料例如爲具有阻障 層/黏著層222的金屬層224。其中,障層/黏著層222之材 質例如爲鈦/氮化鈦、鉅、氮化鉅、氮化鎢' 氮化鈦或氮砍 化鉅;金屬層224之材質例如爲金屬鋁、金屬鎢或金屬銅。 其作法係在基底200上先形成一層與雙重金屬鑲嵌開口 218共形的阻障層/黏著層222,然後,再於基底200上形成 9 --1--------裝--K---_--訂------線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4规格(2丨0X297公嫠) 405223 3241twf.doc./005 五、發明説明(?) · 一層金屬層224使其塡滿雙重金屬鑲嵌開口 218。其後,再 進行平坦化’例如,利用化學機械硏磨法,硏磨元件的表 面’以去除覆蓋於介電層210上的阻障層/黏著層222與金 屬層224’而形成與導體層202電性藕接的雙重金屬枏嵌結 構 226。 由於以電漿處理之介電層206a與介電層210a的表面 結構極爲緻密’因此,將導體材料塡入雙重金屬相嵌開口 218之後,可以避免介電層2〇6a與介電層21〇a的出氣現 象’防止雙重金屬相嵌結構之金屬溝渠與介層窗的毒化。 因此’本發明的特徵之一是可以使用低介電常數之介 電材料’以減少元件的寄生電容,提高元件的執行效能 本發明的另一特徵是本發明可以避免使用低介電常數 之介電材料造所造成雙重金屬相嵌結構中之溝渠與介層窗 的毒化現象,因此可以增進元件的可靠性。 經浐部中戒«.隼而只-T消资合作私印絮 - J-----穿-- (請先閲讀背面之注項再填寫本頁) 雖然本發明已以一雙重金屬相嵌的製造方法揭露如 上’然而其並非用以限定本發明。任何熟習此技藝者當明 白本發明之以電漿處理介電層的方法,在不脫離本發明之 精神和範圍內,當可作各種之更動與潤飾,其可以適用於 各種製程所形成的雙重金屬相嵌開口、介層窗開口、與接 ^窗開口之中,因此本發明之保護範圍當視後附之申請專 利範圍所界定者爲準。 Τ网国家樣準(CNS )从胁(21〇χ297公兼)

Claims (1)

  1. 經濟部中央標準局員工消費合作社印製 3241twf.doc.4P 5 22 3 B8 , D8 六、申請專利範圍 1. 一種避免雙重金屬鑲嵌結構之溝渠與介層窗毒化 的方法,包括下列步驟: 提供一基底,該基底中已形成有一導體層; 於該基底上形成一介電層; 於該介電層中形成一溝渠與一介層窗開口,以共同形成 一雙重金屬相嵌開口,裸露出該導體層; 以一電漿處理該雙重金屬相嵌開口所裸露的該介電電 層表面;以及 於該雙重金屬相嵌開口中塡入一導體材料,以形成一雙 重金屬相嵌結構。 2. 如申請專利範圍第1項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該介電層之材質包括 氧化矽、氟摻雜氧化矽與磷矽玻璃其中之一。 3. 如申請專利範圍第1項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該介電層之材質包括 低介電常數之介電材料。 4. 如申請專利範圍第1項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該介電層之材質包括 旋塗式高分子。 5. 如申請專利範圍第4項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該介電層之材質包括 芳香環高分子、膠體物質、甲基矽氧烷化合物、氫化矽倍 半氧化物其中之一。 6. 如申請專利範圍第1項所述之避免雙重金屬鑲嵌結 — I I I I I I I I 裝— — I I __ — 訂 I I I I 線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) A8 B8 C8 D8 405223 3241twf.doc./005 六、申請專利範圍 構之溝渠與介層窗毒化的方法,其中該電漿之種類係選自 由氫氣、氮氣、一氧化二氮與氨氣所組成之族群。 7. 如申請專利範圍第丨項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該電漿之能量約爲1〇〇 瓦〜1000瓦左右。 8. 如申請專利範圍第1項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該導體材料包括與該 雙重金屬相嵌開口共形的一阻障層/黏著層與一金屬層。 9. 如申請專利範圍第8項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該阻障層/黏著層之材 質包括鈦/氮化鈦、钽、氮化钽、氮化鎢、氮化鈦與氮矽化 組其中之一。 10. 如申請專利範圍第8項所述之避免雙重金屬鑲嵌結 構之溝渠與介層窗毒化的方法,其中該金屬層之材質包括 金屬鋁、金屬鎢與金屬銅其中之一。 11. 一種雙重金屬鑲嵌結構的製造方法,包括下列步 驟: 提供一基底,該基底中已形成有一導體層; 於該基底上依序形成一第一蝕刻終止層、一第一介電 層、一第二蝕刻終止層與一第二介電層; 以該第二飽刻終止層爲蝕刻終點’將該第二介電層圖案 化’以在該第二介電層中形成一開口,該開口對應於該導 體層的上方; 去除該開口所裸露之該第二蝕刻終止層,使該開口的圖 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) —.--------裝— (請先閲讀背面之注意事項再填寫本頁) 訂 線· 經濟部中央標準局員工消費合作社印製 3241twf.doc4fl 5223 Α8 B8 C8 , D8 六、申請專利範圍 ^ : 案轉移至該第二蝕刻終止層; 以該第一蝕刻終止層與該第二蝕刻終止層爲蝕刻終點 與触刻罩幕,去除部份該第一介電層與部份該第一介電 層,以使該第二介電層之該開口形成面積更廣的一溝渠, 同時使該開口的圖案轉移至該第一介電層; 去除部份該第一蝕刻終止層’以使該開口的圖案轉移至 該第一蝕刻終止層,而形成一介層窗開口,裸露出該導體. 層,使該介層窗開口與該溝渠共同形成一雙重金屬相嵌開 Ρ ; 以一電漿處理該雙重金屬相嵌開口所裸露的該第一與 該第二介電電層表面;以及 於該雙重金屬相嵌開口中塡入一導體材料,以形成一雙 重金屬相嵌結構。 12. 如申請專利範圍第u項所述之雙重金屬鑲嵌結構 的製造方法,其中該第一蝕刻終止層之材質包括氮化矽, 該第二蝕刻終止層之材質包括氮氧化矽。 13. 如申請專利範圍第n項所述之雙重金屬鑲嵌結構 的製造方法’其中該介電層之材質包括氧化矽、氟摻雜氧 化矽與磷矽玻璃其中之一。 14·如申請專利範圍第11項所述之雙重金屬鑲嵌結構 的製造方法,其中該介電層之材質包括低介電常數之介電 材料。 15.如申請專利範圍第11項所述之雙重金屬鑲嵌結構 的製造方法’其中該介電層之材質包括旋塗式高分子。 13 ----------^L——:--^------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印装 本紙張纽適用中關家轉(CNS) Α4^ χ 29 ) A8 B8 C8 D8 3241twf.doA05^ ^ ^ ^ 六、申請專利範圍 16·如申請專利範圍第15項所述之雙重金屬鑲嵌結構 的製造方法,其中該介電層之材質包括芳香環高分子、膠 體物質 '甲基矽氧烷化合物、氫化矽倍半氧化物其中之一。 17.如申請專利範圍第Π項所述之雙重金屬鑲嵌結構 的製造方法,其中該電漿該電漿之種類係選自由氫氣、氮 氣'一氧化二氮與氨氣所組成之族群。 18·如申請專利範圍第U項所述之雙重金屬鑲嵌結構 的製造方法,其中該電漿之能量約爲100瓦〜1000瓦左右。 19·如申請專利範圍第11項所述之雙重金屬鑲嵌結構 的製造方法,其中該導體材料包括與該雙重金屬相嵌開口 共形的一阻障層/黏著層與一金屬層。 20. 如申請專利範圍第19項所述之雙重金屬鑲嵌結構 的製造方法’其中該阻障層/黏著層之材質包括鈦/氮化鈦、 钽、氮化鉅、氮化鎢、氮化鈦與氮矽化鉅其中之一。 21. 如申請專利範圍第19項所述之雙重金屬鑲嵌結構 的製造方法’其中該金屬層之材質包括金屬鋁、金屬鎢與 金屬銅其中之^一'。 22. 如申請專利範圍第10項所述之雙重金屬鑲嵌結構 的製造方法,更包括一平坦化製程。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) U9- (請先閲讀背面之注意事項再填寫本頁) 4° 經濟部中央標準局員工消費合作社印袈
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