TW357358B - Dram architecture with aligned data storage and bond pads - Google Patents

Dram architecture with aligned data storage and bond pads

Info

Publication number
TW357358B
TW357358B TW086109927A TW86109927A TW357358B TW 357358 B TW357358 B TW 357358B TW 086109927 A TW086109927 A TW 086109927A TW 86109927 A TW86109927 A TW 86109927A TW 357358 B TW357358 B TW 357358B
Authority
TW
Taiwan
Prior art keywords
bond pad
bond pads
data
array
lines
Prior art date
Application number
TW086109927A
Other languages
English (en)
Inventor
Masayuki Nakaumura
Brent S Haukness
Takesada Akiba
Original Assignee
Texas Instruments Inc
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc, Hitachi Ltd filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW357358B publication Critical patent/TW357358B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
TW086109927A 1996-07-11 1997-11-11 Dram architecture with aligned data storage and bond pads TW357358B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2156596P 1996-07-11 1996-07-11

Publications (1)

Publication Number Publication Date
TW357358B true TW357358B (en) 1999-05-01

Family

ID=21804930

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086109927A TW357358B (en) 1996-07-11 1997-11-11 Dram architecture with aligned data storage and bond pads

Country Status (6)

Country Link
US (1) US5995404A (zh)
EP (1) EP0818787A3 (zh)
JP (1) JPH10134564A (zh)
KR (1) KR100499844B1 (zh)
SG (1) SG74595A1 (zh)
TW (1) TW357358B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5966343A (en) * 1997-01-02 1999-10-12 Texas Instruments Incorporated Variable latency memory circuit
GB2348317B (en) * 1998-06-23 2001-03-07 Samsung Electronics Co Ltd An arrangement of data input/output circuits for use in a semiconductor memory device
JP2000182370A (ja) * 1998-12-16 2000-06-30 Toshiba Corp 半導体記憶装置
KR100327330B1 (ko) * 1998-12-17 2002-05-09 윤종용 램버스디램반도체장치
JP3557114B2 (ja) 1998-12-22 2004-08-25 株式会社東芝 半導体記憶装置
US6457094B2 (en) 1999-01-22 2002-09-24 Winbond Electronics Corporation Memory array architecture supporting block write operation
US6157560A (en) * 1999-01-25 2000-12-05 Winbond Electronics Corporation Memory array datapath architecture
KR100408716B1 (ko) * 2001-06-29 2003-12-11 주식회사 하이닉스반도체 오토프리챠지 갭리스 보호회로를 가진 반도체 메모리소자의 오토프리챠지장치
JP3990125B2 (ja) 2001-08-29 2007-10-10 株式会社東芝 半導体メモリチップおよび半導体メモリ
DE10223726A1 (de) 2002-05-28 2003-12-24 Infineon Technologies Ag Integrierter Speicher in Prefetch-Architektur und Verfahren zum Betrieb eines integrierten Speichers
JP4267006B2 (ja) * 2006-07-24 2009-05-27 エルピーダメモリ株式会社 半導体記憶装置
JP2009009633A (ja) * 2007-06-27 2009-01-15 Elpida Memory Inc 半導体記憶装置
JP5419431B2 (ja) 2008-11-28 2014-02-19 ルネサスエレクトロニクス株式会社 半導体記憶装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3832328A1 (de) * 1988-09-23 1990-03-29 Broadcast Television Syst Speicheranordnung fuer digitale signale
US5315130A (en) * 1990-03-30 1994-05-24 Tactical Fabs, Inc. Very high density wafer scale device architecture
EP0544247A3 (en) * 1991-11-27 1993-10-20 Texas Instruments Inc Memory architecture
US5550394A (en) * 1993-06-18 1996-08-27 Texas Instruments Incorporated Semiconductor memory device and defective memory cell correction circuit
US5373470A (en) * 1993-03-26 1994-12-13 United Memories, Inc. Method and circuit for configuring I/O devices
JPH0785655A (ja) * 1993-09-16 1995-03-31 Mitsubishi Electric Corp 半導体記憶装置
WO1995016266A1 (en) * 1993-12-07 1995-06-15 Texas Instruments Italia Spa Improvements in or relating to field memories
KR0154601B1 (ko) * 1994-05-20 1998-12-01 기다오까 다까시 반도체 메모리 장치에서 전원공급 패드의 배열
JP3421441B2 (ja) * 1994-09-22 2003-06-30 東芝マイクロエレクトロニクス株式会社 ダイナミック型メモリ
JP3160480B2 (ja) * 1994-11-10 2001-04-25 株式会社東芝 半導体記憶装置
JP3486723B2 (ja) * 1995-08-29 2004-01-13 日本テキサス・インスツルメンツ株式会社 半導体メモリ装置
US5724281A (en) * 1996-01-31 1998-03-03 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having improved wiring in input terminal
US5802005A (en) * 1996-09-23 1998-09-01 Texas Instruments Incorporated Four bit pre-fetch sDRAM column select architecture

Also Published As

Publication number Publication date
KR980012545A (ko) 1998-04-30
KR100499844B1 (ko) 2006-04-21
JPH10134564A (ja) 1998-05-22
EP0818787A3 (en) 1999-08-25
US5995404A (en) 1999-11-30
EP0818787A2 (en) 1998-01-14
SG74595A1 (en) 2000-08-22

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees