TW332272B - Data processor and data processing system - Google Patents

Data processor and data processing system

Info

Publication number
TW332272B
TW332272B TW085114272A TW85114272A TW332272B TW 332272 B TW332272 B TW 332272B TW 085114272 A TW085114272 A TW 085114272A TW 85114272 A TW85114272 A TW 85114272A TW 332272 B TW332272 B TW 332272B
Authority
TW
Taiwan
Prior art keywords
instruction
selector
accordance
unit
executing unit
Prior art date
Application number
TW085114272A
Other languages
Chinese (zh)
Inventor
Shigezumi Matsui
Susumu Kaneko
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW332272B publication Critical patent/TW332272B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets

Abstract

A data processor, which mainly fetches instruction by instruction fetching unit, decodes instruction latched in instruction register by instruction decoder, executes instruction in accordance with decoded result by instruction executing unit, comprises the following characteristics: (1) Many task buffers individually having program storing area and indicator for reading instruction stored in the area in sequence; (2) Buffer means dedicated to each task buffer and disposed to the instruction executing unit; (3) Selector for selectively connecting one of many task buffers and instruction fetching unit to the instruction register; (4) Switching control means for forcing the selector to select the instruction fetching unit in initial state, and in accordance with internal or external happened events controlling the selector; (5) In accordance with the instruction executing unit control forcing all or part of many task buffers to form interface means with external so as to write data into interface.
TW085114272A 1996-09-27 1996-11-20 Data processor and data processing system TW332272B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/002819 WO1998013759A1 (en) 1996-09-27 1996-09-27 Data processor and data processing system

Publications (1)

Publication Number Publication Date
TW332272B true TW332272B (en) 1998-05-21

Family

ID=14153908

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085114272A TW332272B (en) 1996-09-27 1996-11-20 Data processor and data processing system

Country Status (3)

Country Link
JP (1) JP3778573B2 (en)
TW (1) TW332272B (en)
WO (1) WO1998013759A1 (en)

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US6530047B1 (en) 1999-10-01 2003-03-04 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US6557119B1 (en) 1999-10-01 2003-04-29 Stmicroelectronics Limited Microcomputer debug architecture and method
US6591369B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics, Ltd. System and method for communicating with an integrated circuit
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US6701405B1 (en) 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6408381B1 (en) 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6928073B2 (en) 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US6351803B2 (en) 1999-10-01 2002-02-26 Hitachi Ltd. Mechanism for power efficient processing in a pipeline processor
US6546480B1 (en) 1999-10-01 2003-04-08 Hitachi, Ltd. Instructions for arithmetic operations on vectored data
US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
US7266728B1 (en) 1999-10-01 2007-09-04 Stmicroelectronics Ltd. Circuit for monitoring information on an interconnect
US7000078B1 (en) 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US6412047B2 (en) 1999-10-01 2002-06-25 Stmicroelectronics, Inc. Coherency protocol
US6502210B1 (en) 1999-10-01 2002-12-31 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6298394B1 (en) 1999-10-01 2001-10-02 Stmicroelectronics, Ltd. System and method for capturing information on an interconnect in an integrated circuit
US6665816B1 (en) 1999-10-01 2003-12-16 Stmicroelectronics Limited Data shift register
US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US6820195B1 (en) 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US6542983B1 (en) 1999-10-01 2003-04-01 Hitachi, Ltd. Microcomputer/floating point processor interface and method
US6684348B1 (en) 1999-10-01 2004-01-27 Hitachi, Ltd. Circuit for processing trace information
US6598177B1 (en) * 1999-10-01 2003-07-22 Stmicroelectronics Ltd. Monitoring error conditions in an integrated circuit
US6918065B1 (en) 1999-10-01 2005-07-12 Hitachi, Ltd. Method for compressing and decompressing trace information
US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6567932B2 (en) 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6434665B1 (en) 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US7191313B2 (en) 2001-08-28 2007-03-13 Sony Corporation Microprocessor
JPWO2004023291A1 (en) * 2002-08-30 2005-12-22 株式会社ルネサステクノロジ Information processing equipment
CN102135867B (en) * 2010-01-21 2014-04-02 联阳半导体股份有限公司 Data processing module and method thereof
US9552206B2 (en) * 2010-11-18 2017-01-24 Texas Instruments Incorporated Integrated circuit with control node circuitry and processing circuitry

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Also Published As

Publication number Publication date
WO1998013759A1 (en) 1998-04-02
JP3778573B2 (en) 2006-05-24

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