^18889 A7 B7 五、發明説明（1 ) 本發明是有關於半導體製程，特別是有關於一種掩埋 式接觸導電極板的製造方法。 在半導體元件中，爲減小面積提高產能，常採用掩埋 接觸設計，並配合其他適用的元件結構，而得發揮最大運 作效能，茲以第1圖繪示之動態隨機存取記憶體（DRAM) 單元結構剖面圖爲例，其係以建構在一半導體基底10之上 一電晶體連接一電容器而形成。電晶體含源/汲極擴散區16 和18及閘極14。電容器則由一下電極板24、一介電層26 以及一上電極板28所構成。下電極板24實際上是以掩埋 接觸方式與電晶體之源/汲極擴散區18相連，而達到簡省 元件尺寸之效果。由於電容器極板的導電特性對於儲存電 荷的能力影響甚鉅，下電極板24之製造過程及成品特性就 成爲決定靜態隨機存取記憶體運作效能的關鍵角色。 在另一方面，若以掩埋接觸方式形成元件之間電性傳 導的媒介，則做爲導電極板的材質本身須具備均勻的導電 特性，並須儘量降低極板與半導體基底内擴散區之接觸電 阻値。因此，無論做爲靜態随機存取記憶單元之電容極板， 或提供爲其他導電媒介之接觸極板，在製程控制上皆要求 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填{馬本頁) 將掩埋接觸結構最佳化，包括提供低電阻之淺接面（shallow junction)及導電性良好之極板等0 傳統中，製造掩埋接觸極板的方法包含有採用沈積後 佈植及沈積同時佈植（in-situ)二種主要途徑，底下將分別説 明。 請參照第2圖所繪示之元件剖面圖，其中，一半導體 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210'乂297公釐） A7 B7 315889 五、發明説明（2 ) 基底30上方形成有一元件區。一絕缘層32覆蓋在元件區 上，且形成一接觸孔36，而露出基底中的擴散區31。於 是，爲形成掩埋接觸，即以一複晶矽層34沈積在元件發上 方，並經由接觸孔36與擴散區31接觸。爲了使複晶矽層 34具備導電性，随即以一離子佈植程序將雜質掺入其中。 此即沈積後佈植模式。 由於元件區表面高低不平，複晶矽層34亦隨之起伏， 以致經由離子佈植摻入之雜質不易均勻分佈在複晶矽層 34中，如此將使其提供爲掩埋極板用途之效果受到相當影 響，難能將元件最佳化。 另一方面，若採用沈積同時佈植的製造方法，雖可使 雜質均勻分佈，亦將遭遇其他問題。例如，在第3A圖和 第3B圖的剖面圖所示之製造方法中，係先行沈積一未掺 雜質的複晶矽層46，使與基底40中之雜質擴散區42接 觸，再於複晶秒層46上方，依照沈積同時掺入雜質（in-situ) 的方式，形成一掺有雜質的複晶矽層48。第3B圖的結構 經由退火處理後，雜質將自上層複晶矽48擴散到下層原先 未掺雜質的複晶矽層46中，使複晶矽層46導電，並與擴 散區42形成連接。 然而，藉第3A圖和第3B圖方式製成的掩埋接觸極 板，即包括複晶矽層46和48，雖然可使雜質分佈達成均 勻的目的，但是，由複晶矽層48擴散出來的雜質會進入基 底40内，將原先的擴散區42範圍更行擴大，不但失去淺 接面的理想特性，亦將危及元件之間的隔離效果。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀齋面之注^事項再填寫本頁) 裝- 訂 經濟部中央標準局員工消費合作社印製 3*S889 A7 _________B7 五、發明説明（3 ) 第4圖所示電容結構即爲模擬第i圖元件所利用者。 當複晶矽電極板24’和28’分別受到正負電壓偏壓時，複晶 妙内部會形成聚集區（accumulation)25和空乏區（depletion region)23，而達成儲存電荷的目的。而經由前述傳統方法 製成的複晶矽極板並不具有均勻的雜質分佈條件，或爲防 止雜質擴散入基底，致極板内離質濃度過低，都將使空乏 區23在正反向偏屋時發生不對稱的現象。亦即，當第4圖 所之偏壓模式反相，使上極板28’接受負電壓，下極板24, 接受正電展時’下極板形成的空乏區會比第4圖所示區域 23還要大，或更小，致其電容値大幅改變，不利元件的運 作一致性。 經濟部中央標準局員工消費合作社印袋 (請先閱讀背面之注會事項再填寫本頁) 根據實際量測結果，更可顯現前述問題。例如，以第 2圖的製造方法形成的電容結構中，下極板34厚度控制在 2700人，並受8〇KeV能量8 X 10i5濃度的磷摻入，而上極 板係以沈積同時摻雜方式形成，具有1〇〇〇A的厚度。並經 由800 °C的熱處理。此結構在-2.5伏特至+2 5伏特的電容 値量測結構如第5A圖所示：從最低的34 8ρρ到最高的 36.4pF，變動量相差了超過l.5pF。再以第3A圖和第3B 圖的製造方法爲例，當下極板之複晶矽層46厚1〇〇〇人，另 一複晶矽層48厚1500人，而上極板厚1〇〇〇A，並經由8〇〇 。(：熱處理後，其電容値量測結果如第5B圖所示，高低範 面在35.8和36.7之間，亦有將近lpF的變動。而且第5A 圖和第5B圖之量測結果均呈現不對稱形態，此等電容値 的不一致性對元件運作並無好處，反而是會使一般動態元 5 本纸張尺度適用中國國家標準（CNS ) 規格（21 Οχ297公釐） A7 B7 五、發明説明（4 ) 件，如動態隨機存取記憶體等，在產品特性控制上造成困 擾，甚至將影響產品良率。 爲此，本發明即提出一種掩埋式接觸導電極板的製造 方法，使極板内雜質分佈均勻，力求其導電性一致，而能 達到減小電容値變動範圍的目的。 又本發明提出之掩埋式接觸導電極板的製造方法得提 高極板的雜質濃度，卻不會將基底内的雜質擴散區範圍擴 大，能避免破壞元件的隔離特性。 再者，本發明提出之掩埋式接觸導電極板的製造方法 可以利用傳統製程的光罩設計，在製造成本上並不增加， 且能與習知技術相容，發揮實際運用效果。 經濟部中央標準局員工消費合作社印製 (請先閱讀^^面之注倉事項再填寫本頁) 依照本發明一較佳實施例之製造方法是先在一半導體 基底上形成元件區，其中包括有基底内供掩埋接觸用的雜 質擴散區。其次在元件區上形成一障礙層，以及障礙層上 的掺有雜質的複晶矽層。接著定義出一掩埋接觸區，並將 掩埋接觸區内的複晶矽層及障礙層去除，使掩埋接觸的雜 質擴散區露出。然後，形成一未掺雜質的複晶矽層於元件 區上方，並延伸與雜質擴散區相接觸。於是，經由加熱處 理，使摻有雜質的複晶矽中部份雜質擴散到未摻雜質的複 晶矽層内，即構成一掩埋式接觸導電極板。在前述方法中， 亦可在加熱處理之前實施一離子佈植程序，更進一步改善 掩埋電阻値。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂 ，下文特舉一較佳實施例，並配合所附圖式，作詳細説明 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 310889 A7 B7 五、發明説明（5 ) 如下： 圖式之簡單説明： 第1圖爲一動態随機存取記憶體單元的剖面示意圖； 第2圖爲一習知掩埋接觸極板製造過程之元件剖面示 意圖； 第3A和第3B圖爲另一掩埋接觸極板製造過程之元件 剖面示意圖； 第4圖爲一電容結構示意圖； 第5A圖和第5B圖爲依照習知製法製成之電容器電容 値量測結果 第6圖到第10圖爲依照本發明一較佳實施例之掩埋式 接觸導電極板的製造方法中各階段元件剖面示意圖；以及 第11圖爲依照本發明一較佳實施例構成之電容器電 容値量測結果。 實施例 經濟部中央標準局員工消費合作社印製 (請先閱讀"--面之注會事項再填寫本頁) 請參照第6圖。本發明之掩埋式接觸導電極板的製造 方法適用於一半導體基底50。首先，在基底50上形成元 件區。元件區含主動元件結構，如電晶體閘極56和源/汲 極擴散區53和54等，並以場氧化物52隔離。而其中之雜 質擴散區54即提供掩埋接觸所用。於是便在元件區上方形 成一障礙層58，將整個元件區包覆住。障礙層58可以是 一層氧化層（如TEOS氧化層），用以形成雜質擴散的障礙。 其次，請參照第7圖，一層較厚的摻有雜質複晶矽層 60乃形成於障礙層58上方。複晶矽層60是利用沈積同時 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（6) 摻入雜質（in-situ)的方式形成，因此其内部雜質分佈均勻， 且濃度可適量提高。 請 先 閲 ή 背‘ ιέ 意· 事 項 再 填 寫 本 頁 接著，在元件區上定義出掩埋接觸區。此每一掩埋接 觸區均落在擴散區54之内。藉形成光阻罩幕，掩埋接觸區 以外的區域得受到保護，而掩埋接觸區内的複晶矽層60 及障礙層則予以去除。如第8圖所示，元件區中將形成一 接觸孔62，而使雜質擴散區54的表面露出。接觸孔62中 複晶矽層60及障礙層58是藉由蝕刻技術去除，爲熟此技 藝者所詳知，不擬細述。 再如第9圖所示，形成一未掺雜質的複晶矽層64於元 件區上，並延伸入接觸孔62中，與雜質擴散區54相接觸。 未掺雜質的複晶矽層64是以傳統沈積法形成，其厚度不及 已掺雜質的複晶矽層60。二者厚度比率以約3至10倍之 間較佳，即未掺雜質複晶矽層厚約200至700A，而掺入雜 質之複晶矽層厚約1800A至2300A之間爲佳。此等參考數 値當可随實際製造需求調整，本發明並不予強制限定。 經濟部中央標準局員工消費合作社印製 第9圖之元件結構經由加熱處理後，將使掺有雜質之 複晶矽層60中的部份雜質擴散到未掺雜質之複晶矽層64 中，而讓後者具有導電性。加熱過程可利用傳統爐管加熱 至約800 °C，持續30分鐘。由於元件製程尚未完成，後續 製程中仍有加熱程序，因此，此加熱過程並不要求雜質完 全均勻擴散，即其時間無需太長，待其他加熱程序加入後， 自當使複晶矽層60和64内的雜質分佈更加均勻，導電性 更優良。 本紙張又度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） A7 B7 五、發明説明（7) 請 先 閱 讀 背- 之 注 意_ 事 項 再 填 衰裝 頁 另一方面，若爲再降低掩埋接觸區的接觸電阻値，可 在加熱之前施實一離子佈植程序，將少量雜質掺入複晶矽 層64和雜質擴散區54界面附近，而使此部份的複晶矽導 電性提高。佈植可以用20-40KeV能量，而掺入1013至1014 濃度的雜質。此一步驟可依需要加入或刪除，掺植條件亦 得按實際情況調整。 訂 於是，若以複晶矽層60和64爲下電極板，經過圖案 定義及蚀刻後，另形成一介電層66和一上電極板，如第 10圖所示，則可構成一電容器。依照前述電容器電容値量 測方式，將第10圖結構在-2.5伏特和2.5伏特間電容値量 出，其結果如第11圖所示。很明顯地，最高和最低電容値 在37.5pF和37.2pF之間，變化量不超過0.3pF，並且，在 正反相電壓供給下，電容値呈對稱形態，有別於習知電容 結構之不對稱。因此，對於元件的運作具有正面影響，並 得以最佳化電路設計。 經濟部中央標準局員工消費合作社印製 由於本發明中，未掺雜質之複晶矽層及障礙層皆可防 止雜質從摻有雜質的複晶矽層擴散到半導體基底中，能避 免雜質擴散區的擴大，因此，在沈積同時掺入雜質方式形 成的複晶矽層内，雜質濃度與分佈都能依需要調整至最好 的狀況，使掩埋接觸極板的導電性進一步提昇。再者，藉 由輔助之離子佈植程序能更降低掩埋接觸電阻値，使元件 運作速度可再提高。而由量測電容値結構可清楚看出，本 發明之極板結構確較傳統製法製成者爲優。 雖然本發明已以較佳實施例揭露如上，然其並非用以 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（8) 限定本發明，任何熟習此項技藝者，在不脱離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀t-vg之注*-事項再填寫本頁) 裝- 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4规格（210X 297公釐）^ 18889 A7 B7 V. Description of the invention (1) The present invention relates to the semiconductor manufacturing process, in particular to a method for manufacturing a buried contact conductive electrode plate. In semiconductor devices, in order to reduce the area and increase production capacity, buried contact design is often used in conjunction with other applicable device structures to maximize the operating efficiency. The dynamic random access memory (DRAM) shown in Figure 1 is here. The cross-sectional view of the cell structure is taken as an example, which is formed by constructing a transistor on a semiconductor substrate 10 and connecting a capacitor. The transistor contains source / drain diffusion regions 16 and 18 and gate electrode 14. The capacitor is composed of a lower electrode plate 24, a dielectric layer 26, and an upper electrode plate 28. The lower electrode plate 24 is actually connected to the source / drain diffusion region 18 of the transistor in a buried contact manner, thereby achieving the effect of simplifying the device size. Since the conductive characteristics of the capacitor plates have a great influence on the ability to store charge, the manufacturing process and finished product characteristics of the lower electrode plate 24 have become a key role in determining the operating performance of the static random access memory. On the other hand, if the medium of electrical conduction between the components is formed by buried contact, the material used as the conductive electrode plate itself must have uniform conductive characteristics, and the contact between the electrode plate and the diffusion region in the semiconductor substrate must be minimized Resistance value. Therefore, regardless of whether it is a capacitor polar plate used as a static random access memory unit or a contact polar plate provided as another conductive medium, it is required to be printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy in the process control (please read the back Matters needing attention and then fill in the {Ma page) to optimize the buried contact structure, including the provision of low resistance shallow junctions and well-conducting plates. 0 Traditionally, the methods of manufacturing buried contact plates include The two main methods of post-deposition planting and in-situ simultaneous planting (in-situ) will be described separately below. Please refer to the cross-sectional view of the device shown in Figure 2. Among them, a semi-conductor 3 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210 'x 297 mm) A7 B7 315889 5. Description of the invention (2) substrate 30 An element area is formed above. An insulating layer 32 covers the device region and forms a contact hole 36 to expose the diffusion region 31 in the substrate. Therefore, in order to form a buried contact, a polycrystalline silicon layer 34 is deposited above the device and contacts the diffusion region 31 via the contact hole 36. In order to make the polycrystalline silicon layer 34 electrically conductive, impurities are then incorporated into it by an ion implantation procedure. This is the post-deposition planting mode. Due to the unevenness of the surface of the device area, the polycrystalline silicon layer 34 also fluctuates, so that the impurities doped through ion implantation are not easily distributed uniformly in the polycrystalline silicon layer 34, which will make it effective for the purpose of burying the plate Quite an influence, it is difficult to optimize the components. On the other hand, if the manufacturing method of simultaneous deposition and deposition is adopted, the impurities will be distributed evenly, but other problems will also be encountered. For example, in the manufacturing method shown in the cross-sectional views of FIGS. 3A and 3B, an undoped polycrystalline silicon layer 46 is deposited in advance to contact the impurity diffusion region 42 in the substrate 40, and then to the polycrystalline Above the second layer 46, a polycrystalline silicon layer 48 doped with impurities is formed in accordance with the method of depositing and doping with impurities (in-situ). In the structure of FIG. 3B, after annealing, impurities will diffuse from the upper polycrystalline silicon 48 to the lower undoped polycrystalline silicon layer 46 to make the polycrystalline silicon layer 46 conductive and form a connection with the diffusion region 42. However, the buried contact plate made by the methods shown in FIGS. 3A and 3B, including the polycrystalline silicon layers 46 and 48, can achieve an even distribution of impurities, but the diffusion from the polycrystalline silicon layer 48 Impurities will enter the substrate 40 and expand the original diffusion region 42 not only to lose the ideal characteristics of the shallow junction, but also to jeopardize the isolation effect between the components. The size of this paper is in accordance with Chinese National Standard (CNS) A4 (210X297mm) (Please read the note of the noodles first ^ Matters and then fill out this page) Packing-Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (3) The capacitor structure shown in Fig. 4 is used by simulating the i-th element. When the polycrystalline silicon electrode plates 24 'and 28' are biased with positive and negative voltages, respectively, an accumulation region 25 and a depletion region 23 are formed inside the polycrystalline silicon to achieve the purpose of storing charge. However, the polycrystalline silicon plate made by the aforementioned traditional method does not have uniform impurity distribution conditions, or in order to prevent impurities from diffusing into the substrate, the ion concentration in the plate is too low, which will cause the depletion region 23 to be in the forward and reverse directions. Asymmetry occurs when the house is partial. That is, when the bias mode shown in Figure 4 is reversed, so that the upper plate 28 'receives a negative voltage, and the lower plate 24 receives a positive electrical development, the lower plate will form a depleted area than shown in Figure 4. The area 23 is still larger or smaller, causing a large change in its capacitance value, which is detrimental to the consistency of the operation of the device. Printed bags of employees' consumer cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling out this page) Based on the actual measurement results, the aforementioned problems can be revealed. For example, in the capacitor structure formed by the manufacturing method of FIG. 2, the thickness of the lower plate 34 is controlled at 2700 people, and is doped with phosphorus at a concentration of 8 × 10i5 at an energy of 8 × KeV, while the upper plate is doped simultaneously by deposition It is formed in a manner with a thickness of 1000A. And by heat treatment at 800 ° C. The capacitance measurement structure of this structure from -2.5 volts to +25 volts is shown in Figure 5A: from the lowest 34 8ρρ to the highest 36.4pF, the variation differs by more than 1.5pF. Taking the manufacturing method of FIG. 3A and FIG. 3B as an example, the polycrystalline silicon layer 46 of the current plate has a thickness of 1,000 people, the other polycrystalline silicon layer 48 has a thickness of 1500 people, and the upper plate has a thickness of 100. 〇A, and via 80. (: After heat treatment, the capacitance value measurement results are shown in Figure 5B, and the high and low range are between 35.8 and 36.7, and there are also changes in lpF. Also, the measurement results in Figures 5A and 5B are not Symmetrical form, the inconsistency of these capacitance values is not beneficial to the operation of the component, but instead will make the general dynamic element 5 This paper standard is applicable to the Chinese National Standard (CNS) specifications (21 Ο 297 mm) A7 B7 V. Description of invention ( 4) Pieces, such as dynamic random access memory, etc., cause trouble in the control of product characteristics, and even affect the yield of the product. Therefore, the present invention proposes a method for manufacturing a buried contact conductive electrode plate, so that Impurity distribution is uniform, and its electrical conductivity is consistent, and the purpose of reducing the range of capacitance value can be achieved. The manufacturing method of the buried contact conductive electrode plate proposed by the present invention can increase the impurity concentration of the electrode plate, but it will not The range of the impurity diffusion region is expanded, which can avoid destroying the isolation characteristics of the device. Furthermore, the manufacturing method of the buried contact conductive electrode plate proposed by the present invention can use the photomask design of the traditional process , Does not increase in manufacturing cost, and can be compatible with conventional technology, and play a practical effect. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the ^^ surface note before filling this page) The manufacturing method of a preferred embodiment of the present invention is to first form a device region on a semiconductor substrate, which includes an impurity diffusion region in the substrate for burying contacts. Secondly, a barrier layer is formed on the device region, and the barrier layer is formed on the barrier region An impurity-doped polycrystalline silicon layer. Next, a buried contact area is defined, and the polycrystalline silicon layer and barrier layer in the buried contact area are removed to expose the impurity diffusion area of the buried contact. Then, an undoped impurity layer is formed The polycrystalline silicon layer is above the device region and extends in contact with the impurity diffusion region. Then, by heat treatment, some impurities in the polycrystalline silicon doped with impurities diffuse into the undoped polycrystalline silicon layer, ie It constitutes a buried contact electrode plate. In the aforementioned method, an ion implantation procedure can also be implemented before the heat treatment to further improve the buried resistance value. , Features, and advantages can be more clearly understood, the following is a preferred embodiment, combined with the attached drawings, for a detailed description of the paper size applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm) 310889 A7 B7 5. Description of the invention (5) is as follows: Brief description of the drawings: Figure 1 is a schematic cross-sectional view of a dynamic random access memory cell; Figure 2 is a schematic cross-sectional view of a component of a conventional manufacturing process of buried contact plates Figures 3A and 3B are cross-sectional schematic diagrams of another buried contact plate manufacturing process; Figure 4 is a schematic diagram of a capacitor structure; Figures 5A and 5B are capacitor capacitance values measured in accordance with conventional manufacturing methods Results Figures 6 to 10 are schematic cross-sectional views of components in various stages in the method of manufacturing a buried contact electrode plate according to a preferred embodiment of the present invention; and Figure 11 is a capacitor constructed in accordance with a preferred embodiment of the present invention Capacitance measurement results. Example Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read "-face notes before filling in this page) Please refer to Figure 6. The manufacturing method of the buried contact electrode plate of the present invention is suitable for a semiconductor substrate 50. First, an element region is formed on the substrate 50. The device region contains active device structures, such as transistor gate 56 and source / drain diffusion regions 53 and 54, etc., and is isolated by field oxide 52. Among them, the impurity diffusion region 54 provides a buried contact. Thus, a barrier layer 58 is squarely formed on the element area, covering the entire element area. The barrier layer 58 may be an oxide layer (such as a TEOS oxide layer) to form an impurity diffusion barrier. Next, referring to FIG. 7, a thick polysilicon layer 60 doped with impurities is formed above the barrier layer 58. The polycrystalline silicon layer 60 is formed by depositing the paper while applying the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 5. Description of the invention (6) Incorporation of impurities (in-situ), so its interior Impurity distribution is uniform, and the concentration can be increased in an appropriate amount. Please read the "Italy" and "Events" and fill in this page. Next, define the buried contact area on the component area. Each of the buried contact areas falls within the diffusion area 54. By forming a photoresist mask, the area outside the buried contact area is protected, and the polycrystalline silicon layer 60 and the barrier layer in the buried contact area are removed. As shown in FIG. 8, a contact hole 62 is formed in the element region, and the surface of the impurity diffusion region 54 is exposed. The polycrystalline silicon layer 60 and the barrier layer 58 in the contact hole 62 are removed by an etching technique, which is well known to those skilled in the art and will not be described in detail. As shown in FIG. 9 again, an undoped polycrystalline silicon layer 64 is formed on the element region and extends into the contact hole 62 to contact the impurity diffusion region 54. The undoped polycrystalline silicon layer 64 is formed by a conventional deposition method and has a thickness less than that of the doped polycrystalline silicon layer 60. The thickness ratio of the two is preferably about 3 to 10 times, that is, the thickness of the undoped polycrystalline silicon layer is about 200 to 700A, and the thickness of the doped polycrystalline silicon layer is preferably about 1800A to 2300A. These reference numbers can be adjusted according to the actual manufacturing requirements, and the invention is not limited to them. The element structure printed in Figure 9 by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs after heat treatment will diffuse some of the impurities in the polycrystalline silicon layer 60 doped with impurities into the undoped polycrystalline silicon layer 64. And let the latter have conductivity. The heating process can be heated to about 800 ° C using a traditional furnace tube for 30 minutes. Since the device process has not been completed, there is still a heating process in the subsequent process, so this heating process does not require the impurities to diffuse uniformly, that is, the time does not need to be too long. After other heating processes are added, the polycrystalline silicon layer 60 and The impurity distribution in 64 is more uniform and the conductivity is better. This paper is again applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297mm) A7 B7 V. Description of the invention (7) Please read the back-attention _ matters before filling the decay page, on the other hand, if you want to reduce the buried For the contact resistance value of the contact area, an ion implantation procedure can be implemented before heating, and a small amount of impurities are doped into the vicinity of the interface between the polycrystalline silicon layer 64 and the impurity diffusion region 54 to improve the conductivity of the polycrystalline silicon in this part. Planting can use 20-40KeV energy, and doped with 1013 to 1014 concentration of impurities. This step can be added or deleted as needed, and the planting conditions must be adjusted according to the actual situation. Therefore, if the polycrystalline silicon layers 60 and 64 are used as the lower electrode plates, after pattern definition and etching, a dielectric layer 66 and an upper electrode plate are formed, as shown in FIG. 10, a capacitor can be formed. According to the aforementioned capacitor capacitance measurement method, the capacitance value of the structure in Figure 10 is measured between -2.5 volts and 2.5 volts, and the result is shown in Figure 11. Obviously, the highest and lowest capacitance values are between 37.5pF and 37.2pF, the variation does not exceed 0.3pF, and under the supply of positive and reverse voltages, the capacitance values are symmetrical, which is different from the conventional capacitor structure. symmetry. Therefore, it has a positive influence on the operation of the device, and the circuit design can be optimized. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. In the present invention, both the undoped polycrystalline silicon layer and the barrier layer can prevent impurities from diffusing from the impurity-doped polycrystalline silicon layer into the semiconductor substrate, and can avoid impurity diffusion regions. As a result, the concentration and distribution of impurities can be adjusted to the best conditions as needed in the polycrystalline silicon layer formed by doping and doping with impurities, so that the conductivity of the buried contact plate is further improved. Furthermore, the auxiliary ion implantation process can further reduce the buried contact resistance value, so that the device operation speed can be further increased. It can be clearly seen from the measurement of the capacitance value structure that the electrode plate structure of the present invention is indeed superior to those manufactured by traditional manufacturing methods. Although the present invention has been disclosed as above with the preferred embodiment, it is not used in this paper scale to apply the Chinese National Standard (CNS) A4 specifications (210X297 mm) A7 B7 5. Description of the invention (8) Limit the invention Those skilled in the art should be able to make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application. (Please read the t-vg's note *-items before filling out this page) Binding-Order Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs