307912 五、發明説明I ) 發明背景 ⑴發明領域 本發明係關於一種在半導麵釀讎電路上騸諭多層次互連之 褸晶矽對複晶矽接觸的方法，更_細地說，是嬲齡一種在互連之 複晶矽化物層之間，形成低電阻之接觸的方法與絵構。 (2)習知技藝 随著离解析度徽影技術與非均询性爾龌麯刻等半導讎製程 技術的精進，半導體元件的特繼尺寸也持纏地編小。特擻尺寸 的縮小，使得接觸窗也鼸之縮小，結果引至麗裹的接觸電阻。 例如，目前通用的接觸竇特檄尺寸一艟都小於0.5黴米(um)。道 種與場效電晶體(FET)—類的電路元件串連的寄生電容增离了以 後，會降低電路的功效，道是非常不好的現廉。另一個問題是 接觸電極(Re)的分佈很廣，道也裹非常不好的現象。 在半導體產業界中，通常會用多層制定遢的灌摻雜複晶 矽/矽化物眉（一般稱爲複晶砂化物眉），來作爲半導籲元件 的互連*然後再以金雇雇形成穰鑛電路。在基板上各種複晶矽 化物層和金屬層之間，則用介雇絕緣層OLD)加以電性隔維。道 些介層絕緣層在裡£矽化物層之間具有一竖接_窗（通孔）， 以下將簡稱爲絕緣雇。在超大型額體_路(1】1^1)中，接觸的數目 逮遠超過一百萬個，所以很重驀的是备個捿觸嚇需91有很低的 接觸電阻(¾，而且彼此很一致。 習知技藝中，使鋁金屬層次之閲的禳_有一致的低禳钃電 阻的方法，是在物理氣相沉積下一屬次的鎺金钃之前，以同步 濺鍍的方式清洗接觸窗*道樣可以避免暴露在義圓時立刻形成 氣化鋁。伹是，道欏作薷要在沉穰工具上加裝瀾鍍系統，不但 (請先»讀背面之注意亨項再填寫本頁} 装 訂 丄 本紙法尺度遑用申8讓家蟋傘（CXS ) A4规格（210Χ ：19Ί1;) 绳多柘泣夹碟2&為|二消费含作.吐.51*. 五、發明説明、厶Ί 妨礙了工具的效率，也使驅程更爲議雜。 矽化物/播晶矽（襯晶矽化物）的蟹層結權*常用來製作 動態隨機存取記憶鐮①^冲、_雄鼸機存取祖嫌镰(SRAM)、 和微處理器等類的拥醒電路，在暹些電路上作爲FETRI極、字元 線、位元繅等半導體元件的一部份。但是砂化物/複晶砂（複 晶矽化物）與矽化物/複晶矽（複晶矽化物）兩層之閹仍熬會 有离接觸電阻的問題。 1中，說明了兩層矽化物/複晶矽 (複晶矽化物）制定雇之間、一備傳統典型的摟觸。鼸中的接 觸結構，是製作在上有絕緣層12的一面半導體基板10上。圖中 有第一複晶矽雇，包括了第一複晶矽層14和第一矽化物層16， 這兩層另外也形成FET的鬮棰。然後沉積一層絕綠層20 *用以電 性隔絕第一複晶败化物雇*舉例来銳，可以利用化學氣相沉稂 法(CVD)所沉積的氣化物。接蕃利用傳統的辙影技術與非均向性 電漿蝕刻，在絕緣眉20內形成接觸窗4，直到第一矽化物層16 的表面。同樣在 1中，在絕緣雇20上和接麵講內沉積一雇未 經摻雜的第二複晶矽層21，作爲通往第一襬晶矽化物層16頂面 的接觸。在未經摻雜的第二襪晶傲層21上，沉種一層摻雜的複 晶矽層24。如果接觸是製作在FET源/汲欏通之類的細胞元接觸 區(N~)上方時，未經摻雜的複晶矽層21可以避免複晶矽層24內的 雜霣擴散進入基板10而形成很深的接面。接蕃再沉穑第二矽化 物眉26，就完成了第二雇次的互遍纖嫌屬。最後刹用傳統的檄 影與電漿触刻，制定26、24、21等臟層的案，形成了第二雇 制定的導電層。 伹是，匯1中的接觸窗4在餘刻時所殘留的离分子很難清 除，隨後所用的光阻接觸光羣也银讎去除，使得像圓1中的接307912 V. Description of the invention I) Background of the invention (1) Field of the invention The present invention relates to a method of contacting multi-level interconnected crystalline silicon to polycrystalline silicon on a semiconducting surface-brewed circuit. More specifically, it is A method and structure for forming low-resistance contacts between interconnected polycrystalline silicide layers. (2) Known skills With the advancement of semi-conducting process technologies such as resolution resolution shadowing technology and non-uniform interrogative engraved engravings, the size of semiconductor devices has also been kept small. The shrinking of the special size makes the contact window shrink, which leads to the contact resistance of Libao. For example, the current common contact Dou Ting size is less than 0.5 millimeters (um). The parasitic capacitance of the circuit type and the field effect transistor (FET) -type circuit components increases, which will reduce the efficiency of the circuit. The road is very bad. Another problem is that the distribution of the contact electrode (Re) is very wide, and the channel is also very bad. In the semiconductor industry, multi-layered implanted doped polycrystalline silicon / silicide brows (commonly known as polycrystalline sand brows) are often used as interconnects for semiconducting devices * and then hired as gold Form a rein mine circuit. Between the various polysilicon layers and the metal layer on the substrate, a dielectric insulation layer (OLD) is used to electrically isolate the dimension. These interlayer insulating layers have a vertical connection between the silicide layers _window (through hole), which will be referred to as insulation for short below. In the super-large frontal _ road (1] 1 ^ 1), the number of contacts is far more than one million, so it is very important to prepare a touch to scare 91 has a very low contact resistance (¾, and It is very consistent with each other. In the conventional art, the method of making aluminum alloy layers have a consistent low metal resistance is to use a simultaneous sputtering method before physical vapor deposition of the next metal gold metal Washing the contact window * Dai samples can avoid the formation of vaporized aluminum immediately when exposed to the Yiyuan.Yes, the Dao Zuo should be equipped with a Lan plating system on the Shen Yan tool. Fill out this page} Bindery paper standard method of using the Shen 8 Cricket Umbrella (CXS) A4 specification (210Χ: 19Ί1;) Rope Duo Weeping Clip 2 & for | two consumption included. Spit. 51 *. Five , Description of invention, 劶 Ί hinders the efficiency of the tool and makes the drive more complicated. The crab layer of the silicide / silicon crystal (lining crystal silicide) * commonly used to make dynamic random access memory sickle ① ^ Oki, _ male machine access to ancestral sickle (SRAM), and microprocessors and other wake-up circuits, in these circuits as FETRI pole, word line, bit A part of semiconductor components such as Yuanzhen. However, the castration of the two layers of sand / polycrystalline sand (polycrystalline silicide) and silicide / polycrystalline silicon (polycrystalline silicide) still has the problem of contact resistance. In 1, the traditional two-layer silicide / polysilicon (polysilicide) formulation is used, and a traditional and typical contact is described. The contact structure in the projectile is made on the side of the semiconductor substrate with the insulating layer 12 on the side 10. On the picture there is the first polycrystalline silicon layer, including the first polycrystalline silicon layer 14 and the first silicide layer 16, these two layers also form the FET. Then deposit a layer of green layer 20 * Take the example of electrically isolating the first polycrystalline chemical compound as an example *, it can use the vapor deposited by chemical vapor deposition (CVD) method. Then the traditional rutting technique and anisotropic plasma etching are used. A contact window 4 is formed in the insulating eyebrow 20 until the surface of the first silicide layer 16. Also in 1, an undoped second polycrystalline silicon layer 21 is deposited on the insulating layer 20 and in the junction , As a contact to the top surface of the first pendulum crystal silicide layer 16. On the undoped second sock crystal layer 21, Shen A layer of doped polycrystalline silicon layer 24. If the contact is made above the cell contact area (N ~) of FET source / drain channel, the undoped polycrystalline silicon layer 21 can avoid polycrystalline silicon The impurities in the layer 24 diffuse into the substrate 10 to form a very deep junction. Then, the second silicide eyebrow 26 is deposited, and the second pass is completed. The traditional fiber is finally used. The contact between the shadow and the plasma, and the formation of the dirty layer of 26, 24, 21, etc., formed the second conductive layer. Anyway, it is difficult for the contact ion 4 in the sink 1 to remain in the remaining moment. Clear, the photoresist contact light group used later is also removed, making the junction like circle 1
Hi —^^1 i— I 1 n ^ 1^1 n {請先》讀背面之注意事項再填寫夂3f> 訂 本紙張又度逋用申騸家«聿（CNS ) A4规格（：10·Χ29^·1 5 307812_ 五、發明説明 i 觸，很難維持一致的低接觸爾組。例如，最小特黴尺寸爲〇.5mn 或更小的接觸，接觸電阻可以從低至i〇〇歐姆，裹至超過2000歐 姆。而且，以(：?14和02混含氣讎的電娥麯刻來處理矽化鎢表面等 類的介面處理，即使去除矽化物漏16部份頂面以後，都不見得 有效。另一方面，對接觸窗內的矽化鎢雇16進行雜質植入，也 無法使接觸電阻很一致、很低。 因此，在半導體產雄界中仍然股切地讎嬰羅理想的方法， 可以爲暹些互連的嫌線層形成接麵電阻很備的播儀，又毋需爲 蕃降低電阻增加製程步驟，才能使製稚更符成本效益。 發明的籣要說明 訂 因此，本發明的主嬰目的是提出一種方法興續構，可以在複晶 矽化物Λ之間形成電阻很穩定、很低的電性接謂。 本發明另一個目的是在提出上逋的耱嫌的罔時，降低製程的複 雜程度，使得製程更符成本效益。 .¾脊4K0夹438.-^1 二消f·合作.fiffs. 根據以上的目的，本發明的第一個資施例銳明了一個方法和所 作成的結構，爲積黼電路上的互遑，在制定後的複晶矽化物雇之 間，形成具有低接觸電阻(R〇)的電性接觸。這個方法闢始時，先要 預備一面半導體基板，可以是單晶矽晶圈，在元件匾周圓並有場氧 化物(FOX)區作爲電性隔絕。最常用的FOX是用LOCOS(LOCal Oxidation of Silicon)方法形成的，氣化時，利用一層制定後的氰化 矽層遮住元件區。在場氣化物區域中露出的矽基楣經熱氣化的結 果，形成了相當厚的氧化矽(SiOJ。鼸即在元件匯形成一層薄薄的 閘極氧化眉，然後在基板上沉積一層第一複晶砂雇，並偟複晶矽層 接受N+搂雜，成爲導電雇。道時，在第一裡晶矽漏上沉穰砂化鎢 一類的第一矽化物眉，所形成的複暴称化物層可以進一步提离導電 表紙浪又度逋用中*家漂瘳（CNS ) A4規格（：l〇x 公t M菸 «9夬埭 Α ή 貝二？·«*合作.fips. 五、發明説明仏） ' 性。現在利用一道光罩和非均向性艙刻，制定襯暴败化物（複晶破 /矽化物）的臞案，其結果，暴例来說，可以在元件匾上形成 FET閘棰，並同時在埸氣化物區上形成欐晶矽化物的互連邏。繼然 道個方法所描述的是如何製作一锢搐觸，通柱作爲FET_欐之第一 複晶矽化物層，但熟罾本技藝的人應可瞭解，邋個方法一樣可以用 來製作基板上兩層複晶矽化物之間的低電阻接觸。一艨說來，在形 成閘極之後，還薷要其他的製程步驩才能完成FET。例如，以_子 植入形成淡摻雜汲棰(LDD)、在閜欐上沉積一層氧化矽（CVD氣化 物）並以非均向性的回触刻形成緦綠的側壁空閜子、然後形成濃摻 雜的FET源/汲檷接觸區。道些製程步驟都是產業界常用的，所以 不會加以詳細脫明，以簡化本發明的射_。 繼嫌回到本發明。在制定後的第一權晶矽化物]上，沉積一雇 絕緣眉*使第一複晶矽化物屬與下一雇次的互遍鑛此_維。一般說 來，在習知技藝中，接觸窗都是從維綣濯黼始餽刻，91到底下已制 定之複晶败化物雇上败化物層的表面，道常常使褥播_電阻很离， 電阻値的差異很大。本發明的方法在蝕刻接觸窗時，是利用一道光 罩和非均向性的蝕刻，從維錄層關始、鉞穿第一欲化物層，直到第 一複晶矽層。一直到已經触去部份的第一複晶矽層時，才中止電漿 蝕刻。形成暹些接觸窗後，本發明的方法繼績在纖_層上輿接觸窗 內，沉積第二複晶砂層，形成通往第一複晶矽層的接_。接蕃摻雜 第二複晶矽層，可以植入P31_子，以形成第一複晶矽/第二複晶 砂的介面，大大地改蕃了接钃的特性，使播觸電阻(¾更低，阻値 的分佈更窄。本發明免除了額外的製程，也降低了_種度。暴例 來說，同步灘鍍清洗很困難，實施的成本也高。此外* 〇14和02混 合氣體的電漿蝕刻 '或尉砂化鐮層缠行雜質植入等钃的介面處理， {請先》讀背面之注意事項再填窝本I) iM. 訂 本紙乐尺度遴用申麵家媒聿（CNS ) .\4规格（公t ) 507312 ；- 五、發明説明 Γ、 都不是很有效，也很難控制。 在第二_晶矽層上沉稹第二矽化物眉後，就形成第二樓晶矽化 物層。利用傳統的撤影技術與非均向性ft藿豔刻_定第二複晶矽化 物層後，完成了第二層次的互連，而且與第_襯晶砂化物互連眉之 間具有特性更爲理想的接觸。 根據同樣的精神，本發明另外攮出第二個資施例*與第一個資 施例很類似。在第二個實施例中，黼刻禳钃窗蹄，暴利用一道窗口 對準場氧化物匾的光覃。然後触刻播嶋窗，先齡刻維緣層，然後触 穿制定後的第一矽化物與襯晶矽層，直到底下的氣化物(FOX) 區。場氣化物區可作爲蝕刻中止層*使褥形成接麵窗時，有更大的 製程自由。道個方法繼纜在絕嫌雇上和接騰薄內沉積第二複晶矽 層，接觸到第一複晶矽雇的側壁。遷樣所得的播觸，接m姐低， 阻値的分佈也很窄。在第二樓晶矽屬上沉稹蕖二矽化物屬後，完成 了具有改良之接觸的多靥複晶矽化物*最後利用傳統的黴影技術和 非均向性電漿触刻制定暹兩層的案，定義出第二層次的互連繞繅 層。 附的籣要說明 以下將參照附*以具體的實_鮮細銳明本霍明的目的與其 他效益，所附的附酾包括： 圖1是罾知技藝中兩雇複晶矽化物之閜形成之接_的樣剖面 ，其中上眉（第二）複晶碎化物屬的權晶砂接觸到底下複晶矽化 物雇的矽化物。 圖2至圖4是第一實施例之方法與赫__面，所形成的 兩層複晶矽化物互連中，上層（第二）複晶矽化物靥的裡晶矽接觸 到底下襪晶矽化物雇在禳觸窗內的櫬晶矽。 本紙浪尺度遑用中*讕家樣皋（CNS > A4规格（：丨ox 公釐、 ----->一----^ ..------ΪΤ------{、I (請先《讀背面之注意事項再填寫主頁) 鳗菸4<(.{|夬涑奂鬲員二:'flt合作·f.ss. 三、發明説明.b) 圔5至圈7是第二實施例之方法與縮構的横剖面，所形成的 兩層複晶矽^物互連中，接_窗一國触刻至底下場氧化物(FOX)匾 的表面。 圖8是以歐姆爲簞位的鑛觸繼隱_對雇弑晶钃瀾最位龌作圈 的結果，在騙中比較了習知技藝與本發明的瀾flfc鋪果。 具髓實施例的詳細銳明 圖2至_4中，說明了本發明的第一實施例，製作兩濯襯晶矽 化物層之間的低電阻接觸。通些櫬籲砂化物層都是用来作爲積镰電 路上的電性互連。形成道種低電阻播觸的一系列步賺關始畤，先要 預備一面半導髓基板10，從_ 2可知，道面基板上已經有部份完成 的元件。基板最好是單晶矽，結晶方向<1〇〇>。對本發明來說，不 諭是P型或N型接雜的基板都可逋用，另一方面基板上也可具有形 成CMOS型積髑電路所讎的P型或N型井區。但是，爲了鳙化說 明，在圖2中只盡出製作N通道FET所爵的P_基板。本發明方法製 作之低電阻接觸所通往的第一襪晶矽化物層，也可作爲N通道FET 的閜極。 同樣在圆2中，壜氣化物12_)用来隔絕元件fi，但只畫出 兩個元件區之間的部份FOX。一個形成FOX的傳統方法是 LOCOS(LOCal Oxidation of Silicon)法。暹種方法先在元件區上沉 積一層制定的氮化矽(Si3N4)，作爲鑼化的陳蔽。然镰對基板進行熱 氣化，使露出來的場氣化物區形成了相當厚的觐化砂(Si02)，厚約 4000至5000埃。 同樣在2中，去除元件區的瓤化砂後，接蕃_元件匾上以熱 成畏的方式形成一層薄薄的氧化層8，作爲FETK__氣化層。一 般說來，閘楹氣化層蹕[約60至200埃。然後在轚儀基板上全面沉積 (請先«讀背*之注#事項再填寫主夏) k 訂 夂紙伕尺度適用中家螵皋（CNS ) A4规格i 五、發明説明、7、 第一複晶矽雇14，覆躉在颺楣氧化雇8與場氣化物12上。第一複晶 矽層最好厚約500至1500埃。第一襦晶矽層14是以低壓化學氰相沉 積法(LPCVD)沉積的。第一複晶矽雇14隨即以磷(Ρ31)或砷(As75)的 難子植入加以摻雜。雜質湯瘇最好在1.0X1019至1.0X1021難子/立 方公分，植入能置在30至50keV之間。 繼績回到圖2，接蕃就在全面沉種的第一襬晶砂篇14上沉積 第一矽化物眉16，形成了第一複晶矽化物層*可以進一步改蕃導電 性。矽化物雇最好是矽化銷(WSi2)，而且厚約500至2000埃。舉例 來說，形成矽化物層的一個最好的方法，是用六鼸化鎢(WF6)和矽 烷(SiH4)的化學氣相沉積法(CVD)。矽化鎢雇是用来改善第一複晶 矽化物雇的導電性。 現在就可利用檄影技術與非均向性電獎豔刻来制定第一複晶矽 化物層的圔案，而此第一複晶败化物是由第一複墨被層14與第一矽 化物層16所組成的。裡晶矽化物雇的横剖面是沿著制定部位的長 度，所以從2看並不明顬。道屬制定好的第一襯晶砂化物靥通常 是用來在元件區中的_極氧化層8上形成FET的鬮欐，圖2只盡出 了一部份。暹層制定好的第一複晶破化物層同時也延伸到壜氧化物 區上，因此也作爲第一雇次的互連纗嫌。鼸然本發明的方法所描述 的是如何製作一個低電阻接觸，通柱作爲ΡΈΤ閾權之第一樓晶矽化 物眉，但熟習本技藝的人應可瞭解*道個方法一樣可以用來製作基 板上任何兩雇複晶矽化物之間的低電阻接钃。一般銳來，形成FET 邋黑要其他的製程步臟，伹並非本镫明的主要部份，所以不曹加以 詳細說明，以籣化討諭，只是略加描述以說明本發明的製程連績 性。例如，由第一裡晶败化物雇形成_檷之後，就以龌子植入在閘 棰兩邊形成淡摻雜汲檷(LDD)。饋後在阑播上沉積一雇氣化矽 {請先閱讀背面之注意H.項再填寫一4莧> •乂二 訂 本紙張尺度逋用申家蘼皐（CNS ) A4規格：210X 29,公廣） .«.溱-is.e 夹*盘為貝二？5费合作‘»±.知_S. 五、發明説明..s ) ' (CVD氣化層），再全面回触刻CVD氣化雇，而形成了緇緣的側 壁空間子。辁側壁空閜子兩旁植入雜質，然後形成漏摻雜的FET源 /汲極接觸區，作爲良好的FET接觸，道樣一來就宪成的FET。 2的横剖面·並沒有畫出這些製程步驟。 雄纜回到本發明，·2中，在制定好的篛一櫬&敏化物靥上沉 積一層絕緣層20，使第一慯晶矽化物雇與下一屬次的互遍彼此隔 絕。絕緣層20最好是氱化矽(Si02)，並在反應器中利用LPCVD法分 解四乙基矽氣烷(TEOS)沉積而成。緦緣雇20最錄約500至2000 埃。雖然圖中所盡的絕緣眉是保形的(conformal)，本方法一樣通用 於平坦化的絕緣層。現在在絕緣層20上纖佈一層光阻雇22，並如· 2，在即將作爲接觸窗的位置形成釀孔。 在習知技藝中，接觸窗鄘是從維綠雇20钃始黼刻，醢到底下 已制定之複晶矽化物層上的矽化物雇16裹面。這嫌作常常使得接觸 電阻很高，電阻値的差異很大。道翟播雇囑臞高和羞厲很大的現 象，一般說來是因爲矽化鎢(WSi2)上的高分子和其他殘留物很難去 除。而且，〇^和〇2混合氣讎的電鏞麯刻、或對矽化鏞雇進行雜質 植入等類的介面處理，都不聶很有效，也使製程增加額外的成本。 _3中本發明的方法，是利用光軍22和非均向性的舳刻，在 絕緣靥內關始触刻接觸窗3。電漿蝕刻會在罔一個Μ刻機合上一直 持績到完全去除第一矽化物雇16，並蝕去底下第一櫬晶矽層14的一 部份。最好是在反應離子_刻檐(R!E)中進行蝕刻，以便進行非均 向性的鈾刻，所用的触刻氣鼸可以最四氰化磯(CF4)和氣氣(〇2>的混 合氣體。蝕刻至第一複晶矽層，可以免除任何額外清洗接_的介面 處理，也毋需另外對接觸植Λ雜質。暴例來說，本鼗明所作成的接 觸，當直徑只有0.4微米(um)時，電組約只有200至500歐姆，相對 -----卜I — U:T, <請先Μ讀背面之注意事項專填寫.恭頁} 訂 本紙悵尺度逋用肀家播舉（CNS ) Α4现格（ZlO'x 公t 307912 ；： 五、發明説明.，1 ) 習知技藝中阻値离達2000歐姆、彼此幾曩又很大的摘觸，道是非常 顯著的改赛。 露出來的接觸鼸即經通_道短暫的鶬戴釀(HF)鷂刻，然後再沉 積第二褸晶矽層。 圖4中*本發明的方法接下来使接觸審中靄出的複晶妙眉16 經過一道短暂的班^触刻，然後去除光阻層22。在維綠層20上舆接 觸窗3內，沉積第二複晶碎層24，形成通往第一複晶孩眉14的接 觸。所形成第一播晶矽對第二複晶矽的介面，接娜1阻很低。沉積 第二複晶矽眉24時，最好和沉稹第一複晶矽靥14類似，利用 LPCVD法，並且厚度在500至3000埃之間。接«摻雜第二複晶矽 眉，可以植入P31離子，或者在複晶矽的LPCVD沉積過程中在矽烷 (Sffl4)中加入（PH3)—類的雄質氣讎同步摻雜。第二複晶矽層內的 雜質濃度最好在1.0 X 1〇19至1 .〇 X 1〇21麵子/立方公分。 圖4中，繼嫌在第二複晶矽靥24上沉穰第二矽化物層26，形 成了第二複晶矽化物層。沉稍第二砂化物眉26時，與第一败化物眉 16類似，舉例來說，可用六氟化鑛和矽焼的LPCVD。矽化物層26 並不需要形成低接觸電阻的接觸，但在半_«產業界中卻常用來進 —步降低繅電阻。層26最好ϋ約500至2000埃。利用傳統的微影技 #與非均向性電漿蝕刻制定層24與26所組成之第二複晶砂化物雇 後，就完成了第二層次的互邊。暹樣一來，就完成了具有接觸電阻 更低的接觸的兩雇複晶矽化物互連。 現在請參考圖5至圖7，其中所說明的第二實施例，是在制定 好的複晶矽化物眉之間，形成低電隱之接觸的方法與結構。道個方 法中，除了触刻接觸窗的方法以外，都與第一實施例钃似。因此所 有的標號都與第一資施例相同，而凰圈5在触刻播觸窗之前都與第 本紙*尺度遴用中騸家壎筚（cns ) A<wiyi· (公廣） {诗先《讀背面之注意事項再填寫本頁) 订Hi — ^^ 1 i— I 1 n ^ 1 ^ 1 n {please read the precautions on the back and then fill in 3f > the paper of the order is also used in Shenjia «Yu (CNS) A4 specification (10. Χ29 ^ · 1 5 307812_ Fifth, the description of the invention i touch, it is difficult to maintain a consistent low-contact group. For example, the minimum contact size is 0.5mn or less, the contact resistance can be as low as i〇〇ohm, Wrapped to more than 2000 ohms. Moreover, the interface treatment such as tungsten silicide surface is treated with (: 14 and 02 mixed with gas and electric claws), even after removing the top surface of the 16 part of the silicide leakage, it is not always possible Effective. On the other hand, the impurity implantation of tungsten silicide 16 in the contact window can not make the contact resistance very consistent and low. Therefore, in the semiconductor industry, the ideal method is still cut. It is possible to form a broadcast device with very good junction resistance for the interconnected trace layers of Siam, and it is not necessary to increase the process steps for lowering the resistance, so that the system can be more cost-effective. The invention must be specified. The main purpose of the main infant is to propose a method for continuous construction, which can be used in polycrystalline silicide Λ The electrical resistance is very stable and low. Another object of the present invention is to reduce the complexity of the process when making the suspicion, and make the process more cost-effective. Ridge 4K0 clip 438. -^ 1 Two elimination f. Cooperation. Fiffs. According to the above purpose, the first embodiment of the present invention clearly clarifies a method and the resulting structure, for mutual interference on the integrated circuit, after the formulation of the compound crystal Between the silicides, an electrical contact with low contact resistance (R〇) is formed. When this method is initiated, a semiconductor substrate must be prepared, which can be a single crystal silicon ring, which is oxidized around the element plaque and has a field oxidation The FOX area is used as electrical isolation. The most commonly used FOX is formed by the LOCOS (LOCal Oxidation of Silicon) method. During gasification, a layer of formulated silicon cyanide layer is used to cover the element area. In the field gasification area The exposed silicon-based lintel is thermally vaporized, resulting in the formation of a relatively thick silicon oxide (SiOJ). That is, a thin layer of gate oxide is formed on the element sink, and then a layer of first polycrystalline sand is deposited on the substrate. And the polycrystalline silicon layer accepts N + doping and becomes a guide At the time of Dao, the first silicide eyebrow such as tungsten was deposited on the first crystalline silicon drain, and the formed resurrection scale can be further lifted away from the conductive surface paper and used in home. (CNS) A4 specifications (: l〇x 黃 t M smoke «9 夬 埭 Αή Beier? ·« * Cooperation. Fips. Fifth, description of invention)) 'Nature. Now use a mask and anisotropic capsule Now, formulate a case of lining the defeated compound (polycrystal broken / silicide). As a result, for example, it is possible to form a FET gate on the device plaque, and at the same time form a crystalline silicide on the gasification area The interconnection logic. Then this method describes how to make a constriction contact, the through column is used as the first polycrystalline silicide layer of FET_ 欐, but those skilled in the art should understand that this method It can also be used to make low-resistance contacts between two layers of polysilicide on the substrate. In short, after the gate is formed, other process steps are required to complete the FET. For example, by implanting ions to form a lightly doped drain (LDD), depositing a layer of silicon oxide (CVD gasification) on the edge, and forming a green side wall empty hole with anisotropic back-etching, and then A heavily doped FET source / kibble contact area is formed. These process steps are commonly used in the industry, so they will not be elaborated in detail in order to simplify the process of the present invention. Return to the present invention. On the first power crystal silicide after enactment], deposit an insulating eyebrow * so that the first polycrystalline silicide belongs to the next pass and mine this dimension. Generally speaking, in the conventional art, the contact window is fed from the dimensional angle, and the compound crystal compound that has been formulated under the 91 is hired on the surface of the layer of the compound. , The resistance value varies greatly. In the method of the present invention, when etching the contact window, a mask and anisotropic etching are used, starting from the closing of the dimensional recording layer, and piercing through the first object layer until the first polycrystalline silicon layer. The plasma etching was stopped until the first polysilicon layer was partially touched. After forming the contact windows, the method of the present invention succeeds in depositing a second polycrystalline sand layer on the fiber layer and the contact window to form a connection to the first polycrystalline silicon layer. The second polycrystalline silicon layer is doped with Pian, and P31_ can be implanted to form the interface of the first polycrystalline silicon / second polycrystalline sand, which greatly improves the characteristics of the photodiode and makes the contact resistance (¾ Lower, the distribution of the resistance value is narrower. The present invention eliminates the extra process, and also reduces the degree of species. For example, simultaneous beach plating cleaning is very difficult and the cost of implementation is also high. In addition * 〇14 and 02 mixed Plasma etching of gas' or weed sand sickle layer entangled impurity implantation and other metal interface treatment, {please read the precautions on the back before filling the nest I) iM. Book paper music standard selection Shenmian media Yu (CNS). \ 4 specifications (male t) 507312;-Fifth, the invention description Γ, are not very effective and difficult to control. After sinking the second silicide eyebrow on the second crystalline silicon layer, the second floor crystalline silicide layer is formed. Using the traditional shadow-removal technique and anisotropic ft., The second polycrystalline silicide layer is completed, and the second level of interconnection is completed, and it has the characteristics of interconnecting the eyebrows with the first lining crystallized silicide. More ideal contact. According to the same spirit, the present invention additionally creates a second resource embodiment * which is very similar to the first resource embodiment. In the second embodiment, the window hooves are engraved, and a window is used to align the light of the field oxide plaque. Then touch the engraved window, engrave the marginal layer first, and then touch the first silicide and crystalline silicon layer after the formulation, until the underlying vaporization (FOX) area. The field vaporization zone can be used as an etch stop * to allow the mattress to form a junction window with greater process freedom. This method deposits a second polysilicon layer on the top of the cable and in the thin film, and contacts the side wall of the first polysilicon. The spreading contact obtained from the sample transfer is lower than that of sister m, and the distribution of resistance is also very narrow. After the second floor of the crystalline silicon genus Shen Zhenyi and the second silicide genus, completed the improved contact multi-titanium polycrystalline silicide * Finally, using traditional mold technology and anisotropic plasma contact engraving The layer case defines the second layer of interconnected reeling layers. The attached buns are to be explained below with reference to the specific details of the purpose and other benefits of this book. The attached attachments include: Figure 1 is a summary of two hired polycrystalline silicides in the know-how The formation of the joint profile, in which the right crystal sand belonging to the upper eyebrow (second) polycrystal crushed compound contacts the silicide employed by the bottom polycrystalline silicide. Figures 2 to 4 are the method of the first embodiment and the H-plane. In the two-layer polysilicide interconnection formed, the upper layer (second) polycrystalline silicide is made of crystalline silicon contacting the bottom sock crystal Silicide is employed in the crystalline silicon inside the window. In this paper, the scale is used in the middle * 鰰 家 样 皋 (CNS > A4 specification (: 丨 ox mm, ----- >> ---- ^ ..------ ΪΤ ---- -{, I (please read "Notes on the back and then fill in the homepage") Eyan 4 < (. {| 夬 涑 契 嬂 鬲 员 二: 'flt cooperation · f.ss. Third, the invention description.b) 圔 5 Circle 7 is the cross-section of the method and the reduced structure of the second embodiment. In the formed two-layer polycrystalline silicon interconnect, the window is etched to the surface of the bottom field oxide (FOX) plaque. Fig. 8 shows the results of the mining contact with ohms as the position of the _ the most circumscribed circle for the hired crystal Jinglan, and compared the conventional techniques with the Lanflfc of the present invention in the deception. Figures 2 through 4 illustrate the first embodiment of the present invention, making a low-resistance contact between two crystalline silicon silicide layers. These sand layers are all used as accumulator circuits. A series of steps to form a low-resistance touch of the Dao kind. The first step is to prepare a semi-conductive substrate 10. From _2, it can be seen that there are already partially completed components on the Dao-base substrate. The substrate is preferably single-crystal silicon, with a crystal orientation < 1〇〇 >. For the purposes of the present invention, substrates that are not P-type or N-type contaminated can be used, on the other hand, P-type or N-type wells formed by CMOS-type integrated circuits can also be provided on the substrate. However, in order to It is illustrated that only the P-substrate for making N-channel FETs is shown in Fig. 2. The first sock crystal silicide layer to which the low-resistance contact produced by the method of the present invention can also be used as the n-channel FET. Pole. Also in circle 2, the gasification compound 12_) is used to isolate the element fi, but only a part of the FOX between the two element regions is drawn. A traditional method of forming FOX is the LOCOS (LOCal Oxidation of Silicon) method. Siam's method first deposits a layer of formulated silicon nitride (Si3N4) on the component area as a grate of the gong. Ran Si thermally gasifies the substrate, so that the exposed field gasification area forms a very thick sand. (Si02), about 4000 to 5000 Angstroms thick. Also in 2, after removing the crusted sand in the element area, a thin oxide layer 8 is formed on the plaque of the element in a thermally intimidating manner as FETK__ gas Chemical layer. Generally speaking, the gasification layer of Zhazhan is about 60 to 200 angstroms. Then it is fully deposited on the substrate (Please read «READBACK * 之 注 # before filling in the main summer) k Set the size of the paper to apply to the China Home Office (CNS) A4 specification i V. Invention description 7, 7. The first polycrystalline silicon hire 14, cover On the lintel oxide layer 8 and the field vaporizer 12. The first polycrystalline silicon layer is preferably about 500 to 1500 angstroms thick. The first polycrystalline silicon layer 14 is deposited by low pressure chemical cyanide deposition (LPCVD). A polycrystalline silicon alloy 14 is then doped with phosphorus (P31) or arsenic (As75) implantation. The impurity soup is best at 1.0X1019 to 1.0X1021 implantation / cubic centimeter, and the implantation can be set at 30 to Between 50keV. Returning to Figure 2, Jifan deposited the first silicide eyebrow 16 on the first full-scale crystal sand 14 to form the first polycrystalline silicide layer *, which can further improve the conductivity of the fan. The silicide is preferably a silicide pin (WSi2) and is about 500 to 2000 angstroms thick. For example, one of the best ways to form a silicide layer is chemical vapor deposition (CVD) using tungsten hexamide (WF6) and silane (SiH4). Tungsten silicide is used to improve the conductivity of the first polycrystalline silicide. It is now possible to formulate the first polycrystalline silicide layer by using shadow technology and anisotropic electro-engraving, and the first polycrystalline silicide is composed of the first compound ink layer 14 and the first siliconized layer The object layer 16 is composed. The cross-section of the crystalline silicide is along the length of the designated part, so it is not clear from the perspective of 2. The first crystallized crystallized tungsten compound is usually used to form FETs on the _ pole oxide layer 8 in the device area. FIG. 2 shows only a part. The first polycrystalline disruptor layer formulated by the Siam layer also extends to the oxide area, so it is also regarded as the first interconnection. Ran Ran's method of the present invention describes how to make a low-resistance contact. The through-pillar is used as the first floor crystalline silicide eyebrow of the PTI threshold, but those skilled in the art should understand that the same method can be used to make The low resistance junction between any two polysilicides on the substrate. Generally speaking, the formation of FET and sloppy black requires other process steps, so it is not the main part of this article, so I will not elaborate on it in detail to discuss it, but only a brief description to illustrate the process performance of the present invention. . For example, after the formation of 擷 from the first crystal, it is implanted on both sides of the gate with a ladle to form a lightly doped drain (LDD). After feeding, deposit a piece of vaporized silicon on the sowing {please read the note H. item on the back and fill in a 4 苋 >> the second edition of the paper size is used Shenjia Chenggao (CNS) A4 specification: 210X 29 , Gongguang). «. Qi-is.e folder * is Bei Er? 5 fee cooperation ‘» ±. 知 _S. V. Description of the invention (s) (CVD vaporization layer), and then fully touch the CVD vaporization employment, and form the side wall space of the margin. Impurities are implanted on both sides of the empty side walls of the side wall, and then the drain-doped FET source / drain contact area is formed. As a good FET contact, the FET is constructed in the same way. 2 Cross-section · These process steps are not drawn. Returning to the present invention, the male cable, in [2], deposits an insulating layer 20 on the formulated zigzag & sensitizer, so that the first crystalline silicide and the next subordinate are isolated from each other. The insulating layer 20 is preferably silicon trioxide (Si02), and is deposited by decomposing tetraethylsilane (TEOS) in the reactor by LPCVD. The marginal employment of the 20 most recorded about 500 to 2000 Angstroms. Although the insulating eyebrows shown in the figure are conformal, this method is also common for flattened insulating layers. Now a layer of photoresist 22 is fibrously clothed on the insulating layer 20, and as shown in Fig. 2, holes are formed at the positions to be used as contact windows. In the conventional technique, the contact window is engraved from 20% of the green layer, and the silicide layer 16 on the polysilicon layer has been formulated under the bottom. This suspicion often makes the contact resistance very high, and the resistance value varies greatly. Dao Zhaibo's employment orders are high and shy. Generally speaking, it is because the polymers and other residues on tungsten silicide (WSi2) are difficult to remove. Moreover, the interface treatments such as electrical dysfunction of 〇 ^ and 〇2 mixed gas chrysanthemum, or impurity implantation of silicon ytterbium are not very effective, and it also adds extra cost to the process. The method of the present invention in _3 is to use the Guangjun 22 and anisotropic engraving to start engraving the contact window 3 in the insulating gate. Plasma etching will be performed on an M-etching machine until the first silicide 16 is completely removed, and a portion of the underlying first crystalline silicon layer 14 is etched away. It is best to etch in the reactive ion _ carved eaves (R! E) in order to carry out anisotropic uranium engraving, the contact gas rams used can be the most four cyanide rock (CF4) and gas (〇2>) Mixed gas. Etching to the first polycrystalline silicon layer can eliminate any additional interface cleaning process, and no additional impurities are needed for contacting. For example, the contact made by Ben Ming when the diameter is only 0.4 In the case of micrometers (um), the electrical group is only about 200 to 500 ohms, relative to ----- Bu I — U: T, < Please read the notes on the back first and fill them out. Congratulations page} The standard paper is used Cangjia Broadcasting (CNS) Α4 present style (ZlO'x public t 307912 ;: V. Description of the invention., 1) In the conventional arts, the resistance is up to 2000 ohms, and each of them has a lot of contact with each other. Very significant game change. The exposed contact mule is engraved shortly after passing through the channel, and then the second layer of crystalline silicon is deposited. Figure 4 * The method of the present invention next enables the contact review The compound crystal eyebrow 16 produced by Zhong Jiao undergoes a short period of time, and then the photoresist layer 22 is removed. On the green layer 20 and the contact window 3, the second compound crystal fragments are deposited 24. Forming a contact to the first polycrystalline silicon eyebrow 14. The formed interface between the first seed crystal silicon and the second polycrystalline silicon has very low resistance. It is best to deposit the second polycrystalline silicon eyebrow 24 Similar to Shen Zhen's first polycrystalline silicon compound 14, using the LPCVD method, and the thickness is between 500 and 3000 Angstroms. Connect «doped second polycrystalline silicon eyebrows, you can implant P31 ions, or LPCVD in polycrystalline silicon During the deposition process, (PH3) -like male gas is added to the silane (Sffl4) simultaneously. The impurity concentration in the second polycrystalline silicon layer is preferably 1.0 X 1019 to 1.0 X 1021. Face / cubic centimeter. In Fig. 4, the second polysilicide layer 26 is formed after sinking the second silicide layer 26 on the second polycrystalline silicon oxide 24. The first chemical compound 16 is similar. For example, LPCVD of hexafluoride ore and silicon can be used. The silicide layer 26 does not need to form a contact with low contact resistance, but it is often used in semi- «industry industry. Lower the reeling resistance step by step. Layer 26 is preferably about 500 to 2000 angstroms. The second polycrystalline sand composed of layers 24 and 26 is etched using conventional lithography technique # and anisotropic plasma etching After the chemical compound is hired, the second level of mutual edge is completed. In the same way, the interconnection of two polysilicon silicides with lower contact resistance is completed. Now please refer to FIGS. 5-7. The second embodiment described is a method and structure for forming a contact with low electric potential between the formulated polycrystalline silicide eyebrows. In this method, all methods except the method of touching the contact window are the same as the first implementation. The example is similar. Therefore, all the labels are the same as the first example, and the Phoenix Circle 5 is the same as the first paper before the engraved broadcast window. The standard is used. (Cns) A < wiyi Guang) {Poem first "Read the notes on the back and then fill out this page."
五、發明説明八0 ) ' 一資施例的圖2相周。在暹個實施例中，接餳窗只形成在場氣化物 區之類的絕緣雇上，'而且在繼緣層20內触刻播觸窗之後，接觸窗內 層14與16所組成的第一複晶矽化物眉也完全去除，臟到場氣化物 區0 5中，與_ 2—樣，由擄雜之襬晶砂層14與矽化物雇16所 組成的複晶矽化物層*沉獼在基板上*覆蠆住場氣化物區12與 FET閘極氣化靥8 (在圓5中只畫出部份）。制定櫬晶矽化物靥並 完成形成FET的步驟（LDD、側壁空間子、和源/汲極，未叢出） 之後，就沉積一層維緣層20。在雇20上塗佈_層光阻，並用傳統的 微影技術形成蝕刻光羣22，其鬮孔5正對舉FOX。 現在關始以非均向性蝕刻，在維緣靥20內齡刻禳觸窗。触刻 會持績到完全去除矽化物層16和權晶矽層14，瘋到FOX12的表面。 (在所形成的許多接觸中，附圓只畫出一個播_窗5。）從鼸6可 知，道遒非均向性蝕刻在襦晶矽化物層中形成了垂直的側壁，並露 出接觸窗5內摻雜之樓晶矽屬14的侧壁7。 沉積第二矽化物層24、加以摻雜，並形成WSi2—類的複晶矽 化物雇26以後，就完成了兩層的複晶矽化物互連。通兩層利用傳統 的徼影技術和非均向性電漿触刻制定以後，形成了第二雇次的複晶 矽化物互連。因爲在摻雜之第二複暴败JB26輿摻義之第一複晶矽層 的側壁之間，形成了電阻很低的複晶砂對観晶矽矇姆介面，所以可 以形成接觸電阻W很低、分佈很窄的接钃。場氧化物匾作爲触刻 中止層。像暹樣，在接觸窗5內触刻複晶矽層14薩到FOX12的表 面，可以容忍相當程度的通嗛鈾刻，所以成爲容黑繅作的製程。 例子 圖8的例子裏，脫明了第一實_的删試鑛«Μ罾知技藝所製 -· (請先》讀背V*之注意爭項再填寫本頁)Fifth, the description of the invention eight 0) 'Figure 2 of the same embodiment. In the Siam embodiment, the sugar-bonding window is only formed on the insulation of the field gasification zone and the like, and after the contact window is touched in the secondary layer 20, the contact window inner layer 14 and 16 A polycrystalline silicide eyebrow is also completely removed, and it is dirty in the field gasification zone 0 5. Like _ 2, the polycrystalline silicide layer composed of the extraneous pendulum crystal sand layer 14 and the silicide layer 16 Shen Ke On the substrate, cover the field vaporization area 12 and the FET gate vaporization gas 8 (only a part is drawn in circle 5). After formulating the crystalline silicide and completing the steps to form the FET (LDD, sidewall spacers, and source / drain, not clustered), a marginal layer 20 is deposited. A layer of photoresist is coated on the laser 20, and an etched light group 22 is formed by a conventional lithography technique, and its hole 5 is opposite to FOX. Now Guan Shi uses anisotropic etching to engrave the touch window in the 20-year-old Weiyuan. The etching will be successful until the silicide layer 16 and the right crystal silicon layer 14 are completely removed, and the surface of FOX12 is mad. (Among the many contacts formed, only one broadcast window 5 is drawn in the attached circle.) It can be seen from Man 6 that Dao Qi's anisotropic etching forms vertical sidewalls in the undersilicide layer and exposes the contact window 5. The side wall 7 of the doped crystalline silicon belongs to 14. After depositing a second silicide layer 24, doping it, and forming a WSi2-type polysilicon compound 26, the two layers of polysilicide interconnection are completed. After the two layers are formulated using traditional ray shadow technology and anisotropic plasma contact, the second polysilicide interconnection is formed. Since the sidewall of the first polycrystalline silicon layer of JB26 and the first polycrystalline silicon layer of the doped second complex defeat is formed, a low-resistance polycrystalline sand-to-silicon silmon interface is formed, so the contact resistance W can be formed very low , Very narrow distribution. The field oxide plaque acts as a contact stop layer. Like Siam, the polysilicon layer 14 touched on the surface of the FOX12 in the contact window 5 can tolerate a considerable degree of uranium engraving, so it becomes a process of Rong Hei reeling. Example In the example shown in Figure 8, the first real _ deletion test mine «M 罾 知 技艺 制 的--(please read the notes of V * before filling this page)
.T 本觥浪又度逋用申*钃家ϋ拿（CMS ) A4規格（：10 X29?公釐 經多邡士夬噤达兩—二消f合作.吐印S- 307912 五、發明説明、' 作的控制結構。 8是接觸電阻以黢姆爲II位，對70個瀾置點 作圖的結果。测試結構中，場氣化物Ι140(Χ)埃，第一複晶砂層厚約 1000埃，第一矽化物層厚約1000埃，緦緣層厚約1000埃。本發明 的第一實施例在蝕刻接觸窗時，是由緇緣眉起，触穿第一矽化物 層，一直到襦晶矽層的表面。控制轟圓的擁隱則_到第一矽化物 眉的表面。接著，在測試晶臞與控制墨圓上的接觸審都接受一道氫 氟酸(HF)/水(1 : 100)的蝕刻，然後才去除挖鼸搂嶋窗所用的光阻 光罩。接著用Rc迴路测試来瀾量接_電阻(RJ。匾8中的毎一個測 置點都代表晶圖上的一點，而毎一個測置黏都包括了2000個串連的 接觸。接觸電阻(Rc)是一個接觸的平均電阻。由_ 8中欏爲30的資 料點可以看出，一個直徑〇.4um的播觸，接钃電祖可以從約2500歐 姆到商達4900歐姆，而櫬爲32的資料黏，即習知技藝所製作一個直 徑0.5um的接觸，接觸電阻可以從約1300歃姆到約4300歐姆。 圖8的表中也顯示出本發明的方法所得到的捿觸電阻(RJ。 由欏爲40的資料點可以看出，直徑0.4um的接觸，接觸電阻約從 250歐姆到約700歐姆，而11徑0.5um的接觸，由嫌爲42的資料點可 以看出，其接觸電阻約爲200歐姆，而且阻値兼興很小。很明顬 地，本發明的方法確實能在複晶矽化物靥之間製作更爲改庚的接 觸。 雖然本發明係以悬佳11癱例加以讎糊，伹熟_釀技藝的人士都 能瞭解，本發明尚有許多細節上不岡的變化，並不邏僱難本發明的 範與精神。 {請先W讀背ή之注意亨項再填寫本頁) •Λ 訂 本纸張尺度適用中困國家螵車（〇5}.\4規格（110<；：9”公廣>.T The original wave again uses Shen * Jinjia (CMS) A4 specification (10 X29? Mm through the cooperation of two-two eliminations by multi-persons. Sprint 307912 V. Description of invention , 'Control structure. 8 is the result of the contact resistance with the black position as the II position, plotted against 70 points. In the test structure, the field vaporization Ι140 (Χ) Angstrom, the thickness of the first polycrystalline sand layer is about 1000 Angstroms, the thickness of the first silicide layer is about 1000 Angstroms, and the thickness of the edge layer is about 1000 Angstroms. In the first embodiment of the present invention, when the contact window is etched, the edge is raised from the edge of the edge, and the first silicide layer is touched. To the surface of the crystalline silicon layer. The control of the round circle's embedding is to the surface of the first silicide eyebrow. Then, the test of the contact between the test crystal and the control ink circle received a hydrofluoric acid (HF) / water (1: 100) etching, then remove the photoresist mask used for digging the window. Then use the Rc loop test to measure the resistance_R (RJ. Each measurement point in the plaque 8 represents the crystal One point on the graph, and each measurement stick includes 2000 contacts in series. The contact resistance (Rc) is the average resistance of a contact. You can see from the data points of 30 in _8 , A broadcast contact with a diameter of 0.4um, the electric ancestor can be from about 2500 ohms to 4900 ohms, and the data of 32 is sticky, that is, a contact with a diameter of 0.5um made by the conventional technology, the contact resistance can be from From about 1300 ohms to about 4300 ohms. The table in Figure 8 also shows the contact resistance (RJ) obtained by the method of the present invention. It can be seen from the data point of 40 for a contact with a diameter of 0.4um, the contact resistance is about From 250 ohms to about 700 ohms, and the 11-diameter 0.5um contact, it can be seen from the data point of 42 that the contact resistance is about 200 ohms, and the resistance is very small. It is very clear that the present invention The method can indeed make a more modified contact between polycrystalline silicides. Although the present invention is based on the example of Xuanjia 11 paralysis, people familiar with _ brewing technology can understand that there are many The changes in the details do not make it difficult to hire the scope and spirit of the present invention. {Please read the important terms of the book first and then fill out this page) • The standard paper size is suitable for the caravans in the troubled countries (〇 5}. \ 4Specifications (110 <;: 9 "public broadcasting >