TW202510109A - A semiconductor device, an optical devices, and a manufacturing method for semiconductor structures - Google Patents

Abstract

This application discloses a semiconductor device, an optical device, and a manufacturing method for semiconductor structures, wherein the manufacturing method comprises: forming a stacked structure on a substrate, the stacked structure comprising alternately stacked functional layers and sacrificial layers, the functional layers and sacrificial layers being composed of the same material, the sacrificial layer being doped with n-type or p-type impurities, and the doping concentration of the sacrificial layer being greater than that of the functional layer; selectively removing sacrificial layers from the stacked structure.

Description

Semiconductor device, optical device and method for manufacturing semiconductor structure

The present application belongs to the field of semiconductor technology, and specifically relates to a method for manufacturing a semiconductor device, an optical device and a semiconductor structure.

With the continuous advancement of Moore's Law, after the semiconductor process has developed to the 3nm node, the gate all around (GAA) transistor is considered to be an effective replacement for the fin field effect transistor (FinFET). In the GAA manufacturing process engineering, high selectivity is crucial to etching the horizontal stacked nanosheets of the sacrificial layer. The industry usually selectively removes SiGe in the Si and SiGe multi-layer stack to produce vertically stacked Si nanowires, thereby forming n-type GAA-FET.

However, due to the large difference in lattice constant between Si and SiGe, as the number of stacked Si and SiGe layers increases, internal stress will continue to accumulate. When the number of stacked Si and SiGe layers reaches a certain level, it will cause the wafer to warp, and in severe cases, it will even cause the wafer to break, thus limiting the number of stacked Si and SiGe layers. In addition, due to the lattice mismatch between the Si and SiGe layers, the dislocation defects of the Si layer epitaxially grown on the SiGe layer will increase. Since the Si layer will serve as the channel of the GAA-FET, the dislocation defects in the Si layer will also reduce the performance of the GAA-FET.

The present application embodiment discloses a method for manufacturing a semiconductor device, an optical device and a semiconductor structure to solve the problem in the related technology that the number of stacked layers is not high and dislocation defects are easily generated.

In order to solve the above technical problems, according to a first aspect, an embodiment of the present application discloses a method for manufacturing a semiconductor structure, comprising: forming a stacked structure on a substrate, the stacked structure comprising alternatingly stacked functional layers and sacrificial layers, the functional layers and the sacrificial layers being made of the same material, the sacrificial layers being doped with n-type or p-type impurities, and the doping concentration of the sacrificial layers being greater than the doping concentration of the functional layers; and selectively removing the sacrificial layers from the stacked structure.

In some embodiments, there are multiple functional layers and multiple sacrificial layers, at least a portion of at least one of the functional layers is curved or folded; and/or at least a portion of at least one of the sacrificial layers is curved or folded.

In some embodiments, the substrate is a plane and the stacked structure is formed on the plane; or the substrate includes a wavy surface and the stacked structure is adaptively formed on the wavy surface; or the substrate includes a protruding structure protruding from the surface of the substrate body, and the stacked structure is adaptively formed on the surface of the substrate body and the protruding structure.

In some embodiments, the protrusion structure includes: a first protrusion located on the substrate body; a second protrusion located on the first protrusion, the projection area of the second protrusion on the plane where the substrate body is located is larger than the projection area of the first protrusion on the plane where the substrate body is located, and the projection of the first protrusion on the plane where the substrate body is located is located within the projection of the second protrusion on the plane where the substrate body is located.

In some embodiments, selectively removing the sacrificial layer from the stacked structure includes: performing anisotropic etching on the stacked structure to retain the stacked structure directly below the second protrusion; and selectively removing the sacrificial layer from the retained stacked structure.

In some embodiments, the functional layer is a non-doped layer; or the doping concentration of the functional layer is less than 5×10 ¹⁴ cm ^-3 ; or the doping concentration of the sacrificial layer is greater than 5×10 ¹⁴ cm ^-3 ; or the doping concentration of the sacrificial layer is 6×10 ¹⁴ cm ^-3 to 5×10 ²¹ cm ^-3 .

In some embodiments, forming the stacked structure on the substrate includes: using a chemical vapor deposition process to alternately epitaxially grow the functional layer and the sacrificial layer on the substrate.

In some embodiments, the material of the functional layer and the sacrificial layer is silicon; the step of epitaxially growing the functional layer includes: introducing a silicon-containing gas into a process chamber; the step of epitaxially growing the sacrificial layer includes: introducing the silicon-containing gas and a gas containing impurity elements into the process chamber.

In some embodiments, the silicon-containing gas includes at least one of SiH ₄ , Si ₂ H ₆ , and SiH ₂ Cl ₂ ; the impurity-containing gas includes B ₂ H ₆ , or the impurity-containing gas includes at least one of PH ₃ , AsH ₃ , SbH ₃ , and BiH ₃ .

In some embodiments, the epitaxial growth temperature is 400°C to 750°C.

In some embodiments, the selectively removing the sacrificial layer from the stacked structure includes: performing isotropic plasma etching on the stacked structure using a process gas.

In some embodiments, the material of the functional layer and the sacrificial layer is silicon; and the process gas includes at least one of a chlorine-containing gas and a bromine-containing gas.

In some embodiments, the chlorine-containing gas includes at least one of Cl ₂ and HCl; the bromine-containing gas includes at least one of Br ₂ and HBr; and the process gas further includes at least one of N ₂ , He, and Ar.

In some embodiments, after the sacrificial layer is selectively removed from the stacked structure, the method further includes: performing an oxidation treatment on the functional layer; and removing the oxide layer on the surface of the functional layer.

According to the second aspect, the embodiment of the present application discloses a semiconductor device, comprising: a substrate; at least one functional layer, arranged on the substrate, at least one of the functional layers is arranged at intervals in the vertical direction, and at least a portion of at least one of the functional layers is curved or bent; a gate structure, arranged around each of the functional layers; and a source/drain region, respectively arranged on both sides of the functional layer and connected to the functional layer.

According to the third aspect, the embodiment of the present application discloses a semiconductor device, comprising: a substrate; at least one functional layer, arranged on the substrate, at least one of the functional layers is arranged at intervals in the vertical direction, and the functional layers are obtained by the manufacturing method of the semiconductor structure described in the first aspect above; a gate structure, arranged around each of the functional layers; and a source/drain region, respectively arranged on both sides of the functional layer and connected to the functional layer.

According to a fourth aspect, an embodiment of the present application discloses an optical device, comprising: at least one functional layer for transmitting an optical signal, wherein the functional layer is obtained by the manufacturing method of the semiconductor structure described in the first aspect above.

In the manufacturing method of the semiconductor device, optical device and semiconductor structure of the embodiment of the present application, the functional layer and the sacrificial layer are made of the same material, and only the doping concentration is different. There is almost no difference in the lattice constant of the functional layer and the sacrificial layer. There will be no stress caused by lattice mismatch at the interface between the functional layer and the sacrificial layer, and there will be no Dislocation defects are introduced into the functional layer; and, compared with the related technology using a gradient sacrificial layer, the thickness of the sacrificial layer of the embodiment of the present application can be made very thin, and the manufacturing process is simple, the number of stacked layers is high, and the production capacity is large. The number of stacked layers of the stacked structure of the embodiment of the present application can reach hundreds of layers, and there will be no phenomenon of wafer warping or even cracking.

The following disclosure provides many different embodiments or examples for implementing the different components of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, a first component formed above or on a second component in the following description may include an embodiment in which the first component and the second component are formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeatedly refer to numbers and/or letters in each example. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another element or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted similarly.

Although the numerical ranges and parameters setting forth the broad scope of the present disclosure are approximate, the numerical values set forth in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors necessarily due to the standard deviation found in the respective testing measurements. Furthermore, as used herein, the term "approximately" generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "approximately" means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Except in the operating/working examples, or unless otherwise explicitly specified, all numerical ranges, quantities, values and percentages for the amount of materials disclosed herein, the duration of time, temperature, operating conditions, the ratio of quantities and the like should be understood as being modified by the term "approximately" in all instances. Accordingly, unless otherwise indicated, the numerical parameters set forth in the present disclosure and the accompanying invention claims are approximate values that may vary as needed. At least, each numerical parameter should be interpreted in view of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to another or between two end points. All ranges disclosed herein include endpoints unless otherwise specified.

As mentioned above, due to the lattice mismatch between the Si layer and the SiGe layer, on the one hand, the number of stacked layers of the Si layer and the SiGe layer is limited, and on the other hand, dislocation defects are introduced into the Si layer, resulting in poor performance of the manufactured GAA-FET. In order to solve this technical problem, a solution is provided in the related technology, as shown in FIG1 . In this solution, when the SiGe layer 2 is epitaxially grown on the surface of the substrate 1, the Ge concentration in the SiGe layer 2 needs to be gradually changed, that is, the Ge concentration is first gradually increased as the thickness of the SiGe layer 2 grows, and then the Ge concentration is gradually reduced as the thickness of the SiGe layer 2 grows, so that the lattice constants of the two sides where the SiGe layer 2 contacts the Si layer 3 are close to those of the Si layer 3, so as to avoid or reduce the stress between the Si layer and the SiGe layer caused by lattice mismatch and the introduction of dislocation defects in the Si layer. However, since this solution requires continuous adjustment of Ge concentration during the epitaxial growth of SiGe layer 2, the process is highly complex and the manufacturing cost is high; on the other hand, since a thicker SiGe layer 2 needs to be formed to achieve a gradual buffer effect, the number of stacked layers is still not high and the production capacity is low.

To solve the above technical problems, the present application embodiment provides a method for manufacturing a semiconductor structure, as shown in FIG2 , the method may include the following steps:

S110. Forming a laminate structure on a substrate.

As shown in FIG4 and FIG5, FIG4 shows a schematic top view of the semiconductor structure of the embodiment of the present application, and FIG5 is a schematic cross-sectional view along the A-A line in FIG1. A stacked structure 200 is formed on the substrate 100, and the stacked structure 200 includes alternating functional layers 201 and sacrificial layers 202. Among them, the functional layer 201 is used to realize the function of the semiconductor structure. For example, when the semiconductor structure is used for GAA-FET, the functional layer 201 serves as a channel of the GAA-FET, and the sacrificial layer 202 is removed in the subsequent process. Those skilled in the art should understand that the present application is not limited to this, and the functional layer 201 can also realize other functions in different application scenarios, such as playing the role of a waveguide in an active or passive optical device.

The functional layer 201 and the sacrificial layer 202 are made of the same material, for example, both are made of Si. Those skilled in the art should understand that the functional layer 201 and the sacrificial layer 202 can also be made of other materials, for example, they can also be made of Ge, SiGe, GaAs, InSb, GaP, GaN, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. It should be noted that when the functional layer 201 and the sacrificial layer 202 are made of compound materials, the "same material" in the embodiment of the present application means that the compound material contains the same type of elements, and the proportion of each element is the same, only the doping concentration is different. There is a clear definition of n-type or p-type impurities in the art. By doping a small amount of n-type or p-type impurities into a semiconductor material, the main element composition of the semiconductor material will not be changed. The purpose is usually to change the concentration of free electrons or free holes in the semiconductor material to change the electrical properties of the semiconductor material. Those skilled in the art should understand that since the doping concentration of a conventional semiconductor doping process is extremely small relative to the content of the main element, different doping concentrations will hardly change the lattice constants of the functional layer 201 and the sacrificial layer 202. This "same material" with different doping concentrations makes the lattice constants of the functional layer 201 and the sacrificial layer 202 almost the same. For example, if the functional layer 201 and the sacrificial layer 202 are both composed of Si _x Ge _y , then the "same material" in the embodiment of the present application means that the proportions of Si and Ge are the same, that is, the values of x and y are the same, and only SiGe with different doping concentrations is doped. If the proportions of the elements constituting the compound material are different, even if the compound materials of the functional layer 201 and the sacrificial layer 202 contain the same type of elements, it will cause a large difference in the lattice constants of the functional layer 201 and the sacrificial layer 202. Therefore, when the compound materials of the functional layer 201 and the sacrificial layer 202 have different proportions of the elements, the problem of stress between the Si layer and the SiGe layer and introduction of dislocation defects in the Si layer caused by lattice mismatch in the related art cannot be solved. Those skilled in the art should understand that compound materials have the same constituent elements but different proportions of each element and should not be considered as the "same material" referred to in the embodiments of the present application. In some implementations of the embodiments of the present application, the sacrificial layer 202 may be doped with n-type or p-type impurities, and the functional layer 201 may be non-doped. For example, if the functional layer 201 is an intrinsic semiconductor, the doping concentration of the sacrificial layer 202 must be greater than the doping concentration of the functional layer 201 (i.e., no doping). In some other implementations of the present application, the functional layer 201 may also be doped, for example, the functional layer 201 is doped with n-type or p-type impurities, and the doping concentration of the sacrificial layer 202 is greater than the doping concentration of the functional layer 201.

In some implementations of the present application, the functional layer 201 may be a non-doped layer or a lightly doped layer, and the sacrificial layer 202 may be a heavily doped layer. Due to the difference in doping concentration between the functional layer 201 and the sacrificial layer 202, the sacrificial layer 202 can be selectively etched from the stacked structure 200 in a subsequent etching process. In some embodiments, the functional layer 201 may be made of an intrinsic semiconductor material, or the doping concentration of the functional layer 201 may be less than 5×10 ¹⁴ cm ^-3 , and the doping concentration of the sacrificial layer 202 may be greater than 5×10 ¹⁴ cm ^-3 . The inventors of the present application have found that the doping concentration of 5×10 ¹⁴ cm ^-3 is a cutoff point. Taking n-type doped Si material as an example, a doped layer with a doping concentration greater than 5×10 ¹⁴ cm ^-3 has a good etching selectivity relative to a doped layer or a non-doped layer with a doping concentration less than 5×10 ¹⁴ cm ^-3 . Furthermore, the doping concentration of the sacrificial layer 202 is not suitable to be too high. When the doping concentration of the sacrificial layer 202 is too high, the difference between the lattice constants of the functional layer 201 and the sacrificial layer 202 will increase. In some embodiments, the doping concentration of the sacrificial layer 202 is 6×10 ¹⁴ cm ^-3 to 5×10 ²¹ cm ^-3 , and more preferably 1×10 ¹⁵ cm ^-3 to 5×10 ²¹ cm ^-3 .

The substrate 100 includes a single crystal semiconductor layer on at least a portion of its surface. The substrate 100 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaN, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 100 may be made of crystalline Si. There may be other layers between the substrate 100 and the stacked structure 200. The materials of the substrate 100 and the functional layer 201 or the sacrificial layer 202 may be the same or different. When the materials of the substrate 100 and the functional layer 201 or the sacrificial layer 202 are different, a buffer layer may be present between the substrate 100 and the stacked structure 200. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate 100 to the lattice constant of the functional layer 201 or the sacrificial layer 202.

In the SiGe layer in the related technology, the Ge content is in the order of 20% to 50%, as shown in FIG11 , which makes the lattice constant of SiGe and the lattice constant of Si very different. Therefore, as the number of stacked Si and SiGe layers increases, the internal stress will also accumulate. When the number of stacked Si and SiGe layers reaches a certain level, it will cause the wafer to warp, and in severe cases, it may even cause the wafer to break, thereby limiting the number of stacked Si and SiGe layers. In the embodiment of the present application, the functional layer 201 and the sacrificial layer 202 are made of the same material, and only the doping concentration is different. The difference in lattice constant between the functional layer 201 and the sacrificial layer 202 is very small. Taking the functional layer 201 and the sacrificial layer 202 as Si materials as an example, when the sacrificial layer 202 is doped with V group elements such as P, the P atoms replace a small amount of Si atoms in the Si crystal and occupy the position on its lattice. The doping concentration of the conventional semiconductor doping process is extremely small compared with the Ge content in the SiGe layer, as shown in Figure 12, and the lattice constant of the sacrificial layer 202 is almost unchanged. Therefore, the lattice constants of the functional layer 201 and the sacrificial layer 202 are almost the same, and there will be no stress accumulation due to lattice mismatch at the interface between the functional layer 201 and the sacrificial layer 202, and no dislocation defects will be introduced into the functional layer 201. Compared with the related technology shown in FIG1 , the thickness of the sacrificial layer 202 of the stacked structure of the embodiment of the present application can be made very thin, for example, consistent with the thickness of the functional layer, the process is simple, the number of stacked layers is high and the production capacity is high. The number of stacked layers of the stacked structure of the embodiment of the present application can reach hundreds of layers, and there will be no phenomenon of wafer warping or even cracking, and no dislocation defects caused by lattice mismatch will be introduced into the functional layer 201.

In some implementations of the present application, the step S110 may include: using a chemical vapor deposition process to alternately epitaxially grow the functional layer 201 and the sacrificial layer 202 on the substrate 100.

In the example of FIG. 5 , the sacrificial layer 202 is first epitaxially grown on the substrate 100 , and then the functional layer 201 is epitaxially grown. However, the present application is not limited thereto. The functional layer 201 may be first epitaxially grown, and then the sacrificial layer 202 may be epitaxially grown. Furthermore, other layers may exist between the functional layer 201 and the sacrificial layer 202 .

Still taking the functional layer 201 and the sacrificial layer 202 as Si materials as an example, the step of epitaxially growing the functional layer 201 includes: introducing a silicon-containing gas into the process chamber; the step of epitaxially growing the sacrificial layer 202 includes: introducing a silicon-containing gas and a gas containing impurity elements into the process chamber. More specifically, the process chamber is a chemical vapor deposition (CVD) process chamber, and the silicon-containing gas may include at least one of SiH ₄ , Si ₂ H ₆ , and SiH ₂ Cl _2. In the step of epitaxially growing the functional layer 201, the silicon-containing gas is decomposed by heat, and Si atoms are deposited on the substrate surface to form a film. In the step of epitaxially growing the sacrificial layer 202, the gas containing silicon and the gas containing impurity elements are decomposed by heat, and Si atoms and impurity atoms are deposited on the substrate surface to form a film, that is, in-situ doping to form a doped semiconductor layer. When n-type doping is required, the gas containing impurity elements may include at least one of PH ₃ , AsH ₃ , SbH ₃ , and BiH ₃ ; when p-type doping is required, the gas containing impurity elements may include B ₂ H ₆ , for example. In some embodiments, the sacrificial layer 202 is doped with impurity elements with large atomic weight, such as As, Sb, Bi, etc. Correspondingly, the gas containing impurity elements used in the step of epitaxially growing the sacrificial layer 202 may include AsH ₃ , SbH ₃ , BiH ₃ , etc. Impurity elements with large atomic weight are more difficult to diffuse into the functional layer, which can avoid reducing the difference in doping concentration between the sacrificial layer 202 and the functional layer 201 and improve the etching selectivity of the sacrificial layer 202 relative to the functional layer 201.

In some implementations of the present application, the temperature of the epitaxial growth is 400° C. to 750° C. The temperature of the epitaxial growth should not be too high. If the temperature of the epitaxial growth is too high, some impurity atoms in the sacrificial layer 202 may diffuse into the functional layer 201, which will reduce the difference in doping concentration between the sacrificial layer 202 and the functional layer 201, thereby reducing the etching selectivity of the sacrificial layer 202 relative to the functional layer 201 in the subsequent selective etching process.

S120. Selectively removing the sacrificial layer from the laminate structure.

As shown in FIG9 , FIG9 is a schematic cross-sectional view along the A-A line in FIG1 , in which the sacrificial layer 202 is selectively removed from the stacked structure 200, and only the functional layer 201 is retained. In some implementations of the present application embodiment, the functional layer 201 can be used as a channel of a GAA-FET, for example, and a gate structure is formed around the functional layer 201 in a subsequent process.

In some implementations of the present application embodiment, as shown in FIG3 , after step S110 and before step S120, the following steps may also be included:

S111. Removing the sacrificial layer 202 of a predetermined thickness.

As shown in FIG6 , FIG6 is a schematic cross-sectional view along the B-B line in FIG4 . In the direction along the B-B line, both sides of the sacrificial layer 202 are removed by a predetermined thickness, which is approximately 3 nm to 10 nm, and more preferably approximately 5 nm.

S112. Filling the space formed by removing the predetermined thickness of the sacrificial layer 202 with the insulating layer 203.

As shown in FIG. 7 , the insulating layer 203 may be, for example, silicon nitride, and may be formed by, for example, an atomic layer deposition (ALD) process. The insulating layer 203 may be used, for example, to prevent a gate structure formed subsequently from being conductively connected to a source region or a drain region.

S113. Epitaxially grow an epitaxial layer 204 on the side surface of the functional layer 201.

As shown in Fig. 8, the epitaxial layer 204 can be used as the source and drain regions of the GAA-FET. Due to the support of the epitaxial layer 204, after removing the sacrificial layer 202, multiple functional layers 201 separated from each other can be formed as shown in Fig. 9.

In some implementations of the present application, the step S120 may include: performing isotropic plasma etching on the stacked structure 200 using process gas.

Since the sacrificial layer 202 needs to be etched laterally, isotropic plasma etching is required. During the etching process, the power of the lower electrode of the process chamber is 0, or a low power lower electrode is applied.

In order to improve the etching selectivity of the sacrificial layer 202 relative to the functional layer 201, and to completely remove the sacrificial layer 202 while leaving the functional layer 201 undamaged or only slightly damaged, the inventors of the present application have found through research that using chlorine-containing gas and/or bromine-containing gas as the main etching gas has good selectivity for the highly doped sacrificial layer 202, wherein the chlorine-containing gas may include at least one of Cl ₂ and HCl, and the bromine-containing gas may include at least one of Br ₂ and HBr. In order to further improve the etching morphology, the process gas may also include an auxiliary etching gas, and the auxiliary etching gas may include at least one of N ₂ , He, and Ar. Furthermore, in the process gas, the flow ratio of the auxiliary etching gas to the main etching gas can be 3 to 2500, wherein the flow rate of the main etching gas can be 20 sccm to 1000 sccm, and the flow rate of the auxiliary etching gas can be 3 slm to 50 slm. According to the test, the isotropic plasma etching of the embodiment of the present application can realize lateral etching of tens of microns and has a good etching selectivity.

In some implementations of the present application embodiment, after step S120, the following steps may also be included:

S121. Performing oxidation treatment on the functional layer 201.

The functional layer 201 may have residual impurity elements due to various factors. For example, in the process of forming the functional layer 201 by epitaxial growth, some impurity atoms in the heavily doped sacrificial layer 202 may diffuse into the functional layer 201, or after the selective etching of the sacrificial layer 202 in step S120, a small amount of the sacrificial layer 202 may still remain on the surface of the functional layer 201. In some application scenarios, the impurity elements remaining in the functional layer 201 may have adverse effects. For example, when the functional layer 201 is used as a channel of a GAA-FET, the residual impurity elements may make it difficult to completely close the channel. In order to remove these impurities, the functional layer 201 may be oxidized to form an oxide layer on the surface of the functional layer 201. When the functional layer 201 is made of Si material, the oxide layer is, for example, a silicon oxide layer. The oxide layer can enrich the impurity atoms near the surface of the functional layer 201 in the oxide layer.

S122. Removing the oxide layer on the surface of the functional layer 201.

Since impurity elements are concentrated in the oxide layer, after removing the oxide layer generated by oxidation of the surface of the functional layer 201, the impurity elements remaining in the functional layer 201 can be removed.

After the above steps S121 and S122, not only the impurity elements remaining in the functional layer 201 can be removed, but also the surface of the functional layer 201 can be made smoother. Since the burrs protruding from the surface of the functional layer 201 are more easily oxidized, after the oxide layer on the surface of the functional layer 201 is selectively removed, the burrs on the surface of the functional layer 201 can be removed to further improve the performance of the device manufactured later. In some embodiments, since the above steps S121 and S122 will remove a certain thickness of the functional layer, the thickness of the functional layer can be slightly greater than the predetermined thickness during the epitaxial growth of the functional layer, so that the thickness of the functional layer can be exactly equal to the predetermined thickness after the steps S121 and S122.

In order to form a semiconductor device, in some implementations of the present application embodiment, after step S120, the following steps may also be included:

S130. A gate structure is formed around the functional layer.

As shown in FIG10 , a gate structure is formed around the functional layer 201 , so that the functional layer 201 serves as a trench of the semiconductor device, and the gate structure is disposed around the trench. The gate structure may include a gate dielectric layer 205 and a gate electrode layer 206 disposed around the functional layer 201 . The gate dielectric layer 205 may, for example, include one or more layers of dielectric materials, such as high-k dielectric materials such as _HfO2 ; the gate electrode layer 206 may include one or more layers of conductive materials, such as polycrystalline silicon, aluminum, copper, titanium, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys thereof, other suitable materials and/or combinations thereof.

Correspondingly, when the functional layer is used as a channel of a semiconductor device, the embodiment of the present application also provides a semiconductor device, as shown in FIG. 3 to FIG. 10, the semiconductor device may include a substrate 100; at least one functional layer 201, disposed on the substrate 100, at least one functional layer 201 is disposed at intervals in the vertical direction, and the functional layer 201 is obtained by the manufacturing method of the semiconductor structure described above; a gate structure, disposed around each functional layer 201; a source/drain region 204, disposed on both sides of the functional layer 201, and connected to the functional layer 201. Preferably, there are multiple functional layers 201. More specifically, the semiconductor device may be, for example, a 3D DRAM.

When the functional layer is used as a waveguide of an optical device, the embodiment of the present application further provides an optical device, which includes at least one functional layer 201, the functional layer 201 is used to transmit an optical signal, and the functional layer 201 is obtained by the manufacturing method of the semiconductor structure described above. Preferably, there are multiple functional layers 201.

Since each layer in the stacked structure of the embodiment of the present application is made of the same material, the difference in lattice constant between the layers is extremely small, and stress will not be accumulated during the epitaxial growth process to cause the wafer to warp or even break, and dislocation defects will not be introduced into the functional layer. Therefore, the stacked structure of the embodiment of the present application can be formed not only on a plane, but also on various complex surfaces to meet the needs of different application scenarios. In this case, at least a portion of at least one of the functional layers of the stacked structure is bent or folded, and/or at least a portion of at least one of the sacrificial layers of the stacked structure is bent or folded. The conventional Si/SiGe stacked structure cannot be manufactured because the bends or bends will introduce greater stress. The stacked structure with a bend or bend in the embodiment of the present application will be described in detail through several examples. Those skilled in the art should understand that the examples below are not exhaustive. Since there is almost no lattice constant difference between the functional layer and the sacrificial layer of the stacked structure implemented in the present application, those skilled in the art can design other stacked structures with a bend or bend according to actual conditions.

In an example of an embodiment of the present application, as shown in FIG. 13 and FIG. 14 , the substrate 110 includes a wavy surface. It should be understood by those skilled in the art that the substrate 110 need not be entirely a wavy surface, but may only be partially a wavy surface. A stacked structure 210 is adaptively formed on the wavy surface of the substrate 110. The stacked structure 210 includes alternately stacked functional layers 211 and sacrificial layers 212. Similarly, the functional layers 211 and sacrificial layers 212 may be alternately epitaxially grown on the substrate 110 using a chemical vapor deposition process. After the sacrificial layer 212 is selectively removed from the stacked structure 210, a plurality of mutually spaced wavy functional layers 211 are formed as shown in FIG. 14 . For further details on the steps of forming a laminate structure on a substrate and selectively removing the sacrificial layer from the laminate structure, reference may be made to the corresponding description above and will not be repeated here.

In another example of the embodiment of the present application, as shown in Figures 15 and 16, the substrate 120 includes a protruding structure 122 protruding from the surface of the substrate body 121, and the stacking structure 220 is adaptively formed on the surface of the substrate body 121 and the protruding structure 122. The stacking structure 220 includes alternatingly stacked functional layers 221 and sacrificial layers 222. After the sacrificial layer 222 is selectively removed from the stacking structure 220, a plurality of mutually spaced functional layers 221 similar to the character Ω are formed as shown in Figure 16. In the examples of FIG. 15 and FIG. 16 , the cross section of the protrusion structure 122 is rectangular, but the present application is not limited thereto, and the protrusion structure may also be in other shapes, as shown in FIG. 17 , the protrusion structure may be a sawtooth-shaped protrusion structure 123 or a trapezoidal protrusion structure 124, etc. In the examples of FIG. 15 and FIG. 16 , the top and side surfaces of the protrusion structure 122 are both planes, but the present application is not limited thereto, and the surface of the protrusion structure may be all curved, such as the protrusion structure 125 in FIG. 17 , or partially curved, such as the protrusion structure 126 in FIG. 17 . Those skilled in the art should also understand that the upper surface of the lining body 121 is not limited to being a plane, and may also include a curved or bent surface. For further details on the steps of forming a laminate structure on a substrate and selectively removing the sacrificial layer from the laminate structure, reference may be made to the corresponding description above and will not be repeated here.

In another example of the embodiment of the present application, as shown in Figures 18 to 20, the substrate 130 has a protruding structure protruding from the surface of the substrate body 131, and the protruding structure may include a first protruding portion 132 and a second protruding portion 133, wherein the first protruding portion 132 is located on the substrate body 131, and the second protruding portion 133 is located on the first protruding portion 132, and the projection area of the second protruding portion 133 on the plane where the substrate body 131 is located is larger than the projection area of the first protruding portion 132 on the plane where the substrate body 131 is located, and the projection of the first protruding portion 132 on the plane where the substrate body 131 is located is located within the projection of the second protruding portion 133 on the plane where the substrate body 131 is located. The laminated structure 230 is adaptively formed on the surface of the substrate body 131 and the protruding structure, and the laminated structure 230 includes alternately stacked functional layers 231 and sacrificial layers 232. For further details of the step of forming the laminated structure on the substrate, reference can be made to the corresponding description above, which will not be repeated here.

Furthermore, the step of selectively removing the sacrificial layer 232 from the stacked structure 230 may include:

S120a. Performing anisotropic etching on the stacked structure 230.

In this step, the lower electrode power can be applied to the process chamber to realize anisotropic plasma etching. In the anisotropic etching process, the substrate body 131 and the second protrusion 133 have a high etching selectivity relative to the functional layer 231 and the sacrificial layer 232, that is, the second protrusion 133 becomes an etching mask, and the stacked structure 230 except directly below the second protrusion 133 is etched, and only the stacked structure 230 directly below the second protrusion 133 is retained, as shown in FIG. 19 .

S120b. Selectively removing the sacrificial layer 232 from the retained stacked structure 230.

As shown in Figure 20, after the sacrificial layer 232 is selectively removed from the stacked structure 230, a plurality of mutually separated functional layers 221 similar to those in brackets are formed. For further details on the step of selectively removing the sacrificial layer from the stacked structure, reference can be made to the corresponding description above, which will not be repeated here.

In the examples shown in Figures 13 to 20, the formation of a stacking structure on substrates of various morphologies is described exemplarily, and the functional layer and sacrificial layer in the stacking structure are adaptively formed on the substrate to form a curved or folded shape, and the sacrificial layer is selectively removed from the stacking structure to obtain functional layers of different morphologies separated from each other. These functional layers of different morphologies can meet the needs of different application scenarios. For example, when the semiconductor structure is used in GAA-FET, the functional layer in the embodiment of the present application is curved or bent, and compared with the straight channel in the conventional GAA-FET, when a gate structure is formed around the functional layer of the embodiment of the present application, the gate width is wider, which can better suppress the short channel effect and achieve better control of the leakage current. When the semiconductor structure is used in an active or passive optical device, the functional layer in the embodiment of the present application can play the role of a waveguide, and can realize the propagation of optical signals between endpoints in different scenarios.

Correspondingly, the embodiment of the present application further provides a semiconductor device, as shown in FIG. 21 , the semiconductor device may include: a substrate 110; at least one functional layer 211, disposed on the substrate, at least one functional layer 211 is disposed at intervals in the vertical direction, and at least a portion of at least one of the functional layers 211 is curved; a gate structure, disposed around each functional layer 211; source/drain regions (not shown), disposed on both sides of the plurality of functional layers 211, and connected to the functional layers 211. In the present embodiment, the gate structure may include a gate dielectric layer 215 and a gate electrode layer 216 disposed around the functional layer 211. Since the functional layer of the semiconductor device of the embodiment of the present application is curved or bent, compared with the conventional straight channel, the gate width of the semiconductor device of the embodiment of the present application is wider, which can better suppress the short channel effect and achieve better control of the leakage current. Preferably, there are multiple functional layers 211. More specifically, the semiconductor device can be, for example, a 3D DRAM.

In the example of FIG. 21 , all functional layers 211 are curved. A person skilled in the art should understand that only some functional layers 211 may be curved. A functional layer 211 need not be all curved. A partial section of a functional layer 211 may be curved. A person skilled in the art should understand that a functional layer may be bent, such as the bent shape shown in FIGS. 15 to 20 . Similarly, not all functional layers need be bent. Only some functional layers 211 may be bent. A functional layer need not be all curved. A partial section of a functional layer may be bent. Those skilled in the art should also understand that in the semiconductor device of the embodiment of the present application, some functional layers may include curved segments or all may be curved, some functional layers may include bent segments or all may be bent, or one functional layer may include both curved segments and bent segments, and the present application does not impose any limitation on this.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

100: substrate 110: substrate 120: substrate 121: substrate body 122: raised structure 123: sawtooth raised structure 124: trapezoidal raised structure 125: raised structure 126: raised structure 130: substrate 131: substrate body 132: first raised portion 133: second raised portion 200: stacked structure 201: functional layer 202: sacrificial layer 203: insulating layer 204: epitaxial layer 205: gate dielectric layer 206: gate electrode layer 210: stacked structure 211: functional layer 212: sacrificial layer 215: gate dielectric layer 216: gate electrode layer 220: stacked structure 221: functional layer 222: sacrificial layer 230: stacked structure 231: functional layer 232: sacrificial layer S110-S130: steps

The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. Figure 1 shows a schematic diagram of a Si/SiGe stacked structure in the related art; Figure 2 shows a flow chart of a method for manufacturing a semiconductor structure of an embodiment of the present application; Figure 3 shows another flow chart of a method for manufacturing a semiconductor structure of an embodiment of the present application; Figures 4 to 10 respectively show schematic diagrams of the structures of each step of the method for manufacturing a semiconductor structure of an embodiment of the present application; Figure 11 shows a schematic diagram of the lattice of a SiGe material; Figure 12 shows a schematic diagram of the lattice of a Si material doped with P elements; Figures 13 and 14 show schematic diagrams of the structures of each step of a method for manufacturing an example semiconductor structure of an embodiment of the present application; Figures 15 and 16 show schematic diagrams of the structures of each step of a method for manufacturing an example semiconductor structure of an embodiment of the present application; FIG. 17 shows a schematic diagram of another example of a protruding structure in an embodiment of the present application; FIG. 18 to FIG. 20 show schematic diagrams of the structures of each step of a method for manufacturing an example semiconductor structure in an embodiment of the present application; FIG. 21 shows a schematic diagram of a semiconductor device in an embodiment of the present application.

S110, S120: Steps

Claims (17)

A method for manufacturing a semiconductor structure, comprising: Forming a stacked structure on a substrate, the stacked structure comprising a functional layer and a sacrificial layer alternately stacked, the functional layer and the sacrificial layer being made of the same material, the sacrificial layer being doped with n-type or p-type impurities, and the doping concentration of the sacrificial layer being greater than the doping concentration of the functional layer; Selectively removing the sacrificial layer from the stacked structure. The manufacturing method as described in claim 1, wherein the functional layer and the sacrificial layer are multiple, at least a portion of at least one of the functional layers is curved or folded; and/or At least a portion of at least one of the sacrificial layers is curved or folded. The manufacturing method as described in claim 1, wherein the substrate is a plane and the laminated structure is formed on the plane; or the substrate includes a wavy surface and the laminated structure is adaptively formed on the wavy surface; or the substrate includes a protruding structure protruding from the surface of the substrate body, and the laminated structure is adaptively formed on the surface of the substrate body and the protruding structure. The manufacturing method as described in claim 3, wherein the protrusion structure comprises: a first protrusion located on the substrate body; a second protrusion located on the first protrusion, the projection area of the second protrusion on the plane where the substrate body is located is larger than the projection area of the first protrusion on the plane where the substrate body is located, and the projection of the first protrusion on the plane where the substrate body is located is located within the projection of the second protrusion on the plane where the substrate body is located. The manufacturing method as described in claim 4, wherein the sacrificial layer is selectively removed from the stacked structure, comprising: performing anisotropic etching on the stacked structure to retain the stacked structure directly below the second protrusion; selectively removing the sacrificial layer from the retained stacked structure. The manufacturing method as described in claim 1, wherein the functional layer is a non-doped layer; or the doping concentration of the functional layer is less than 5×10 ¹⁴ cm ^-3 ; or the doping concentration of the sacrificial layer is greater than 5×10 ¹⁴ cm ^-3 ; or the doping concentration of the sacrificial layer is 6×10 ¹⁴ cm ^-3 to 5×10 ²¹ cm ^-3 . The manufacturing method as described in any one of claims 1 to 6, wherein forming the stacked structure on the substrate comprises: Using a chemical vapor deposition process, alternately epitaxially growing the functional layer and the sacrificial layer on the substrate. The manufacturing method as described in claim 7, wherein the material of the functional layer and the sacrificial layer is silicon; The step of epitaxially growing the functional layer includes: introducing a silicon-containing gas into a process chamber; The step of epitaxially growing the sacrificial layer includes: introducing the silicon-containing gas and the gas containing impurity elements into the process chamber. _The manufacturing method as described in claim 8, wherein the silicon-containing gas includes at least one of _SiH4 , _Si2H6 , _{and SiH2Cl2} ; the gas containing impurity elements includes _B2H6 , or the gas containing impurity elements includes at least one of _PH3 , _AsH3 , _SbH3 , _{and BiH3} . A manufacturing method as described in claim 7, wherein the temperature of the epitaxial growth is 400°C to 750°C. A manufacturing method as described in any one of claims 1 to 6, wherein the sacrificial layer is selectively removed from the stacked structure, comprising: Isotropically plasma etching the stacked structure using a process gas. The manufacturing method as described in claim 11, wherein the material of the functional layer and the sacrificial layer is silicon; The process gas includes at least one of a chlorine-containing gas and a bromine-containing gas. The manufacturing method as described in claim 12, wherein the chlorine-containing gas includes at least one of Cl ₂ and HCl; the bromine-containing gas includes at least one of Br ₂ and HBr; and the process gas further includes at least one of N ₂ , He, and Ar. The manufacturing method as described in any one of claims 1 to 6, wherein after the sacrificial layer is selectively removed from the laminate structure, it further includes: Oxidizing the functional layer; Removing the oxide layer on the surface of the functional layer. A semiconductor device, comprising: a substrate; at least one functional layer, disposed on the substrate, at least one of the functional layers being disposed at intervals in the vertical direction, at least a portion of at least one of the functional layers being curved or bent; a gate structure, disposed around each of the functional layers; a source/drain region, disposed on both sides of the functional layer, and connected to the functional layer. A semiconductor device, comprising: a substrate; at least one functional layer, disposed on the substrate, at least one of the functional layers being disposed at intervals in the vertical direction, the functional layers being obtained by the method for manufacturing a semiconductor structure described in any one of claims 1 to 14; a gate structure, disposed around each of the functional layers; a source/drain region, disposed on both sides of the functional layer, and connected to the functional layer. An optical device, comprising: At least one functional layer for transmitting an optical signal, the functional layer being obtained by the method for manufacturing a semiconductor structure as described in any one of claims 1 to 14.

Images