TW202137416A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TW202137416A
TW202137416A TW109110881A TW109110881A TW202137416A TW 202137416 A TW202137416 A TW 202137416A TW 109110881 A TW109110881 A TW 109110881A TW 109110881 A TW109110881 A TW 109110881A TW 202137416 A TW202137416 A TW 202137416A
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layer
contact
capacitive contact
semiconductor
bit line
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TW109110881A
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TWI713156B (en
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池田典昭
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華邦電子股份有限公司
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Abstract

A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

Description

半導體元件及其製造方法Semiconductor element and its manufacturing method

本發明實施例是有關於一種半導體元件及其製造方法,且特別是有關於一種動態隨機存取記憶體元件及其製造方法。The embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a dynamic random access memory device and a manufacturing method thereof.

動態隨機存取記憶體(dynamic random access memory,DRAM)是一種廣泛應用的半導體記憶元件。DRAM積體電路的記憶體胞元包括場效電晶體和儲存電容。場效電晶體的閘極連接到字元線,而場效電晶體的源極、汲極則分別連接到位元線及儲存電容。為了在不過度縮小DRAM積體電路中相鄰儲存電容之間的間距之情況下提高儲存電容的面積(也就是提高儲存電容的電容值),儲存電容可相對於其下方的電容接觸結構而位移一特定距離。然而,此儲存電容的位移可能造成儲存電容和位元線的交疊,而可能導致發生於此兩者之間的擊穿效應(punch through effect)。Dynamic random access memory (DRAM) is a widely used semiconductor memory element. The memory cell of a DRAM integrated circuit includes field effect transistors and storage capacitors. The gate of the field effect transistor is connected to the word line, and the source and drain of the field effect transistor are respectively connected to the bit line and the storage capacitor. In order to increase the area of the storage capacitor (that is, increase the capacitance value of the storage capacitor) without excessively reducing the distance between adjacent storage capacitors in the DRAM integrated circuit, the storage capacitor can be displaced relative to the capacitor contact structure below it A certain distance. However, the displacement of the storage capacitor may cause the overlap of the storage capacitor and the bit line, and may cause a punch through effect between the two.

本發明實施例提供一種DRAM元件及其製造方法,可避免位元線和儲存電容之間的擊穿效應。The embodiment of the present invention provides a DRAM element and a manufacturing method thereof, which can avoid the breakdown effect between the bit line and the storage capacitor.

本發明的半導體元件包括主動區域、位元線、電容接觸結構、導電環以及儲存電容。主動區域形成在基底中。位元線和電容接觸結構設置於基底上且與主動區域電性連接。位元線與電容接觸結構彼此側向分離,且位元線的頂面低於電容接觸結構的頂面。導電環圍繞電容接觸結構的頂部。儲存電容設置於電容接觸結構及導電環上,且電性連接於電容接觸結構與導電環。The semiconductor device of the present invention includes an active area, a bit line, a capacitive contact structure, a conductive ring, and a storage capacitor. The active area is formed in the substrate. The bit line and the capacitive contact structure are arranged on the substrate and electrically connected with the active area. The bit line and the capacitor contact structure are laterally separated from each other, and the top surface of the bit line is lower than the top surface of the capacitor contact structure. The conductive ring surrounds the top of the capacitive contact structure. The storage capacitor is arranged on the capacitor contact structure and the conductive ring, and is electrically connected to the capacitor contact structure and the conductive ring.

本發明的記憶體元件的製造方法包括:在基底上形成主動區域;在基底上形成位元線與電容接觸結構,其中位元線與電容接觸結構彼此側向分離,位元線與電容接觸結構電性連接於主動區域,且位元線的頂面低於電容接觸結構的頂面;形成圍繞電容接觸結構的頂部的導電環;以及在電容接觸結構與導電環上形成儲存電容。The manufacturing method of the memory device of the present invention includes: forming an active area on a substrate; forming a bit line and a capacitor contact structure on the substrate, wherein the bit line and the capacitor contact structure are laterally separated from each other, and the bit line and the capacitor contact structure It is electrically connected to the active area, and the top surface of the bit line is lower than the top surface of the capacitive contact structure; a conductive ring surrounding the top of the capacitive contact structure is formed; and a storage capacitor is formed on the capacitive contact structure and the conductive ring.

基於上述,藉由設置環繞電容接觸結構的頂部的導電環,導電環CR可保護位於其下方的構件,以使其免於在形成儲存電容的期間受到損害。因此,可避免電荷經由導電環下方的此些構件而擊穿至下方的位元線,而可提高半導體元件的可靠度。再者,藉由在電容接觸結構的頂部周圍設置導電環,可擴大儲存電容能著陸(land over)的導電區域。據此,增加儲存電容與電容接觸結構之間的接觸裕度(contact margin)。此外,由於可藉由自對準圖案化製程來形成導電環,因此不需要進行額外的微影製程。Based on the above, by providing a conductive ring surrounding the top of the capacitive contact structure, the conductive ring CR can protect the components located below it from damage during the formation of the storage capacitor. Therefore, it is possible to prevent the charge from breaking down to the bit line below through these components under the conductive ring, and the reliability of the semiconductor device can be improved. Furthermore, by arranging a conductive ring around the top of the capacitor contact structure, the conductive area where the storage capacitor can land over can be enlarged. Accordingly, the contact margin between the storage capacitor and the capacitor contact structure is increased. In addition, since the conductive ring can be formed by a self-aligned patterning process, no additional lithography process is required.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1是依照本發明一實施例的半導體元件的製造方法的流程圖。圖2A至圖2K是圖1所示的半導體元件的製造方法中各階段的結構的上視示意圖。圖3A至圖3K分別為圖2A至圖2K的線X-X’的剖視示意圖。FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2A to 2K are schematic top views of the structure at each stage in the method of manufacturing the semiconductor device shown in FIG. 1. 3A to 3K are schematic cross-sectional views taken along the line X-X' of FIGS. 2A to 2K, respectively.

請參照圖1與圖2A,進行步驟S100,以形成場效電晶體T、電容接觸結構CC、字元線WL以及位元線BL。在一實施例中,字元線WL沿方向D1延伸,而位元線BL沿交錯於方向D1的方向D2延伸。舉例而言,方向D1可垂直於方向D2。至少一場效電晶體T交疊於一主動區域AA。舉例而言,如圖2A所示,兩個場效電晶體T形成於同一主動區域AA的範圍內。舉例而言,主動區域AA可為設置於基底S中的摻雜區(如圖3A所示),且場效電晶體T為埋入式場效電晶體。儘管在圖2A中僅描繪出單一主動區域AA,實際上基底S中形成有多個主動區域AA(如圖3A所示)。多個主動區域AA彼此分離,並沿交錯於方向D1及方向D2的方向D3延伸。在一實施例中,方向D2與方向D3之間的夾角為20°至40°。場效電晶體T的閘極(未繪示)交疊且電性連接於其中一條字元線WL。在一實施例中,字元線WL可為埋入式字元線且形成在基底S(如圖3A所示)內。此外,場效電晶體T的源極與汲極(未繪示)中的一者交疊且電性連接於一條位元線BL,而另一者交疊且電性連接於一個電容接觸結構CC。1 and 2A, step S100 is performed to form a field effect transistor T, a capacitor contact structure CC, a word line WL, and a bit line BL. In one embodiment, the word line WL extends along the direction D1, and the bit line BL extends along the direction D2 staggered with the direction D1. For example, the direction D1 may be perpendicular to the direction D2. At least one field effect transistor T overlaps an active area AA. For example, as shown in FIG. 2A, two field effect transistors T are formed in the same active area AA. For example, the active area AA may be a doped area disposed in the substrate S (as shown in FIG. 3A), and the field effect transistor T is a buried field effect transistor. Although only a single active area AA is depicted in FIG. 2A, in fact, multiple active areas AA are formed in the substrate S (as shown in FIG. 3A). The multiple active areas AA are separated from each other and extend along the direction D3 which is staggered with the direction D1 and the direction D2. In one embodiment, the angle between the direction D2 and the direction D3 is 20°-40°. The gates (not shown) of the field effect transistor T overlap and are electrically connected to one of the word lines WL. In an embodiment, the word line WL may be a buried word line and formed in the substrate S (as shown in FIG. 3A). In addition, one of the source and drain (not shown) of the field effect transistor T overlaps and is electrically connected to a bit line BL, while the other overlaps and is electrically connected to a capacitive contact structure CC.

電容接觸結構CC經配置以電性連接於場效電晶體T以及在後續步驟中所形成的儲存電容SC(如圖2K和圖3K所示)之間。在一實施例中,多個電容接觸結構CC可陣列排列,而具有沿方向D1延伸的列與沿方向D2延伸的行。在一實施例中,每一行的電容接觸結構CC至少部分地交疊於一字元線WL。在替代實施例中,電容接觸結構CC並未交疊於字元線WL。另一方面,每一行的電容接觸結構CC位於一位元線BL一旁,且並未與其電性連接。此外,在一實施例中,電容接觸結構CC的上視圖形實質上為矩形。然而,所屬領域中具有通常知識者可根據設計需求改變電容接觸結構CC的上視圖形,本發明並不以此為限。The capacitive contact structure CC is configured to be electrically connected between the field effect transistor T and the storage capacitor SC formed in the subsequent steps (as shown in FIG. 2K and FIG. 3K). In an embodiment, the plurality of capacitive contact structures CC may be arranged in an array, and have columns extending along the direction D1 and rows extending along the direction D2. In one embodiment, the capacitive contact structure CC in each row at least partially overlaps a word line WL. In an alternative embodiment, the capacitive contact structure CC does not overlap the word line WL. On the other hand, the capacitive contact structure CC in each row is located beside the bit line BL, and is not electrically connected to it. In addition, in an embodiment, the top view of the capacitive contact structure CC is substantially rectangular. However, those skilled in the art can change the top view of the capacitive contact structure CC according to design requirements, and the present invention is not limited to this.

在一實施例中,每行的電容接觸結構CC形成於一條隔離結構IS中。隔離結構IS可包括多個接觸結構間隔離結構IS1以及多個隔離壁IS2。沿著行方向(亦即方向D2)來看,接觸結構間隔離結構IS1位於相鄰的電容接觸結構CC之間,隔離壁IS2沿著多個電容接觸結構CC及多個接觸結構間隔離結構IS1的彼此相對的側壁而延伸。如此一來,在行方向(亦即方向D2)上相鄰的電容接觸結構CC藉由接觸結構間隔離結構IS1而彼此間隔開。此外,沿著列方向(亦即方向D1)來看,電容接觸結構CC藉由隔離壁IS2而與與其相鄰的位元線BL彼此間隔開。在一實施例中,接觸結構間隔離結構IS1與隔離壁IS2的材料分別包括氮化矽,氧化矽,氮氧化矽,低介電常數(介電常數低於4)介電材料或其組合。在另一實施例中,隔離壁IS2可為多層結構,例如是氧化物-氮化物-氧化物(oxide/nitride/oxide,ONO)多層結構。此外,在其他實施例中,隔離壁IS2中具有空氣間隙。In an embodiment, the capacitive contact structure CC of each row is formed in a line of isolation structure IS. The isolation structure IS may include a plurality of isolation structures IS1 between contact structures and a plurality of isolation walls IS2. Viewed along the row direction (that is, direction D2), the inter-contact structure isolation structure IS1 is located between adjacent capacitive contact structures CC, and the isolation wall IS2 is along the plurality of capacitive contact structures CC and the plurality of inter-contact structure isolation structures IS1 The sidewalls opposite to each other extend. In this way, adjacent capacitive contact structures CC in the row direction (that is, the direction D2) are spaced apart from each other by the inter-contact structure isolation structure IS1. In addition, viewed along the column direction (ie, the direction D1), the capacitive contact structure CC is separated from the adjacent bit line BL by the isolation wall IS2. In one embodiment, the materials of the isolation structure IS1 between the contact structures and the isolation wall IS2 include silicon nitride, silicon oxide, silicon oxynitride, low-k (dielectric constant less than 4) dielectric materials, or a combination thereof. In another embodiment, the isolation wall IS2 may have a multilayer structure, such as an oxide/nitride/oxide (ONO) multilayer structure. In addition, in other embodiments, there is an air gap in the partition wall IS2.

圖3A是沿圖2A的線X-X’的剖視示意圖。請參照圖2A與圖3A,多個溝渠隔離結構TI形成於基底S中。溝渠隔離結構TI經配置以使多個主動區域AA彼此隔離。溝渠隔離結構TI由基底S的頂面向下延伸。在一實施例中,多個溝渠隔離結構TI可為淺溝渠隔離結構、深溝渠隔離結構或其組合。另外,在一實施例中,溝渠隔離結構TI的材料包括氧化矽或其他絕緣材料。Fig. 3A is a schematic cross-sectional view taken along the line X-X' of Fig. 2A. 2A and 3A, a plurality of trench isolation structures TI are formed in the substrate S. The trench isolation structure TI is configured to isolate the multiple active areas AA from each other. The trench isolation structure TI extends downward from the top surface of the substrate S. In an embodiment, the plurality of trench isolation structures TI may be shallow trench isolation structures, deep trench isolation structures, or a combination thereof. In addition, in an embodiment, the material of the trench isolation structure TI includes silicon oxide or other insulating materials.

隔離結構IS包括形成於基底S上的多個接觸結構間隔離結構IS1及多個隔離壁IS2。電容接觸結構CC及位元線BL可視為設置於隔離結構IS中。此外,電容接觸結構CC與位元線BL電性連接於位於基底S中的主動區域AA,以使電容接觸結構CC與位元線BL可分別電性連接到設置於主動區域AA中的場效電晶體T的源極與汲極(未繪示)。如圖3A所示,多個電容接觸結構CC與多條位元線BL沿著列方向(亦即方向D1)而交替地排列,且隔離壁IS2設置於相鄰的電容接觸結構CC與位元線BL之間。在一實施例中,位元線接觸結構BC設置於且電性連接於主動區域AA與位元線BL之間。位元線BL與其下方的位元線接觸結構BC位於相鄰的隔離壁IS2之間。在一實施例中,位元線BL與其下方的位元線接觸結構BC位於且實體接觸於相鄰的隔離壁IS2之間。此外,位元線BL的側壁可實質上共面於下方的位元線接觸結構BC之側壁。在一實施例中,多個位元線接觸結構BC分別包括導電結構CS1及覆蓋於導電結構CS1的頂面上的阻障層BR1。另一方面,在一實施例中,多個電容接觸結構CC分別包括導電結構CS2及覆蓋導電結構CS2的底面及側面的阻障層BR2。除此之外,在一實施例中,多個接觸插塞CP分別設置於一電容接觸結構CC與基底之間。多個接觸插塞CP分別電性連接於一電容接觸結構CC與基底S中的一主動區域AA之間。電容接觸結構CC及其下方的接觸插塞CP位於相鄰的隔離壁IS2之間。在一實施例中,電容接觸結構CC及其下方的接觸插塞CP實體接觸於相鄰的間隔壁IS2之間。此外,電容接觸結構CC的側壁可實質上共面於其下方的接觸插塞CP的側壁。再者,在一實施例中,可在接觸插塞CP與電容接觸結構CC之間設置金屬矽化物層MS。在一實施例中,位元線BL及接觸插塞CP的材料可包括多晶矽。導電結構CS1及導電結構CS2的材料包括可包括鎢,而阻障層BR1及阻障層BR2的材料可包括氮化鈦、氮化鉭、鈦鎢合金、其類似者或其組合。此外,此金屬矽化物層MS的材料可包括矽化鈷、矽化鎢、矽化鈦、矽化鉭、其類似者或其組合。The isolation structure IS includes a plurality of inter-contact structure isolation structures IS1 and a plurality of isolation walls IS2 formed on the substrate S. The capacitive contact structure CC and the bit line BL can be regarded as being disposed in the isolation structure IS. In addition, the capacitive contact structure CC and the bit line BL are electrically connected to the active area AA in the substrate S, so that the capacitive contact structure CC and the bit line BL can be electrically connected to the field effects provided in the active area AA, respectively. The source and drain of the transistor T (not shown). As shown in FIG. 3A, the plurality of capacitive contact structures CC and the plurality of bit lines BL are alternately arranged along the column direction (that is, the direction D1), and the isolation wall IS2 is disposed on the adjacent capacitive contact structure CC and the bit cell. Between the lines BL. In one embodiment, the bit line contact structure BC is disposed and electrically connected between the active area AA and the bit line BL. The bit line BL and the bit line contact structure BC below it are located between adjacent isolation walls IS2. In one embodiment, the bit line BL and the bit line contact structure BC below it are located and physically contacted between the adjacent isolation walls IS2. In addition, the sidewall of the bit line BL may be substantially coplanar with the sidewall of the underlying bit line contact structure BC. In an embodiment, the plurality of bit line contact structures BC respectively include a conductive structure CS1 and a barrier layer BR1 covering the top surface of the conductive structure CS1. On the other hand, in one embodiment, the plurality of capacitive contact structures CC respectively include a conductive structure CS2 and a barrier layer BR2 covering the bottom and side surfaces of the conductive structure CS2. In addition, in one embodiment, a plurality of contact plugs CP are respectively disposed between a capacitive contact structure CC and the substrate. A plurality of contact plugs CP are respectively electrically connected between a capacitive contact structure CC and an active area AA in the substrate S. The capacitive contact structure CC and the contact plug CP below it are located between adjacent isolation walls IS2. In one embodiment, the capacitive contact structure CC and the contact plug CP below it physically contact between the adjacent partition walls IS2. In addition, the sidewall of the capacitive contact structure CC may be substantially coplanar with the sidewall of the contact plug CP below it. Furthermore, in an embodiment, a metal silicide layer MS may be provided between the contact plug CP and the capacitive contact structure CC. In an embodiment, the material of the bit line BL and the contact plug CP may include polysilicon. The material of the conductive structure CS1 and the conductive structure CS2 may include tungsten, and the material of the barrier layer BR1 and the barrier layer BR2 may include titanium nitride, tantalum nitride, titanium-tungsten alloy, the like or a combination thereof. In addition, the material of the metal silicide layer MS may include cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, the like or a combination thereof.

在一實施例中,位元線接觸結構BC的導電結構CS1縱向地延伸至基底S中的主動區域AA內。多個導電結構CS1的延伸部分分別位於相鄰的溝渠隔離結構TI之間。此外,在一實施例中,一些導電結構CS1的延伸部分相對於其他導電結構CS1的延伸部分而沿著行方向(亦即方向D2)而偏移。在此實施例中,如圖3A所示,一些導電結構CS1的延伸部分並未顯示於線X-X’的剖視示意圖(例如是中央的導電結構CS1)。另一方面,在一實施例中,接觸插塞CP亦延伸至基底S中的主動區域AA內。多個接觸插塞CP的延伸部分以及多個位元線接觸結構BC的導電結構CS1之延伸部分沿著列方向(亦即方向D1)交替地排列。在一實施例中,接觸插塞CP延伸至主動區域AA與溝渠隔離結構TI中。在此實施例中,接觸插塞CP交疊於溝渠隔離結構TI,而可縮短相鄰接觸插塞CP與導電結構CS1之間的間距。In one embodiment, the conductive structure CS1 of the bit line contact structure BC extends longitudinally into the active area AA in the substrate S. The extension portions of the plurality of conductive structures CS1 are respectively located between adjacent trench isolation structures TI. In addition, in an embodiment, the extension portions of some conductive structures CS1 are offset along the row direction (that is, the direction D2) relative to the extension portions of other conductive structures CS1. In this embodiment, as shown in FIG. 3A, some extensions of the conductive structures CS1 are not shown in the cross-sectional schematic diagram of the line X-X' (for example, the central conductive structure CS1). On the other hand, in one embodiment, the contact plug CP also extends into the active area AA in the substrate S. The extension portions of the plurality of contact plugs CP and the extension portions of the conductive structure CS1 of the plurality of bit line contact structures BC are alternately arranged along the column direction (that is, the direction D1). In an embodiment, the contact plug CP extends into the active area AA and the trench isolation structure TI. In this embodiment, the contact plug CP overlaps the trench isolation structure TI, so that the distance between the adjacent contact plug CP and the conductive structure CS1 can be shortened.

在一實施例中,於基底S中形成多個隔離壁IS3,且此些隔離壁IS3分別設置於接觸插塞CP與相鄰導電結構CS1的延伸部分之間。在一實施例中,多個隔離壁IS3分別實體接觸於接觸插塞CP的延伸部分及導電結構CS1的延伸部分在基底S上的隔離壁IS2之一部分以及設置於基底S中的隔離壁IS3均位於相鄰的接觸插塞CP與位元線接觸結構BC之間,且隔離壁IS3交疊於隔離壁IS2。在一實施例中,隔離壁IS3可設置於溝渠隔離結構TI中,且橫向延伸至相鄰的主動區域AA中。此外,在一實施例中,隔離壁IS3的底面低於接觸插塞CP與導電結構CS1的底面。隔離壁IS3的材料可包括氮化矽、氧化矽、氮氧化矽、低介電常數(介電常數低於4)介電材料或其組合。在特定實施例中,隔離壁IS3可為多層結構,例如是ONO多層結構。在其他實施例中,隔離壁IS3中具有空氣間隙。In one embodiment, a plurality of isolation walls IS3 are formed in the substrate S, and these isolation walls IS3 are respectively disposed between the contact plug CP and the extension portion of the adjacent conductive structure CS1. In one embodiment, the plurality of isolation walls IS3 are in physical contact with the extended portion of the contact plug CP and the extended portion of the conductive structure CS1. A portion of the isolation wall IS2 on the substrate S and a portion of the isolation wall IS3 disposed in the substrate S are both physically contacted. It is located between the adjacent contact plug CP and the bit line contact structure BC, and the isolation wall IS3 overlaps the isolation wall IS2. In an embodiment, the isolation wall IS3 may be disposed in the trench isolation structure TI and extend laterally into the adjacent active area AA. In addition, in an embodiment, the bottom surface of the isolation wall IS3 is lower than the bottom surface of the contact plug CP and the conductive structure CS1. The material of the isolation wall IS3 may include silicon nitride, silicon oxide, silicon oxynitride, low-k (dielectric constant less than 4) dielectric material, or a combination thereof. In a specific embodiment, the partition wall IS3 may have a multilayer structure, such as an ONO multilayer structure. In other embodiments, there is an air gap in the partition wall IS3.

在一實施例中,襯墊層PL設置於隔離結構IS與基底S之間。在此實施例中,接觸插塞CP與位元線接觸結構BC的導電結構CS1可視為穿過襯墊層PL而延伸至基底S中。襯墊層PL的材料可包括氧化矽、氮化矽、其類似者或其組合。再者,在一實施例中,位元線BL的頂面低於電容接觸結構CC的頂面,且第一介電結構DS1和第二介電結構DS2分別位於由相鄰隔離壁IS2的側壁與位元線BL的頂面所定義出的凹槽中。第二介電結構DS2堆疊在第一介電結構DS1之上。如圖2A和圖3A所示,第一介電結構DS1和第二介電結構DS2也可視為具有其中設置有電容接觸結構CC與隔離結構IS的多個溝渠。如圖3A所示,第二介電結構DS2、隔離壁IS2以及電容接觸結構CC的頂面實質上共面。在一實施例中,第二介電結構DS2相對於第一介電結構DS1具有足夠的蝕刻選擇比。舉例而言,第二介電結構DS2的材料可包括氮化矽,而第一介電結構DS1的材料可包括氧化矽。In an embodiment, the liner layer PL is disposed between the isolation structure IS and the substrate S. In this embodiment, the conductive structure CS1 of the contact plug CP and the bit line contact structure BC can be regarded as extending into the substrate S through the liner layer PL. The material of the liner layer PL may include silicon oxide, silicon nitride, the like, or a combination thereof. Furthermore, in an embodiment, the top surface of the bit line BL is lower than the top surface of the capacitive contact structure CC, and the first dielectric structure DS1 and the second dielectric structure DS2 are respectively located on the sidewalls of the adjacent isolation wall IS2 And in the groove defined by the top surface of the bit line BL. The second dielectric structure DS2 is stacked on the first dielectric structure DS1. As shown in FIGS. 2A and 3A, the first dielectric structure DS1 and the second dielectric structure DS2 can also be regarded as having a plurality of trenches in which the capacitive contact structure CC and the isolation structure IS are arranged. As shown in FIG. 3A, the top surfaces of the second dielectric structure DS2, the isolation wall IS2, and the capacitive contact structure CC are substantially coplanar. In an embodiment, the second dielectric structure DS2 has a sufficient etching selection ratio to the first dielectric structure DS1. For example, the material of the second dielectric structure DS2 may include silicon nitride, and the material of the first dielectric structure DS1 may include silicon oxide.

請參照圖1、圖2B及圖3B,進行步驟S102,以移除第二第二介電結構DS2與隔離結構IS的高於第一介電結構DS1的部分。如此一來,電容接觸結構CC此時凸出於隔離結構IS(包含接觸結構間隔離結構IS1與隔離壁IS2)的頂面以及第一介電結構DS1的頂面。在一實施例中,可藉由蝕刻製程移除第二介電結構DS2與隔離結構IS的高於第一介電結構DS1的部分。舉例而言,蝕刻製程為等向性蝕刻製程或非等向性蝕刻製程。在此蝕刻製程期間,電容接觸結構CC可作為蝕刻遮罩。此外,在第二介電結構DS2相對於第一介電結構DS1具有足夠的蝕刻選擇比之實施例中,第一介電結構DS1可在蝕刻製程期間作為蝕刻停止層。1, 2B, and 3B, step S102 is performed to remove parts of the second second dielectric structure DS2 and the isolation structure IS that are higher than the first dielectric structure DS1. As a result, the capacitive contact structure CC protrudes from the top surface of the isolation structure IS (including the isolation structure IS1 between the contact structures and the isolation wall IS2) and the top surface of the first dielectric structure DS1 at this time. In one embodiment, the second dielectric structure DS2 and the part of the isolation structure IS higher than the first dielectric structure DS1 can be removed by an etching process. For example, the etching process is an isotropic etching process or an anisotropic etching process. During this etching process, the capacitive contact structure CC can be used as an etching mask. In addition, in an embodiment where the second dielectric structure DS2 has a sufficient etching selection ratio with respect to the first dielectric structure DS1, the first dielectric structure DS1 may serve as an etch stop layer during the etching process.

請參照圖1、圖2C及圖3C,進行步驟S104,以形成導電材料層CM。在一實施例中,導電材料層CM共形地且全面地形成於圖2B及圖3B所示的結構上。如此一來,導電材料層CM覆蓋電容接觸結構CC的頂面與側壁、隔離結構IS的頂面以及第一介電結構DS1的頂面。導電材料層CM的水平部分CM1覆蓋電容接觸結構CC的頂面、隔離結構IS的頂面以及第一介電結構DS1的頂面,而導電材料層CM的垂直部分CM2覆蓋電容接觸結構CC的側壁。在一實施例中,導電材料層CM並未完全地填滿位於多個凸出的電容接觸結構CC之間的凹陷,且導電材料層CM對應於下方結構的表面形貌而亦具有凹陷。在一實施例中,導電材料層CM的材料包括鈦鎢、鎢、氮化鎢、其類似者或其組合。此外,導電材料層CM的形成方法包括沉積製程(例如物理氣相沉積製程)、鍍覆製程、其類似者或其組合。Please refer to FIG. 1, FIG. 2C and FIG. 3C to perform step S104 to form a conductive material layer CM. In one embodiment, the conductive material layer CM is conformally and fully formed on the structure shown in FIGS. 2B and 3B. In this way, the conductive material layer CM covers the top surface and sidewalls of the capacitive contact structure CC, the top surface of the isolation structure IS, and the top surface of the first dielectric structure DS1. The horizontal portion CM1 of the conductive material layer CM covers the top surface of the capacitive contact structure CC, the top surface of the isolation structure IS, and the top surface of the first dielectric structure DS1, while the vertical portion CM2 of the conductive material layer CM covers the sidewalls of the capacitive contact structure CC . In one embodiment, the conductive material layer CM does not completely fill the recesses between the plurality of protruding capacitive contact structures CC, and the conductive material layer CM also has recesses corresponding to the surface topography of the underlying structure. In an embodiment, the material of the conductive material layer CM includes titanium tungsten, tungsten, tungsten nitride, the like or a combination thereof. In addition, the method for forming the conductive material layer CM includes a deposition process (for example, a physical vapor deposition process), a plating process, the like, or a combination thereof.

請參照圖1、圖2D及圖3D,進行步驟S106,以移除導電材料層CM的水平部分CM1而保留導電材料層CM的垂直部分CM2。如圖3D所示,導電材料層CM的殘留部分(即垂直部分CM2)分別圍繞電容接觸結構CC的凸出部分,且亦稱為導電環CR。在一實施例中,以非等向性蝕刻製程移除導電材料層CM的水平部分CM1。在此實施例中,藉由自對準圖案化製程來圖案化導電材料層CM以形成導電環CR,而不需要進行微影製程。此外,在非等向性蝕刻製程期間,第一介電結構DS1的頂部可能隨著導電材料層CM的水平部分CM1一起被移除。因此,第一介電結構DS1的頂面相較於隔離結構IS的頂面而下凹。1, 2D, and 3D, step S106 is performed to remove the horizontal portion CM1 of the conductive material layer CM while leaving the vertical portion CM2 of the conductive material layer CM. As shown in FIG. 3D, the remaining part of the conductive material layer CM (ie, the vertical part CM2) respectively surrounds the protruding part of the capacitive contact structure CC, and is also referred to as a conductive ring CR. In one embodiment, the horizontal portion CM1 of the conductive material layer CM is removed by an anisotropic etching process. In this embodiment, the conductive material layer CM is patterned by a self-aligned patterning process to form the conductive ring CR, without the need for a lithography process. In addition, during the anisotropic etching process, the top of the first dielectric structure DS1 may be removed along with the horizontal portion CM1 of the conductive material layer CM. Therefore, the top surface of the first dielectric structure DS1 is concave compared to the top surface of the isolation structure IS.

請參照圖1、圖2E及圖3E,進行步驟S108,以在圖2D及圖3D所示的結構上形成覆蓋層CL。在一實施例中,覆蓋層CL是全面地形成於圖2D及圖3D所示的結構上。此外,覆蓋層CL更可填入相鄰導電環CR之間的凹陷中。如此一來,覆蓋層CL覆蓋電容接觸結構CC、導電環CR、隔離結構IS以及第一介電結構DS1的暴露出來的表面。在一實施例中,覆蓋層CL填滿此些凹陷。覆蓋層CL的材料可包括氧化矽、氮化矽、其類似者或其組合。此外,覆蓋層CL的形成方法可包括沉積製程(例如化學氣相象沉積製程)或溶液製程(例如旋轉塗佈製程)。Please refer to FIG. 1, FIG. 2E, and FIG. 3E to perform step S108 to form a cover layer CL on the structure shown in FIG. 2D and FIG. 3D. In one embodiment, the cover layer CL is formed entirely on the structure shown in FIG. 2D and FIG. 3D. In addition, the cover layer CL can further fill the recesses between adjacent conductive rings CR. In this way, the cover layer CL covers the exposed surfaces of the capacitive contact structure CC, the conductive ring CR, the isolation structure IS, and the first dielectric structure DS1. In one embodiment, the cover layer CL fills these recesses. The material of the capping layer CL may include silicon oxide, silicon nitride, the like, or a combination thereof. In addition, the method for forming the cover layer CL may include a deposition process (for example, a chemical vapor image deposition process) or a solution process (for example, a spin coating process).

請參照圖1、圖2F及圖3F,進行步驟S110,以移除覆蓋層CL的高於電容接觸結構CC的部分。如此一來,暴露出電容接觸結構CC與導電環CR的頂面。在一實施例中,電容接觸結構CC、導電環CR以及覆蓋層CL的殘留部分的等面彼此實質上共面。移除覆蓋層CL的高於電容接觸結構CC之部分的方法可包括平坦化製程(例如化學機械拋光製程)、蝕刻製程或其組合。Please refer to FIG. 1, FIG. 2F and FIG. 3F to perform step S110 to remove the part of the cover layer CL higher than the capacitor contact structure CC. In this way, the top surfaces of the capacitive contact structure CC and the conductive ring CR are exposed. In an embodiment, the iso-planes of the capacitive contact structure CC, the conductive ring CR, and the remaining part of the cover layer CL are substantially coplanar with each other. The method for removing the part of the capping layer CL higher than the capacitive contact structure CC may include a planarization process (for example, a chemical mechanical polishing process), an etching process, or a combination thereof.

請參照圖1、圖2G及圖3G,進行步驟S112,以在圖2F及圖3F所示的結構上形成支撐層SL。在一實施例中,支撐層SL全面地覆蓋於圖2F及圖3F所示的結構上。如此一來,支撐層SL覆蓋導電環CR、電容接觸結構CC以及覆蓋層CL之殘留部分的頂面。在一實施例中,在形成支撐層SL之前,先在圖2F及圖3F所示的結構上形成全面披覆的鈍化層PV。在一實施例中,支撐層SL的材料可包括氧化矽,而鈍化層PV的材料可包括氮化矽。形成支撐層SL及鈍化層PV的方法可分別包括沉積製程(例如化學氣相沉積製程)或是溶液製程(例如旋轉塗佈製程)。Please refer to FIG. 1, FIG. 2G and FIG. 3G to perform step S112 to form a support layer SL on the structure shown in FIG. 2F and FIG. 3F. In one embodiment, the supporting layer SL completely covers the structure shown in FIG. 2F and FIG. 3F. In this way, the support layer SL covers the top surface of the conductive ring CR, the capacitive contact structure CC, and the remaining part of the cover layer CL. In one embodiment, before forming the support layer SL, a passivation layer PV covering the entire surface is first formed on the structure shown in FIG. 2F and FIG. 3F. In an embodiment, the material of the support layer SL may include silicon oxide, and the material of the passivation layer PV may include silicon nitride. The method of forming the support layer SL and the passivation layer PV may respectively include a deposition process (for example, a chemical vapor deposition process) or a solution process (for example, a spin coating process).

請參照圖1、圖2H及圖3H,進行步驟S114,以移除支撐層SL及鈍化層PV的一些部分而形成多個開口W。多個開口W分別暴露出一部分的電容接觸結構CC以及一部分的導電環CR。此外,在一實施例中,每個開口W更暴露出相鄰的覆蓋層CL之一部分。在一實施例中,開口W的中心軸A1相對於下方的電容接觸結構CC之中心軸A2而沿特定方向(例如方向D1)偏離。在此實施例中,開口W可能不會完整地暴露出電容接觸結構CC的頂面及其周圍的導電環CR的頂面。換言之,電容接觸結構CC的頂面及其周圍的導電環CR的頂面仍部分地被支撐層SL及鈍化層PV所覆蓋。如圖2H所示,在一實施例中,多個開口W分別交疊於下方的主動區域。再者,在一實施例中,開口W的上視圖形為圓形。然而,所屬技術領域中具有通常知識者當可變更開口W的上視圖形,本發明實施例並不以此為限。Please refer to FIG. 1, FIG. 2H and FIG. 3H to perform step S114 to remove some parts of the support layer SL and the passivation layer PV to form a plurality of openings W. The plurality of openings W respectively expose a part of the capacitive contact structure CC and a part of the conductive ring CR. In addition, in an embodiment, each opening W further exposes a portion of the adjacent cover layer CL. In one embodiment, the central axis A1 of the opening W is offset from the central axis A2 of the lower capacitive contact structure CC along a specific direction (for example, the direction D1). In this embodiment, the opening W may not completely expose the top surface of the capacitive contact structure CC and the top surface of the conductive ring CR around it. In other words, the top surface of the capacitive contact structure CC and the top surface of the surrounding conductive ring CR are still partially covered by the support layer SL and the passivation layer PV. As shown in FIG. 2H, in one embodiment, a plurality of openings W respectively overlap the active area below. Furthermore, in one embodiment, the top view of the opening W is circular. However, those skilled in the art can change the top view shape of the opening W, and the embodiment of the present invention is not limited to this.

請參照圖1、圖2I及圖3I,進行步驟S116,以在圖3H所示的結構上共形地形成底電極層BE。如此一來,底電極層BE覆蓋電容接觸結構CC、導電環CR、覆蓋層CL的暴露出來的表面,且覆蓋支撐層SL與鈍化層PV的暴露出來的表面。在一實施例中,底電極層BE的材料可包括鈦、氮化鈦、鉭、氮化鉭、釕、其類似者或其組合。底電極層BE的形成方法包括沉積製程(例如物理氣相沉積製程)、鍍覆製程或其組合。Please refer to FIG. 1, FIG. 2I, and FIG. 3I to perform step S116 to conformally form the bottom electrode layer BE on the structure shown in FIG. 3H. In this way, the bottom electrode layer BE covers the exposed surfaces of the capacitive contact structure CC, the conductive ring CR, and the cover layer CL, and covers the exposed surfaces of the support layer SL and the passivation layer PV. In an embodiment, the material of the bottom electrode layer BE may include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, the like or a combination thereof. The formation method of the bottom electrode layer BE includes a deposition process (for example, a physical vapor deposition process), a plating process, or a combination thereof.

請參照圖1、圖2J及圖3J,進行步驟S118,以移除底電極層BE的高於支撐層SL的部分。另一方面,底電極層BE的位於開口W中的部分仍保留下來,且稱為多個底電極BE1。多個底電極BE1分別位於一開口W的範圍內。每一底電極BE1覆蓋一開口W的底面與側壁,且電性連接到部分地交疊於開口W的電容接觸結構CC及其周圍的導電環CR。在開口W暴露出覆蓋層CL的一些部分之實施例中,覆蓋層CL的此些部分此時被多個底電極BE1所覆蓋。在一實施例中,例如是先形成藉由平坦化製程移除底電極層BE的高於支撐層SL的部分。舉例而言,平坦化製程可以包括化學機械拋光製程、蝕刻製程或研磨製程。在移除底電極層BE的高於支撐層SL的部分後,暴露出支撐層SL的頂面。Please refer to FIG. 1, FIG. 2J and FIG. 3J to perform step S118 to remove the portion of the bottom electrode layer BE that is higher than the support layer SL. On the other hand, the part of the bottom electrode layer BE located in the opening W still remains, and is called a plurality of bottom electrodes BE1. A plurality of bottom electrodes BE1 are respectively located in the range of an opening W. Each bottom electrode BE1 covers the bottom surface and sidewalls of an opening W, and is electrically connected to the capacitive contact structure CC partially overlapping the opening W and the conductive ring CR around it. In the embodiment where the opening W exposes some parts of the cover layer CL, these parts of the cover layer CL are now covered by a plurality of bottom electrodes BE1. In one embodiment, for example, the portion of the bottom electrode layer BE higher than the support layer SL is first formed by a planarization process. For example, the planarization process may include a chemical mechanical polishing process, an etching process, or a grinding process. After removing the portion of the bottom electrode layer BE higher than the support layer SL, the top surface of the support layer SL is exposed.

請參照圖1、圖2K及圖3K,進行步驟S120,以移除支撐層SL,且接著形成介電層DL及於介電層DL上共形地形成頂電極層TE。在一實施例中,移除支撐層SL的方法包括蝕刻製程。在移除支撐層SL之後,底電極BE1的一些部分可視為豎立於下方的結構上且凸出於鈍化層PV。介電層DL共形地形成於底電極BE1與鈍化層PV上。隨後,在介電層DL上共形地形成頂電極層TE。在一實施例中,頂電極層TE填入於開口W以及支撐層SL先前所佔據的空間,且頂電極層TE的高度大於底電極BE1的豎立部分的高度,而可覆蓋介電層DL的最頂面。多個底電極BE1、介電層DL及頂電極層TE構成多個儲存電容SC。每一儲存電容SC電性連接到一電容接觸結構CC及其周圍的導電環CR,且每一儲存電容SC包括一個底電極BE1、頂電極層TE的一部分以及介電層DL的位於上述兩者之間的一部分。多個儲存電容SC的多個底電極BE1彼此側向分離且分別電性連接到一電容接觸結構CC及其周圍的導電環CR,而介電層DL及頂電極層TE則可視為被多個儲存電容SC共用。值得注意的是,以簡潔起見,圖2K僅繪示出多個儲存電容SC的位於多個開口W中的部分,而省略繪示多個儲存電容SC的其他部分。在一實施例中,介電層DL的材料可包括氧化矽、氮化矽、氧化鉭、氧化鈦、氧化鋯、氧化鋁或是其它高介電常數(介電常數高於4)的介電材料、其類似者或其組合。此外,頂電極層TE的材料可包括氮化鈦、矽鍺、鎢、其類似者或其組合。在一實施例中,介電層DL的形成方法包括沉積製程(例如化學氣相沉積製程),而頂電極層TE的形成方法包括沉積製程(例如物理氣相沉積製程)、鍍覆製程或其組合。1, 2K and 3K, step S120 is performed to remove the support layer SL, and then the dielectric layer DL is formed and the top electrode layer TE is conformally formed on the dielectric layer DL. In one embodiment, the method of removing the support layer SL includes an etching process. After the support layer SL is removed, some parts of the bottom electrode BE1 can be regarded as standing on the underlying structure and protruding from the passivation layer PV. The dielectric layer DL is conformally formed on the bottom electrode BE1 and the passivation layer PV. Subsequently, a top electrode layer TE is conformally formed on the dielectric layer DL. In one embodiment, the top electrode layer TE is filled in the space previously occupied by the opening W and the support layer SL, and the height of the top electrode layer TE is greater than the height of the vertical portion of the bottom electrode BE1, and can cover the dielectric layer DL The top surface. The plurality of bottom electrodes BE1, the dielectric layer DL, and the top electrode layer TE constitute a plurality of storage capacitors SC. Each storage capacitor SC is electrically connected to a capacitor contact structure CC and the surrounding conductive ring CR, and each storage capacitor SC includes a bottom electrode BE1, a part of the top electrode layer TE, and a dielectric layer DL located on the two Part in between. The bottom electrodes BE1 of the storage capacitors SC are laterally separated from each other and are electrically connected to a capacitor contact structure CC and the surrounding conductive ring CR. The dielectric layer DL and the top electrode layer TE can be regarded as being multiple The storage capacitor SC is shared. It is worth noting that, for the sake of brevity, FIG. 2K only shows the parts of the storage capacitors SC located in the openings W, while omitting other parts of the storage capacitors SC. In one embodiment, the material of the dielectric layer DL may include silicon oxide, silicon nitride, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, or other high-permittivity (permittivity higher than 4) dielectric Materials, their analogs, or combinations thereof. In addition, the material of the top electrode layer TE may include titanium nitride, silicon germanium, tungsten, the like or a combination thereof. In one embodiment, the method for forming the dielectric layer DL includes a deposition process (for example, a chemical vapor deposition process), and the method for forming the top electrode layer TE includes a deposition process (for example, a physical vapor deposition process), a plating process or the like combination.

在替代實施例中,頂電極層TE亦可填滿於圖2J所示的開口W以及支撐層SL先前所佔據的空間。換言之,頂電極層TE可為非共形地形成於介電層DL上。在此些實施例中,可對頂電極層TE進行平坦化製程(例如化學機械拋光製程、蝕刻製程或研磨製程),而使頂電極層TE具有實質上平坦的頂表面(未繪示)。In an alternative embodiment, the top electrode layer TE can also fill up the space previously occupied by the opening W shown in FIG. 2J and the support layer SL. In other words, the top electrode layer TE may be non-conformally formed on the dielectric layer DL. In these embodiments, the top electrode layer TE may be subjected to a planarization process (for example, a chemical mechanical polishing process, an etching process, or a grinding process), so that the top electrode layer TE has a substantially flat top surface (not shown).

至此,已完成半導體元件10的製造。半導體元件10可為DRAM元件。半導體元件10包括了設置於基底S中的主動區域AA內的場效電晶體T(如圖2A所示),且包括設置於基底S上的儲存電容SC。電容接觸結構CC設置於且電性連接於主動區域AA及儲存電容SC之間,且導電環CR圍繞電容接觸結構CC的頂部。在形成儲存電容SC的過程中,導電環CR可保護位於其下方的絕緣構件(例如是隔離壁IS2及第一介電結構DS1),以使其免於在可能使用的蝕刻製程期間受到損害。因此,可避免電荷經由導電環CR下方的絕緣結構擊穿至下方的位元線BL,而可提高半導體元件10的可靠度。再者,藉由在電容接觸結構CC的頂部周圍設置導電環CR,可擴大儲存電容SC能著陸(land over)的導電區域。據此,增加儲存電容SC與電容接觸結構CC之間的接觸裕度(contact margin)。此外,由於可藉由自對準圖案化製程來形成導電環CR,因此不需要進行額外的微影製程。So far, the manufacture of the semiconductor element 10 has been completed. The semiconductor element 10 may be a DRAM element. The semiconductor device 10 includes a field effect transistor T (as shown in FIG. 2A) disposed in the active area AA in the substrate S, and includes a storage capacitor SC disposed on the substrate S. The capacitive contact structure CC is disposed and electrically connected between the active area AA and the storage capacitor SC, and the conductive ring CR surrounds the top of the capacitive contact structure CC. In the process of forming the storage capacitor SC, the conductive ring CR can protect the insulating members (for example, the isolation wall IS2 and the first dielectric structure DS1) underneath it from damage during the etching process that may be used. Therefore, it is possible to prevent the charge from breaking down to the bit line BL underneath the insulating structure under the conductive ring CR, and the reliability of the semiconductor device 10 can be improved. Furthermore, by arranging a conductive ring CR around the top of the capacitor contact structure CC, the conductive area where the storage capacitor SC can land over can be enlarged. Accordingly, the contact margin between the storage capacitor SC and the capacitor contact structure CC is increased. In addition, since the conductive ring CR can be formed by a self-aligned patterning process, no additional lithography process is required.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10:半導體元件 A1、A2:中心軸 AA:主動區域 BC:位元線接觸結構 BE:底電極層 BE1:底電極 BL:位元線 BR1、BR2:阻障層 CC:電容接觸結構 CM:導電材料層 CM1:水平部分 CM2:垂直部分 CL:覆蓋層 CP:接觸插塞 CR:導電環 CS1、CS2:導電結構 D1~D3:方向 DL:介電層 DS1:第一介電結構 DS2:第二介電結構 IS:隔離結構 IS1:接觸結構間隔離結構 IS2、IS3:隔離壁 MS:金屬矽化物層 PL:襯墊層 PV:鈍化層 S:基底 S102、S104、S106、S108、S110、S112、S114、S116、S118、S120:步驟 SC:儲存電容 SL:支撐層 T:場效電晶體 TE:頂電極層 TI:溝渠隔離結構 W:開口 WL:字元線10: Semiconductor components A1, A2: central axis AA: active area BC: bit line contact structure BE: bottom electrode layer BE1: bottom electrode BL: bit line BR1, BR2: barrier layer CC: Capacitive contact structure CM: Conductive material layer CM1: Horizontal part CM2: vertical part CL: cover layer CP: contact plug CR: Conductive ring CS1, CS2: conductive structure D1~D3: Direction DL: Dielectric layer DS1: The first dielectric structure DS2: second dielectric structure IS: Isolation structure IS1: Isolation structure between contact structures IS2, IS3: separation wall MS: metal silicide layer PL: Lining layer PV: Passivation layer S: base S102, S104, S106, S108, S110, S112, S114, S116, S118, S120: steps SC: storage capacitor SL: Support layer T: field effect transistor TE: top electrode layer TI: trench isolation structure W: opening WL: Character line

圖1是依照本發明一實施例的半導體元件的製造方法的流程圖。 圖2A至圖2K是圖1所示的半導體元件的製造方法中各階段的結構的上視示意圖。 圖3A至圖3K分別為圖2A至圖2K的線X-X’的剖視示意圖。FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2A to 2K are schematic top views of the structure at each stage in the method of manufacturing the semiconductor device shown in FIG. 1. 3A to 3K are schematic cross-sectional views taken along the line X-X' of FIGS. 2A to 2K, respectively.

10:半導體元件10: Semiconductor components

D1:方向D1: direction

AA:主動區域AA: active area

DL:介電層DL: Dielectric layer

BC:位元線接觸結構BC: bit line contact structure

DS1:第一介電結構DS1: The first dielectric structure

BE1:底電極BE1: bottom electrode

IS2、IS3:隔離壁IS2, IS3: separation wall

BL:位元線BL: bit line

MS:金屬矽化物層MS: metal silicide layer

BR1、BR2:阻障層BR1, BR2: barrier layer

PL:襯墊層PL: Lining layer

CC:電容接觸結構CC: Capacitive contact structure

PV:鈍化層PV: Passivation layer

CL:覆蓋層CL: cover layer

S:基底S: base

CP:接觸插塞CP: contact plug

SC:儲存電容SC: storage capacitor

CR:導電環CR: Conductive ring

TE:頂電極層TE: top electrode layer

CS1、CS2:導電結構CS1, CS2: conductive structure

TI:溝渠隔離結構TI: trench isolation structure

Claims (20)

一種半導體元件,包括: 主動區域,形成於基底中; 位元線及電容接觸結構,設置於所述基底上且電性連接於所述主動區域,其中所述位元線與所述電容接觸結構彼此側向分離,且所述位元線的頂面低於所述電容接觸結構的頂面; 導電環,圍繞所述電容接觸結構的頂部;以及 儲存電容,設置於所述電容接觸結構與所述導電環上,且電性連接於所述電容接觸結構及所述導電環。A semiconductor component, including: Active area, formed in the substrate; The bit line and the capacitive contact structure are disposed on the substrate and electrically connected to the active area, wherein the bit line and the capacitive contact structure are laterally separated from each other, and the top surface of the bit line Lower than the top surface of the capacitive contact structure; A conductive ring surrounding the top of the capacitive contact structure; and A storage capacitor is arranged on the capacitive contact structure and the conductive ring, and is electrically connected to the capacitive contact structure and the conductive ring. 如請求項1所述的半導體元件,其中所述儲存電容包括底電極、頂電極層及位於所述底電極與所述頂電極層之間的介電層,且所述底電極部分地交疊於所述電容接觸結構及所述導電環。The semiconductor device according to claim 1, wherein the storage capacitor includes a bottom electrode, a top electrode layer, and a dielectric layer between the bottom electrode and the top electrode layer, and the bottom electrode partially overlaps On the capacitive contact structure and the conductive ring. 如請求項2所述的半導體元件,其中所述介電層與所述頂電極層實質上完整地交疊於所述電容接觸結構及所述導電環。The semiconductor device according to claim 2, wherein the dielectric layer and the top electrode layer substantially completely overlap the capacitive contact structure and the conductive ring. 如請求項2所述的半導體元件,其中所述底電極交疊於所述位元線。The semiconductor device according to claim 2, wherein the bottom electrode overlaps the bit line. 如請求項2所述的半導體元件,更包括鈍化層,其中所述鈍化層設置於所述儲存電容的所述底電極一側,且其中所述鈍化層與所述底電極覆蓋所述電容接觸結構與所述導電環。The semiconductor device according to claim 2, further comprising a passivation layer, wherein the passivation layer is disposed on the side of the bottom electrode of the storage capacitor, and wherein the passivation layer and the bottom electrode cover the capacitor contact Structure and the conductive ring. 如請求項1所述的半導體元件,其中所述位元線的頂面低於所述導電環的底面。The semiconductor device according to claim 1, wherein the top surface of the bit line is lower than the bottom surface of the conductive ring. 如請求項1所述的半導體元件,其中所述儲存電容實體接觸於所述電容接觸結構及所述導電環。The semiconductor device according to claim 1, wherein the storage capacitor is physically in contact with the capacitor contact structure and the conductive ring. 如請求項1所述的半導體元件,更包括: 隔離結構,設置於所述基底上,且圍繞所述電容接觸結構的下部,其中所述隔離結構的一部分位於所述電容接觸結構與所述位元線之間。The semiconductor component as described in claim 1, further including: The isolation structure is disposed on the substrate and surrounds the lower part of the capacitive contact structure, wherein a part of the isolation structure is located between the capacitive contact structure and the bit line. 如請求項8所述的半導體元件,其中所述導電環及所述隔離結構圍繞所述電容接觸結構。The semiconductor element according to claim 8, wherein the conductive ring and the isolation structure surround the capacitive contact structure. 如請求項1所述的半導體元件,更包括: 接觸插塞,延伸於所述電容接觸結構與所述主動區域之間。The semiconductor component as described in claim 1, further including: The contact plug extends between the capacitive contact structure and the active area. 如請求項10所述的半導體元件,所述接觸插塞延伸至所述主動區域中。In the semiconductor device according to claim 10, the contact plug extends into the active area. 如請求項1所述的半導體元件,更包括: 位元線接觸結構,延伸於所述位元線與所述主動區域之間。The semiconductor component as described in claim 1, further including: The bit line contact structure extends between the bit line and the active area. 一種半導體元件的製造方法,包括: 在基底中形成主動區域; 在所述基底上形成位元線與電容接觸結構,其中所述位元線與所述電容接觸結構彼此側向分離,所述位元線與所述電容接觸結構電性連接於所述主動區域,且所述位元線的頂面低於所述電容接觸結構的頂面; 形成圍繞所述電容接觸結構的頂部的導電環;以及 在所述電容接觸結構與所述導電環上形成儲存電容。A method for manufacturing a semiconductor element includes: An active area is formed in the substrate; A bit line and a capacitive contact structure are formed on the substrate, wherein the bit line and the capacitive contact structure are laterally separated from each other, and the bit line and the capacitive contact structure are electrically connected to the active area , And the top surface of the bit line is lower than the top surface of the capacitive contact structure; Forming a conductive ring surrounding the top of the capacitive contact structure; and A storage capacitor is formed on the capacitor contact structure and the conductive ring. 如請求項13所述的半導體元件的製造方法,其中形成所述導電環的方法包括自對準圖案化製程。The method of manufacturing a semiconductor device according to claim 13, wherein the method of forming the conductive ring includes a self-aligned patterning process. 如請求項13所述的半導體元件的製造方法,其中形成所述導電環的方法包括: 在所述基底上形成絕緣材料,其中所述位元線與所述電容接觸結構位於所述絕緣材料中; 移除所述絕緣材料的頂部以暴露出所述電容接觸結構的上部,其中所述位元線仍埋於所述絕緣材料中; 在所述絕緣材料以及所述電容接觸結構的暴露部分上共形地形成導電材料層;以及 移除所述導電材料層的水平部分,其中所述導電材料層的殘留部分形成所述導電環。The method of manufacturing a semiconductor element according to claim 13, wherein the method of forming the conductive ring includes: Forming an insulating material on the substrate, wherein the bit line and the capacitive contact structure are located in the insulating material; Removing the top of the insulating material to expose the upper part of the capacitive contact structure, wherein the bit line is still buried in the insulating material; Forming a conductive material layer conformally on the insulating material and the exposed portion of the capacitive contact structure; and The horizontal part of the conductive material layer is removed, wherein the remaining part of the conductive material layer forms the conductive ring. 如請求項15所述的半導體元件的製造方法,其中移除所述導電材料層的所述水平部分的方法包括非等向性蝕刻製程。The method for manufacturing a semiconductor device according to claim 15, wherein the method of removing the horizontal portion of the conductive material layer includes an anisotropic etching process. 如請求項15所述的半導體元件的製造方法,更包括: 在所述絕緣材料、所述導電環及所述電容接觸結構上形成覆蓋層;以及 移除所述覆蓋層的高於所述電容接觸結構及所述導電環的部分。The method of manufacturing a semiconductor element according to claim 15, further including: Forming a cover layer on the insulating material, the conductive ring, and the capacitive contact structure; and Remove the part of the cover layer that is higher than the capacitive contact structure and the conductive ring. 如請求項13所述的半導體元件的製造方法,其中形成所述儲存電容的方法包括: 在所述電容接觸結構及所述導電環上依序形成鈍化層及支撐層; 移除所述支撐層的一部分及所述鈍化層的一部分,以形成部分地暴露出所述電容接觸結構及所述導電環的開口; 於所述支撐層以及所述電容接觸結構與所述導電環的暴露部分上共形地形成底電極層; 移除所述底電極層的高於所述支撐層的部分,其中所述底電極層的殘留部分形成底電極; 移除所述支撐層;以及 形成覆蓋所述底電極層及所述鈍化層的介電層; 於所述介電層上共形地形成頂電極層,其中所述底電極、所述介電層及所述頂電極層構成所述儲存電容。The method of manufacturing a semiconductor element according to claim 13, wherein the method of forming the storage capacitor includes: Sequentially forming a passivation layer and a support layer on the capacitive contact structure and the conductive ring; Removing a part of the support layer and a part of the passivation layer to form an opening partially exposing the capacitive contact structure and the conductive ring; Forming a bottom electrode layer conformally on the supporting layer and the exposed portions of the capacitive contact structure and the conductive ring; Removing a part of the bottom electrode layer higher than the support layer, wherein the remaining part of the bottom electrode layer forms a bottom electrode; Removing the support layer; and Forming a dielectric layer covering the bottom electrode layer and the passivation layer; A top electrode layer is conformally formed on the dielectric layer, wherein the bottom electrode, the dielectric layer, and the top electrode layer constitute the storage capacitor. 如請求項18所述的半導體元件的製造方法,其中所述開口的中心軸偏離所述電容接觸結構的中心軸。The method of manufacturing a semiconductor element according to claim 18, wherein the central axis of the opening is deviated from the central axis of the capacitive contact structure. 如請求項17所述的半導體元件的製造方法,其中所述開口交疊於所述位元線。The method of manufacturing a semiconductor device according to claim 17, wherein the opening overlaps the bit line.
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