TW202118046A - 納米片電晶體堆疊 - Google Patents

納米片電晶體堆疊 Download PDF

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TW202118046A
TW202118046A TW109122683A TW109122683A TW202118046A TW 202118046 A TW202118046 A TW 202118046A TW 109122683 A TW109122683 A TW 109122683A TW 109122683 A TW109122683 A TW 109122683A TW 202118046 A TW202118046 A TW 202118046A
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里辛 傑
曄 呂
約翰 建宏 朱
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美商高通公司
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Abstract

本發明呈現用於一堆疊內之不同類型之非平面電晶體的方法及設備。該設備包括以一堆疊豎直地配置於一基板上方之一p型電晶體及一n型電晶體，該p型電晶體及該n型電晶體為非平面電晶體。該p型電晶體包括一p型通道及第一組功函數層。該第一組功函數層環繞該p型通道。該p型通道經組態以用於基於該第一組功函數層的p型導電性。該n型電晶體包括一n型通道及第二組功函數層。該第二組功函數層環繞該n型通道。該n型通道經組態以用於基於該第二組功函數層的n型導電性。該第一組功函數層與該第二組功函數層不同。

Description

納米片電晶體堆疊
本發明大體上係關於具有非平面電晶體堆疊之方法及設備，且更特定言之，係關於堆疊內之不同類型之非平面電晶體。
諸如人工智慧及5G通信的新興應用需要不斷提高計算裝置的效能及減少功率。提高效能及減少功率之一種方式為縮小充當此等計算裝置之大腦的電晶體之大小。然而，平面電晶體正接近裝置縮小之製程極限。因此，半導體行業正向非平面電晶體轉移以繼續縮小電晶體。在一些實例中，非平面電晶體可包括納米片及納米線裝置。
此發明內容識別一些實例態樣之特徵，且並非對所揭示主題的排他性或窮盡性描述。描述額外特徵及態樣，且熟習此項技術者在閱讀以下實施方式且查看形成其一部分的圖式後，該等額外特徵及態樣將變得顯而易見。
根據至少一個實施例之設備堆疊內之不同類型之非平面電晶體。該設備包括p型電晶體及n型電晶體。該p型電晶體及該n型電晶體以堆疊豎直地配置於基板上方，該p型電晶體及該n型電晶體為非平面電晶體。該p型電晶體包括p型通道及第一組功函數層。該第一組功函數層環繞該p型通道。該p型通道經組態以用於基於該第一組功函數層之p型導電性。該n型電晶體包括n型通道及第二組功函數層。該第二組功函數層環繞該n型通道。該n型通道經組態以用於基於該第二組功函數層之n型導電性。該第一組功函數層與該第二組功函數層不同。
根據至少一個實施例，一種用以在一堆疊內形成不同類型之電晶體的方法包括在一基板上形成多個通道層及在該基板上之一堆疊內形成複數個通道，該多個通道係非平面的。該方法進一步包括形成遮罩層；形成至少一個功函數層；及藉由自複數個通道之一部分遮蔽至少一個功函數層的遮罩層在該堆疊內形成不同類型的電晶體。
本專利申請案主張在2020年7月1日申請之題為「納米片電晶體堆疊(NANOSHEET TRANSISTOR STACK)」的美國非臨時申請案第16/918,770號之優先權，該美國非臨時申請案主張題為「納米片電晶體堆疊(NANOSHEET TRANSISTOR STACK)」且在2019年7月3日申請之美國臨時申請案第62/870,453號的優先權益，該美國臨時申請案之全部內容明確地以引用之方式併入本文中。
下文結合附圖所闡述之詳細描述意欲作為對各種組態之描述，且並不意欲表示可實踐本文中所描述之概念的僅有組態。出於提供對各種概念之透徹理解之目的，詳細描述包括特定細節。然而，熟習此項技術者將顯而易見，可在無此等特定細節之情況下實踐此等概念。在一些情況下，熟知結構及組件係以方塊圖形式展示以避免混淆此等概念。
如本文中所使用，在動詞「耦接(couple)」的各種時態中，術語「耦接至(coupled to)」可意謂元件A直接連接至元件B或其他元件可連接於元件A與B之間(亦即，元件A與元件B間接連接)，以操作某些預期功能。在電組件之狀況下，術語「耦接至」在本文中亦可用以意謂使用導線、跡線或其他導電材料以電連接元件A及B (及電連接於其間的任何組件)。在一些實例中，術語「耦接至」意謂在元件A與B之間轉移電能，以操作某些預期功能。
在一些實例中，術語「電連接」意謂具有電流或可組態以使電流在元件A與B之間流動。舉例而言，除導線、跡線或其他導電材料及組件以外，元件A及B亦可經由電阻器、電晶體或電感器連接。此外，對於射頻功能，元件A及B可經由電容器或其他組件「電連接」。
為易於參考，採用術語「第一」、「第二」、「第三」等，且該等術語可能不帶有實質性含義。同樣，為易於參考，可採用組件/模組之名稱，且該等名稱可能不限制組件/模組。在本發明中呈現的模組及組件可實施於硬體或硬體與軟體之組合中。
術語「匯流排系統」可規定：耦接至「匯流排系統」之元件可在其間直接地或間接地交換資訊。以此方式，「匯流排系統」可涵蓋多個實體連接以及介入級，諸如緩衝器、鎖存器、暫存器等。
術語「安置於……上」、「在……上」(當用以描述實體關係時)、「貼附於……上」可指示多個元件直接地(其間無介入元件)或間接地(其間具有至少一個額外元件)進行實體連接。因此，在一些實例中，術語「安置於……上」可指示直接安置於實物上；「在……上」可指示直接在實物上；及/或「貼附」可指示直接貼附。
在本發明中，術語「堆疊」或對其之參考可表示單一堆疊。堆疊可為單體結構。舉例而言，堆疊可能並非個別部分之總成。如在例如環繞電晶體通道(下文中為「通道」)的閘極電極中，術語「環繞」可指直接或間接地在所環繞目標之外表面上方。在一些實例中，術語「環繞」可表示在50%或超過50%之外表面上方。在一些實例中，術語「環繞」可表示以足夠進行全方位圍閘(gate-all-around)製程之方式處於所環繞目標上方。
隨著效能需求的增長，半導體行業正轉向非平面電晶體，以繼續縮小裝置來滿足彼等需求。非平面電晶體可具有在多個維度上的通道區(例如，傳導電流)，且可包括例如納米片及納米線電晶體。通常，p型電晶體及n型電晶體成不同堆疊而形成，每個堆疊僅含有一種類型之電晶體。在單一堆疊內具有不同類型之電晶體將減小晶粒大小且改善效能。
圖1說明根據本發明之某些態樣的併有納米片電晶體的設備之組件。舉例而言，設備100可為計算系統(例如，伺服器、資料中心、桌上型電腦)、行動計算裝置(例如，膝上型電腦、蜂巢式電話、載具等)、物聯網裝置、虛擬實境系統或擴增實境系統中之一者，且可經組態以起使用者裝備或基地台作用。圖1說明併有至少一個處理器110、記憶體112、基頻處理器114及天線模組140之設備100。基頻處理器114耦接至記憶體112，且可經組態以利用記憶體112執行計算功能(例如，用於計算系統、行動計算裝置、物聯網裝置、虛擬實境系統或擴增實境系統之圖形、顯示功能或感測等)。舉例而言，記憶體112可儲存用於計算功能之指令或資料。
至少一個處理器110耦接至基頻處理器114且耦接至天線模組140以執行例如無線通信。基頻處理器114耦接至天線模組140，且可經組態以經由無線通信網路操作RF通信功能。舉例而言，基頻處理器114可經組態以基於數位網域中之無線通信網路(例如，5G、LTE、WiFi、藍芽等)之協定來制定邏輯層及實體層發信。基頻處理器114可經組態以輸出至天線模組140 (或自天線模組140輸入)以供經由天線模組140傳輸(或接收) RF發信。
天線模組140包括天線138、收發器120、電力管理積體電路(PMIC) 125及射頻(RF)前端131。在一些實例中，天線模組140可包括包絡追蹤電路(未圖示)。天線模組140可進一步包括被動組件(諸如，電感器及電容器；未圖示)。此等組件操作以執行基頻處理器114與天線138之間的RF通信。
天線138可經組態以傳輸或接收用於無線通信網路之RF信號。天線138可為例如貼片天線。PMIC 125可經組態以將電力提供至收發器120 (及/或RF前端131)。收發器120可經組態以將來自基頻處理器114之數位發信轉換成載波頻率中之RF發信以供天線138傳輸，及/或將自天線138接收之載波頻率下的RF信號轉換成用於基頻處理器114之數位發信。圖1說明收發器120經由RF前端131自天線138接收發信或提供發信以傳輸至天線138。
RF前端131可經組態以選擇及調整用於傳輸的RF信號或由天線138接收的RF信號。舉例而言，RF前端131可在將信號提供至天線138與自天線138接收信號之間、在多輸入及多輸出系統中之發信路徑之間、在不同無線通信協定或不同頻帶之間切換。RF前端131可進一步調整RF發信，諸如信號放大及濾波。
圖2說明根據本發明之某些態樣的以堆疊豎直地配置於基板上方的不同類型之納米片電晶體的實施例之橫截面圖。堆疊204安置於基板202上。舉例而言，基板202可為矽或絕緣體。堆疊204包括豎直地配置於基板202上方的p型電晶體206_1及206_2以及n型電晶體208_1及208_2。
諸如p型電晶體206_1、206_2以及n型電晶體208_1及208_2的納米片電晶體各自包括片狀通道。舉例而言，此通道可具有大於高度之表面積。p型電晶體206_1包括延伸入或延伸出圖2的p型通道210。圖2為區段橫截面圖，電晶體206_1、206_2、208_1及208_2之源極區及汲極區在圖內或圖外，且因此未圖示。在一些實例中，p型通道210可為矽。
在一些實例中，p型電晶體206_1、206_2以及n型電晶體208_1及208_2為全方位圍閘電晶體。p型電晶體206_1可包括全方位圍繞p型通道210的介電層212。術語「全方位圍繞」可為例如相對於基板202在豎直方向及水平方向上全方位圍繞。在一些實例中，介電層212可為高k介電質。
p型電晶體206_1可進一步包括環繞p型通道210之第一組功函數層213。在一些實例中，第一組功函數層213可全方位圍繞p型通道210。第一組功函數層213可包括一個或多個功函數層。納米片通道之諸如臨限電壓之極性的導電特性可基於一組功函數層中之一個或多個功函數層(例如，基於多個功函數層的組合)。
舉例而言，一個或多個功函數層可經組態以使得納米片通道之臨限電壓為負，且納米片通道將具有p型導電性。舉例而言，負閘極-源極電壓(VGS )將使具有p型導電性之納米片通道傳導電流，藉此接通納米片通道的(p型)電晶體。替代地，一個或多個功函數層可經組態以使得納米片通道之臨限電壓為正，且納米片通道將具有n型導電性。舉例而言，正閘極-源極電壓(VGS )將使具有n型導電性之納米片通道傳導電流，藉此接通納米片通道的(n型)電晶體。替代地，一個或多個功函數層可經組態以使得納米片通道的臨限電壓為負，且納米片通道將具有p型導電性。
第一組功函數層213包括TiN層214、TaN層216、TiN層218及TiAl層219。TiN層214可環繞(例如，全方位圍繞)介電層212。TaN層216可環繞(例如，全方位圍繞) TiN層214。TiN層218可環繞(例如，全方位圍繞) TaN層216。TiAl層219可環繞(例如，全方位圍繞) TiN層218。第一組功函數層213經由功函數層214、216、218及219的組合使p型通道210具有p型導電性。閘極電極230藉由環繞第一組功函數層213而環繞(例如，全方位圍繞) p型通道210。在一些實例中，閘極電極230可為金屬，諸如鎢。
n型電晶體208_1包括延伸入或延伸出圖2的n型通道220。圖2為區段橫截面圖，電晶體206_1、206_2、208_1及208_2之源極區及汲極區在圖內或圖外，且因此未圖示。在一些實例中，n型通道220可為矽。
n型電晶體208_1可包括全方位圍繞n型通道220之介電層222。術語「全方位圍繞」可為例如相對於基板202在豎直方向及水平方向上全方位圍繞。在一些實例中，介電層222可為高k介電質。
n型電晶體208_1可進一步包括環繞n型通道220之第二組功函數層223。在一些實例中，第二組功函數層223可全方位圍繞n型通道220。第二組功函數層223可包括一個或多個功函數層。納米片通道之諸如臨限電壓之極性的導電特性可基於一組功函數層中之一個或多個功函數層(例如，基於多個功函數層的組合)。第一組功函數層213與第二組功函數層223不同，在其間具有至少一個不同層。
第二組功函數層223可包括TiN層224、TaN層226及TiAl層229。TiN層224可環繞(例如，全方位圍繞)介電層222。TaN層226可環繞(例如，全方位圍繞) TiN層224。TiAl層229可環繞(例如，全方位圍繞) TaN層226。第二組功函數層223經由功函數層224、226及229的組合使n型通道220具有n型導電性。閘極電極230藉由環繞第一組功函數層223而環繞(例如，全方位圍繞) n型通道220。在一些實例中，閘極電極230可為金屬，諸如鎢。
如由圖2所呈現，p型電晶體206_1、206_2及n型電晶體208_1、208_2以堆疊204豎直地配置於基板202上方。p型電晶體206_1、206_2及n型電晶體208_1、208_2可為非平面電晶體，諸如納米片或納米線電晶體。p型電晶體206_1、206_2及n型電晶體208_1、208_2可為全方位圍閘電晶體。
p型電晶體206_1包括p型通道210及第一組功函數層213。第一組功函數層213環繞p型通道210，且p型通道210經組態以用於基於第一組功函數層213的p型導電性。n型電晶體208_1包括n型通道220及第二組功函數層223。第二組功函數層223環繞n型通道220。n型通道220經組態以用於基於第二組功函數層223的n型導電性。
第一組功函數層213與第二組功函數層223的不同之處在於例如具有至少一個不同功函數層，或功函數層之不同排序。舉例而言，TiN層218為第一組功函數層213之部分且並非第二組功函數層223之部分。在一些實例中，第一組功函數層213及第二組功函數層223共用至少一個共同功函數層。舉例而言，TiN層2114及224為由第一組功函數層213及第二組功函數層223共用的共同功函數層。
圖3說明根據本發明的某些態樣的以堆疊豎直地配置於基板上方的不同類型之納米片電晶體的另一實施例之橫截面圖。圖3說明堆疊204，該堆疊與圖2的不同之處在於堆疊204中具有多個閘極電極。舉例而言，第一閘極電極304環繞(例如，多於一半之外表面；例如，全方位圍繞) p型電晶體206_2的p型通道210。第二閘極電極306環繞(例如，多於一半；例如，全方位圍繞) n型電晶體208_1的n型通道220。第一閘極電極304及第二閘極電極306藉由絕緣層305分離及/或隔離。絕緣層305可為例如氧化矽。在藉由絕緣層305絕緣之情況下，第一閘極電極304及第二閘極電極306可經組態以獨立地操作。舉例而言，第一閘極電極304及第二閘極電極306可在不同邏輯位準下操作至少一段時間。
在一些實例中，計算系統、行動計算系統、物聯網裝置、虛擬實境系統或擴增實境系統中之一者(諸如，圖1之設備100)併有p型電晶體206_1、206_2及n型電晶體208_1、208_2。
圖4A至圖4E說明根據本發明之某些態樣的在堆疊內形成不同類型之電晶體的各種階段。不同類型之電晶體可為例如p型電晶體及n型電晶體。圖4A說明階段402、406、408及408-2。階段402、406及408係以水平X軸及豎直Z軸(與圖2及3相同之定向)說明。階段408-2為具有水平Y軸及豎直Z軸之階段408。階段408-2為圍繞Z軸旋轉90度的階段408之視圖。
在402處，多個通道層403形成於基板202 (參見圖2及圖3)上。通道層403將成為堆疊中之不同類型電晶體的電晶體通道。介入層404與通道層403交替地形成以分離通道層403。通道層403及/或介入層404可藉由磊晶生長形成。在一些實例中，通道層403可為Si，及/或介入層404可為SiGe。介入層404可為稍後待在製程中移除之犧牲層。通道層403係非平面的。舉例而言，通道層403可為納米線或納米片(例如，具有大於其高度之平面表面)。併有通道層403之電晶體將因此為非平面電晶體。
在406處，在基板202上方形成在豎直方向(Z軸)上具有多個通道層403之堆疊204。可單獨在X軸之各種位置處蝕刻掉階段402之通道層403及介入層404以形成包括堆疊204的各種堆疊。以此方式，選擇堆疊204 (及因此，堆疊204內之電晶體)之寬度。堆疊204在Z軸上延伸(例如，延伸入或延伸出頁面)。間隔物及源極/汲極電極可形成於堆疊204的邊緣上方(在此視圖中間隔物不可見，此係因為邊緣在頁面內或頁面外)。
在408處，蝕刻掉介入層404，從而使通道層403之表面曝露。在408處，階段408之視圖旋轉90度，其中Y軸為水平軸。間隔物409形成於堆疊204之邊緣上。針對堆疊204中之不同類型之電晶體形成源極/汲極電極209，源極/汲極電極209藉由間隔物409與通道層403分離。
圖4B說明階段412，其中形成介電層422及各種功函數層以環繞通道層403中之每一者。階段412係與階段402、406及408相同之視圖(X軸係水平的，Z軸係豎直的)。通道層403將成為圖2中所說明的電晶體通道(例如，p型通道210及n型通道220；參見圖2)。為易於參考，通道層403經標記為403_1、403_2、403_3、403_4。介電層422經形成以分別環繞通道層403中之每一者。在一些實例中，介電層422可為高k介電質。在一些實例中，介電層422中之每一者可環繞通道層403中的每一者之大部分(例如，多於一半)表面。在一些實例中，介電層422中之每一者全方位圍繞通道層403中之每一者的表面以來自全方位圍閘電晶體之部分。參看圖2，介電層422將成為圖2中所說明的介電層(例如，用於p型電晶體206-1及206-2的介電層212；用於n型電晶體208-1及208-2的介電層222)。
將成為第一組功函數層213及第二組功函數層223 (圖2)之一部分的功函數層424及426形成於介電層422上方。功函數層424可包括TiN，且功函數層426可包括TaN。功函數層424及426可藉由原子層沈積形成。功函數層424及426可環繞介電層422中的每一者(及因此，通道層403中之各別者)之大部分(例如，多於一半)表面。在一些實例中，功函數層424及426全方位圍繞介電層422中的每一者(及因此，通道層403中之各別者)的表面以來自全方位圍閘電晶體之部分。功函數層424將成為圖2之TiN層214及224。功函數層426將成為圖2之TaN層216及226。
圖4C說明階段414，其中形成遮罩層415以遮蔽通道層403中之某些通道層，且遮蔽與經遮蔽通道層403相關聯之介電層422及功函數層(例如，層424及426)。階段414係與階段402、406及408相同之視圖(X軸係水平的，Z軸係豎直的)。形成遮罩層415以遮蔽通道層403_3及403_4，該等通道層將分別成為n型電晶體208_1及208_2之通道。遮罩層415可包括碳基有機可流動介電質或抗反射塗層材料。在一些實例中，遮罩層415包括SiNx。
圖4D說明階段416，其中形成額外功函數層428以環繞在階段414中未由遮罩層415遮蔽的通道層403 (例如，通道層403_1及403_2)，且環繞與其相關聯之介電層422及功函數層(例如，層424及426)。階段416係與階段402、406及408相同之視圖(X軸係水平的，Z軸係豎直的)。額外功函數層428形成於通道層403_1及403_2周圍，且不形成於由遮罩層415遮蔽之通道層403_3及403_4周圍。在一些實例中，額外功函數層428可包括TiN且將成為圖2之TiN層218。
圖4E說明階段418，其中移除遮罩層415且在通道層403_1、403_2、403_3及403_4周圍(以及在與通道層相關聯之介電層422及功函數層周圍，例如層424、426及428)形成額外功函數層429。階段418係與階段402、406及408相同之視圖(X軸係水平的，Z軸係豎直的)。在一些實例中，額外功函數層429可包括TiAl。在一些實例中，額外功函數層429將成為圖2中所展示之TiAl層。
以此方式，包括功函數層424 (例如，TiN層214)、功函數層426 (例如，TaN層216)、功函數層428 (例如，TiN層218)及額外功函數層429 (例如，TiAl層219)之第一組功函數層213形成於通道層403_1及403_2周圍。第一組功函數層213向通道層403_1及403_2顯現且具有p型導電性。通道層403_1將成為p型通道210以及p型電晶體206_1及206_2之部分。
包括功函數層424 (例如，TiN層214)、功函數層426 (例如，TaN層216)及額外功函數層429 (例如，TiAl層219)之第二組功函數層223形成於通道層403_3及403_4周圍。第二組功函數層223向通道層403_3及403_4顯現且具有n型導電性。通道層403_3將成為n型通道220以及n型電晶體208_1及208_2之部分。
閘極電極可形成於第一組功函數層213及/或第二組功函數層223上方。參看圖2，閘極電極230可形成於堆疊204中之p型電晶體206_1、206_2及n型電晶體208_1、208_2上方。參看圖3，可針對p型電晶體206_1 (或p型電晶體206_2)形成閘極電極302 (或閘極電極304)。可針對n型電晶體208_1 (或n型電晶體208_2)形成閘極電極306 (或閘極電極308)。絕緣層303、305、307可經形成以使閘極電極302、304、306及/或308絕緣。舉例而言，用於p型電晶體206_2的閘極電極304可藉由絕緣層305與用於n型電晶體208_1的閘極電極306絕緣。
圖5說明根據本發明之某些態樣的用以在堆疊內形成不同類型之電晶體的方法。所展示之操作可能不指示操作之排序。在502處，多個通道層形成於基板上。舉例而言，參看圖4A之402，多個通道層403形成於基板202上。介入層404與通道層403交替地形成以分離通道層403。通道層403及/或介入層404可藉由磊晶生長形成。在一些實例中，通道層403可為Si，及/或介入層404可為SiGe。
在504處，在基板上的堆疊內形成複數個通道，該複數個通道為非平面的。參見例如圖4A的404。可單獨在X軸之各種位置處蝕刻掉階段402之通道層403及介入層404，以形成包括堆疊204 (參見圖2)的各種堆疊。在基板202上方，堆疊204在豎直方向(Z軸)上包括多個通道層403。可單獨在X軸之各種位置處蝕刻掉階段402之通道層403及介入層404，以形成包括堆疊204的各種堆疊。以此方式，選擇堆疊204 (及因此，堆疊204內之電晶體)之寬度。堆疊204在Z軸上延伸(例如，延伸入或延伸出頁面)。間隔物及源極/汲極電極可形成於堆疊204的邊緣上方(在此視圖中間隔物不可見，此係因為邊緣在頁面內或頁面外)。
在一些實例中，通道層403為用於非平面電晶體(諸如，納米片或納米線電晶體)之通道。通道層403可為納米片通道。舉例而言，通道層403的X-Y區域可大於通道層403在Z軸上的高度。
在506處，形成遮罩層。參見例如圖4C。形成遮罩層415以遮蔽通道層403_3及403_4，該等通道層將分別成為n型電晶體208_1及208_2之通道。遮罩層415可包括碳基有機可流動介電質或抗反射塗層材料。在一些實例中，遮罩層415包括SiNx。除可流動介電質外，在實例中，亦可形成介電質以覆蓋所有元件，隨後自上而下蝕刻以自某些區域移除介電質。
在508處，形成至少一個功函數層。參見例如圖4D。形成至少一個功函數層428以環繞在階段414中未由遮罩層415遮蔽之通道層403 (例如，通道層403_1及403_2)。至少一個功函數層428形成於通道層403_1及403_2周圍，且不形成於由遮罩層415遮蔽之通道層403_3及403_4周圍。在一些實例中，額外功函數層428可包括TiN且將成為圖2之TiN層218。
在510處，藉由自複數個通道之一部分遮蔽至少一個功函數層的遮罩層在堆疊內形成不同類型之電晶體。在512處，形成第二功函數層。第二功函數層未由遮罩層遮蔽。參見例如圖4E。移除遮罩層415，且在通道層403_1、403_2、403_3及403_4周圍(以及在與通道層相關聯之介電層422及功函數層周圍，例如功函數層424、426及428)形成第二功函數層429。第二功函數層429未由遮罩層415遮蔽，該遮罩層被移除。
以此方式，包括功函數層424 (例如，TiN層214)、功函數層426 (例如，TaN層216)、功函數層428 (例如，TiN層218)及功函數層429 (例如，TiAl層219)之第一組功函數層213形成於通道層403_1及403_2周圍。第一組功函數層213向通道層403_1及403_2顯現且具有p型導電性。通道層403_1將成為p型通道210以及p型電晶體206_1及206_2之部分。
包括功函數層424 (例如，TiN層214)、功函數層426 (例如，TaN層216)及功函數層429 (例如，TiAl層219)之第二組功函數層223形成於通道層403_3及403_4周圍。第二組功函數層223向通道層403_3及403_4顯現且具有n型導電性。通道層403_3將成為n型通道220以及n型電晶體208_1及208_2之部分。
在514處，形成用於不同類型中之一種類型之電晶體的第一電極。在516處，形成用於不同類型中之第二類型之電晶體的第二電極。在518處，形成絕緣層以使第一電極絕緣，且形成第二電極。參見例如圖3。第一電極304經形成以用於p型電晶體206_2。形成用於n型電晶體208_1之第二電極306。形成絕緣層305以使第一電極304與第二電極306絕緣。
提供先前描述以使得任何熟習此項技術者能夠實踐本文中所描述之各種態樣。對此等態樣的各種修改對於熟習此項技術者而言將容易顯而易見，且本文中定義的一般原理可適用於其他態樣。因此，申請專利範圍不意欲限於本文中所展示的態樣，而是應符合與語言申請專利範圍一致的完整範圍，其中以單數形式參考一元件不意欲意謂「一個且僅有一個」，除非明確地如此陳述，否則意謂「一或多個」。詞「例示性」在本文中用以意謂「充當實例、例項或說明」。不必將本文中描述為「例示性」之任何態樣解釋為較佳或優於其他態樣。除非另外特定地陳述，否則術語「一些」指一或多個。諸如「A、B或C中之至少一者」、「A、B或C中之一或多者」、「A、B及C中之至少一者」、「A、B及C中之一或多者」及「A、B、C或其任何組合」之組合包括A、B及/或C之任何組合，且可包括多個A、多個B或多個C。具體言之，諸如「A、B或C中之至少一者」、「A、B或C中之一或多者」、「A、B及C中之至少一者」、「A、B及C中之一或多者」及「A、B、C或其任何組合」之組合可僅為A、僅為B、僅為C、A及B、A及C、B及C，或A及B及C，其中任何此等組合可含有A、B或C中之一或多個成員。對於一般熟習此項技術者而言已知或稍後將已知的貫穿本發明所描述之各種態樣的要素之所有結構及功能等效物明確地以引用的方式併入本文中，且意欲由申請專利範圍所涵蓋。此外，本文中所揭示之任何內容均不意欲專用於公眾，無論申請專利範圍中是否明確敍述此揭示內容。詞「模組」、「機構」、「元件」、「裝置」及其類似者不可取代詞「構件」。因而，任何申請專利範圍元件皆不應解釋為構件加功能，除非該元件使用片語「用於......的構件」來明確地敍述。
100:設備 110:處理器 112:記憶體 114:基頻處理器 120:收發器 125:電力管理積體電路(PMIC)131:射頻(RF)前端 138:天線 140:天線模組 202:基板 204:堆疊 206_1:p型電晶體 206_2:p型電晶體 208_1:n型電晶體 208_2:n型電晶體 210:p型通道 212:介電層 213:第一組功函數層 214:TiN層/功函數層 216:TaN層/功函數層 218:TiN層/功函數層 219:TiAl層/功函數層 220:n型通道 222:介電層 223:第二組功函數層 224:TiN層/功函數層 226:TaN層/功函數層 229:TiAl層/功函數層 230:閘極電極 302:閘極電極 303:絕緣層 304:第一閘極電極 305:絕緣層 306:第二閘極電極 307:絕緣層 308:閘極電極 402:階段 403:通道層 403_1:通道層 403_2:通道層 403_3:通道層 403_4:通道層 404:介入層406:階段 408:階段 408-2:階段 409:間隔物 412:階段 414:階段 415:遮罩層 416:階段 418:階段 422:介電層 424:功函數層 426:功函數層 428:額外功函數層 429:第二功函數層 502:步驟 504:步驟 506:步驟 508:步驟 510:步驟 512:步驟 514:步驟 516:步驟 518:步驟
現將參看隨附圖式作為實例而非作為限制在實施方式中呈現設備及方法之各種態樣，在隨附圖式中：
圖1說明根據本發明之某些態樣的併有納米片電晶體的設備之組件。
圖2說明根據本發明之某些態樣的以堆疊豎直地配置於基板上方的不同類型之納米片電晶體的實施例之橫截面圖。
圖3說明根據本發明之某些態樣的以堆疊豎直地配置於基板上方的不同類型之納米片電晶體的另一實施例之橫截面圖。
圖4A至圖4E說明根據本發明之某些態樣的在堆疊內形成不同類型之電晶體的各種階段。
圖5說明根據本發明之某些態樣的用以在堆疊內形成不同類型之電晶體的方法。
202:基板
204:堆疊
206_1:p型電晶體
206_2:p型電晶體
208_1:n型電晶體
208_2:n型電晶體
210:p型通道
212:介電層
213:第一組功函數層
214:TiN層/功函數層
216:TaN層/功函數層
218:TiN層/功函數層
219:TiAl層/功函數層
220:n型通道
222:介電層
223:第二組功函數層
224:TiN層/功函數層
226:TaN層/功函數層
229:TiAl層/功函數層
230:閘極電極

Claims (10)

  1. 一種設備，其包含： 一p型電晶體； 一n型電晶體，該p型電晶體及該n型電晶體以一堆疊豎直地配置於一基板上方，該p型電晶體及該n型電晶體為非平面電晶體， 其中該p型電晶體包含一p型通道及第一組功函數層，該第一組功函數層環繞該p型通道，該p型通道經組態以用於基於該第一組功函數層的p型導電性，且 其中該n型電晶體包含一n型通道及第二組功函數層，該第二組功函數層環繞該n型通道，該n型通道經組態以用於基於該第二組功函數層的n型導電性，該第一組功函數層與該第二組功函數層不同。
  2. 如請求項1之設備，其中該p型通道及該n型通道為納米片通道。
  3. 如請求項2之設備，其中該p型電晶體及該n型電晶體為全方位圍閘電晶體。
  4. 如請求項1之設備，其進一步包含一計算系統、一行動計算系統、一物聯網裝置、一虛擬實境系統或一擴增實境系統中的一者，該裝置併有該p型電晶體及該n型電晶體。
  5. 如請求項4之設備，該第一組功函數層及該第二組功函數層共用至少一個共同功函數層。
  6. 如請求項5之設備，其進一步包含： 用於該p型電晶體的一第一閘極電極，該第一閘極電極環繞該p型通道；及 用於該n型電晶體的一第二閘極電極，該第二閘極電極環繞該n型通道，該第一閘極電極及該第二閘極電極經組態以獨立地操作。
  7. 一種用以在一堆疊內形成不同類型之電晶體的方法，其包含： 在一基板上形成複數個通道層； 在該基板上之一堆疊內形成複數個通道，該複數個通道為非平面的； 形成一遮罩層； 形成至少一個功函數層； 藉由該遮罩層自該複數個通道的一部分遮蔽該至少一個功函數層，在該堆疊內形成不同類型的電晶體。
  8. 如請求項7之方法，其中該複數個通道包含納米片通道。
  9. 如請求項8之方法，其進一步包含形成一第二功函數層，該第二功函數層未由該遮罩層遮蔽。
  10. 如請求項9之方法，其進一步包含： 形成用於該等不同類型中之一種類型之電晶體的一第一電極； 形成用於該等不同類型中之一第二類型之電晶體的一第二電極；及 形成一絕緣層以使該第一電極與該第二電極絕緣。
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