TW202029509A - Method of manufacturing semiconductor arrangement - Google Patents

Method of manufacturing semiconductor arrangement Download PDF

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Publication number
TW202029509A
TW202029509A TW108138973A TW108138973A TW202029509A TW 202029509 A TW202029509 A TW 202029509A TW 108138973 A TW108138973 A TW 108138973A TW 108138973 A TW108138973 A TW 108138973A TW 202029509 A TW202029509 A TW 202029509A
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Taiwan
Prior art keywords
semiconductor
fin
layer
stress
dielectric
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TW108138973A
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Chinese (zh)
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王培宇
世海 楊
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台灣積體電路製造股份有限公司
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Priority to US201862753176P priority Critical
Priority to US62/753,176 priority
Priority to US16/577,389 priority
Priority to US16/577,389 priority patent/US11088281B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202029509A publication Critical patent/TW202029509A/en

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    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys

Abstract

A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.

Description

半導體配置之製造方法Manufacturing method of semiconductor configuration
本發明實施例是關於半導體技術,特別是關於一種包含應力誘發材料(stress-inducing material)之半導體配置的製造方法。The embodiments of the present invention are related to semiconductor technology, and in particular to a manufacturing method of a semiconductor configuration including a stress-inducing material.
隨著半導體產業為了追求更高的裝置密度、更高的效能和更低的成本而進入奈米科技製程節點,製造方法與設計上面臨的挑戰促使了3D設計的發展,像是鰭式場效電晶體(fin-like field effect transistor, FinFET)。鰭式場效電晶體包括延伸的半導體鰭片,其在基本上垂直於基底頂面的平面方向延伸。在此鰭片中形成鰭式場效電晶體的通道。提供閘極在鰭片之上,且部分地環繞鰭片。場效電晶體可減少短通道效應(short channel effect)。As the semiconductor industry enters the nanotechnology process node in pursuit of higher device density, higher performance, and lower cost, manufacturing methods and design challenges have prompted the development of 3D design, such as fin-type field effect devices. Crystal (fin-like field effect transistor, FinFET). The fin-type field effect transistor includes an extended semiconductor fin which extends in a plane direction substantially perpendicular to the top surface of the substrate. A channel for a fin-type field effect transistor is formed in this fin. The gate is provided above the fin and partially surrounds the fin. Field effect transistors can reduce short channel effects.
一種半導體配置之製造方法,包括在半導體層上形成鰭片,並且形成閘極結構於此鰭片的第一部分上方。移除鰭片鄰近於第一部分之第二部分、以及於鰭片之第二部分下方的半導體層的一部分以定義凹槽。形成應力誘發材料於凹槽中。形成第一半導體材料於凹槽中的應力誘發材料之上,其中第一半導體材料與應力誘發材料不同。A method for manufacturing a semiconductor configuration includes forming a fin on a semiconductor layer, and forming a gate structure above the first part of the fin. The second part of the fin adjacent to the first part and a part of the semiconductor layer under the second part of the fin are removed to define a groove. A stress-inducing material is formed in the groove. A first semiconductor material is formed on the stress inducing material in the groove, wherein the first semiconductor material is different from the stress inducing material.
一種半導體配置之製造方法,包括在半導體層上形成鰭片。移除鰭片之第一部分及半導體層之第一部分以定義第一凹槽,並且移除鰭片之第二部分及半導體層之第二部分以定義第二凹槽。形成應力誘發材料於第一凹槽及第二凹槽中,且形成第一半導體材料於第一凹槽及第二凹槽中的應力誘發材料之上,其中第一半導體材料與應力誘發材料不同。第一凹槽中之第一半導體材料定義一第一源極/汲極區域,以及第二凹槽中之第一半導體材料定義第二源極/汲極區域。A method for manufacturing a semiconductor configuration includes forming fins on a semiconductor layer. The first part of the fin and the first part of the semiconductor layer are removed to define a first groove, and the second part of the fin and the second part of the semiconductor layer are removed to define a second groove. Forming a stress inducing material in the first groove and the second groove, and forming a first semiconductor material on the stress inducing material in the first groove and the second groove, wherein the first semiconductor material is different from the stress inducing material . The first semiconductor material in the first recess defines a first source/drain region, and the first semiconductor material in the second recess defines a second source/drain region.
一種半導體配置,包括位於半導體層之上的鰭片,及位於鰭片的一部分及半導體層的一部分之上的閘極結構。包括鄰近於鰭片之部分以及半導體層之部分的應力誘發材料,以及第一半導體材料鄰近於鰭片之部分且於應力誘發材料之上,其中,第一半導體材料與應力誘發材料不同。A semiconductor configuration includes a fin on the semiconductor layer, and a gate structure on a part of the fin and a part of the semiconductor layer. The stress-inducing material includes a part adjacent to the fin and a part of the semiconductor layer, and the first semiconductor material is adjacent to the part of the fin and above the stress-inducing material, wherein the first semiconductor material is different from the stress-inducing material.
以下揭露提供了許多不同的實施例或範例,用於實施所提供的標的物之不同部件。各部件和其配置的具體範例描述如下,以簡化本發明實施例之說明。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例而言,敘述中若提及第一部件形成在第二部件之上或上,可能包含第一和第二部件直接接觸的實施例,也可能包含額外的部件形成在第一和第二部件之間,使得它們不直接接觸的實施例。此外,本發明實施例可能在不同的範例中重複參考數字及∕或字母。如此重複是為了簡明和清楚,而非用以表示所討論的不同實施例及∕或配置之間的關係。The following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first component is formed on or on the second component, it may include an embodiment in which the first and second components are in direct contact, or it may include additional components formed on the first and second components. Between, so that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments and/or configurations discussed.
此外,在本發明實施例中,敘述中若提及一個部件形成於另外一個部件上方、與另一個部分連接、及∕或與另一個部件耦合,可能包含部件之間直接接觸的實施例,也可能包含額外的部件插入部件之間而形成,使得它們不直接接觸的實施例。In addition, in the embodiments of the present invention, if the description mentions that a part is formed above another part, is connected to another part, and/or is coupled to another part, it may include an embodiment in which the parts are in direct contact. It may include an embodiment in which additional components are inserted between components so that they do not directly contact.
再者,其中可能用到與空間相對用詞,例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。Furthermore, words that are relative to space may be used, such as "below", "below", "lower", "above", "higher" and other similar words for ease of description The relationship between one component or feature(s) and another component or feature(s) in the diagram. Spatial relative terms are used to include the different orientations of the device in use or operation, as well as the orientation described in the diagram. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used in it will also be interpreted according to the turned position.
本文提供一個或多個製造半導體配置的技術。根據一些發明實施例,形成應力誘發材料於凹槽中,此凹槽延伸進比鰭片低的半導體層。應力誘發材料施加應力至電晶體裝置的通道區域。在一些實施例中,應力誘發材料為介電材料。在一些實施例中,應力誘發材料為矽合金材料。This article provides one or more techniques for manufacturing semiconductor configurations. According to some embodiments of the invention, a stress-inducing material is formed in the groove, and the groove extends into the semiconductor layer lower than the fin. The stress-inducing material applies stress to the channel area of the transistor device. In some embodiments, the stress-inducing material is a dielectric material. In some embodiments, the stress inducing material is a silicon alloy material.
第1到第12圖為根據一些實施例繪示出在各種製造階段的半導體配置100。第1到第12圖包括一簡化的平面圖,顯示所截取的各種剖面圖。參照第1圖,視圖X-X為從半導體配置100對應於閘極長度方向穿過鰭片或奈米片所截取的剖面圖,視圖Y1-Y1為從半導體配置100對應於閘極寬度方向穿過閘極結構所截取的剖面圖,視圖Y2-Y2為從半導體配置100對應於閘極寬度方向穿過源極/汲極區域所截取的剖面圖。並非每個在剖面圖中顯示的製程步驟都繪示於平面圖中。Figures 1 to 12 illustrate the semiconductor configuration 100 in various manufacturing stages according to some embodiments. Figures 1 to 12 include a simplified plan view showing various cross-sectional views taken. Referring to Figure 1, view XX is a cross-sectional view taken through the fin or nanosheet from the semiconductor configuration 100 corresponding to the gate length direction, and views Y1-Y1 are cross-sectional views taken from the semiconductor configuration 100 corresponding to the gate width direction through the gate A cross-sectional view taken through the electrode structure, and views Y2-Y2 are cross-sectional views taken from the semiconductor configuration 100 through the source/drain region corresponding to the gate width direction. Not every process step shown in the cross-sectional view is shown in the plan view.
參照第1圖,其根據一些實施例繪示在半導體配置100之製程中使用的複數個層。在一些實施例中,半導體配置100包括鰭式電晶體,例如鰭式場效電晶體。形成複數個層於半導體層105之上。在一些實施例中,半導體層105為包括磊晶層、單晶半導體材料(例如但不限於Si、Ge、SiGe、InGaAs、GaAs、InSb、GaP 、GaSb、InAlAs 、GaSbP、GaAsSb以及InP)、絕緣體上覆矽(silicon-on-insulator, SOI)結構、晶圓、或由晶圓形成的晶粒(die)之中的至少一種的基底的一部分。在一些實施例中,半導體層105包括結晶矽(crystalline silicon)。Referring to FIG. 1, it illustrates a plurality of layers used in the manufacturing process of the semiconductor configuration 100 according to some embodiments. In some embodiments, the semiconductor configuration 100 includes a fin transistor, such as a fin field effect transistor. A plurality of layers are formed on the semiconductor layer 105. In some embodiments, the semiconductor layer 105 includes an epitaxial layer, a single crystal semiconductor material (such as but not limited to Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb and InP), an insulator A part of the substrate of at least one of a silicon-on-insulator (SOI) structure, a wafer, or a die formed from the wafer. In some embodiments, the semiconductor layer 105 includes crystalline silicon.
在一些實施例中,鰭片110形成於半導體層105之上。在一些實施例中,透過使用圖案化硬遮罩(patterned hard mask)在半導體層105中蝕刻溝槽來形成鰭片110。因此,鰭片110由半導體層105中殘留在溝槽之間的部分形成。在一些實施例中,形成(例如生長)鰭片110在半導體層105之上。在一些實施例中,藉由形成第二半導體層在半導體層105上方,並且在第二半導體層中蝕刻溝槽來在半導體層105之上形成鰭片110。在一些實施例中,最初形成在半導體層105中的鰭片被置換。例如,在一些實施例中,一開始藉由在半導體層105中形成溝槽來定義鰭片,形成介電層於最初形成的鰭片之間,並且將介電層平坦化以暴露最初形成的鰭片的上表面,且執行蝕刻製程以移除至少部分最初形成的鰭片,執行成長製程以形成與初始鰭片比起來具有一個或多的不同的材料特徵的置換鰭片,像是不同的矽合金材料、不同的摻質濃度等等。在一些實施例中,半導體層105中的摻質種類及∕或摻質濃度與鰭片110之摻質種類及∕或摻質濃度不同。在鰭片110與半導體層105之間定義有界面115於半導體層105的最頂面。根據一些實施例,鰭片110定義用於形成像是鰭式場效電晶體的裝置的主動區域。在一些實施例中,隔離結構117,像是淺溝槽隔離(shallow trench isolation, STI),藉由沉積介電層在鰭片110之間,且凹蝕介電層以再暴露鰭片110之側壁的一部分來形成。在一些實施例中,隔離結構117包括矽和氧或其他適合的介電材料。In some embodiments, the fin 110 is formed on the semiconductor layer 105. In some embodiments, the fin 110 is formed by etching trenches in the semiconductor layer 105 using a patterned hard mask. Therefore, the fin 110 is formed of a portion of the semiconductor layer 105 remaining between the trenches. In some embodiments, the fin 110 is formed (eg grown) on the semiconductor layer 105. In some embodiments, the fin 110 is formed on the semiconductor layer 105 by forming a second semiconductor layer over the semiconductor layer 105 and etching trenches in the second semiconductor layer. In some embodiments, the fins originally formed in the semiconductor layer 105 are replaced. For example, in some embodiments, the fins are initially defined by forming trenches in the semiconductor layer 105, forming a dielectric layer between the initially formed fins, and planarizing the dielectric layer to expose the initially formed The upper surface of the fin, and an etching process is performed to remove at least part of the originally formed fin, and a growth process is performed to form a replacement fin having one or more different material characteristics compared with the initial fin, such as different Silicon alloy materials, different dopant concentrations, etc. In some embodiments, the dopant type and/or dopant concentration in the semiconductor layer 105 are different from the dopant type and/or dopant concentration of the fin 110. An interface 115 is defined on the top surface of the semiconductor layer 105 between the fin 110 and the semiconductor layer 105. According to some embodiments, the fin 110 defines an active area for forming a device like a fin-type field effect transistor. In some embodiments, the isolation structure 117, such as shallow trench isolation (STI), is formed by depositing a dielectric layer between the fins 110, and etching the dielectric layer to expose the fins 110. Part of the side wall is formed. In some embodiments, the isolation structure 117 includes silicon and oxygen or other suitable dielectric materials.
在一些實施例中,形成閘極結構120於鰭片110之上。在一些實施例中,閘極結構120包括第一閘極絕緣層和犧牲閘極電極。在一些實施例中,第一閘極絕緣層包括矽和氧。在一些實施例中,第一閘極絕緣層包括高介電常數介電材料。本文所使用的用語「高介電常數介電質」為介電常數大於或等於氧化矽之介電常數 (約3.9)的材料。高介電常數介電層的材料可為任何適合的材料。高介電常數介電層的材料例子包括但不限於Al2 O3 、HfO2 、ZrO2 、La2 O3 、TiO2 、SrTiO3 、LaAlO3 、Y2 O3 、Al2 Ox Ny 、HfOx Ny 、ZrOx Ny 、La2 Ox Ny 、 TiOx Ny 、SrTiOx Ny 、LaAlOx Ny 、Y2 Ox Ny 、SiON、SiNx 、上述之矽化物,及上述之合金。每個x值範圍獨立地為0.5至3,且每個y值範圍獨立地為0至2。In some embodiments, the gate structure 120 is formed on the fin 110. In some embodiments, the gate structure 120 includes a first gate insulating layer and a sacrificial gate electrode. In some embodiments, the first gate insulating layer includes silicon and oxygen. In some embodiments, the first gate insulating layer includes a high-k dielectric material. The term "high-permittivity dielectric" as used herein refers to a material with a dielectric constant greater than or equal to that of silicon oxide (approximately 3.9). The material of the high-k dielectric layer can be any suitable material. Examples of materials for the high-k dielectric layer include but are not limited to Al 2 O 3 , HfO 2 , ZrO 2 , La 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , Al 2 O x N y , HfO x N y , ZrO x N y , La 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , SiON, SiN x , the aforementioned silicides, And the above alloys. Each x value range is independently 0.5 to 3, and each y value range is independently 0 to 2.
在一些實施例中,第一閘極絕緣層包括原生氧化物層,此原生氧化物層藉由在製程流程中的各個點使半導體配置100暴露於氧氣而形成,使得鰭片110暴露的表面上形成二氧化矽。根據一些實施例,透過形成一層犧牲電極材料與一層硬遮罩層在鰭片110上來形成閘極結構120。在一些實施例中,執行圖案化製程以將硬遮罩層依照將形成的閘極結構的圖案進行圖案化,且利用硬遮罩層執行蝕刻製程以蝕刻犧牲電極層來定義閘極結構120。在一些實施例中,犧牲電極材料包括多晶矽。在一些實施例中,硬遮罩的剩餘部分形成一蓋層125在閘極結構120之上。In some embodiments, the first gate insulating layer includes a native oxide layer, which is formed by exposing the semiconductor arrangement 100 to oxygen at various points in the process flow, so that the exposed surface of the fin 110 Forms silicon dioxide. According to some embodiments, the gate structure 120 is formed by forming a layer of sacrificial electrode material and a hard mask layer on the fin 110. In some embodiments, a patterning process is performed to pattern the hard mask layer according to the pattern of the gate structure to be formed, and the hard mask layer is used to perform an etching process to etch the sacrificial electrode layer to define the gate structure 120. In some embodiments, the sacrificial electrode material includes polysilicon. In some embodiments, the remaining part of the hard mask forms a cap layer 125 on the gate structure 120.
在一些實施例中,側壁間隔物130鄰近於閘極結構120而形成。在一些實施例中,形成側壁間隔物130可藉由沉積一保形間隔物層(conformal spacer layer)在閘極結構120之上,且執行一非等向性(anisotropic)蝕刻步驟以移除間隔物層在蓋層125、鰭片110和半導體層105的水平表面之上的部分。在一些實施例中,側壁間隔物130包括與蓋層125相同的材料組成。在一些實施例中,側壁間隔物130包括氮和矽。在一些實施例中,閘極結構120形成於鰭片110的第一部分135和半導體層105的第一部分135之上,並且鰭片110的第二部分140暴露於閘極結構120及側壁間隔物130之間。在一些實施例中,鰭片110的第一部分135包括通道部分。在一些實施例中,鰭片110的寬度136約10到20奈米。在一些實施例中,包括側壁間隔物130的閘極結構120之間的間隔137約15到30奈米。在一些實施例中,在界面115上方的鰭片110的初始高度138約40至60奈米。In some embodiments, the sidewall spacer 130 is formed adjacent to the gate structure 120. In some embodiments, the sidewall spacers 130 can be formed by depositing a conformal spacer layer on the gate structure 120, and performing an anisotropic etching step to remove the spacers. The object layer is above the horizontal surface of the cap layer 125, the fin 110, and the semiconductor layer 105. In some embodiments, the sidewall spacer 130 includes the same material composition as the cap layer 125. In some embodiments, the sidewall spacer 130 includes nitrogen and silicon. In some embodiments, the gate structure 120 is formed on the first portion 135 of the fin 110 and the first portion 135 of the semiconductor layer 105, and the second portion 140 of the fin 110 is exposed to the gate structure 120 and the sidewall spacer 130 between. In some embodiments, the first portion 135 of the fin 110 includes a channel portion. In some embodiments, the width 136 of the fin 110 is about 10 to 20 nanometers. In some embodiments, the spacing 137 between the gate structures 120 including the sidewall spacers 130 is about 15 to 30 nanometers. In some embodiments, the initial height 138 of the fin 110 above the interface 115 is about 40 to 60 nanometers.
參照第2圖,根據一些實施例,移除鰭片110的第二部分140及在鰭片110之第二部分140下方的半導體層105的部分145,以形成凹槽150且延伸進界面115下方之半導體層105中。在一些實施例中,執行蝕刻製程以移除鰭片110之第二部分140以及在鰭片110之第二部分140下方的半導體層105的部分145。在一些實施例中,蝕刻製程為定時蝕刻製程(timed etch process),並選定蝕刻時間以將凹槽150的深度延伸至界面115之下並進入半導體層105之中。在一些實施例中,蝕刻製程利用甲烷或其他適合的蝕刻劑進行蝕刻。在一些實施例中,對應於鰭片110的上表面之凹槽150的深度152約60至90奈米。在一些實施例中,對應於界面115之凹槽150的深度154約20至50奈米。在一些實施例中,若對應於界面115之凹槽150的深度154大於50奈米,可能在製造過程中產生製程問題。例如,若對應於界面115之凹槽150的深度154大於50奈米,鰭片110可能遭受到導致鰭片110在製造過程中彎曲或傾斜的力,造成鰭片110的破壞。若對應於界面115之凹槽150的深度154少於20奈米,鰭片下方可能形成不足量的應力誘發材料160(如第3、4圖所示),導致鰭片110中誘發的應力量不足。Referring to FIG. 2, according to some embodiments, the second portion 140 of the fin 110 and the portion 145 of the semiconductor layer 105 under the second portion 140 of the fin 110 are removed to form a recess 150 and extend below the interface 115 The semiconductor layer 105. In some embodiments, an etching process is performed to remove the second portion 140 of the fin 110 and the portion 145 of the semiconductor layer 105 under the second portion 140 of the fin 110. In some embodiments, the etching process is a timed etch process, and the etching time is selected to extend the depth of the recess 150 below the interface 115 and into the semiconductor layer 105. In some embodiments, the etching process uses methane or other suitable etchant for etching. In some embodiments, the depth 152 of the groove 150 corresponding to the upper surface of the fin 110 is about 60 to 90 nm. In some embodiments, the depth 154 of the groove 150 corresponding to the interface 115 is about 20-50 nanometers. In some embodiments, if the depth 154 of the groove 150 corresponding to the interface 115 is greater than 50 nm, process problems may occur during the manufacturing process. For example, if the depth 154 of the groove 150 corresponding to the interface 115 is greater than 50 nanometers, the fin 110 may be subjected to a force that causes the fin 110 to bend or tilt during the manufacturing process, causing damage to the fin 110. If the depth 154 of the groove 150 corresponding to the interface 115 is less than 20 nm, an insufficient amount of stress-inducing material 160 (as shown in Figures 3 and 4) may be formed under the fin, resulting in the stress induced in the fin 110 insufficient.
參照第3圖,根據一些實施例,一介電材料155形成於凹槽150之中。在一些實施例中,執行沉積製程以形成介電材料155。介電材料155鄰近於鰭片110的第一部分135。在一些實施例中,介電材料155延伸至界面115上方。在一些實施例中,介電材料155的最上層表面位在高於界面115的高度。在一些實施例中,執行旋轉塗布(spin-on)沉積製程以形成介電材料155。在一些實施例中,介電材料155包括矽和氮。在一些實施例中,介電材料155包括矽和氧。在一些實施例中,介電材料155包括其他適合的介電材料。在一些實施例中,介電材料155從凹槽150的底部到介電材料155之上表面的高度157約10到30奈米。在一些實施例中,介電材料155的高度157控制在10到30奈米,使介電材料可在鰭片110底部的上方延伸(例如:在界面115上方延伸)少於10奈米。如此一來,當第一半導體材料165形成於凹槽150之中,如第5圖所示,且在介電材料155之上(在介電材料155轉換為應力誘發材料160之後,如圖4所示),第一半導體材料165之底部與鰭片110之底部的距離被最小化,使電流可以從第一半導體材料165流動至鰭片110的底部。若第一半導體材料165的底部與鰭片110的底部之間距離太大,裝置效能可能因應力誘發材料160所導致的電阻而受影響或下降,因而影響從第一半導體材料165流至鰭片110底部的電流。Referring to FIG. 3, according to some embodiments, a dielectric material 155 is formed in the groove 150. In some embodiments, a deposition process is performed to form the dielectric material 155. The dielectric material 155 is adjacent to the first portion 135 of the fin 110. In some embodiments, the dielectric material 155 extends above the interface 115. In some embodiments, the uppermost surface of the dielectric material 155 is located at a height higher than the interface 115. In some embodiments, a spin-on deposition process is performed to form the dielectric material 155. In some embodiments, the dielectric material 155 includes silicon and nitrogen. In some embodiments, the dielectric material 155 includes silicon and oxygen. In some embodiments, the dielectric material 155 includes other suitable dielectric materials. In some embodiments, the height 157 of the dielectric material 155 from the bottom of the groove 150 to the upper surface of the dielectric material 155 is about 10 to 30 nanometers. In some embodiments, the height 157 of the dielectric material 155 is controlled to be 10 to 30 nanometers, so that the dielectric material can extend above the bottom of the fin 110 (for example, extend above the interface 115) less than 10 nanometers. In this way, when the first semiconductor material 165 is formed in the recess 150, as shown in FIG. 5, and on the dielectric material 155 (after the dielectric material 155 is converted to the stress inducing material 160, as shown in FIG. 4 (Shown), the distance between the bottom of the first semiconductor material 165 and the bottom of the fin 110 is minimized, so that current can flow from the first semiconductor material 165 to the bottom of the fin 110. If the distance between the bottom of the first semiconductor material 165 and the bottom of the fin 110 is too large, the device performance may be affected or degraded due to the resistance caused by the stress inducing material 160, thereby affecting the flow from the first semiconductor material 165 to the fin. 110 current at the bottom.
根據一些實施例,介電材料155包括一應力誘發材料,此應力誘發材料在介電材料155的初沉積(as-deposited)狀態下於鰭片110的第一部分135施加應力。在一些實施例中,執行沉積製程以至少部分地填充凹槽150,並且執行蝕刻製程以從凹槽150移除介電材料155的一部分。在一些實施例中,於初沉積狀態下施加應力的介電材料155包括矽,以及碳或氮中的至少一種。在一些實施例中,介電材料155包括SiOx 、SiNx 、SiONx 、SiOCN或其他適合材料。According to some embodiments, the dielectric material 155 includes a stress-inducing material that applies stress to the first portion 135 of the fin 110 in the as-deposited state of the dielectric material 155. In some embodiments, a deposition process is performed to at least partially fill the groove 150 and an etching process is performed to remove a portion of the dielectric material 155 from the groove 150. In some embodiments, the dielectric material 155 that is stressed in the initial deposition state includes silicon and at least one of carbon or nitrogen. In some embodiments, the dielectric material 155 includes SiO x , SiN x , SiON x , SiOCN or other suitable materials.
在一些實施例中,介電材料155包括一多孔材料,其在介電材料155的初沉積狀態下並不會誘發應力。在一些實施例中,孔洞材料包括矽,以及氧或氮的至少其中一種。在一些實施例中,介電材料155包括SiOx 、SiNx 、SiONx 、SiOCN或其他適合材料。參照第4圖,根據一些實施例,例如介電材料155包括多孔材料、且介電材料155在初沉積狀態下不會誘發應力的實施例,來執行退火製程158以收縮介電材料155。介電材料155的收縮產生應力誘發材料160,此應力誘發材料施加拉伸應力於鰭片110的第一部分135。在一些實施例中,當介電材料155在初沉積狀態下包括應力誘發材料時,不執行退火製程158。在一些實施例中,退火製程的溫度介於約400°C及1700°C之間。在一些實施例中,應力誘發材料160施加約至少1.5GPa的應力。在一些實施例中,藉由在鰭片110的第一部分135施加至少1.5GPa的壓縮應力,電洞遷移率(hole mobility)上升,且P型電晶體的效能因而上升。在一些實施例中,藉由在鰭片110的第一部分135施加至少1.5GPa的拉伸應力,載子遷移率(carrier mobility)上升,且N型電晶體的效能因而上升。In some embodiments, the dielectric material 155 includes a porous material, which does not induce stress in the initial deposition state of the dielectric material 155. In some embodiments, the hole material includes silicon, and at least one of oxygen or nitrogen. In some embodiments, the dielectric material 155 includes SiO x , SiN x , SiON x , SiOCN or other suitable materials. Referring to FIG. 4, according to some embodiments, such as an embodiment where the dielectric material 155 includes a porous material and the dielectric material 155 does not induce stress in the initial deposition state, an annealing process 158 is performed to shrink the dielectric material 155. The shrinkage of the dielectric material 155 produces a stress-inducing material 160 that applies tensile stress to the first portion 135 of the fin 110. In some embodiments, when the dielectric material 155 includes a stress inducing material in the initial deposition state, the annealing process 158 is not performed. In some embodiments, the temperature of the annealing process is between about 400°C and 1700°C. In some embodiments, the stress-inducing material 160 applies a stress of about at least 1.5 GPa. In some embodiments, by applying a compressive stress of at least 1.5 GPa to the first portion 135 of the fin 110, hole mobility is increased, and the performance of the P-type transistor is thereby increased. In some embodiments, by applying a tensile stress of at least 1.5 GPa on the first portion 135 of the fin 110, carrier mobility is increased, and the performance of the N-type transistor is thereby increased.
參照第5圖,根據一些實施例,形成第一半導體材料165在介電材料155上方之凹槽150中。在一些實施例中,執行沉積製程以形成第一半導體材料165。在一些實施例中,沉積製程包括磊晶成長製程。在一些實施例中,例如在應力誘發材料包括氧或氮的情況下,可藉由磊晶成長製程形成第一半導體材料165,其中第一半導體材料165從鰭片110的側壁橫向成長。根據一些實施例,第一半導體材料165定義源極/汲極區域的一部分。在一些實施例中,第一半導體材料165的上表面在鰭片110的上表面以及隔離結構117的上表面上方延伸。Referring to FIG. 5, according to some embodiments, the first semiconductor material 165 is formed in the groove 150 above the dielectric material 155. In some embodiments, a deposition process is performed to form the first semiconductor material 165. In some embodiments, the deposition process includes an epitaxial growth process. In some embodiments, for example, when the stress-inducing material includes oxygen or nitrogen, the first semiconductor material 165 may be formed by an epitaxial growth process, wherein the first semiconductor material 165 is grown laterally from the sidewall of the fin 110. According to some embodiments, the first semiconductor material 165 defines a part of the source/drain region. In some embodiments, the upper surface of the first semiconductor material 165 extends above the upper surface of the fin 110 and the upper surface of the isolation structure 117.
參照第6圖,形成介電層170在第一半導體材料165之上。在一些實施例中,執行沉積製程以形成介電層170。在一些實施例中,平坦化介電層170以暴露蓋層125。在一些實施例中,介電層170包括二氧化矽或一低介電常數材料。在一些實施例中,介電層170包括一個或多個低介電常數介電材料層。低介電常數介電材料的k值(介電常數)低於約3.9。一些低介電常數介電材料的k值低於約3.5,且可能低於約2.5。介電層170的材料包括Si、O、C或H的至少其中一種,像是SiCOH和SiOC,或其他適合材料。有機材料(像是聚合物)也可用於介電層170。在一些實施例中,介電層170包括一層或多層含碳材料、有機矽玻璃、含造孔劑(porogen)材料或上述的組合。在一些實施例中,介電層170也可包含氮。介電層170可藉由,例如,電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition, PECVD)、低壓化學氣相沉積(low pressure CVD, LPCVD)、原子層化學氣相沉積 (atomic layer CVD, ALCVD)或旋轉塗布技術中的至少其中一種方法形成。在一些實施例中,當介電層170藉由電漿輔助化學氣相沉積形成,介電層170在約25° C至約400° C的範圍內的基底溫度以及小於100Torr的壓力下沉積。Referring to FIG. 6, a dielectric layer 170 is formed on the first semiconductor material 165. In some embodiments, a deposition process is performed to form the dielectric layer 170. In some embodiments, the dielectric layer 170 is planarized to expose the cap layer 125. In some embodiments, the dielectric layer 170 includes silicon dioxide or a low dielectric constant material. In some embodiments, the dielectric layer 170 includes one or more low-k dielectric material layers. The k value (dielectric constant) of a low-k dielectric material is less than about 3.9. Some low-k dielectric materials have k values below about 3.5, and possibly below about 2.5. The material of the dielectric layer 170 includes at least one of Si, O, C, or H, such as SiCOH and SiOC, or other suitable materials. Organic materials (such as polymers) can also be used for the dielectric layer 170. In some embodiments, the dielectric layer 170 includes one or more layers of carbon-containing materials, organic silicon glass, porogen-containing materials, or a combination thereof. In some embodiments, the dielectric layer 170 may also include nitrogen. The dielectric layer 170 can be formed by, for example, plasma-enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), and atomic layer chemical vapor deposition (atomic layer chemical vapor deposition). CVD, ALCVD) or at least one of spin coating technology. In some embodiments, when the dielectric layer 170 is formed by plasma-assisted chemical vapor deposition, the dielectric layer 170 is deposited at a substrate temperature in the range of about 25° C. to about 400° C. and a pressure less than 100 Torr.
參照第7圖,根據一些實施例,蓋層125被移除,並且側壁間隔物130和介電層170的高度下降。在一些實施例中,執行平坦化製程以移除蓋層125,並且減少側壁間隔物130和介電層170的高度。在一些實施例中,平坦化製程暴露閘極結構120。在一些實施例中,平坦化製程是執行於介電層170的平坦化製程的延續。Referring to FIG. 7, according to some embodiments, the capping layer 125 is removed, and the heights of the sidewall spacers 130 and the dielectric layer 170 are decreased. In some embodiments, a planarization process is performed to remove the cap layer 125 and reduce the height of the sidewall spacers 130 and the dielectric layer 170. In some embodiments, the planarization process exposes the gate structure 120. In some embodiments, the planarization process is a continuation of the planarization process performed on the dielectric layer 170.
參照第8圖,根據一些實施例,移除閘極結構120,包括第一閘極介電層及犧牲閘極電極,以定義閘極凹孔(cavities)175及暴露鰭片110的多個部分。在一些實施例中,執行一道或多道蝕刻製程以移除閘極結構120。在一些實施例中,一道或多道蝕刻製程包括對閘極結構120的材料具有選擇性的一道或多道濕式蝕刻製程。在一些實施例中,僅移除一部分的閘極結構120,像是犧牲閘極電極,以定義閘極凹孔175。在一些實施例中,當移除閘極結構120時,不移除第一閘極介電層,且不暴露鰭片110的多個部分。Referring to Figure 8, according to some embodiments, the gate structure 120, including the first gate dielectric layer and the sacrificial gate electrode, is removed to define gate cavities 175 and expose portions of the fin 110 . In some embodiments, one or more etching processes are performed to remove the gate structure 120. In some embodiments, the one or more etching processes include one or more wet etching processes that are selective to the material of the gate structure 120. In some embodiments, only a portion of the gate structure 120, such as a sacrificial gate electrode, is removed to define the gate recess 175. In some embodiments, when the gate structure 120 is removed, the first gate dielectric layer is not removed, and portions of the fin 110 are not exposed.
參照第9圖,根據一些實施例,置換閘極(replacement gate)結構180形成於閘極凹孔175之中。在一些實施例中,置換閘極結構180包括閘極介電層、閘極電極層及其他適合的層。在一些實施例中,第一閘極介電層為包括在置換閘極結構180內的閘極介電層。在一些實施例中,閘極介電層包括高介電常數介電材料。在一些實施例中,閘極電極層包括一金屬填充層。在一些實施例中,置換閘極結構180包括形成於閘極介電層上方之導電功函數材料層,且金屬填充層形成於功函數材料層上方。在一些實施例中,功函數材料層包括一p型功函數材料層,像是TiN、 TaN、 Ru、Mo、Al、WN、ZrSi2 、MoSi2 、TaSi2 、NiSi2 中的至少一種,或其他合適的p型功函數材料。在一些實施例中,功函數材料層包括一n型功函數金屬,像是Ti、Ag、TiAl、TiAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr中的至少一種,或其他合適的n型功函數材料。在一些實施例中,功函數材料層包括複數個層。在一些實施例中,金屬填充層包括鎢或其他適合的材料。在一些實施例中,閘極結構180中的閘極介電層、閘極電極層及其他適合的層藉由原子層沉積、物理氣相沉積(physical vapor deposition, PVD)、化學氣相沉積或其他適合的製程來形成。根據一些實施例,執行平坦化製程以移除形成位於介電層170上方的置換閘極結構180的部分材料。Referring to FIG. 9, according to some embodiments, a replacement gate structure 180 is formed in the gate recess 175. In some embodiments, the replacement gate structure 180 includes a gate dielectric layer, a gate electrode layer, and other suitable layers. In some embodiments, the first gate dielectric layer is a gate dielectric layer included in the replacement gate structure 180. In some embodiments, the gate dielectric layer includes a high-k dielectric material. In some embodiments, the gate electrode layer includes a metal filling layer. In some embodiments, the replacement gate structure 180 includes a conductive work function material layer formed on the gate dielectric layer, and a metal filling layer is formed on the work function material layer. In some embodiments, the work function material layer includes a p-type work function material layer, such as at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , and NiSi 2 , or Other suitable p-type work function materials. In some embodiments, the work function material layer includes an n-type work function metal, such as at least one of Ti, Ag, TiAl, TiAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or other suitable n-type Work function material. In some embodiments, the work function material layer includes a plurality of layers. In some embodiments, the metal filling layer includes tungsten or other suitable materials. In some embodiments, the gate dielectric layer, the gate electrode layer and other suitable layers in the gate structure 180 are deposited by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition or Other suitable processes can be formed. According to some embodiments, a planarization process is performed to remove part of the material forming the replacement gate structure 180 above the dielectric layer 170.
參照第10圖,根據一些實施例,凹蝕置換閘極結構180並且形成蓋層185在置換閘極結構180上方。在一些實施例中,利用蝕刻製程凹蝕置換閘極結構180。在一些實施例中,利用沉積製程形成蓋層185。在一些實施例中,蓋層185包括介電材料。在一些實施例中,蓋層185包括矽和氮,矽和氧,或其他適合材料。在一些實施例中,蓋層185包括與側壁間隔物130相同的材料。參照第11圖,根據一些實施例,接觸開口190形成於介電層170之中以暴露下方的第一半導體材料165的部分。在一些實施例中,形成圖案化蝕刻遮罩以曝光介電層170將要形成接觸開口190的部分。在一些實施例中,利用圖案化蝕刻遮罩執行蝕刻製程,以移除介電層170的部分。Referring to FIG. 10, according to some embodiments, the replacement gate structure 180 is etched back and a cap layer 185 is formed above the replacement gate structure 180. In some embodiments, the gate structure 180 is replaced by etchback by an etching process. In some embodiments, the cap layer 185 is formed using a deposition process. In some embodiments, the cap layer 185 includes a dielectric material. In some embodiments, the capping layer 185 includes silicon and nitrogen, silicon and oxygen, or other suitable materials. In some embodiments, the cap layer 185 includes the same material as the sidewall spacer 130. Referring to FIG. 11, according to some embodiments, a contact opening 190 is formed in the dielectric layer 170 to expose a portion of the first semiconductor material 165 below. In some embodiments, a patterned etching mask is formed to expose a portion of the dielectric layer 170 where the contact opening 190 will be formed. In some embodiments, an etching process is performed using a patterned etching mask to remove portions of the dielectric layer 170.
參照第12圖,根據一些實施例,形成源極/汲極接觸件195於接觸開口190之中。在一些實施例中,執行沉積製程以形成源極/汲極接觸件195。在一些實施例中,源極/汲極接觸件195包括一金屬矽化物。在一些實施例中,源極/汲極接觸件195為線型結構,其在對應於裝置的閘極寬度方向上,基本上在主動區的全長上延伸。在一些實施例中,執行蝕刻製程以凹蝕源極/汲極接觸件195,並執行沉積製程以形成蓋層197於經凹蝕之源極/汲極接觸件195上方。在一些實施例中,蓋層197包括與蓋層185不同的材料。Referring to FIG. 12, according to some embodiments, a source/drain contact 195 is formed in the contact opening 190. In some embodiments, a deposition process is performed to form source/drain contacts 195. In some embodiments, the source/drain contact 195 includes a metal silicide. In some embodiments, the source/drain contact 195 has a linear structure, which extends substantially over the full length of the active region in a direction corresponding to the width of the gate of the device. In some embodiments, an etching process is performed to etch the source/drain contact 195, and a deposition process is performed to form a cap layer 197 over the etched source/drain contact 195. In some embodiments, the cap layer 197 includes a different material from the cap layer 185.
根據一些實施例,形成額外的介電層於介電層170上方,並執行額外的製程以形成接觸件,此接觸件埋置於額外的介電層中、並且接觸置換閘極結構180與源極/汲極接觸件195。在一些實施例中,蓋層185、197的不同材料提供蝕刻選擇性,使被選擇的置換閘極結構180或被選擇的源極/汲極接觸件195暴露,且沒有暴露鄰近的置換閘極結構180或源極/汲極接觸件195以避免形成閘極至源極/汲極的短路(gate-to-source/drain short)。According to some embodiments, an additional dielectric layer is formed over the dielectric layer 170, and an additional process is performed to form a contact, which is buried in the additional dielectric layer, and contacts the replacement gate structure 180 and the source极/drain contact 195. In some embodiments, the different materials of the capping layers 185 and 197 provide etching selectivity, so that the selected replacement gate structure 180 or the selected source/drain contact 195 is exposed without exposing the adjacent replacement gate The structure 180 or the source/drain contact 195 avoids the formation of a gate-to-source/drain short.
根據一些實施例,置換閘極結構180、鰭片110及第一半導體材料165包括電晶體的一部分。介電材料155或應力誘發材料160產生的應力類型取決於電晶體的導電類型。施加壓縮應力於鰭片110的第一部分135,將增加電洞遷移率並且提升P型電晶體的效能。施加拉伸應力於鰭片110的第一部分135,將增加載子遷移率並且提升N型電晶體的效能。According to some embodiments, the replacement gate structure 180, the fin 110, and the first semiconductor material 165 include a part of a transistor. The type of stress generated by the dielectric material 155 or the stress inducing material 160 depends on the conductivity type of the transistor. Applying compressive stress to the first portion 135 of the fin 110 will increase the hole mobility and improve the performance of the P-type transistor. Applying tensile stress to the first portion 135 of the fin 110 will increase the carrier mobility and improve the performance of the N-type transistor.
第13至15圖根據一些實施例繪示在各種製造階段的半導體配置200。第13至第15圖包括一簡化的平面圖,顯示所截取的各種剖面圖。參照第13圖,視圖X-X為從半導體配置200對應於閘極長度方向且穿過鰭片或奈米片所截取的剖面圖,視圖Y1-Y1為從半導體配置200對應於閘極寬度方向且穿過閘極結構的剖面圖,視圖Y2-Y2為從半導體配置200對應於閘極寬度方向且穿過源極/汲極區域的剖面圖。並非每個在剖面圖中顯示的製程步驟都繪示於平面圖中。第13圖中的半導體配置200從繪示於第2圖中的半導體配置100開始。Figures 13-15 illustrate the semiconductor configuration 200 in various manufacturing stages according to some embodiments. Figures 13 to 15 include a simplified plan view showing various cross-sectional views taken. Referring to FIG. 13, view XX is a cross-sectional view taken from the semiconductor configuration 200 corresponding to the gate length direction and through the fin or nanosheet, and views Y1-Y1 are from the semiconductor configuration 200 corresponding to the gate width direction and through A cross-sectional view of the gate structure, views Y2-Y2 are cross-sectional views corresponding to the gate width direction from the semiconductor configuration 200 and passing through the source/drain regions. Not every process step shown in the cross-sectional view is shown in the plan view. The semiconductor configuration 200 in FIG. 13 starts from the semiconductor configuration 100 shown in FIG. 2.
參照第13圖,根據一些實施例,形成第一半導體材料205於凹槽150之中。在一些實施例中,執行第一沉積製程以在凹槽150中形成第一半導體材料205。第一半導體材料205鄰近於鰭片110的第一部分135。在一些實施例中,第一半導體材料205在界面115上方延伸。在一些實施例中,第一半導體材料205的最上層表面高度高於界面115。在一些實施例中,第一半導體材料205從凹槽150的底部至第一半導體材料205上表面的高度202為約10至30奈米。根據一些實施例,第一半導體材料205包括一應力誘發材料,其施加應力在鰭片110之第一部分135。在一些實施例中,第一半導體材料205施加至少約1.5GPa的應力。Referring to FIG. 13, according to some embodiments, the first semiconductor material 205 is formed in the recess 150. In some embodiments, a first deposition process is performed to form the first semiconductor material 205 in the groove 150. The first semiconductor material 205 is adjacent to the first portion 135 of the fin 110. In some embodiments, the first semiconductor material 205 extends above the interface 115. In some embodiments, the uppermost surface of the first semiconductor material 205 is higher than the interface 115. In some embodiments, the height 202 of the first semiconductor material 205 from the bottom of the groove 150 to the upper surface of the first semiconductor material 205 is about 10 to 30 nanometers. According to some embodiments, the first semiconductor material 205 includes a stress-inducing material that applies stress to the first portion 135 of the fin 110. In some embodiments, the first semiconductor material 205 applies a stress of at least about 1.5 GPa.
在一些實施例中,第一半導體材料205包括矽合金。相較於形成半導體層105及鰭片110之材料的晶格常數,矽合金的合金種類影響第一半導體材料205的晶格常數。在一些實施例中,合金種類包括鍺、錫或其他適合的材料,使得第一半導體材料205具有比形成半導體層105及鰭片110的材料還大的晶格常數,且產生壓縮應力在鰭片110的第一部分135。在一些實施例中,第一半導體材料205包括InAs、GaAs、InGaAs或其他適合材料。在一些實施例中,合金種類包括碳或其他適合的材料,使得第一半導體材料205具有比形成半導體層105及鰭片110之材料還小的晶格常數,並且在鰭片110的第一部分135上產生拉伸應力。在一些實施例中,依照元素組成來計算,合金種類濃度介於約20%及60%之間。In some embodiments, the first semiconductor material 205 includes a silicon alloy. Compared with the lattice constant of the material forming the semiconductor layer 105 and the fin 110, the alloy type of the silicon alloy affects the lattice constant of the first semiconductor material 205. In some embodiments, the alloy type includes germanium, tin or other suitable materials, so that the first semiconductor material 205 has a larger lattice constant than the material forming the semiconductor layer 105 and the fin 110, and compressive stress is generated on the fin The first part of 110 135. In some embodiments, the first semiconductor material 205 includes InAs, GaAs, InGaAs, or other suitable materials. In some embodiments, the alloy type includes carbon or other suitable materials, so that the first semiconductor material 205 has a smaller lattice constant than the material forming the semiconductor layer 105 and the fin 110, and the first part 135 of the fin 110 Tensile stress is generated on it. In some embodiments, the alloy species concentration is between about 20% and 60% calculated according to the element composition.
參照第14圖,根據一些實施例,第二半導體材料210形成於第一半導體材料205上方之凹槽150之中。在一些實施例中,執行第二沉積製程以在凹槽150中形成第二半導體材料210。在一些實施例中,沉積製程包括一磊晶成長製程。根據一些實施例,第二半導體材料210定義源/極汲極區域的一部分。在一些實施例中,第二半導體材料210的上表面在鰭片110的上表面上方及隔離結構117的上表面上方延伸。在一些實施例中,第一半導體材料205為無摻雜,第二半導體材料210包括一摻質。在一些實施例中,與第一半導體材料205未延伸至界面115上方的情況相較之下,形成第一半導體材料205並延伸至界面115上方的情況會減少漏電(leakages)。在一些實施例中,第二半導體材料210包括一矽合金。在一些實施例中,第一半導體材料205的矽合金包括與第二半導體材料210相同的矽合金。在一些實施例中,第一半導體材料205中合金種類的濃度和第二半導體材料210中合金種類的濃度不同。在一些實施例中,第一半導體材料205與第二半導體材料210包括矽鍺。Referring to FIG. 14, according to some embodiments, the second semiconductor material 210 is formed in the groove 150 above the first semiconductor material 205. In some embodiments, a second deposition process is performed to form the second semiconductor material 210 in the groove 150. In some embodiments, the deposition process includes an epitaxial growth process. According to some embodiments, the second semiconductor material 210 defines a part of the source/drain region. In some embodiments, the upper surface of the second semiconductor material 210 extends above the upper surface of the fin 110 and the upper surface of the isolation structure 117. In some embodiments, the first semiconductor material 205 is undoped, and the second semiconductor material 210 includes a dopant. In some embodiments, compared with the case where the first semiconductor material 205 does not extend above the interface 115, the case where the first semiconductor material 205 is formed and extends above the interface 115 will reduce leakages. In some embodiments, the second semiconductor material 210 includes a silicon alloy. In some embodiments, the silicon alloy of the first semiconductor material 205 includes the same silicon alloy as the second semiconductor material 210. In some embodiments, the concentration of the alloy species in the first semiconductor material 205 and the concentration of the alloy species in the second semiconductor material 210 are different. In some embodiments, the first semiconductor material 205 and the second semiconductor material 210 include silicon germanium.
參照第15圖,根據一些實施例,形成介電層170於第二半導體材料210之上。在一些實施例中,執行沉積製程以形成介電層170。在一些實施例中,將介電層170平坦化以暴露蓋層125。在一些實施例中,介電層170包括二氧化矽或低介電常數材料。在一些實施例中,介電層170包括一層或多層低介電常數介電材料。低介電常數介電材料的k值(介電常數)低於約3.9。一些低介電常數介電材料的k值低於約3.5,且可能低於約2.5。介電層170的材料包括Si、O、C或H的至少其中一種,像是SiCOH 和 SiOC,或其他適合材料。有機材料(像是聚合物)也可用於介電層170。在一些實施例中,介電層170包括一個或多個層,具有含碳材料、有機矽玻璃、造孔劑(porogen)或上述的組合。在一些實施例中,介電層170也可包含氮。介電層170可藉由,例如,電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、旋轉塗布技術中的至少其中一種方法形成。在一些實施例中,當介電層170藉由電漿輔助化學氣相沉積形成,介電層170在約25°C至約400°C的範圍內的基底溫度以及小於100Torr的壓力下沉積。Referring to FIG. 15, according to some embodiments, a dielectric layer 170 is formed on the second semiconductor material 210. In some embodiments, a deposition process is performed to form the dielectric layer 170. In some embodiments, the dielectric layer 170 is planarized to expose the cap layer 125. In some embodiments, the dielectric layer 170 includes silicon dioxide or a low-k material. In some embodiments, the dielectric layer 170 includes one or more layers of low-k dielectric materials. The k value (dielectric constant) of a low-k dielectric material is less than about 3.9. Some low-k dielectric materials have k values below about 3.5, and possibly below about 2.5. The material of the dielectric layer 170 includes at least one of Si, O, C, or H, such as SiCOH and SiOC, or other suitable materials. Organic materials (such as polymers) can also be used for the dielectric layer 170. In some embodiments, the dielectric layer 170 includes one or more layers with carbon-containing materials, organic silicon glass, porogen, or a combination thereof. In some embodiments, the dielectric layer 170 may also include nitrogen. The dielectric layer 170 can be formed by, for example, at least one method of plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, and spin coating technology. In some embodiments, when the dielectric layer 170 is formed by plasma-assisted chemical vapor deposition, the dielectric layer 170 is deposited at a substrate temperature in the range of about 25° C. to about 400° C. and a pressure less than 100 Torr.
根據一些實施例,於半導體配置200上執行第8至12圖中繪示的製程以移除閘極結構120且形成置換閘極結構180,以形成暴露第一半導體材料165的接觸開口190,且形成源極/汲極接觸件195於接觸開口190之中。在一些實施例中,在額外的介電層中形成額外的接觸件,以接觸置換閘極結構180或源極/汲極接觸件195所選定的部分。According to some embodiments, the process shown in Figures 8 to 12 is performed on the semiconductor configuration 200 to remove the gate structure 120 and form a replacement gate structure 180 to form a contact opening 190 exposing the first semiconductor material 165, and A source/drain contact 195 is formed in the contact opening 190. In some embodiments, an additional contact is formed in the additional dielectric layer to contact the selected portion of the replacement gate structure 180 or the source/drain contact 195.
根據一些實施例,閘極結構120、鰭片110以及第二半導體材料210包括電晶體部分。第一半導體材料205產生的應力類型取決於電晶體的導電類型。施加壓縮應力於鰭片110的第一部分135,將增加電洞遷移率並且提升P型電晶體的效能。施加拉伸應力於鰭片110的第一部分135,將增加載子遷移率並且提升N型電晶體的效能。According to some embodiments, the gate structure 120, the fin 110, and the second semiconductor material 210 include a transistor part. The type of stress generated by the first semiconductor material 205 depends on the conductivity type of the transistor. Applying compressive stress to the first portion 135 of the fin 110 will increase the hole mobility and improve the performance of the P-type transistor. Applying tensile stress to the first portion 135 of the fin 110 will increase the carrier mobility and improve the performance of the N-type transistor.
在一些實施例中,選擇凹槽150的深度154及介電材料155的高度157或第一半導體材料205的高度202以提供足夠量的應力誘發材料。在一些實施例中,若凹槽150的深度太深,鰭片110可能發生彎曲變形(warping)。在一些實施例中,若介電材料155或應力誘發材料160的高度157、或者第一半導體材料205從凹槽150底部算起的高度202太高,則鰭片110中的電阻可能增加,從而降低效能。In some embodiments, the depth 154 of the groove 150 and the height 157 of the dielectric material 155 or the height 202 of the first semiconductor material 205 are selected to provide a sufficient amount of stress inducing material. In some embodiments, if the depth of the groove 150 is too deep, the fin 110 may warping. In some embodiments, if the height 157 of the dielectric material 155 or the stress-inducing material 160, or the height 202 of the first semiconductor material 205 from the bottom of the groove 150 is too high, the resistance in the fin 110 may increase, thereby Reduce efficiency.
根據一些實施例,在延伸至低於鰭片的半導體層中的凹槽中形成應力誘發材料的步驟使得應力施加於電晶體裝置的通道區域。在一些實施例中,應力誘發材料為介電材料。在一些實施例中,應力誘發材料為矽合金材料。According to some embodiments, the step of forming a stress-inducing material in the groove in the semiconductor layer extending below the fin causes stress to be applied to the channel region of the transistor device. In some embodiments, the stress-inducing material is a dielectric material. In some embodiments, the stress inducing material is a silicon alloy material.
在一些實施例中,應力誘發材料產生壓縮應力以增加電洞遷移率。在一些實施例中,應力誘發材料產生拉伸應力以增加電子遷移率。應力誘發材料所產生的應力類型可取決於所使用的應力誘發材料種類。In some embodiments, the stress-inducing material generates compressive stress to increase hole mobility. In some embodiments, the stress-inducing material generates tensile stress to increase electron mobility. The type of stress generated by the stress-inducing material may depend on the type of stress-inducing material used.
在一些實施例中,半導體配置之製造方法包括在半導體層上形成鰭片。形成閘極結構於此鰭片的第一部分上方。移除鰭片鄰近於第一部分之第二部分、以及於鰭片之第二部分下方的半導體層的一部分以定義凹槽。形成應力誘發材料於凹槽中。形成第一半導體材料於凹槽中的應力誘發材料之上,其中第一半導體材料與應力誘發材料不同。In some embodiments, the method of manufacturing a semiconductor configuration includes forming fins on the semiconductor layer. A gate structure is formed above the first part of the fin. The second part of the fin adjacent to the first part and a part of the semiconductor layer under the second part of the fin are removed to define a groove. A stress-inducing material is formed in the groove. A first semiconductor material is formed on the stress inducing material in the groove, wherein the first semiconductor material is different from the stress inducing material.
在一些實施例中,應力誘發材料包括介電材料。在一些例子中,製造半導體配置的方法包括在凹槽中形成應力誘發材料之後,將應力誘發材料退火,以產生拉伸應力。在一些例子中,形成應力誘發材料的步驟包括磊晶成長第二半導體材料。在一些例子中,第一半導體材料包括摻質,且第二半導體材料並不包括摻質。在一些實施例中,第二半導體材料包括矽合金,在一些例子中,此矽合金包括矽,以及鍺或錫的至少其中之一,且應力誘發材料產生壓縮應力。在一些例子中,矽合金包括矽和碳,且應力誘發材料產生拉伸應力。在一些例子中,在半導體層及位於半導體層的上表面之鰭片之間定義界面、並且形成應力誘發材料在凹槽之中的步驟,包括形成應力誘發材料在凹槽中以在界面上方延伸。In some embodiments, the stress-inducing material includes a dielectric material. In some examples, the method of manufacturing the semiconductor configuration includes forming the stress-inducing material in the groove, and then annealing the stress-inducing material to generate tensile stress. In some examples, the step of forming the stress-inducing material includes epitaxial growth of the second semiconductor material. In some examples, the first semiconductor material includes dopants, and the second semiconductor material does not include dopants. In some embodiments, the second semiconductor material includes a silicon alloy. In some examples, the silicon alloy includes silicon and at least one of germanium or tin, and the stress-inducing material generates compressive stress. In some examples, the silicon alloy includes silicon and carbon, and the stress-inducing material generates tensile stress. In some examples, the step of defining an interface between the semiconductor layer and the fin located on the upper surface of the semiconductor layer and forming the stress-inducing material in the groove includes forming the stress-inducing material in the groove to extend above the interface .
在一些實施例中,半導體配置之製造方法包括在半導體層上形成鰭片。移除鰭片之第一部分及半導體層之第一部分以定義第一凹槽。移除鰭片之第二部分及半導體層之第二部分以定義第二凹槽。形成應力誘發材料於第一凹槽及第二凹槽中。形成第一半導體材料於第一凹槽及第二凹槽中的應力誘發材料之上。第一半導體材料與應力誘發材料不同。第一凹槽中之第一半導體材料定義一第一源極/汲極區域。第二凹槽中之第一半導體材料定義第二源極/汲極區域。In some embodiments, the method of manufacturing a semiconductor configuration includes forming fins on the semiconductor layer. The first part of the fin and the first part of the semiconductor layer are removed to define the first groove. The second part of the fin and the second part of the semiconductor layer are removed to define a second groove. A stress inducing material is formed in the first groove and the second groove. A first semiconductor material is formed on the stress inducing material in the first groove and the second groove. The first semiconductor material is different from the stress inducing material. The first semiconductor material in the first recess defines a first source/drain region. The first semiconductor material in the second recess defines the second source/drain region.
在一些實施例中,半導體配置的製造方法包括在移除鰭片之第一部分及移除鰭片之第二部分之前,先形成閘極結構於鰭片的第三部份之上。在一些實施例中,半導體配置的製造方法包括將應力誘發材料退火以減少應力誘發材料之體積。在一些例子中,將應力誘發材料退火的步驟包括在形成第一半導體材料之前,將應力誘發材料退火。在一些實施例中,形成應力誘發材料的步驟包括磊晶成長第二半導體材料。在一些例子中,第二半導體材料包括矽,以及鍺、錫或碳中的至少一種。在一些情況下,應力誘發材料包括介電材料。In some embodiments, the manufacturing method of the semiconductor configuration includes forming a gate structure on the third part of the fin before removing the first part of the fin and the second part of the fin. In some embodiments, the method of manufacturing the semiconductor device includes annealing the stress-inducing material to reduce the volume of the stress-inducing material. In some examples, the step of annealing the stress-inducing material includes annealing the stress-inducing material before forming the first semiconductor material. In some embodiments, the step of forming the stress-inducing material includes epitaxial growth of the second semiconductor material. In some examples, the second semiconductor material includes silicon and at least one of germanium, tin, or carbon. In some cases, the stress-inducing material includes a dielectric material.
在一些實施例中,半導體配置包括位於半導體層之上的鰭片。位於鰭片的一部分及半導體層的一部分之上的閘極結構。鄰近於鰭片之部分以及半導體層之部分的應力誘發材料。第一半導體材料鄰近於鰭片之部分且於應力誘發材料之上,其中,第一半導體材料與應力誘發材料不同。In some embodiments, the semiconductor configuration includes fins on the semiconductor layer. A gate structure located on a part of the fin and a part of the semiconductor layer. The stress-inducing material adjacent to the part of the fin and the part of the semiconductor layer. The first semiconductor material is adjacent to the part of the fin and above the stress inducing material, wherein the first semiconductor material is different from the stress inducing material.
在一些實施例中,應力誘發材料包括介電材料。在一些例子中,應力誘發材料包括矽合金。在一些實施例中,一界面定義於半導體層及位於半導體層之上表面的鰭片之間,且應力誘發材料之頂面在此界面之上。In some embodiments, the stress-inducing material includes a dielectric material. In some examples, the stress-inducing material includes silicon alloy. In some embodiments, an interface is defined between the semiconductor layer and the fin on the upper surface of the semiconductor layer, and the top surface of the stress-inducing material is above the interface.
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及∕或優勢。在本發明所屬技術領域中具有通常知識者也應理解到,此類等效的製程和結構並無悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍之下,做各式各樣的改變、取代和替換。The components of several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can more easily understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.
雖然專利標的以特定的結構特徵或方法動作描述,應理解的是,附加的所請專利標的不限於上述的特定特徵或動作。反而,上述的特定特徵或動作係做為實施至少一些申請專利範圍的實施例形式。Although the patented subject matter is described in terms of specific structural features or method actions, it should be understood that the additional claimed patent subject matter is not limited to the specific features or actions described above. Instead, the above-mentioned specific features or actions are taken as an embodiment form implementing at least some of the scope of the patent application.
在此提供實施例的各種操作。此處所描述的一些或全部的操作順序並非暗示這些操作必定取決於順序。可理解替代的順序具有此敘述的好處。此外,可理解並非所有的操作在本文提供的每一個實施例中都是必要的。並且,可理解在一些實施例中,並非所有的操作都是必要的。Various operations of the embodiment are provided here. The order of some or all of the operations described here does not imply that these operations necessarily depend on the order. It is understood that the order of substitution has the benefit of this description. In addition, it is understood that not all operations are necessary in every embodiment provided herein. And, it can be understood that in some embodiments, not all operations are necessary.
可理解的是,此處所描述的層、特徵、元件等以相對於彼此的特定尺寸顯示,像是結構尺寸或方位,例如,在一些實施例中,為了簡化及易於了解的目的,其實際尺寸基本上不同於此處所繪示。此外,此處所提及的各種用以形成層、區域、特徵、元件等的技術,像是蝕刻技術、平坦化技術、佈植技術、摻雜(doping)技術、旋轉塗布技術、濺擊(sputtering)技術、生長(growth)技術、或是沉積技術,例如化學氣相沉積。It is understandable that the layers, features, elements, etc. described herein are displayed in specific dimensions relative to each other, such as structural dimensions or orientations. For example, in some embodiments, the actual dimensions are for simplicity and ease of understanding. Basically different from what is shown here. In addition, the various technologies mentioned here to form layers, regions, features, components, etc., such as etching technology, planarization technology, implantation technology, doping technology, spin coating technology, sputtering ( sputtering technology, growth technology, or deposition technology, such as chemical vapor deposition.
此外,此處使用「實施例(exemplary)」代表做為一實例(example)、例子(instance)、例證(illustration)等,且不一定為優選的。在本發明使用的「或(or)」是為了表達包容性的「或」而不是排他性的「或」。此外,除非特別說明,或者內文已清楚指示為單數形式,否則本發明中使用的「一(a) 」或「一(an) 」以及附加的申請專利範圍被視為代表「一或多個」。還有, A及B中的至少一個及∕或其類似用語一般代表A或B,或者A和B兩者。此外,在使用「包括(includes)」、「具有(having) 」、「具有(has) 」、「具有(with) 」、或其變化的範圍中,這樣的用語被用來代表與用語「包括(comprising) 」類似的包容性。還有,除非特別說明,「第一」、「第二」或類似的用語並非用來暗示時間概念、空間概念及順序等。反而,這些用詞僅用以做為特徵、元件、項目等的辨識符號、名稱等。例如,第一元件和第二元件一般對應至元件A和元件B或兩個不同或兩個完全相同的(identical)元件或相同的元件。In addition, "exemplary" is used here to represent an example, instance, illustration, etc., and is not necessarily preferred. The "or" used in the present invention is to express an inclusive "or" rather than an exclusive "or". In addition, unless otherwise specified, or the content has clearly indicated that it is in the singular form, the "一(a)" or "一(an)" used in the present invention and the additional scope of patent application are deemed to represent "one or more ". Also, at least one of A and B and/or similar terms generally represent A or B, or both A and B. In addition, in the use of "includes", "having", "has", "with", or variations thereof, such terms are used to represent the same (comprising) "Similar inclusiveness. Also, unless otherwise specified, "first", "second" or similar terms are not used to imply the concept of time, space, order, etc. Instead, these terms are only used as identifying symbols, names, etc. for features, elements, items, etc. For example, the first element and the second element generally correspond to the element A and the element B or two different or two identical elements or the same element.
還有,雖然已以一個或多個實施例顯示或描述本發明,其他所屬技術領域中具有通常知識者可基於閱讀或了解本說明書及所附的圖式進行相當的替代或修飾。本發明包括所有這類的修飾及替代且僅受限於以下的申請專利範圍。特別是關於上述元件(例如:元件、資源等)所表現的各種功能,除非特別說明,否則描述這種元件的用語是用來對應至表現所述元件的特定功能的任何元件(例如:功能相當),即使在結構上並未等同於所揭露結構。此外,雖然本發明僅以數個實施例中的其中一實施例揭露特定元件,當受期望或對任何給定或特定的發明有利時,這種特徵可與其他實施例的一或多個其他特徵結合。Also, although the present invention has been shown or described in one or more embodiments, those with ordinary knowledge in other technical fields can make equivalent substitutions or modifications based on reading or understanding this specification and the accompanying drawings. The present invention includes all such modifications and substitutions and is only limited to the scope of the following patent applications. Especially with regard to the various functions performed by the above-mentioned elements (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe such elements are used to correspond to any element that performs the specific function of the element (e.g., equivalent in function) ), even if the structure is not equivalent to the disclosed structure. In addition, although the present invention uses only one of several embodiments to disclose a specific element, when desired or beneficial to any given or specific invention, this feature can be combined with one or more other embodiments of other embodiments. Feature combination.
100、200:半導體配置 105:半導體層 110:鰭片 115:界面 117:隔離結構 120:閘極結構 125、185、197:蓋層 130:側壁間隔物 135:鰭片110之第一部分與半導體層105之第一部分 136:寬度 137:間隔 138、157、202:高度 140:鰭片110之第二部分 145:半導體層105之部分 150:凹槽 152、154:深度 155:介電材料 158:退火製程 160:應力誘發材料 165、205:第一半導體材料 170:介電層 175:閘極凹孔 180:置換閘極結構 190:接觸開口 195:源極/汲極接觸件 210:第二半導體材料 X、Y1、Y2:剖面圖擷取方向100, 200: Semiconductor configuration 105: semiconductor layer 110: Fins 115: interface 117: Isolation structure 120: gate structure 125, 185, 197: cover layer 130: sidewall spacer 135: The first part of the fin 110 and the first part of the semiconductor layer 105 136: width 137: Interval 138, 157, 202: height 140: The second part of fin 110 145: Part of the semiconductor layer 105 150: Groove 152, 154: depth 155: Dielectric materials 158: Annealing process 160: Stress-inducing materials 165, 205: The first semiconductor material 170: Dielectric layer 175: Gate hole 180: replacement gate structure 190: contact opening 195: source/drain contacts 210: second semiconductor material X, Y1, Y2: the direction of section view capture
以下將配合所附圖式詳述本發明實施例。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製且僅用以說明例示。事實上,可能任意地放大或縮小元件的尺寸,以清楚地表現出本發明實施例的特徵。 第1圖至第12圖是根據一些實施例所繪示之各個製造階段的半導體配置。 第13圖至第15圖是根據一些實施例所繪示之各個製造階段的半導體配置。The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention. Figures 1 to 12 show the semiconductor configuration at various manufacturing stages according to some embodiments. Figures 13 to 15 illustrate the semiconductor configuration at various manufacturing stages according to some embodiments.
100:半導體配置 100: Semiconductor configuration
105:半導體層 105: semiconductor layer
110:鰭片 110: Fins
115:界面 115: interface
117:隔離結構 117: Isolation structure
130:側壁間隔物 130: sidewall spacer
135:鰭片110之第一部分與半導體層105之第一部分 135: The first part of the fin 110 and the first part of the semiconductor layer 105
137:間隔 137: Interval
145:半導體層105之部分 145: Part of the semiconductor layer 105
160:應力誘發材料 160: Stress-inducing materials
165:第一半導體材料 165: The first semiconductor material
180:置換閘極結構 180: replacement gate structure
185、197:蓋層 185, 197: cover layer
190:接觸開口 190: contact opening
195:源極/汲極接觸件 195: source/drain contacts
X、Y1、Y2:剖面圖擷取方向 X, Y1, Y2: the direction of section view capture

Claims (1)

  1. 一種半導體配置之製造方法,包括: 形成一鰭片於一半導體層之上; 形成一閘極結構於該鰭片的一第一部分之上; 移除該鰭片鄰近於該第一部分之一第二部分、以及於該鰭片之該第二部分下方的該半導體層的一部分以定義一凹槽; 形成一應力誘發材料於該凹槽中;以及 形成一第一半導體材料於該凹槽中的該應力誘發材料之上,其中該第一半導體材料與該應力誘發材料不同。A manufacturing method of semiconductor configuration, including: Forming a fin on a semiconductor layer; Forming a gate structure on a first part of the fin; Removing a second part of the fin adjacent to the first part and a part of the semiconductor layer under the second part of the fin to define a groove; Forming a stress inducing material in the groove; and A first semiconductor material is formed on the stress inducing material in the groove, wherein the first semiconductor material is different from the stress inducing material.
TW108138973A 2018-10-31 2019-10-29 Method of manufacturing semiconductor arrangement TW202029509A (en)

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