TW202013194A - Method for performing adaptive locking range management, and associated data storage device and controller thereof - Google Patents

Abstract

A method for performing adaptive locking range management, an associated data storage device and the controller thereof are provided. The method may include:receiving a security command from outside of the data storage device, wherein the security command is related to changing an old locking range into a new locking range; obtaining a start Logical Block Address (LBA) and a length value of the new locking range according to the security command; determining whether the start LBA of the new locking range is less than an end LBA of the old locking range, and determining whether the end LBA of the new locking range is greater than a start LBA of the old locking range; and in response to both determination results being true, performing data trimming on any respective non-overlapped portions of the new locking range and the old locking range.

Description

Method and data storage device and controller for adaptive lock range management

The present invention relates to the access of flash memory, especially a method for adaptive locking range management and related data storage device and its controller.

Flash memory can be widely used in various portable or non-portable data storage devices (for example: memory cards that comply with SD/MMC, CF, MS, XD or UFS standards; for example: solid-state hard drives; for example : Embedded storage devices that meet UFS or EMMC specifications). In terms of commonly used NAND flash memory, there are initially single-level cells (SLC), multiple-level cells (MLC) and other types of flash memory. Due to the continuous development of memory technology, newer data storage device products can use triple level cell (TLC) flash memory, or even quadruple level cell (QLC) flash memory. In order to ensure that the data storage device's access control to the flash memory can meet the relevant specifications, the controller of the flash memory is usually equipped with certain management mechanisms to properly manage its internal operations.

According to related technologies, the data storage devices with these management mechanisms still have deficiencies. For example, when a manufacturer attempts to implement a data storage device to comply with certain specifications regarding data encryption, related operations may need to be modified, which may cause some parts of these management mechanisms to become more complicated. As a result, the overall performance of the data storage device may be reduced. Therefore, there is a need for a novel method and related architecture to implement a data storage device with a reliable management mechanism without side effects or less likely to cause side effects.

An object of the present invention is to provide a method for adaptive lock range management and related data storage device and its controller to solve the above problems.

Another object of the present invention is to provide a method for adaptive lock range management and related data storage devices and their controllers to confer reliable management mechanisms without side effects or less likely to cause side effects Data storage device.

At least one embodiment of the present invention provides a method for adaptive lock range management, wherein the method is applied to a data storage device including a non-volatile memory (NV memory ), and the non-volatile memory includes at least one non-volatile memory element (NV memory element). The method may include: receiving a security command from outside the data storage device, wherein the security command is about changing an old locking range (Locking Range) to a new locking range; obtaining the new lock according to the security command A starting logical block address (LBA) and a length value of the range, where an ending logical block address of the new locked range is the starting logical block address of the new locked range and the The sum of the length values; determine whether the start logical block address of the new lock range is less than an end logical block address of the old lock range, and determine whether the end logical block address of the new lock range is greater than A starting logical block address of the old locking range; and the starting logical block address corresponding to the new locking range is smaller than the ending logical block address of the old locking range and the ending logic of the new locking range The block address is greater than a starting logical block address of the old lock range, and data trimming is performed on the new lock range and the portion of the old lock range that does not overlap.

At least one embodiment of the present invention provides a data storage device, which may include: a non-volatile memory for storing information, wherein the non-volatile memory includes at least one non-volatile memory element; and a controller, The non-volatile memory is coupled to control the operation of the data storage device. The controller may include a processing circuit, and the processing circuit may control the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller body. For example: the controller receives a security command from the host, where the security command is about changing an old lock range to a new lock range; the controller obtains a starting logical block bit of the new lock range according to the security command Address (LBA) and a length value, where an end logical block address of the new lock range is the sum of the start logical block address of the new lock range and the length value; the controller determines the new lock Whether the starting logical block address of the range is less than an ending logical block address of the old locking range, and it is determined whether the ending logical block address of the new locking range is greater than a starting logical area of the old locking range Block address; and the starting logical block address corresponding to the new locked range is less than the ending logical block address of the old locking range and the ending logical block address of the new locking range is greater than the old locking range A starting logical block address, the controller performs data pruning on the new locked range and the portion of the old locked range that does not overlap.

At least one embodiment of the present invention provides a controller for a data storage device, wherein the data storage device includes the controller and a non-volatile memory, and the non-volatile memory includes at least one non-volatile memory element. The controller may include a processing circuit, and the processing circuit may control the controller according to a plurality of host commands from a host to allow the host to access the non-volatile memory through the controller. For example: the controller receives a security command from the host, where the security command is about changing an old lock range to a new lock range; the controller obtains a starting logical block bit of the new lock range according to the security command Address (LBA) and a length value, where an end logical block address of the new lock range is the sum of the start logical block address of the new lock range and the length value; the controller determines the new lock Whether the starting logical block address of the range is less than an ending logical block address of the old locking range, and it is determined whether the ending logical block address of the new locking range is greater than a starting logical area of the old locking range Block address; and the starting logical block address corresponding to the new locked range is less than the ending logical block address of the old locking range and the ending logical block address of the new locking range is greater than the old locking range A starting logical block address, the controller performs data pruning on the new locked range and the portion of the old locked range that does not overlap.

One of the advantages of the present invention is that, through a carefully designed management mechanism, the present invention can properly control the operation of the controller, and in particular, can implement a data encryption architecture that meets certain specifications without degrading the overall performance. In addition, implementation according to the embodiments of the present invention does not increase many additional costs. Therefore, the problems of the related art can be solved without increasing the overall cost much. Compared with the traditional architecture, the present invention can achieve the optimized performance of the data storage device without side effects or less likely to cause side effects.

Please refer to FIG. 1, which is a schematic diagram of a data storage device 100 and a host device 50 according to a first embodiment of the present invention. For example, the data storage device 100 may be a solid state drive (SSD). In addition, examples of the host 50 may include (but are not limited to): multifunctional mobile phones, tablet computers, and personal computers such as desktop computers and laptop computers. According to this embodiment, the data storage device 100 may include a controller such as a memory controller 110, and may further include a non-volatile memory (NV memory) 120, wherein the controller is used to store The non-volatile memory 120 is accessed, and the non-volatile memory 120 is used to store information.

The non-volatile memory 120 may include a plurality of non-volatile memory elements (NV memory elements) 122-1, 122-2, ..., and 122-N, where the symbol "N" may represent a positive integer greater than one. For example, the non-volatile memory 120 may be a flash memory, and the non-volatile memory elements 122-1, 122-2, ..., and 122-N may be a plurality of flash memory chips, respectively. (Flash memory chip; may be referred to as flash chip) or a plurality of flash memory die (Flash memory die; may be referred to as flash die), but the invention is not limited thereto. In addition, the data storage device 100 may further include a volatile memory element to cache data, wherein the volatile memory element is preferably a dynamic random access memory (Dynamic Random Access Memory, DRAM for short). Volatile memory components can provide appropriate data temporary storage space to cache data, or only provide a small amount of data temporary storage space to cache small amounts of data.

The memory controller 110 may include a processing circuit such as a microprocessor 112, a storage such as a read-only memory (Read Only Memory, ROM) 112M, a control logic circuit 114, a buffer memory 116, and a transmission interface circuit 118, of which The components can be coupled to each other through a bus bar. The buffer memory 116 is preferably a static random access memory (Static Random Access Memory, SRAM for short). For example, if the data storage device 100 is further configured with dynamic random access memory (Dynamic Random Access Memory, DRAM for short), the memory controller 110 may use the buffer memory 116 as a first-level cache, and Use DRAM as the second layer cache. The data storage capacity of the DRAM is preferably greater than the data storage capacity of the buffer memory 116, and the data buffered by the DRAM comes from the buffer memory 116 or the non-volatile memory 120.

The read-only memory 112M of this embodiment is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the non-volatile memory 120. Please note that the code 112C must also be stored in the buffer memory 116 or any form of memory. In addition, the control logic circuit 114 may include an error correction code circuit (not shown) to protect data and/or perform error correction, and the transmission interface circuit 118 may comply with a specific communication standard (such as Serial Advanced Technology Attachment (Serial Advanced Technology Attachment) Technology Attachment (SATA) standard, Peripheral Component Interconnect Express (PCIE) standard or Non-Volatile Memory Express (NVME) standard) and can communicate according to the specific communication standard.

In this embodiment, the host 50 can access the non-volatile memory 120 (eg, read or write) by sending a plurality of host commands to the data storage device 100 through the memory controller 110 For data, in particular, to access data (or user data) stored in the non-volatile memory 120 in the data storage device 100, the host command includes a logical address, such as a logical block address (Logical Block Address, abbreviated as LBA). The memory controller 110 receives host commands and translates the host commands into memory operation commands (abbreviated as operation commands), and then controls the non-volatile memory 120 with the operation commands to read, write/program A page with a specific physical address in the volatile memory 120. The memory controller 110 records the mapping relationship between the logical address of the data and the physical address in a logical-to-physical address mapping table ("L2P table" for short), where the physical bit The address can be composed of channel (Channel) number, logical unit number (Logical Unit Number, LUN), plane (Plane) number, block number, page number, and offset (Offset). In some embodiments, the implementation of the physical address may be changed. For example, the physical address may include channel number, logical unit number, plane number, block number, page number, and/or offset.

The L2P table can be stored in one of the management tables in the non-volatile memory 120, and can be divided into multiple groups (Group), and the memory controller 110 can divide the multiple according to the size of the buffer memory 116 One or all of the groups are loaded from the non-volatile memory 120 into the buffer memory 116 as a temporary L2P table for quick reference, but the invention is not limited thereto. When the user data is updated, the memory controller 110 may update the temporary L2P table and/or the L2P table in the management table according to the latest mapping relationship of the user data. The size of one group of the L2P table is preferably equal to the size of one page of the non-volatile memory element 122-n, for example 16KB, where the symbol "n" can represent any integer in the interval [1, N] . For another example, the size of one group of the L2P table in the management table may be equal to the size of one page of multiple non-volatile memory elements 122, for example, in the case of N=4, four non-volatile The size of one page of the sexual memory element 122 is 64KB, and the pages of the four non-volatile memory elements 122 may also be referred to as super pages.

For the host 50, the storage space available in the data storage device 100 can be accessed through a series of LBAs. For ease of understanding, it is assumed that the host 50 is full of data in the data storage device 100. In this case, each document has a unique LBA. For example, the series of LBAs may contain a predetermined number of LBAs, and the values of these LBAs fall within the range from LBA#0 to LBA#Max, where Max is a positive integer. The range from LBA#0 to LBA#Max can be called the Global Range. The host 50 can set the types of global access rights, for example, normal, read-locked (Read-Locked), write-locked (Write-Locked), and so on. In addition, the value of LBA may be continuous or discontinuous, and the starting value of LBA may be 0 or any positive integer.

Data can be divided into accessible data and restricted access data. For restricting access to data, the host 50 may create one or more locking ranges (Locking Range) in the global range and set the types of access rights for the one or more locking ranges, for example, normal, read-lock (Read- Locked), Write-Locked, etc. For example, the one or more locking ranges may include a plurality of locking ranges, such as locking range #0, locking range #1, and locking range #2 shown in FIG. 2. After that, the host 50 can set the user's access right to restrict access to the data according to the user-related information (such as user identity, user group, etc.).

For the data in the locked range, the host 50 preferably instructs the data storage device 100 to encrypt the data into a ciphertext (Ciphertext) using a key, or directly encrypt the data into a ciphertext using the key, and then store the ciphertext to the data存装置100。 Storage device 100. Assuming that the global access authority is normal, the data in the lock scope #0 is encrypted with the key #0, and the access authority is read lock. When an unauthorized user wants to read the data in the locked range #0 through the host 50, the data storage device 100 returns a return message (such as data access error or data protection) to the host 50. The data in the lock range #1 is preferably encrypted with the key #1, or still encrypted with the key #0, and the access authority is write lock. When an unauthorized user wants to update or write data in the locked range #1 through the host 50, the data storage device 100 returns a return message (such as data access error or data protection) to the host 50. In addition, the key #0 and the key #1 are preferably encrypted with the key #2 into a ciphertext to protect the key #0 and the key #1. In addition, encryption or decryption is preferably performed by the memory controller 110 of the data storage device 100.

The host 50 can output a security command or a trusted command to the data storage device 100 (especially, the memory controller 110) to adjust or set the lock range. When the lock range is changed, the data that is not in the (new) lock range must be trimmed (Trim) to protect the confidentiality of the data in the original lock range, and the data in the new lock range must also be trimmed. Since the lock range affects the user's right to access data, after the lock range is adjusted or set, how to quickly make the (new) lock range take effect and quickly complete data trimming has become an important technical issue.

At least one embodiment of the present invention discloses a method for adaptive lock range management. This method can be applied to the data storage device 100 and is executed by the memory controller 110 of the data storage device 100, and can be quickly enabled ( New) The locking scope is in effect, for example, through its efficient workflow, as shown in Figure 3. In addition, for the sake of brief description, the global access rights are assumed to be normal, and the data storage device 100 already has (old) lock range #0~#2, for example: (old) lock range #0 has a starting LBA such as LBA #A, and has an end LBA such as LBA#B, and its access authority is read lock; (old) lock range #1 has a start LBA such as LBA#C, and has an end LBA such as LBA#D, and Its access right is write lock; and (old) lock range #2 has a start LBA such as LBA#E and an end LBA such as LBA#F, and the access right is read lock.

In step S12, the memory controller 110 receives a security command from the outside. According to this embodiment, the memory controller 110 can receive multiple security commands (such as those transmitted by the host 50) from outside the data storage device 100, and the workflow shown in FIG. 3 can be executed multiple times to target The multiple security commands perform corresponding operations, where the security commands may indicate that the host 50 requires the memory controller 110 to update or change the corresponding lock range of the plurality of lock ranges. The corresponding lock range may include lock range #0, lock range #1, and lock range #2 shown in FIG. 2. The memory controller 110 can change the lock range #0, the lock range #1 and the lock range #2 according to these security instructions, in particular, from the original version or the old version of the lock range #0, the lock range #1 and the lock range #2 The version (marked as "(old)" in Figure 4) is changed to the new version of lock range #0, lock range #1, and lock range #2 (marked as "(new)" in Figure 4) .

In step S14, the memory controller 110 obtains the lock range number, starting LBA, and length value of the (new) lock range according to the security command. The security command may further include the access permission of the (new) lock range. For example, among the multiple security instructions, the first security instruction states that for (new) lock range #0, the start LBA is LBA#A', the end LBA is LBA#B', and the access authority is read locking. The second security instruction states that for (new) lock range #1, the start LBA is LBA#C’, the end LBA is LBA#D’, and the access authority is write lock. The third security instruction states that for (new) lock range #2, the start LBA is LBA#E’ and the end LBA is LBA#F’, and the access authority is read lock, as shown in Figure 4. For any of these locking ranges, the memory controller 110 may determine the ending LBA according to its starting LBA and length value, where the ending LBA value is the starting LBA value plus the length value. The memory controller 110 may use the sum of the start LBA and the length value as the end LBA.

In step S16, the memory controller 110 determines whether the start LBA of the (new) lock range is smaller than the end LBA of the (old) lock range? If it is correct (that is, the judgment result is "True"), then step S18 is performed, if it is not correct (that is, the judgment result is "False"), then step S20 is performed. When judging (new) lock range #0, since LBA#A' is smaller than LBA#B, execute step S18; when judging (new) lock range #1, since LBA#C' is smaller than LBA#D, execute step S18; when it is judged that the (new) lock range #2, since LBA#E' is smaller than LBA#F, step S18 is executed.

In step S18, the memory controller 110 determines whether the end LBA of the (new) lock range is greater than the start LBA of the (old) lock range? If it is correct (that is, the judgment result is "true"), then step S22 is executed, if it is not correct (that is, the judgment result is "false"), then step S20 is executed. When judging (new) locking range #0, since LBA#B' is greater than LBA#A, it means that (old) locking range #0 and (new) locking range #0 have some overlapping overlapping ranges, so execute Step S22; when it is judged that the (new) lock range #1, since LBA#D' is greater than LBA#C, it means that the (old) lock range #1 and the (new) lock range #1 overlap partially, so execute Step S22; when it is judged that (new) lock range #2, since LBA#F' is less than LBA#E, it means that (old) lock range #2 and (new) lock range #2 do not overlap at all, so step S20 is executed.

In step S20, the memory controller 110 performs data trimming on the (new) locked range and the (old) locked range, respectively. Taking lock range #2 as an example, since (new) lock range #2 and (old) lock range #2 do not overlap at all, memory controller 110 pairs (new) lock range #2, that is, LBA#E'~ F', and (old) lock range #2, namely LBA#E~F, perform data pruning separately.

In step S22, the memory controller 110 performs data pruning on the (new) locked range and the portion of the (old) non-overlapping locking range, where the non-overlapping part includes the (new) locked range of the (new) locked range Any part of the overlap and any part of the (old) locked range that is not overlapped by the (new) locked range. Taking lock range #0 as an example, the non-overlapping parts are LBA#A to LBA#A' and LBA#B' to LBA#B, where the value of LBA#A is less than LBA#A' and LBA#B' Is smaller than LBA#B, therefore, the memory controller 110 performs data pruning on LBA#A~A' and LBA#B'~B, respectively. Taking lock range #1 as an example, the non-overlapping parts are LBA#C' to LBA#C and LBA#D' to LBA#D, where the value of LBA#C' is less than LBA#C and LBA#D' The value of is smaller than LBA#D, therefore, the memory controller 110 performs data pruning on LBA#C'~C and LBA#D'~D, respectively.

For a better understanding, the method can be illustrated by the workflow shown in FIG. 3, but the present invention is not limited to this. According to some embodiments, one or more steps may be added, deleted, or modified in the workflow shown in FIG. 3. For example, for any of step S16 and step S18, if the judgment result is "false", then step S20 is executed, which means that in the workflow shown in FIG. 3, step S16 and step are executed The order of S18 can be reversed without affecting the correctness of performing step S20 or step S22. According to an embodiment, such a change may be adopted. In particular, after step S14 is performed, step S18 is performed; if the judgment result of step S18 is "true", then step S16 is performed; if the judgment result of step S18 is "false", then step S20 is performed; if the judgment result of step S16 If it is "true", then step S22 is executed; and if the judgment result of step S16 is "false", then step S20 is executed. For the sake of simplicity, the content of this embodiment that is similar to the foregoing embodiment will not be repeated here.

FIG. 5 is a schematic diagram of an adaptive locking range management method according to an embodiment of the present invention. FIG. 5 can be regarded as a simplified version of FIG. 3 and can be used to illustrate the advantages of the adaptive locking range management method of the present invention. First, the memory controller 110 first determines whether the (new) lock range and the (old) lock range overlap, as shown in steps S16 to S18. If the result of the judgment is that there is no overlap, data pruning is performed on the (new) lock range and the (old) lock range, as shown in step S20. If the result of the judgment is that there is overlap, data trimming is performed only on the non-overlapped parts, as shown in step S22. Since the adaptive locking range management method of the present invention is easy to implement, the change of the locking range can be quickly implemented and effective, and the purpose of the present invention is achieved.

In addition, when the host 50 sets the lock range, if the lock ranges of different lock range numbers overlap, the memory controller 110 directly returns a return message such as an invalid command back to the host 50 without data trimming; if different If the lock ranges of the access rights overlap, the memory controller 110 will also directly return a return message such as an invalid command to the host 50.

After the host 50 outputs a security command and the memory controller 110 completes the method for adaptive lock range management of the present invention, the update of the lock range has been completed. After that, the host 50 can output a host command to access the data of the data storage device 100. If the LBA of the data to be accessed is not within the lock range, the data storage device 100 can return the data to the host 50; if the When the LBA of the data is placed in any locking range, the data storage device 100 can return a return message (such as data access error or data protection) to the host 50. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

50: host 100: data storage device 110: memory controller 112: Microprocessor 112C: Code 112M: read-only memory 114: control logic circuit 116: Buffer memory 118: Transmission interface circuit 120: Non-volatile memory 122, 122-1, 122-2, ..., 122-N: non-volatile memory device LBA#0, LBA#Max, LBA#A, LBA#B, LBA#C, LBA#D, LBA#E, LBA#F, LBA#A', LBA#B', LBA#C', LBA#D ', LBA#E', LBA#F': logical block address S12, S14, S16, S18, S20, S22: steps

FIG. 1 is a schematic diagram of a data storage device and a host device according to an embodiment of the invention. Figure 2 shows an example of a global range (Global Range) and multiple locking ranges (Locking Range). FIG. 3 is a workflow of a method for adaptive lock range management according to an embodiment of the invention. FIG. 4 illustrates a locking range update scheme of the method according to an embodiment of the invention. FIG. 5 is a schematic diagram of an adaptive locking range management method according to an embodiment of the present invention.

S12, S14, S16, S18, S20, S22: steps

Claims (20)

A method for adaptive lock range management, the method is applied to a data storage device, the data storage device includes a non-volatile memory (non-volatile memory (NV memory), the non-volatile memory includes at least A non-volatile memory element (NV memory element), the method includes: Receive a security command from outside the data storage device, where the security command is about changing an old locking range (Locking Range) to a new locking range; Obtain a starting logical block address (LBA) and a length value of the new locking range according to the security command, wherein an ending logical block address of the new locking range is the starting of the new locking range The sum of the starting logical block address and the length value; Determine whether the start logical block address of the new lock range is less than an end logical block address of the old lock range, and determine whether the end logical block address of the new lock range is greater than the old lock range A starting logical block address; and The starting logical block address corresponding to the new locking range is smaller than the ending logical block address of the old locking range and the ending logical block address of the new locking range is greater than a starting logical area of the old locking range Block address, perform data trimming (Data Trimming) on the new locked range and the part of the old locked range that does not overlap. The high-efficiency garbage collection method as described in item 1 of the patent application scope, which additionally includes Receiving another security command from outside the data storage device, where the other security command is about changing another old lock range to another new lock range; Obtaining a starting logical block address and a length value of the other new locking range according to the another security command, wherein an ending logical block address of the other new locking range is the other of the new locking range The sum of the starting logical block address and the length value; Determine whether the address of the starting logical block of the other new locked range is less than the address of an end logical block of the other old locked range; In response to the start logical block address of another new locked range being smaller than the end logical block address of the other old locked range, it is determined whether the end logical block address of the other new locked range is greater than the A starting logical block address of another old locked range; and In response to that the end logical block address of another new locked range is not greater than the start logical block address of the other old locked range, data pruning is performed on the other new locked range and the other old locked range, respectively . The high-efficiency garbage collection method as described in item 2 of the scope of patent application, which additionally includes: Receiving another security command from outside the data storage device, wherein the further security command is about changing another old lock range to another new lock range; Obtaining a starting logical block address and a length value of the further new locking range according to the further security command, wherein an ending logical block address of the further new locking range is the The sum of the starting logical block address and the length value; Judging whether the address of the starting logical block of the further new locked range is smaller than the address of an ending logical block of the further old locking range; and Since the address of the starting logical block of the new lock range is not less than the address of the ending logical block of the old lock range, the data is executed for the new lock range and the old lock range respectively prune. The high-efficiency garbage collection method as described in item 3 of the patent application scope, wherein the old lock range overlaps with the new lock range, and the other new lock range and the other old lock range do not overlap at all, And the another new lock range and the another old lock range do not overlap at all. A high-efficiency garbage collection method as described in item 2 of the patent application scope, wherein the old lock range overlaps with the new lock range, and the other new lock range and the other old lock range do not overlap at all . The high-efficiency garbage collection method as described in item 1 of the patent application scope, in which the old lock scope overlaps with the new lock scope. The high-efficiency garbage collection method as described in item 1 of the patent application scope, which additionally includes Receiving another security command from outside the data storage device, where the other security command is about changing another old lock range to another new lock range; Obtaining a starting logical block address and a length value of the other new locking range according to the another security command, wherein an ending logical block address of the other new locking range is the other of the new locking range The sum of the starting logical block address and the length value; Determining whether the starting logical block address of the other new locked range is less than the ending logical block address of the other old locked range; and In response to the start logical block address of another new locked range being not less than the end logical block address of the other old locked range, data is executed for the other new locked range and the other old locked range respectively prune. A high-efficiency garbage collection method as described in item 7 of the patent application scope, in which the old lock range overlaps with the new lock range, and the other new lock range and the other old lock range do not overlap at all . A data storage device, including: A non-volatile memory (NV memory) for storing information, wherein the non-volatile memory includes at least one non-volatile memory element (NV memory element); and A controller, coupled to the non-volatile memory, is used to control the operation of the data storage device. The controller includes: A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller, wherein: The controller receives a security command from the host, where the security command is about changing an old locking range (Locking Range) to a new locking range; The controller obtains a starting logical block address (LBA) and a length value of the new locking range according to the safety command, wherein an ending logical block address of the new locking range is the new locking range The sum of the starting logical block address and the length value; The controller determines whether the start logical block address of the new locked range is less than an end logical block address of the old locked range, and determines whether the end logical block address of the new locked range is greater than the old A starting logical block address of the locked range; and The starting logical block address corresponding to the new locking range is smaller than the ending logical block address of the old locking range and the ending logical block address of the new locking range is greater than a starting logical area of the old locking range Block address, the controller performs data trimming (Data Trimming) on the new lock range and the part of the old lock range that does not overlap. A data storage device as described in item 9 of the patent application scope, wherein the controller receives another security command from outside the data storage device, wherein the other security command is about changing another old lock range to another new Lock range; the controller obtains a start logical block address and a length value of the other new lock range according to the another security command, wherein an end logical block address of the other new lock range is the other The sum of the starting logical block address of a new locked range and the length value; the controller determines whether the starting logical block address of the other new locked range is less than an end of the other old locked range Logical block address; as the start logical block address of another new locked range is less than the end logical block address of the other old locked range, the controller determines the Whether the end logical block address is greater than a start logical block address of the other old locked range; and the end logical block address corresponding to another new locked range is not greater than a start of the other old locked range For logical block addresses, the controller performs data pruning on the other new locked range and the other old locked range, respectively. A data storage device as described in item 10 of the patent application scope, wherein the controller receives another security command from outside the data storage device, wherein the further security command is about changing another old lock range to another new Lock range; the controller obtains a starting logical block address and a length value of the further new locking range according to the further safety command, wherein an ending logical block address of the further new locking range is the The sum of the start logical block address of a new lock range and the length value; the controller determines whether the start logical block address of the further new lock range is less than an end of the further old lock range Logical block address; and the address of the starting logical block corresponding to another new locking range is not less than the ending logical block address of the further old locking range, the controller respectively locks the new block The range and the another old locked range perform data pruning. The data storage device as described in item 11 of the patent application scope, in which the old lock range overlaps with the new lock range in part, the other new lock range and the other old lock range do not overlap at all, and the The new lock range and the old lock range do not overlap at all. The data storage device as described in item 10 of the patent application scope, wherein the old lock range overlaps with the new lock range, and the other new lock range and the other old lock range do not overlap at all. The data storage device as described in item 9 of the patent application scope, in which the old lock scope and the new lock scope partially overlap. A data storage device as described in item 9 of the patent application scope, wherein the controller receives another security command from outside the data storage device, wherein the other security command is about changing another old lock range to another new Lock range; the controller obtains a start logical block address and a length value of the other new lock range according to the another security command, wherein an end logical block address of the other new lock range is the other The sum of the starting logical block address of a new locked range and the length value; the controller determines whether the starting logical block address of the other new locked range is less than an end of the other old locked range The logical block address; and in response to the start logical block address of another new lock range being not less than the end logical block address of the other old lock range, the controller respectively locks the other new block Data pruning is performed on the scope and the other old locked scope. The data storage device as described in item 15 of the patent application scope, wherein the old lock range overlaps with the new lock range, and the other new lock range and the other old lock range do not overlap at all. A controller for a data storage device includes the controller and a non-volatile memory (NV memory), the non-volatile memory includes at least one non-volatile memory element (NV memory element), the controller contains: A processing circuit for controlling the controller according to a plurality of host commands from a host device to allow the host to access the non-volatile memory through the controller, wherein: The controller receives a security command from the host, where the security command is about changing an old locking range (Locking Range) to a new locking range; The controller obtains a starting logical block address (LBA) and a length value of the new locking range according to the safety command, wherein an ending logical block address of the new locking range is the new locking range The sum of the starting logical block address and the length value; The controller determines whether the start logical block address of the new locked range is less than an end logical block address of the old locked range, and determines whether the end logical block address of the new locked range is greater than the old A starting logical block address of the locked range; and The starting logical block address corresponding to the new locking range is smaller than the ending logical block address of the old locking range and the ending logical block address of the new locking range is greater than a starting logical area of the old locking range Block address, the controller performs data trimming (Data Trimming) on the new lock range and the part of the old lock range that does not overlap. A controller as described in item 17 of the patent application scope, wherein the controller receives another security command from outside the data storage device, wherein the other security command is about changing another old lock range to another new lock Range; the controller obtains a start logical block address and a length value of the another new locked range according to the another security command, wherein an end logical block address of the other new locked range is the other The sum of the start logical block address of the new lock range and the length value; the controller determines whether the start logical block address of the other new lock range is less than an end logic of the other old lock range Block address; in response to the start logical block address of another new locked range being less than the end logical block address of the other old locked range, the controller determines the end of the other new locked range Whether the logical block address is greater than a starting logical block address of the other old locked range; and the starting logical block address corresponding to another new locked range is not greater than a starting logic of the other old locked range For the block address, the controller performs data pruning on the other new locked range and the other old locked range, respectively. The controller as described in item 18 of the patent application scope, wherein the controller receives another security command from outside the data storage device, wherein the further security command is about changing another old lock range to another new lock Range; the controller obtains a starting logical block address and a length value of the further new locking range according to the further safety command, wherein an ending logical block address of the further new locking range is the further The sum of the start logical block address of the new lock range and the length value; the controller determines whether the start logical block address of the further new lock range is less than an end logic of the further old lock range Block address; and the address of the starting logical block corresponding to another new lock range is not less than the end logical block address of the another old lock range, the controller respectively responds to the new lock range And that another old lock range performs data trimming. The controller as described in item 19 of the patent application scope, wherein the old lock range and the new lock range partially overlap the lock range, the other new lock range and the other old lock range do not overlap at all, and the The new lock range and the another old lock range do not overlap at all.

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