TW201839849A - Structure with selective barrier layer - Google Patents

Structure with selective barrier layer Download PDF

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Publication number
TW201839849A
TW201839849A TW107113501A TW107113501A TW201839849A TW 201839849 A TW201839849 A TW 201839849A TW 107113501 A TW107113501 A TW 107113501A TW 107113501 A TW107113501 A TW 107113501A TW 201839849 A TW201839849 A TW 201839849A
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Taiwan
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material
method
forming
semiconductor structure
processing chamber
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TW107113501A
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Chinese (zh)
Inventor
姜勝全
吉鏞 李
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美商微材料有限責任公司
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Priority to US201762487728P priority Critical
Priority to US62/487,728 priority
Application filed by 美商微材料有限責任公司 filed Critical 美商微材料有限責任公司
Publication of TW201839849A publication Critical patent/TW201839849A/en

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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes, e.g. for surface treatment of objects such as coating, plating, etching, sterilising or bringing about chemical reactions
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357Generation remote from the workpiece, e.g. down-stream

Abstract

A processing method can be performed to form a semiconductor structure that can include a three-dimensional memory structure. The method can include the step of: plasma of a fluorine-containing precursor formed in a distal plasma region of the processing chamber. The method can include the step of contacting the semiconductor substrate with the effluent of the plasma. The semiconductor substrate can be housed in a processing region of the processing chamber. The method can include the step of selectively selectively etching the metallic material between exposed regions of the dielectric material on the semiconductor substrate. The method may also include the step of subsequently depositing a cover material on the metallic material. The cover material can be selectively deposited on the metal material relative to the exposed areas of the dielectric material.

Description

Structure with selective barrier layer

This technology relates to semiconductor systems, processing, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing layers of materials on a semiconductor device.

It is possible to fabricate an integrated circuit by processing a layer of intricately patterned material on the surface of the substrate. Producing a patterned material on a substrate requires a control method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring the pattern in the photoresist to a layer underneath, a thinned layer, or a thinned lateral dimension of a feature that has been rendered on the surface. It is generally desirable to have an etching process that etches one material faster than the other to facilitate, for example, pattern transfer processing or separate material removal. This etching process is said to be selective for the first material. Due to the variety of materials, circuits, and processes, etching processes have been developed that are selective for a variety of materials. However, the deposition process is typically performed using a blanket coating or conformal fill to continue across the substrate.

As device sizes continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a particular layer is only a few nanometers (especially when the material is critical in the formation of the transistor). Many different etch processing options have been developed between various materials, but standard selectivity may no longer be applicable to current and future device sizes. Moreover, based on the number of masking, forming, and removing operations required to form and protect the various critical dimensions of the features across the device, the processing time continues to increase while patterning and formation is performed elsewhere on the substrate.

Therefore, there is a need for a system and method that can be used to produce high quality devices and structural improvements. This technology addresses these and other needs.

A processing method can be performed to form a semiconductor structure that can include a three-dimensional memory structure. The method can include the step of forming a plasma of a fluorine-containing precursor in a distal plasma region of the processing chamber. The method can include the step of contacting the semiconductor substrate with the effluent of the plasma. The semiconductor substrate can be housed in a processing region of the processing chamber. The method can include the step of selectively selectively etching the metallic material between exposed regions of the dielectric material on the semiconductor substrate. The method may also include the step of subsequently depositing a cover material on the metallic material. The cover material can be selectively deposited on the metal material relative to the exposed areas of the dielectric material.

In some embodiments, the etching can be performed in the first processing chamber and the deposition can be performed in the second processing chamber. The method can also include the steps of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring can be performed without breaking the vacuum. The metal material may include tungsten or cobalt. The dielectric material can include ruthenium oxide. The cover material may include a metal nitride or a metal oxide. The metal material can be etched laterally less than 10 nm from the sidewalls of the channel. Etching can be performed using a selectivity of the metallic material that is greater than or about 10: 1 relative to the dielectric material. Deposition can be performed using a selectivity of the metallic material that is greater than or about 2: 1 relative to the dielectric material. Moreover, in some embodiments, the step of selectively depositing the cap material can include the step of inhibiting growth of the cap material on the dielectric material.

The techniques of the present invention also include a method of forming a semiconductor structure. The method can include the step of: plasma of a fluorine-containing precursor formed in a distal plasma region of the processing chamber. The method can include the step of contacting the semiconductor substrate with the effluent of the plasma. The semiconductor substrate can be housed in a processing region of the processing chamber. The method can include the step of selectively selectively etching a layer of metallic material between exposed layers of dielectric material on the semiconductor substrate. The method may also include the step of subsequently depositing a cover material on the metallic material. The cover material can be selectively deposited on the metal material relative to the exposed areas of the dielectric material.

In some embodiments, the tantalum nitride layer can be etched laterally less than 10 nm from the sidewalls of the trench. The dielectric material can be yttrium oxide or can include yttrium oxide. The cover material can be a metal nitride or a metal oxide, or can include a metal nitride or a metal oxide. The metal nitride may be titanium nitride or may include titanium nitride. The etching can be performed in the first processing chamber and the deposition can be performed in the second processing chamber. The method can also include the steps of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring can be performed without breaking the vacuum. The semiconductor substrate can define a plurality of channels, and the metal material can be etched on a plurality of surfaces. Etching can be performed using a selectivity of the metallic material that is greater than or about 10: 1 relative to the dielectric material. Deposition can be performed using a selectivity of the metallic material that is greater than or about 2: 1 relative to the dielectric material.

Such techniques can provide many benefits over conventional systems and techniques. For example, these processes can achieve smaller devices due to the improved structure. In addition, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time and allow formation of structures that are difficult to form. These and other embodiments, as well as many of its advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

The techniques of the present invention include systems and components for semiconductor processing of small pitch features. When converting from 2D NAND to 3D NAND, many processing operations are modified from vertical to horizontal to laterally etch and form a layer of material. In addition, as the number of cells formed by the 3D NAND structure grows, the aspect ratio of memory holes and other structures sometimes increases significantly. In conventional 3D NAND processing, the stack of placeholder layers and dielectric materials can form an interelectrode dielectric or IPD layer. These placeholder layers can have various execution operations to place the structure before the placeholder material is completely removed and replaced with metal. As the device size continues to shrink, the aspect ratio of the placeholder layer may increase as the width and depth increase. Therefore, when the material is removed and replaced with metal, complete filling may be more difficult. In addition, seams may form within the metal layer, which may affect device performance or may damage the device.

Many conventional techniques utilize wet etching to access each unit of placeholder material to perform lateral etching of the placeholder prior to incorporation of the metal. Dry etching may not be feasible in the prior art due to the high aspect ratio of the memory holes, which may not allow symmetric etching to be performed. However, wet etching may be more robust than other etching techniques, and wet etching may etch materials in addition to placeholder materials, causing damage within the structure, which may weaken the structure and cause distortion. Subsequent metallization may be incomplete or create seams or voids within the layers of the structure. The resulting memory unit may have reduced capacity or may malfunction. In addition, conventional techniques have been unable to convert to initial metal structures due to problems with core oxide filling operations and adhesion problems with other materials.

The techniques of the present invention overcome these problems by forming structures that avoid conventional placeholder removal operations. In conventional batteries using oxide and nitride materials known as ONON, the present technology may not include alternative materials and may directly form metallization. These new structures (which can be viewed as oxides and metal structures, or OMOM) can overcome the need to extract placeholder materials and deposit metals. The described problem can be avoided by forming an initial structure including metallization. The present technology allows these structures to be formed by utilizing selectively deposited barrier layers to separate nodes and increase the adhesion of subsequently deposited materials (eg, oxides to other core materials). By selectively depositing the barrier layer, complete node separation can be performed without the need for etchback processing that extends further within the metal layer.

While the remainder of the disclosure will routinely identify particular etching and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etching, deposition, and cleaning processes that may occur in the described chambers. . Therefore, the technique should not be considered limited to the etching and deposition processes that can be used only. The present disclosure will discuss one possible system and chamber that can be used with the present technology to perform certain removal and deposition operations prior to the described operations of the exemplary processing sequences in accordance with the present technology.

A top plan view of FIG. 1 illustrates a first embodiment in accordance with one embodiment of the processing system embodiment of deposition, etching, baking, and curing chamber 100. In the drawings, a pair of front open unified pods (FOUPs) 102 are supplied with substrates of various sizes, which are received by robotic arms 104 and placed in a substrate processing chamber 108a located in series sections 109a-c. Before one of the -f, it is placed in the low pressure holding area 106. The second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate processing, Each of the substrate processing chambers 108a-f can be provided to perform a number of substrate processing operations including dry etching processes and selective deposition as described herein.

The substrate processing chambers 108a-f can include one or more system components for depositing, annealing, curing, and/or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (eg, 108c-d and 108e-f) can be used to deposit a dielectric material or metal-containing material on the substrate, while a third pair of processing chambers (eg, 108a-b) It can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (eg, 108a-f) can be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be performed in a chamber separate from the manufacturing system shown in the different embodiments.

In some embodiments, the chamber specifically includes at least one etch chamber as described below and at least one deposition chamber as described below. All of the etching and deposition processes described below can be performed in a controlled environment by including these chambers and combining the processing sides of the factory interface. For example, the vacuum environment can be maintained on the processing side of the holding area 106 such that all of the chambers and transfers in the embodiment are maintained under vacuum. This also limits the contact of water vapor and other air components with the substrate being processed. It should be understood that system 100 can take into account additional configurations for deposition, etching, annealing, and curing of dielectric films.

Figure 2A illustrates a plasma generator having a separated cross-sectional view of an exemplary process chamber system 200 in the processing region of the chamber. During film etching (for example, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, tantalum, polycrystalline germanium, antimony oxide, antimony nitride, antimony oxynitride, antimony oxyhydroxide, etc.), the process gas can pass The gas inlet assembly 205 flows into the first plasma region 215. A remote plasma system (RPS) 201 can optionally be included in the system and can process the first gas that subsequently travels through the gas inlet assembly 205. The inlet assembly 205 can include two or more different gas supply passages, wherein if a second passage (not shown) is included, the second passage can bypass the RPS 201.

A cooling plate 203, a panel 217, an ion eliminator 223, a showerhead 225, and a substrate support 265 having a substrate 255 disposed thereon are illustrated, and each may be included in accordance with an embodiment. The pedestal 265 can have a heat exchange channel through which the heat exchange fluid flows to control the temperature of the substrate, and the temperature of the substrate can be manipulated during processing operations to heat and/or cool the substrate or wafer. It is also possible to use an embedded resistive heater element while resistively heating a wafer support disk of pedestal 265 comprising aluminum, ceramic, or a combination thereof to achieve relatively high temperatures, for example from up to or about 100 ° C to above or about 1100 ° C. .

Panel 217 may be pyramidal, conical, or other similar structure having a narrow top portion that extends to a wide bottom portion. Additionally, panel 217 may be flat and include a plurality of through passages for dispensing process gases, as shown. Depending on the use of the RPS 201, the plasma generating gas and/or the plasma exciting material may pass through a plurality of holes in the panel 217 as shown in FIG. 2B for more uniform delivery into the first plasma region 215.

An exemplary configuration may include the gas inlet assembly 205 passing into the gas supply region 258 separated by the panel 217 from the first plasma region 215 such that gas/substance flows through the holes in the panel 217 into the first plasma region 215. Structural and operational features may be selected to prevent large amounts of plasma from the first plasma region 215 from flowing back into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The illustrated panel 217 or the conductive top portion of the chamber and the showerhead 225, wherein the insulating ring 220 is positioned between the features to allow an AC potential to be applied to the panel 217 relative to the showerhead 225 and/or the ion eliminator 223 . Insulation ring 220 can be positioned between panel 217 and showerhead 225 and/or ion eliminator 223 to allow capacitive coupling plasma (CCP) to be formed in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid through the gas inlet assembly 205 into the region.

Ion eliminator 223 can include a plate or other geometry defining a plurality of pores throughout the structure, the plurality of pores being configured to eliminate migration of ionically charged species exiting first plasma region 215 while allowing uncharged neutrality Or the radical species pass through the ion eliminator 223 into the active gas delivery zone between the eliminator and the showerhead. In an embodiment, the ion eliminator 223 can comprise a multiwell plate having various pore configurations. These uncharged species can include highly reactive species that are transported through the pores with less reactive gas carrier. As noted above, migration of ionic species through the pores may be reduced and, in some cases, completely eliminated. Controlling the amount of ionic species passing through the ion eliminator 223 can advantageously provide increased control of the gas mixture in contact with the underlying wafer substrate, which in turn can increase control of deposition and/or etch characteristics of the gas mixture. For example, the adjustment of the ion concentration of the gas mixture can significantly change its etch selectivity, for example, SiNx: SiOx etch rate, Si: SiOx etch rate, and the like. In an alternative embodiment of performing deposition, the balance of conformal flow deposition of the dielectric material can also be translated.

The plurality of apertures in ion eliminator 223 can be configured to control the passage of reactive gases (i.e., ions, free radicals, and/or neutral species) through ion eliminator 223. For example, the aspect ratio of the holes, or the diameter of the holes to the length, and/or the geometry of the holes can be controlled such that the flow of ionically charged species in the reactive gas passing through the ion eliminator 223 is reduced. The holes in the ion eliminator 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and sized to control the flow of ionic species to the showerhead 225. An adjustable electrical bias can also be applied to the ion eliminator 223 as an additional means of controlling the flow of ionic species through the eliminator.

Ion eliminator 223 can be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generating region to the substrate. Uncharged neutral and free radical species can still pass through the openings in the ion eliminator to react with the substrate. It should be noted that in an embodiment, complete elimination of the ionically charged species in the reaction zone surrounding the substrate may not be performed. In some cases, the ionic species are intended to reach the substrate to perform an etching and/or deposition process. In these cases, the ion eliminator can help control the concentration of ionic species in the reaction zone at the level that facilitates processing.

The showerhead 225 in combination with the ion eliminator 223 can allow plasma present in the first plasma region 215 to avoid direct excitation of gas in the substrate processing region 233 while still allowing the excited species to travel from the chamber plasma region 215. Go to substrate processing area 233. In this manner, the chamber can be configured to prevent plasma from contacting the substrate 255 in the etch. This can advantageously protect the various complex structures and films patterned on the substrate, and various complex structures and films can be damaged, displaced, or otherwise bent if directly in contact with the plasma produced. Furthermore, the rate at which the oxide species is etched may be increased when the plasma is allowed to contact the substrate or near the substrate level. Thus, if the exposed area of the material is an oxide, the material can be further protected by maintaining the plasma at the distal end of the substrate.

The processing system can further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, the ion eliminator 223, the showerhead 225, and/or the pedestal 265 to be in the first plasma region 215 or Plasma is generated in the treatment zone 233. Depending on the processing performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. This configuration can allow tunable plasma for processing in execution. Unlike a remote plasma unit that is typically presented with an on or off function, the tunable plasma can be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow for the formation of specific plasma characteristics such that the precursors may be dissociated in a particular manner to enhance the etch profile created by these precursors.

The plasma may be excited in the chamber plasma region 215 above the showerhead 225 or the substrate processing region 233 below the showerhead 225. In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed using a pedestal as an electrode. A plasma may be present in the chamber plasma region 215 to produce a free radical precursor from the influx of, for example, a fluorine-containing precursor or other precursor. Typically, an AC voltage in the radio frequency (RF) range can be applied between the conductive top portion of the processing chamber (eg, panel 217) and the showerhead 225 and/or ion eliminator 223 to excite the cavity during deposition. The plasma in the chamber plasma region 215. The RF power supply can produce a high RF frequency of 13.56 MHz, but other frequencies can be generated separately or combined with the 13.56 MHz frequency to produce other frequencies.

FIG . 2B illustrates a detailed view 253 of features affecting the distribution of process gases through panel 217. As shown in FIGS. 2A and 2B, panel 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 in which process gas can be delivered from gas inlet 205 into gas supply region 258. The gas may fill the gas supply region 258 and flow through the apertures 259 in the panel 217 to the first plasma region 215. The apertures 259 can be configured to direct flow in a substantially unidirectional manner such that process gases can flow into the processing region 233, but can be partially or completely prevented from flowing back into the gas supply region 258 after passing through the panel 217.

The gas distribution assembly (e.g., showerhead 225 for processing chamber section 200) may be referred to as a dual channel showerhead (DCSH) and is additionally illustrated in detail in the embodiment illustrated in FIG. The dual channel showerhead can provide an etch process to allow separation of the etchant outside of the processing region 233 to provide limited interaction with the chamber components and each other prior to delivery to the processing region.

The showerhead 225 can include an upper plate 214 and a lower plate 216. These plates can be coupled to each other to define a volume 218 between the plates. The coupling of the plates can provide a first fluid passage 219 through the upper and lower plates and a second fluid passage 221 through the lower plate 216. The formed passageway can be configured to provide a fluid inlet and outlet from the volume 218 alone through the second fluid passage 221 through the lower plate 216, while the first fluid passage 219 can be fluidly isolated from the volume 218 between the plate and the second fluid passage 221. The volume 218 can be vented through one side of the gas distribution assembly 225.

FIG. 3 is a system for use with a shower head in accordance with an embodiment of the processing chamber 325 a top view. The showerhead 325 can correspond to the showerhead 225 shown in FIG. 2A. The through holes 365 (the view of the first fluid passage 219 are illustrated) may have a plurality of shapes and configurations to control and influence the flow of the precursor through the showerhead 225. A small aperture 375 (shown as a view of the second fluid passage 221) can be distributed substantially evenly over the surface of the showerhead (even in the through hole 365) and can help the precursor provide a ratio when exiting the showerhead. Other configurations are more evenly mixed.

Turning to FIG . 4 , a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology is illustrated. System 400 can include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 can generally be a sealable outer casing that can be operated under vacuum or at least low pressure. The processing chamber 20 can be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 can seal the process chamber 20 and the load lock chamber 10 in a closed position and can allow the substrate 60 to be transferred from the load lock chamber 10 through the valve to the process chamber 20 in the open position, and vice versa.

System 400 can include a gas distribution plate 30 that can dispense one or more gases across substrate 60. The gas distribution plate 30 can be any suitable distribution plate known to those skilled in the art, and the particular gas distribution plate should not be considered to limit the scope of the present technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60.

The gas distribution plate 30 can include a plurality of gas crucibles and a plurality of vacuum crucibles, the plurality of gas crucibles configured to deliver one or more gas streams to the substrate 60, and a plurality of vacuum crucibles disposed between each gas crucible, And configured to deliver a flow of gas out of the processing chamber 20. As shown in FIG. 4, the gas distribution plate 30 can include a first precursor injector 420, a second precursor injector 430, and a purge gas injector 440. The injectors 420, 430, 440 can be controlled by a system computer (not shown) (e.g., a host) or by a chamber specific controller (e.g., a programmable logic controller). The precursor injector 420 can be configured to inject a continuous or pulsed flow of the reaction precursor of Compound A through the plurality of gas helium 425 into the processing chamber 20. The precursor injector 430 can be configured to inject a continuous or pulsed flow of the reaction precursor of Compound B through a plurality of gas helium 435 into the processing chamber 20. The purge gas injector 440 can be configured to inject a continuous or pulsed flow of non-reactive or purge gas through the plurality of gas helium 445 into the processing chamber 20. The purge gas can be configured to remove reactive materials and reaction byproducts from the processing chamber 20. The purge gas is typically an inert gas such as nitrogen, argon, and helium. A gas crucible 445 may be disposed between the gas crucible 425 and the gas crucible 435 to separate the precursor of the compound A from the precursor of the compound B, thereby avoiding cross-contamination between the precursors.

In another aspect, a distal plasma source (not shown) can be coupled to the precursor injector 420 and the precursor injector 430 prior to injecting the precursor into the processing chamber 20. The plasma of the reactive species can be produced by applying an electric field to the compound in the remote plasma source. Any power source capable of activating the intended compound can be used. For example, power sources using DC, RF, and microwave-type discharge techniques can be used. If an RF power source is used, it can be capacitively or inductively coupled. Activation can also be produced by thermal basic techniques, gas dissociation techniques, high intensity light sources (eg, ultraviolet light sources), or exposure to x-ray sources.

System 400 can further include a pumping system 450 coupled to processing chamber 20. The pumping system 450 can be generally configured to evacuate the gas stream out of the processing chamber 20 by one or more vacuum ports 455. A vacuum crucible 455 can be disposed between each gas crucible to evacuate the gas stream out of the processing chamber 20 after the gas stream reacts with the substrate surface and further limit cross-contamination between the precursors.

System 400 can include a plurality of partitions 460 disposed on processing chamber 20 and between each turn. The lower portion of each partition may extend proximate to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61). In this manner, the lower portion of the partition 460 can be separated from the surface of the substrate by a distance sufficient to allow the flow of gas to flow around the lower portion toward the vacuum crucible 455 after the gas stream reacts with the surface of the substrate. Arrow 498 indicates the direction of the gas flow. Since partition 460 is operable as a physical barrier to gas flow, partition 460 can also limit cross-contamination between precursors. The configurations shown are for illustrative purposes only and are not to be considered as limiting the scope of the technology. Those of ordinary skill in the art will appreciate that the gas distribution system shown is only one possible distribution system and that other types of showerheads can be employed.

In operation, the substrate 60 (e.g., by a robot) can be delivered to the load lock chamber 10 and can be placed on the shuttle 65. After the isolation valve 15 is opened, the shuttle 65 can move along the rail 70. Once the shuttle 65 enters the processing chamber 20, the isolation valve 15 can be closed to seal the processing chamber 20. The shuttle 65 can then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a linear path.

As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 may be repeatedly exposed to the precursor of the compound A from the gas crucible 425 and the precursor of the compound B from the gas crucible 435 with gas from the gas crucible 445 Purge the gas. The injection of the purge gas can be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to various gas streams, the gas stream can be evacuated by vacuum pumping 455 through vacuum pumping 455. Since a vacuum crucible can be placed on both sides of each gas crucible, the gas flow can be evacuated by vacuum crucibles 455 on both sides. Thus, the gas flow can flow vertically downward from the individual gas helium toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portion of the partition 460, and finally upward toward the vacuum crucible 455. In this way, each gas can be evenly distributed across the substrate surface 61. The substrate 60 can also be rotated while exposed to various gas streams. Rotation of the substrate can be useful to prevent strip formation in the formed layer. The rotation of the substrate can be a continuous or separate step.

The extent to which the substrate surface 61 is exposed to each gas can be determined by, for example, the flow rate of each gas from the gas and the rate of movement of the substrate 60. In one embodiment, the flow rate of each gas can be configured without removing the absorbed precursor from the substrate surface 61. The width between each partition, the number of gas imperfections disposed on the processing chamber 20, and the number of times the substrate may be transferred back and forth may also determine the extent to which the substrate surface 61 is exposed to various gases. Therefore, the number and quality of deposited films can be optimized by varying the above factors.

In another embodiment, system 400 can include precursor injector 420 and precursor injector 430 without purge gas injector 440. Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 can be alternately exposed to the precursor of Compound A and the precursor of Compound B without being exposed to the purge gas therebetween.

The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. While the embodiments have been described and illustrated with respect to this upright orientation, it should be understood that the opposite orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downward, and the gas flowing toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 can be positioned to heat the second side of the substrate.

In some embodiments, the shuttle 65 can be a base 66 for carrying the substrate 60. Generally, the pedestal 66 can be a carrier that helps to form a uniform temperature across the substrate. The pedestal 66 can be moved in both left-to-right and left-to-right directions between the load lock chamber 10 and the process chamber 20 with respect to the arrangement of FIG. The pedestal 66 can have a top surface 67 for carrying the substrate 60. The pedestal 66 can be a heated pedestal such that the substrate 60 can be heated for processing. As an example, the pedestal 66 can be heated by a radiant heat source 90 disposed below the susceptor 66, a heater plate, a resistive coil, or other heating device. Although illustrated as a lateral transition, embodiments of system 400 can also be used in a rotary system in which the wheel can be rotated clockwise or counterclockwise to continuously process one or more substrates located below the gas distribution system shown. It should be similarly understood that additional modifications are included in the present technology.

FIG . 5 illustrates a method 500 of forming a semiconductor structure in which a number of operations can be performed, for example, in the aforementioned chambers 200 and 400. Method 500 can include one or more operations prior to initiating the method, including front end processing, deposition, etching, grinding, cleaning, or any other operation that can be performed prior to the operation. The method can include a plurality of selectable operations shown in the figures, which may or may not be particularly associated with methods in accordance with the present techniques. For example, many operations are described in order to provide a broader range of structure formation, but are not critical to the technology, or may be performed by alternative methods, as discussed further below. Method 500 is described first. 6A through 6C schematically illustrated in FIG operation of the method 500 in conjunction with the operation described in the description. It should be understood that FIG. 6 is only a partial schematic view, and the substrate may include any number of transistor segments having the pattern shown in the figures.

Method 500 can involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate that includes regions that are further developed to create a 3D NAND structure. As shown in FIG. 6A, a portion of the processed structure 600 including the substrate 605 can be illustrated as having a plurality of stacked layers overlying the substrate, and can be tantalum, tantalum, or other substrate material. The layers may include memory for producing a dielectric material 610 (which may be an oxide (eg, hafnium oxide)) in alternating layers including a metallic material 620 (which may be tungsten, cobalt, or other low resistivity metal). The layer of the body node. Although only seven layers of material are illustrated, exemplary structures can include any number of layers, such as up to or greater than about 10, greater than or about 15, greater than or about 20, greater than or about 25, greater than or about 30, greater than or about 35. , greater than or about 40, greater than or about 45, greater than or about 50, greater than or about 55, greater than or about 60, greater than or about 65, greater than or about 70, greater than or about 80, greater than or about 90, greater than or about one. One hundred or more layers of material.

Channel 630 (which may be a memory hole) may be defined to the level of substrate 605 by a stacked structure. Channel 630 may be defined by sidewall 632, which may be comprised of alternating layers of dielectric material 610 and metallic material 620. While tungsten and yttrium oxide will be discussed in the remainder of the disclosure, any other known material having similar operational characteristics may be substituted for one or more layers. Some or all of these operations may be performed in the aforementioned chamber or system tool, or may be performed in different chambers on the same system tool, which may include a chamber that performs the operations of method 400.

The method 500 may initially include the step of recessing the metallic material 620 as shown in FIG. 6B. The metal material 620 can be recessed in an etch chamber similar to the chamber 200 previously described. In some embodiments, wet etching or other dry etching can be performed. However, the following describes one possible process for laterally removing tungsten or metal material from within the memory cavity. Once positioned within the processing region of the semiconductor processing chamber, the method can include forming a plasma of the fluorine-containing precursor in the distal plasma region of the processing chamber at operation 505. The distal plasma region can be fluidly coupled to the processing region, but can be physically separated to confine the plasma at the substrate level, which can damage the exposed structure or material.

The effluent of the plasma can flow into the processing region and can be contacted with the semiconductor substrate at operation 510. At operation 515, the metallic material can be selectively etched laterally relative to the exposed regions of dielectric material 610. Lateral etching may be performed through a channel (eg, a memory hole) and may occur along a sidewall of the trench within the exposed portion of each layer of metal material 620 (eg, tungsten). In some embodiments, the lateral etch can be selectively performed on the layer of metallic material and the intercalation layer of yttria or other dielectric material can be substantially maintained. Further, as shown, etching may be performed on a plurality of surfaces of the metal material 620 (eg, from opposite sides of a plurality of channels or memory vias). Prior to the end of the lateral etch operation, method 500 can laterally etch the metal material less than 50 nm from the sidewalls of the trench and the exposed layer of dielectric material 610 in an exemplary operation. In some embodiments, method 500 can laterally etch the metal material to be less than or about 45 nm, less than or about 40 nm, less than or about 35 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or About 10 nm, less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or more. small.

The method 500 can involve reducing the etch rate to allow for more complete diffusion to occur, while helping to provide a more uniform etch from top to bottom. Without the technique described below, the area of metallic material at or near the top of the channel may begin to etch before the bottom region. This may then create a profile within the channel, such as a V-shaped profile of the layer of metallic material from the top to the bottom of the channel. This may occur, for example, when the amount of fluorine in the mixture increases or the temperature increases.

In the case of the conventional dry technique, the V-shaped profile may be unavoidable because a high aspect ratio of the channel or memory hole that is laterally etched can be performed. The diameter or width of the exemplary channel may be tens of nanometers or less, and the height of the channel may be a few microns or more. This may result in an aspect ratio greater than 20:1, greater than 50:1, greater than 75:1, greater than 100:1, or even greater, or a height to width ratio. Thus, in embodiments, more than 25 layers, more than 50 layers, more than 75 layers, or more than one hundred layers of alternating metallic and dielectric materials may be formed and processed in each channel.

Because the dry or gaseous etchant can travel a greater length, the top region of the channel may be exposed to a significant amount of etchant even before the etchant has reached the bottom of the channel. In this way, the metallic material located in the upper region of the channel may be etched more than the portion at the bottom of the trench. Although the wet etch technique can etch the metal material layer more uniformly, the etch may not be less than, reach, or about 10 or more nanometers due to the nature of the etchant and the residence time. Thus, unlike the prior art, conventional techniques may not be able to finely etch a certain amount of material from each metal material layer (eg, only a few nanometers), and may not produce a flat or substantially similar etched metal material throughout the channel. profile. However, the present technology can compensate for larger diffusion paths by limiting the etchant in any manner discussed to allow for a more uniform etch process to occur.

Processing conditions can also affect the operations performed in method 500 and other etching methods in accordance with the present technology. Each of the operations of method 500 can be performed during a constant temperature in an embodiment, while in some embodiments, the temperature can be adjusted during different operations. For example, in an embodiment, the substrate, pedestal, or chamber temperature during the lateral etch operation 515 can be maintained between about -100 °C and about 100 °C. The temperature may also be maintained below or at about 80 ° C, below or at about 60 ° C, below or at about 40 ° C, below or at about 20 ° C, below or at about 0 ° C, below or at about -20 ° C, below Or about -40 ° C, or lower. Temperature can affect the etching process itself, while higher temperatures can result in higher etch rates, increased etching, or other effects. Similarly, lower temperatures can slow down the etching operation and allow for improved diffusion. Thus, in some embodiments, maintaining a temperature below or about 50 ° C or below or about 0 ° C may provide a more uniform amount of etching of the metallic material at the top of the trench and at the bottom of the trench. As the temperature increases, the etching operation can additionally begin to affect the dielectric region and can cause slight rounding of the exposed corners or regions of the dielectric material (eg, yttrium oxide).

The pressure within the chamber can also affect the operation performed, while in embodiments, the chamber pressure can be maintained below about 10 Torr, below about 5 Torr, or below about 1 Torr. In embodiments, a pressure of less than or about 1 Torr may allow the precursor or plasma effluent to more easily flow into the channel or memory pores. However, when the pressure is reduced below about 0.5 Torr, the far end plasma may be affected and may have reduced stability or may become unstable. As previously mentioned, the remote plasma may comprise an RPS unit and may also be a region or portion of a chamber physically separated from the processing region of the chamber to limit or eliminate plasma at the substrate level. In some embodiments utilizing RPS units, for plasma stability with lower pressure within the chamber, a turbulator can be utilized to maintain a higher pressure within the RPS unit for improved precursor or plasma effluent Flow in the channel. Thus, a turbomolecular pump can be used in the chamber to allow the chamber pressure to drop to a few milliTorr while the RPS is maintained above 0.6 Torr or about 0.6 Torr.

Chamber conditions, flow rate ratios, and other operational characteristics can be adjusted to perform controlled etching of the metal material. For example, depending on the thickness of the material to be deposited, each region of the metallic material from the sidewalls of the trench can be laterally etched to a distance or depth of less than or about 10 nm, or any of the foregoing thicknesses. In an embodiment, each layer of metallic material may be etched to a depth or distance from the sidewall of the trench between about 1 nm and about 7 nm, or between about 2 nm and about 6 nm.

By performing the operations in accordance with the present techniques, the etch power can be reduced relative to the diffusion capability of the etchant material, which can allow for a more uniform, substantially uniform implementation at each region of metal material exposed within the trench or memory cavity. Or substantially uniform etching. In an embodiment, a region of metal material at or near the top of the trench or memory hole (eg, within the top 2 layers, within 4 layers, within 6 layers, within 8 layers, The amount of material etched from the sidewall measured within 10 layers or more may be a layer or region of metal material at or near the bottom of the channel of the memory hole (eg, from the bottom) Within 2 layers, 4 layers, 6 layers, 8 layers, 10 layers, or more) are similar.

Depending on the total number of stacked layers of etched channels or memory holes within the structure, the two layers being compared may be by at least 1 layer, at least 5 layers, at least 11 layers, at least 21 layers, at least 51 layers, or More and separate. For the etched upper layer, the lateral etch of the two layers being compared may differ by less than or about 30% compared to no less than 30% of the lower layer. Furthermore, the present technology can perform lateral etching of two layers such that the difference between the amounts of metal material etched between the two layers is less than or about 25%, less than or about 20%, less than or about 15%, less than or About 10%, less than or about 5%, less than or about 1%, or zero difference, in which case the two regions of the metallic material are etched to an equal depth or distance from the sidewalls of the channel. The substrate 605 can exhibit a minimum etch at the bottom of the channel 630 and can be reduced by an amount less than or about 5 nm, and can be reduced by an amount less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or It remains substantially unchanged during the lateral etching operation of the metallic material.

At optional operation 520, the substrate can be transferred from the etch chamber to the deposition chamber. The transfer can be done under vacuum, while both chambers can reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions can be maintained during transfer and transfer can be performed without breaking the vacuum. Once in the deposition chamber (eg, chamber 400 described above), at operation 525, a cap material can be formed or deposited on the recessed metal material 620. As shown in FIG. 6C, a cover material 625 (which may be a barrier material) may be formed directly on or in contact with the recessed metal material 620. The deposition operation may be selective deposition, wherein a cap material is preferably formed on the metal material 620 with respect to the exposed dielectric material 610. Operation 525 may directly perform a subsequent etching operation 515 with respect to conventional techniques that may include additional masking operations.

Although substrate transfer can be performed, other substrate processing may not be performed between selective etching and selective deposition. As will be explained in further detail below, although substrate transfer between operations can be performed in an embodiment, while selective deposition can include multiple operations, the entire deposition process can be performed directly after a set of etching operations. Since blanket deposition or formation of cap material 625 may require additional masking and removal techniques, by performing selective etching and selective deposition in accordance with method 500, the grid time can be significantly reduced over conventional techniques.

Various materials can be utilized in the process, while etching and deposition can be selective for multiple components. Thus, the present technology may not be limited to a single set of materials. For example, as previously discussed, metal material 620 can be several conductive materials used in semiconductor processing. Metal material 620 can be or can include tungsten, cobalt, or any other conductive metal that can act as a metal layer in a memory structure. Dielectric material 610 may also include an insulating material, and may also include a cerium-containing material, an oxygen-containing material, a carbonaceous material, or some combination of these materials (eg, cerium oxide or cerium oxide). Cover material 625 can include one or more dielectric materials, insulating materials, ceramic materials, or barrier materials.

Cover material 625 can be used on tungsten for a variety of uses. In some embodiments, titanium nitride can be used as the cover material 625, although it should be understood that similar materials can be used, including other metal nitrides, oxides, or dielectric materials. Titanium nitride can act as a barrier on tungsten. However, in many conventional deposits, a cap material may also be formed on the dielectric material 610, which may then allow for the connection between separate nodes or layers. Therefore, the etch back process can be performed. When the material is recessed from the dielectric, the treatment can be similar to tungsten or a metallic material to reduce the cover material due to minimal covering or bonding, and the tungsten can be exposed.

Subsequent operations to form the memory structure can include depositing additional core material, and can include a barrier layer (eg, aluminum oxide). Although alumina can be deposited on a dielectric material, tungsten and other metals may have low adhesion, and alumina may not readily deposit on this material, which may cause voids in the barrier layer. The formation of alumina on the exposed tungsten also oxidizes the metal and increases the electrical resistance. Titanium nitride and other barrier layer materials can be adhered to tungsten as a barrier layer and can allow for the formation of aluminum oxide along the sidewalls. Thus, by utilizing a capping material 625 (eg, a titanium nitride barrier layer), an oxide metal NAND structure can be more easily produced.

The etching operation can involve additional precursors along with a particular fluorine-containing precursor. In some embodiments, nitrogen trifluoride can be used to produce a plasma effluent. Additional or alternative fluorine precursors may also be utilized. For example, the fluorine-containing precursor may flow into the distal plasma region, and the fluorine-containing precursor may include a group selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, and six. At least one precursor of the group of sulfur fluoride, and antimony difluoride. The distal plasma zone can be in a different module than the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the RPS unit 201 and the first plasma region 215 can serve as a distal plasma region. The RPS can allow the plasma effluent to dissociate without damaging other chamber components, while the first plasma region 215 can provide a shorter path length to the substrate during which recombination can occur.

Additional precursors can also be delivered to the remote plasma region to enhance the fluorine-containing precursor. For example, a carbon or hydrogen containing precursor or hydrogen precursor can be delivered with a fluorine-containing precursor. For example, the additional precursor can also be a fluorine-containing precursor (eg, fluoromethane). Precursors containing hydrogen or carbon and hydrogen may be included to maintain a specific H:F atomic ratio for the plasma effluent. In an embodiment, etching may be performed using an H:F ratio greater than one, which may provide increased selectivity to tungsten or other metals relative to the dielectric material described above. In an embodiment, the H:F atomic flow ratio can be maintained greater than 2:1 or greater than 3:1, which can be controlled by adjusting the relative flow rate of the fluorine-containing precursor to the hydrogen-containing precursor.

When performing the method, the etch selectivity of tungsten relative to other features exposed on the surface of the substrate can be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1, or greater than or Approximately 100: 1, or greater, for various materials formed on the substrate and may be exposed to the plasma effluent. In the disclosed embodiment, the etch selectivity with respect to tungsten of (poly) germanium may be greater than or about 100:1, greater than or about 150:1, greater than or about 200:1, or greater than or about 250: 1. In embodiments, the etch selectivity to tungsten of yttrium oxide may be greater than or about 15:1, greater than or about 25:1, greater than or about 30:1, or greater than or about 40:1. In embodiments, the etch selectivity to tungsten of tantalum oxycarbide may be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, or greater than or about 40:1. In embodiments, the etch selectivity to tungsten relative to tungsten oxide may be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1, or greater than or about 100:1.

Thus, depending on the feature size, tungsten can be removed from the surface of the substrate while other exposed materials can be reduced by less than 1 nm. In an embodiment, the depth of the recess for the metal material 620 can be less than or about 50 nm, and can be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. Due to this etch depth, a minimum amount of dielectric material can be removed, which can be less than or about 3 nm, less than or about 1 nm, less than or about 0.5 nm, or the material can be substantially or substantially unchanged. Thus, the feature of tungsten etching relative to the dielectric material and the substrate can be any of the above-described options for the material of each structure.

Selective deposition can be performed in a chamber capable of deposition and capable of atomic layer deposition, including chamber 400 described above. The deposition may be preset to selectively deposit an insulating material on a metallic material relative to another insulating material. For example, the cover material 625 can be formed substantially over the metal material 620 while being minimally formed on or limited to the dielectric material 610. Selective deposition may be performed by a variety of operations, which may include forming a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting the formation of a dielectric on other dielectric materials.

A self-assembled monolayer can be formed over the area of the structure to tune the deposition. For example, a first self-assembled monolayer can be formed on the structure and then exposed to remove a single layer from the metallic material 620. A single layer can be maintained on the dielectric material 610. The monolayer may have a capping moiety that may or may not interact with the subsequently delivered precursor. For example, in embodiments, the capping moiety can be hydrophobic and can be capped with a hydrogen containing moiety (eg, a methyl group) that can not interact with the additional precursor. The second self-assembled monolayer may be formed on the metallic material 620, but may be hydrophilic or react with one or more precursors used to create the capping material 625. The second self-assembled monolayer can be selectively formed on the metallic material 620 because the material can be repelled from the first self-assembled monolayer or can be selectively stretched to the component. The second self-assembled monolayer may be capped with a hydroxyl or other hydrophilic moiety, or partially capped with an interaction with an additional precursor used to form the capping material 625.

Atomic layer deposition can then be performed using two or more precursors to develop cover material 625. The deposited precursor can include a metal-containing precursor and includes a precursor configured to interact with a portion of the capped second self-assembled monolayer (rather than the first self-assembled monolayer). For example, when a hydrophilic and hydrophobic capping monolayer is used, one of the atomic layer deposition precursors can include water or some other precursor to develop a capping material that can be hydrophilic. In this way, deposition may not be formed on the first self-assembled monolayer which may be hydrophobic. If the cap material comprises a metal oxide (eg, titanium oxide or titanium nitride), the precursor for atomic layer deposition may include a titanium-containing precursor and water or a nitrogen-containing precursor. Then, during a half reaction with water or other precursors, water may not interact with the first self-assembled monolayer formed on the dielectric material 610, and thus the deposition will not form on the first self-assembled monolayer. In this manner, the capping material 625 can be selectively formed on the metallic material 620 without forming a masking layer that can be chemically etched.

After the cover material 625 has been formed to a suitable height, the first self-assembled monolayer can be exposed to, for example, UV light in one example and removed from the substrate. Thus, the first self-assembled monolayer can be formed directly after selective etching of the metallic material, or after transfer to the additional chamber but prior to additional processing operations, without structurally eliminating the need for chemical removal or etching. Additional mask layer. Similarly, after selective deposition, the cap material 625 may not need to be etched to ensure selective formation of the cap material 625 on the metal material. In this way, multiple operations used in conventional formations can be eliminated, which can significantly reduce the queue time (eg, several hours).

Additional selective deposition techniques (which may include alternative mechanisms) may also be used for selectively depositing dielectric materials (eg, nitrogen-containing materials). For example, the nitrogen-containing material can act as one of the self-assembled monolayers on the material used for deposition (eg, one of the capped portions of the monolayer), while allowing for attraction to form the previously described A specific precursor of one or more of the materials. Other techniques can utilize temperature differences to enhance deposition on metals relative to yttria. For example, atomic layer deposition using a titanium-containing precursor and a nitrogen-containing precursor can be performed at temperatures above or about 500 ° C, and can be above or about 750 ° C, above or about 900 ° C, above. It can be carried out at a temperature of about 1000 ° C, or at, above, or at about 1100 ° C.

As the temperature increases within this range, deposition can occur on tungsten at a higher rate than on yttrium oxide. A selective etch of nitrogen can then be performed to remove the first dielectric material from the yttrium oxide surface. Although it is also possible to reduce the first dielectric material on the surface of the metal material, since the thickness can be many times larger than the thickness on the yttrium oxide, complete removal can be performed on the ruthenium oxide while maintaining the thickness on the metal material.

Embodiments may also utilize an inhibitor to selectively form capping material 625 on metallic material 620 without forming capping material 625 on dielectric material 610. For example, an inhibitor can be applied to the dielectric material. The inhibitor can be any number of materials, and the material can be characterized by a siloxane backbone (e.g., a decane) or a tetrafluoroethylene backbone (e.g., PTFE), as well as other oily or surfactant materials. A material may be applied to cover the exposed portions of the dielectric material 610. The inhibitor material can prevent adhesion or adsorption of a material that can be normally formed or deposited on the metal material 620. A cover material 625 is then formed and a remover can be applied to the substrate to remove the inhibitor material. The remover can be a wet etchant, a reactant, or a surfactant cleaner, and the residual inhibitor material that exposes the underlying dielectric material 610 can be removed. Thus, the inhibitor can be applied directly after selective etching, or after substrate transfer, but prior to other processing operations that affect the substrate. The use of an inhibitor may allow for the formation of a cap material in a defined area without the need for patterning and/or etching definition through subsequent blanket films. By removing the previous and subsequent patterning operations, the processing can further reduce the queue time of conventional processing.

The inhibitor may also be a poisoning agent or a product of a plasma application that can neutralize the surface of the substrate or render the surface of the substrate inert. For example, the modified plasma can be formed from one or more precursors, and can include an inert precursor. The plasma can be applied to the surface of the substrate, which can change the surface of the dielectric material 610, but may not affect the metal material 620. In one possible example, the nitrogen-containing precursor (which may be nitrogen) may be delivered to the plasma processing zone of the processing chamber that produces the plasma. The plasma effluent (which may include a nitrogen-containing plasma effluent) may be delivered to the substrate and may form a nitrided surface along the dielectric material 610.

The plasma effluent may not affect the metallic material 620, which may maintain a neat or unreacted surface. The cover material 625 can then be formed using one or more deposition techniques, which can include atomic layer deposition or other vapor or physical deposition. For example, atomic layer deposition techniques can be utilized, followed by treatment with a plasma effluent. After each cycle of deposition, the nitrogen-containing plasma can be reapplied to the substrate (eg, on dielectric material 610). In this manner, the surface of the dielectric material 610 can be passivated to prevent or limit the formation of the cap material 625 on those areas. Other plasma or non-plasma materials may also be used to modify or poison the dielectric material 610, which may also be processed to repel one or more precursors that may be used to form the cover material 625. Utilizing these plasma effluents on the non-recessed portions of the substrate may allow for the formation of the cap material in the defined regions without the need for patterning and/or etching definitions through subsequent blanket films. By removing the previous and subsequent patterning operations, the processing can further reduce the queue time of conventional processing.

Any of these techniques may selectively deposit or form a dielectric or insulating material on the germanium-containing metal region relative to one or more non-metal, dielectric, or insulating regions. The selectivity may be complete, i.e., the cover material is formed only on the metallic material 620 or the intermediate layer, and the cover material may not be formed entirely on the dielectric material 610. In other embodiments, the selectivity may not be complete, and the ratio of deposition on the metal-containing material relative to the dielectric or insulating material may be greater than about 2:1. The selectivity may also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35. : 1. greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more.

The cover material can be formed to the aforementioned thickness, the thickness can be less than or about 50 nm, and can be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Thus, a selectivity below 50:1 may be acceptable to completely deposit the cap material 625 while forming a limited amount of material on the dielectric material 610 or substantially no material forming. A slight etch back operation can be performed in the chamber 200 after deposition to ensure complete removal of the cover material 625 from the dielectric material 610 to ensure complete separation of the nodes. Since the covering can be done in the recessed area of the metallic material 620, the etch back can not affect the deposited material, or the edges or sidewalls can be cleaned to create a smooth surface. Since the deposition on the metal material 620 may be larger, any amount that may be deposited on the dielectric material 610 may be compensated on the metal material 620 by a slightly longer deposition time, and then may be recessed to the thickness of the recess and may be cleaned. The sidewall of the electrical material 610.

The deposition operation can be performed at any of the foregoing temperatures or pressures, and can be performed at temperatures greater than or about 50 ° C, and can be greater than or about 100 ° C, greater than or about 150 ° C, greater than or about 200 ° C, greater than or about 250 ° C, greater than or about 300 ° C, greater than or about 350 ° C, greater than or about 400 ° C, greater than or about 450 ° C, greater than or about 500 ° C, greater than or about 600 ° C, greater than or about 700 ° C, greater than or about 800 ° C Or at a higher temperature. For example, during an atomic layer deposition operation, temperatures greater than or about 400 ° C can be used to activate the precursors to interact with one another as the layers of material form. By using the present technique, manufacturing can be performed with more selective formation and removal than conventional techniques, which can reduce the array time by several hours compared to conventional processing. By performing the recess operation other than the barrier formation, the node separation can be more clearly defined, and subsequent processing or formation within the memory hole can be performed more easily. These processes can also implement new structures by forming a selective layer to ensure that the metal material is protected while the nodes maintain separation in the memory structure.

In the additional method included in the present technology, the recess of the metal material may not be performed. Turning to Figure 7, there is illustrated a schematic cross-sectional view of the substrate 700 according to an exemplary embodiment of the present technology. Substrate 700 can be similar to substrate 600 previously described and illustrated in FIG. 7A, and can include similar materials or other materials as previously described, and can have features of any of the foregoing dimensions or other characteristics. For example, structure 700 can include substrate 605, and alternating layers of dielectric material 610 and metallic material 620. Memory holes or channels 630 may be formed within the structure and may have features of sidewalls 632.

Unlike the method 500 including the recessed metal material 620, as shown in FIG. 7B, an additional structure can be formed by the present technique. As shown, the recessed metal material 620 may not be performed. The illustrated method can deposit cap material 625 directly onto metal material 620 after forming memory holes or channels 630. A similar method or operation of selectively depositing a capping material as described above can be performed, and the capping material (which can be a barrier material) can be any of the foregoing materials (eg, including titanium nitride).

The cover material may be formed to extend outward from the metal material 620 and extend within the channel 630. Similar to the previously described structure, the cover material 625 may not be formed on the dielectric material 610 or may not be continuous across the dielectric material 610 to create separation between each cell. After forming the cover material 625, additional operations (including cleaning any residual formation on the dielectric material 610, as well as formation of the barrier layer (e.g., alumina) and additional core formations) may be performed. By performing the method without the recess treatment, the stall time can be reduced, and surface roughening and other etching side effects can be limited.

In the previous description, numerous details have been set forth in order to provide an understanding of various embodiments of the present invention. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

The invention has been described in terms of a number of modifications, alternative constructions, and equivalents, which can be used in the art without departing from the spirit of the embodiments. Moreover, many of the known processes and elements are not described in order to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be taken as limiting the scope of the technology.

When a range of values is provided, it is to be understood that unless the context clearly dictates otherwise, each intermediate value between the upper and lower limits of the range is specifically disclosed. Any narrower range between any of the stated or non-described intermediate values in the range and any other stated or intermediate value in the range. Unless the stated range has any specific exclusions, the upper and lower limits of these smaller ranges may be independently included or excluded, and either or both of the upper and lower limits are included or not included. Each of the ranges is also included in the technology. Where the stated range includes one or two limitations, the scope of the one or both of the

The singular forms "a", "an" and "the" Thus, for example, reference to "a" or "an" or "an" or "an"

In addition, the words "including", "including", "including", "including", "including", and "including" are used in the specification and the following claims. The existence of a component, or operation, does not exclude the presence or addition of one or more other features, components, components, operations, acts, or groups.

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498‧‧‧ arrow

500‧‧‧ method

505‧‧‧ operation

510‧‧‧ operation

515‧‧‧ operation

520‧‧‧ operation

525‧‧‧ operation

600‧‧‧ structure

605‧‧‧Substrate

610‧‧‧ dielectric materials

620‧‧‧Metal materials

625‧‧‧ Cover material

630‧‧‧Channel

632‧‧‧ side wall

700‧‧‧ structure

A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the description and the accompanying drawings.

FIG. 1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

2B illustrates a detailed view of an exemplary showerhead in accordance with an embodiment of the present technology.

FIG. 3 illustrates a bottom plan view of an exemplary showerhead in accordance with an embodiment of the present technology.

FIG. 4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

FIG. 5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

6A through 6C illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

7A through 7B illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

Several of the figures are included as schematics. It should be understood that the drawings are for illustrative purposes only and should not be construed as a In addition, the drawings are provided as a schematic diagram to aid understanding, and may not include all aspects or information as compared to the actual representation, and may include exaggerated materials for illustrative purposes.

Similar components and/or features may have the same component symbols in the accompanying drawings. Furthermore, various components of the same type may be distinguished by the use of letters after the component symbols to distinguish similar components. If only the foremost component symbol is used in the specification, the description applies to any similar component having the same topmost component symbol, regardless of the letter.

Domestic deposit information (please note according to the order of the depository, date, number)

Foreign deposit information (please note in the order of country, organization, date, number)

Claims (20)

  1. A method of forming a semiconductor structure, the method comprising the steps of: forming a plasma of a fluorine-containing precursor in a distal plasma region of a processing chamber; contacting a semiconductor substrate with the effluent of the plasma Wherein the semiconductor substrate is housed in a processing region of the processing chamber; a metal material is selectively selectively etched laterally between exposed regions of a dielectric material on the semiconductor substrate; and subsequently deposited on the metal material A cover material, wherein the cover material is selectively deposited on the metal material relative to an exposed area of the dielectric material.
  2. A method of forming a semiconductor structure according to claim 1, wherein the etching step is performed in a first processing chamber, the depositing step being performed in a second processing chamber.
  3. The method of forming a semiconductor structure according to claim 2, further comprising the step of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without breaking the vacuum Execution in case of.
  4. A method of forming a semiconductor structure according to claim 1, wherein the metal material comprises tungsten or cobalt.
  5. A method of forming a semiconductor structure according to claim 1, wherein the dielectric material comprises ruthenium oxide.
  6. A method of forming a semiconductor structure according to claim 1, wherein the capping material comprises a metal nitride or a metal oxide.
  7. A method of forming a semiconductor structure as recited in claim 1, wherein the metal material is laterally etched from the sidewalls of the trench by less than 10 nm.
  8. A method of forming a semiconductor structure as recited in claim 1, wherein the etching step is performed using a selectivity of the metal material that is greater than or about 10:1 relative to the dielectric material.
  9. A method of forming a semiconductor structure as recited in claim 1, wherein the depositing is performed using a selectivity of the metal material that is greater than or about 2:1 relative to the dielectric material.
  10. A method of forming a semiconductor structure according to claim 1, wherein the step of selectively depositing the cap material comprises the step of suppressing growth of the cap material on the dielectric material.
  11. A method of forming a semiconductor structure, the method comprising the steps of: forming a plasma of a fluorine-containing precursor in a distal plasma region of a processing chamber; contacting a semiconductor substrate with the effluent of the plasma Wherein the semiconductor substrate is housed in a processing region of the processing chamber; a layer of a metallic material is selectively selectively etched between the exposed layers of a dielectric material on the semiconductor substrate; and subsequently in the metallic material A capping material is deposited thereon, wherein the capping material is selectively deposited on the metallic material relative to the exposed regions of the dielectric material.
  12. A method of forming a semiconductor structure as recited in claim 11, wherein the layers of tantalum nitride are laterally etched from the sidewalls of the channel by less than 10 nm.
  13. A method of forming a semiconductor structure according to claim 12, wherein the dielectric material comprises ruthenium oxide.
  14. A method of forming a semiconductor structure according to claim 13 wherein the capping material comprises a metal nitride or a metal oxide.
  15. A method of forming a semiconductor structure as described in claim 14, wherein the metal nitride comprises titanium nitride.
  16. A method of forming a semiconductor structure as recited in claim 11, wherein the etching step is performed in a first processing chamber, the depositing step being performed in a second processing chamber.
  17. The method of forming a semiconductor structure according to claim 11, further comprising the step of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without breaking the vacuum Execution in case of.
  18. A method of forming a semiconductor structure as described in claim 11, wherein the semiconductor substrate defines a plurality of channels, and wherein the metal material is etched on the plurality of surfaces.
  19. A method of forming a semiconductor structure as recited in claim 11, wherein the etching step is performed using a selectivity of the metal material that is greater than or about 10:1 relative to the dielectric material.
  20. A method of forming a semiconductor structure as recited in claim 11, wherein the depositing is performed using a selectivity of the metal material that is greater than or about 2:1 relative to the dielectric material.
TW107113501A 2017-04-20 2018-04-20 Structure with selective barrier layer TW201839849A (en)

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KR100655277B1 (en) * 1999-12-04 2006-12-08 삼성전자주식회사 Method of forming a common source line in nand type flash memory
US20070031609A1 (en) * 2005-07-29 2007-02-08 Ajay Kumar Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the same
KR100985881B1 (en) * 2008-05-28 2010-10-08 주식회사 하이닉스반도체 Flash memory device and method of manufacturing the same
TW201214631A (en) * 2010-06-30 2012-04-01 Sandisk Technologies Inc Ultrahigh density vertical NAND memory device and method of making thereof
US9806089B2 (en) * 2015-09-21 2017-10-31 Sandisk Technologies Llc Method of making self-assembling floating gate electrodes for a three-dimensional memory device

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