TW201839849A - Structure with selective barrier layer - Google Patents

Abstract

Processing methods may be performed to form semiconductor structures that may include three-dimensional memory structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma. The semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include selectively etching a metal material laterally between exposed regions of a dielectric material on the semiconductor substrate. The methods may also include subsequently depositing a cap material over the metal material. The cap material may be selectively deposited on the metal material relative to exposed regions of the dielectric material.

Description

Structure with selective barrier layer

This technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to a system and method for selectively etching and selectively depositing a material layer on a semiconductor device.

The integrated circuit may be made by a process of generating an intricately patterned material layer on the surface of the substrate. Creating a patterned material on a substrate requires a control method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring a pattern in a photoresist to a layer underneath, thinning a layer, or thinning lateral dimensions of a feature that has been presented on a surface. It is often desirable to have an etch process that etches one material faster than another to facilitate, for example, a pattern transfer process or individual material removal. This etching process is said to be selective for the first material. Due to the diversity of materials, circuits, and processes, selective etching processes have been developed for a variety of materials. However, a blanket coating or a conformal fill is typically used to continue the deposition process across the substrate.

As device size continues to shrink in next-generation devices, selectivity can play a greater role when the material formed in a particular layer is only a few nanometers (especially when the material is critical in the formation of transistors). Many different etch process selectivities have been developed between materials, but standard selectivity may no longer be applicable to current and future device scales. In addition, based on the number of masking, forming, and removing operations required to form and protect various key dimensions across device features, the queue time for processing continues to increase while patterning and forming are performed elsewhere on the substrate.

Therefore, there is a need for a system and method that can be used to produce high-quality devices and structural improvements. This technology addresses these and other needs.

A processing method may be performed to form a semiconductor structure that may include a three-dimensional memory structure. The method may include the step of forming a plasma of a fluorine-containing precursor in a distal plasma region of the processing chamber. The method may include the step of contacting the semiconductor substrate with the effluent of the plasma. The semiconductor substrate may be housed in a processing area of the processing chamber. The method may include the step of laterally selectively etching the metal material between the exposed regions of the dielectric material on the semiconductor substrate. The method may also include the step of subsequently depositing a capping material on the metallic material. The cap material may be selectively deposited on the metal material relative to the exposed area of the dielectric material.

In some embodiments, etching may be performed in a first processing chamber and deposition may be performed in a second processing chamber. The method may also include the steps of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring may be performed without breaking the vacuum. The metallic material may include tungsten or cobalt. The dielectric material may include silicon oxide. The cover material may include a metal nitride or a metal oxide. Metallic materials can be etched laterally from the sidewall of the channel to less than 10 nm. Etching may be performed with a selectivity of a metal material relative to a dielectric material of greater than or about 10: 1. Deposition may be performed with a selectivity of metallic materials relative to dielectric materials greater than or about 2: 1. In addition, in some embodiments, the step of selectively depositing the capping material may include the step of inhibiting the growth of the capping material on the dielectric material.

The technology of the present invention also includes a method of forming a semiconductor structure. The method may include the step of a plasma of a fluorine-containing precursor formed in a plasma region of a distal end of the processing chamber. The method may include the step of contacting the semiconductor substrate with the effluent of the plasma. The semiconductor substrate may be housed in a processing area of the processing chamber. The method may include the step of laterally and selectively etching the metal material layer between the exposed layers of the dielectric material on the semiconductor substrate. The method may also include the step of subsequently depositing a capping material on the metallic material. The cap material may be selectively deposited on the metal material relative to the exposed area of the dielectric material.

In some embodiments, the silicon nitride layer can be etched laterally from the sidewall of the channel to less than 10 nm. The dielectric material may be silicon oxide, or may include silicon oxide. The cover material may be a metal nitride or a metal oxide, or may include a metal nitride or a metal oxide. The metal nitride may be titanium nitride, or may include titanium nitride. Etching may be performed in the first processing chamber, and deposition may be performed in the second processing chamber. The method may also include the steps of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring may be performed without breaking the vacuum. A semiconductor substrate can define multiple channels, and metal materials can be etched on multiple surfaces. Etching may be performed with a selectivity of a metal material relative to a dielectric material of greater than or about 10: 1. Deposition may be performed with a selectivity of metallic materials relative to dielectric materials greater than or about 2: 1.

Such techniques can provide many benefits over conventional systems and techniques. For example, these processes can enable smaller devices due to the improved structure. In addition, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time and allow formation of difficult-to-form structures. These and other embodiments, and many of their advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

The technology of the present invention includes systems and components for semiconductor processing with small pitch features. When converting from 2D NAND to 3D NAND, many processing operations are modified from vertical to horizontal operations in order to etch and form material layers laterally. In addition, as the number of cells formed by the 3D NAND structure grows, the aspect ratio of memory holes and other structures sometimes increases significantly. In conventional 3D NAND processing, the stacking of the placeholder layer and the dielectric material can form a dielectric or IPD layer between the electrodes. These placeholder layers can have a variety of operations to place structures before the placeholder material is completely removed and replaced with metal. As device size continues to shrink, the aspect ratio of the placeholder layer may increase as the width and depth increase. Therefore, when the material is removed and replaced with metal, full filling may be more difficult. In addition, seams may be formed in the metal layer, which may affect device performance or may damage the device.

Many conventional techniques use wet etching to access each unit of placeholder material to perform lateral etching of the placeholder before incorporation of metal. Due to the high aspect ratio of the memory holes, which may not allow symmetrical etching to be performed, dry etching may not be feasible in conventional techniques. However, wet etching may be more robust than other etching techniques, and wet etching may etch materials other than placeholder materials and cause damage within the structure, which may weaken the structure and cause deformation. Subsequent metallization may be incomplete or create seams or voids within the layers of the structure. The resulting memory unit may have a reduced capacity or may malfunction. In addition, due to the problem of the core oxide filling operation and the problem of adhesion with other materials, the conventional technology cannot be converted into the original metal structure.

The technology of the present invention overcomes these problems by forming a structure that avoids the conventional placeholder removal operation. In conventional batteries using oxide and nitride materials called ONON, the technology may not include alternative materials and may form metallization directly. These new structures (think of oxide and metal structures, or OMOM) can overcome the need to extract placeholder materials and deposit metals. By forming the initial structure including metallization, the problems described can be avoided. This technology allows these structures to be formed by using selectively deposited barrier layers to separate nodes and increase the adhesion capabilities of subsequently deposited materials (eg, oxides and other core materials). By selectively depositing the barrier layer, complete node separation can be performed without the need for an etch-back process that further extends within the metal layer.

Although the remaining disclosure will routinely identify specific etching and deposition processes utilizing the disclosed technology, it should be understood that the systems and methods are equally applicable to various other etching, deposition, and cleaning processes that may occur in the described chambers . Therefore, this technique should not be considered limited to the etching and deposition processes that can only be used. This disclosure will discuss one possible system and chamber that can be used with the present technology to perform certain removal and deposition operations before the described operations of an exemplary processing sequence according to the present technology.

FIG . 1 illustrates a top plan view of one embodiment of a processing system 100 of a deposition, etching, baking, and curing chamber according to an embodiment. In the drawing, a pair of front opening unified pods (FOUP) 102 supply substrates of various sizes. The substrates of various sizes are received by the robot arm 104 and placed in a substrate processing chamber 108a located in the tandem section 109a-c. One of -f is placed in the low-voltage holding area 106. The second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate processing, Each substrate processing chamber 108a-f may be equipped to perform a large number of substrate processing operations including dry etching processes and selective deposition as described herein.

The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (eg, 108c-d and 108e-f) can be used to deposit a dielectric or metal-containing material on a substrate, while a third pair of processing chambers (eg, 108a-b) Can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (eg, 108a-f) may be configured to etch a dielectric film on a substrate. Any one or more of the processes described may be performed in a chamber separate from the manufacturing system shown in the different embodiments.

In some embodiments, the chamber specifically includes at least one etching chamber as described below and at least one deposition chamber as described below. By including these chambers and combining the processing side of the factory interface, all of the etching and deposition processes described below can be performed in a controlled environment. For example, a vacuum environment can be maintained on the processing side of the holding area 106, so that all chambers and transfers in the embodiment are maintained under vacuum. This also restricts water vapor and other air components from contacting the substrate during processing. It should be understood that the system 100 may consider additional configurations for deposition, etching, annealing, and curing chambers of the dielectric film.

FIG . 2A illustrates a cross-sectional view of an exemplary processing chamber system 200 having a separate plasma generation area within a processing chamber. During film etching (eg, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), the process gas can pass through The gas inlet assembly 205 flows into the first plasma region 215. A remote plasma system (RPS) 201 may optionally be included in the system and may process the first gas that subsequently travels through the gas inlet assembly 205. The inlet assembly 205 may include two or more different gas supply channels, and if a second channel (not shown) is included, the second channel may bypass the RPS 201.

The cooling plate 203, the panel 217, the ion eliminator 223, the shower head 225, and the substrate support 265 having the substrate 255 disposed thereon are illustrated, and each may be included according to an embodiment. The pedestal 265 may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate, and the temperature of the substrate may be manipulated during a processing operation to heat and / or cool the substrate or wafer. Embedded resistance heater elements may also be used and resistance heating may include wafer support trays of aluminum, ceramic, or a combination of pedestals 265 to achieve relatively high temperatures, such as from up to or about 100 ° C to above or about 1100 ° C .

The panel 217 may be pyramid-shaped, conical, or other similar structures having a narrow top portion extending to a wide bottom portion. As shown, in addition, the panel 217 may be flat and include a plurality of through-channels for distributing processing gas. Depending on the use of the RPS 201, the plasma-producing gas and / or the plasma-exciting substance may pass through the plurality of holes in the panel 217 as shown in FIG. 2B for more uniform delivery into the first plasma region 215.

An exemplary configuration may include the gas inlet assembly 205 accessing a gas supply region 258 separated by the panel 217 from the first plasma region 215 so that gas / substance flows through the holes in the panel 217 into the first plasma region 215. The structure and operating characteristics may be selected to prevent a large amount of plasma from the first plasma region 215 from flowing back into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The panel 217 or the conductive top portion of the chamber and the showerhead 225 are shown, with an insulating ring 220 located between the features to allow an AC potential to be applied to the panel 217 relative to the showerhead 225 and / or the ion canceller 223 . The insulating ring 220 may be positioned between the panel 217 and the shower head 225 and / or the ion eliminator 223 so that a capacitive coupling plasma (CCP) can be formed in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid into the region through the gas inlet assembly 205.

The ion eliminator 223 may include a plate-like or other geometry defining a plurality of pores through the structure, the plurality of pores being configured to eliminate migration of ionic charged substances leaving the first plasma region 215 while allowing uncharged neutrality Or the free radical species passes through the ion eliminator 223 into the active gas delivery area between the eliminator and the showerhead. In an embodiment, the ion eliminator 223 may include a multiwell plate having various pore configurations. These uncharged materials may include highly reactive materials that are transported through the pores using less reactive gas carrier. As mentioned above, the migration of ionic species through pores may be reduced and, in some cases, completely eliminated. Controlling the amount of ionic species passing through the ion eliminator 223 may advantageously provide increased control of the gas mixture in contact with the underlying wafer substrate, which in turn may increase control of the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture can significantly change its etching selectivity, for example, SiNx: SiOx etching rate, Si: SiOx etching rate, and the like. In an alternative embodiment where the deposition is performed, the balance of the conformal flow deposition of the dielectric material may also be translated.

The plurality of pores in the ion canceller 223 may be configured to control the passage of the reactive gas (ie, ions, free radicals, and / or neutral substances) through the ion canceller 223. For example, the aspect ratio of the pores, or the diameter of the pores versus the length, and / or the geometry of the pores can be controlled so that the flow of ionic charged substances in the active gas passing through the ion canceller 223 is reduced. The holes in the ion eliminator 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and sized to control the flow of ionic material to the showerhead 225. As an additional means of controlling the flow of ionic species through the eliminator, an adjustable electrical bias can also be applied to the ion eliminator 223.

The ion canceller 223 may be used to reduce or eliminate the amount of ionic charged substances traveling to the substrate from the plasma generation area. Uncharged neutral and free radical species can still pass through openings in the ion eliminator and react with the substrate. It should be noted that in the embodiment, the complete elimination of the ion-charged substance in the reaction region surrounding the substrate may not be performed. In some cases, ionic substances are intended to reach the substrate to perform an etching and / or deposition process. In these cases, the ion eliminator can help control the concentration of ionic species in the reaction zone at a level that facilitates processing.

The showerhead 225 combined with the ion eliminator 223 may allow the plasma existing in the first plasma region 215 to avoid direct excitation of the gas in the substrate processing region 233 while still allowing the excited substance to travel from the chamber plasma region 215 Go to the substrate processing area 233. In this manner, the chamber may be configured to prevent the plasma from contacting the substrate 255 during the etching. This can advantageously protect various complex structures and films patterned on the substrate. If they are in direct contact with the generated plasma, the various complex structures and films may be damaged, displaced, or otherwise bent. In addition, when plasma is allowed to contact the substrate or approach the substrate level, the rate of oxide species etching may increase. Therefore, if the exposed area of the material is an oxide, the material can be further protected by maintaining a plasma on the substrate remotely.

The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, the ion eliminator 223, the shower head 225, and / or the pedestal 265 to provide a first plasma area 215 or Plasma is generated in the processing area 233. Depending on the processing performed, the power supply may be configured to deliver an adjustable amount of power to the chamber. This configuration may allow a tunable plasma to be used for processing in progress. Unlike a remote plasma unit, which typically appears to have an on or off function, a tunable plasma can be configured to deliver a specific amount of power to the plasma area 215. This can in turn allow the formation of specific plasma characteristics, so that the precursors can be dissociated in a specific way to enhance the etch profile produced by these precursors.

The plasma may be excited in a chamber plasma region 215 above the shower head 225 or a substrate processing region 233 below the shower head 225. In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed using a pedestal as an electrode. Plasma may be present in the chamber plasma region 215 to generate free radical precursors from, for example, influx of fluorine-containing precursors or other precursors. Typically, an AC voltage in the radio frequency (RF) range may be applied between the conductive top portion of the processing chamber (eg, panel 217) and the showerhead 225 and / or ion canceller 223 to excite the chamber during deposition The plasma in the chamber plasma region 215. The RF power supply can generate a high RF frequency of 13.56MHz, but it can also generate other frequencies alone or in combination with 13.56MHz.

FIG . 2B illustrates a detailed view 253 of the characteristics affecting the distribution of the process gas through the panel 217. As shown in FIG. 2A and FIG. 2B, the panel 217, the cooling plate 203, and the gas inlet assembly 205 intersect to define a gas supply region 258, in which a process gas can be delivered from the gas inlet 205 into the gas supply region 258. The gas may fill the gas supply region 258 and flow through the pores 259 in the panel 217 to the first plasma region 215. The apertures 259 may be configured to direct the flow in a substantially unidirectional manner so that the process gas may flow into the processing region 233, but may be partially or completely prevented from flowing back into the gas supply region 258 after passing through the panel 217.

The gas distribution assembly (for example, the shower head 225 for the processing chamber section 200) may be referred to as a dual-channel shower head (DCSH) and is additionally explained in detail in the embodiment described in FIG. The dual channel showerhead may provide an etching process to allow the etchant to be separated outside the processing area 233 to provide limited interaction with the chamber components and each other before delivery to the processing area.

The shower head 225 may include an upper plate 214 and a lower plate 216. The plates can be coupled to each other to define a volume 218 between the plates. The coupling of the plates may provide a first fluid passage 219 through the upper and lower plates and a second fluid passage 221 through the lower plate 216. The formed channel may be configured to provide fluid access from the volume 218 through the lower plate 216 via the second fluid channel 221 alone, while the first fluid channel 219 may be fluidly isolated from the volume 218 between the plate and the second fluid channel 221. The volume 218 can be accessed by fluid from one side of the gas distribution assembly 225.

FIG . 3 is a top view of a shower head 325 for use with a processing chamber according to an embodiment. The shower head 325 may correspond to the shower head 225 shown in FIG. 2A. The through hole 365 (view illustrating the first fluid channel 219) may have a plurality of shapes and configurations to control and influence the flow of the precursor through the shower head 225. The small holes 375 (showing the view of the second fluid channel 221) can be distributed substantially evenly on the surface of the showerhead (even in the through-holes 365), and can help the precursor to provide a specific Other configurations mix more evenly.

Turning to FIG . 4 , a schematic cross-sectional view of an atomic layer deposition system 400 or a reactor according to one or more embodiments of the present technology is illustrated. The system 400 may include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 may generally be a sealable enclosure and may be operated under vacuum or at least low pressure. The processing chamber 20 may be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 may seal the processing chamber 20 and the loading lock chamber 10 in a closed position, and may allow the substrate 60 to be transferred from the loading lock chamber 10 to the processing chamber 20 through a valve in the open position, and vice versa.

The system 400 may include a gas distribution plate 30 capable of distributing one or more gases across the substrate 60. The gas distribution plate 30 may be any suitable distribution plate known to those having ordinary skill in the art, and the specific gas distribution plate described should not be considered as limiting the scope of the technology. The output surface of the gas distribution plate 30 may face the first surface 61 of the substrate 60.

The gas distribution plate 30 may include a plurality of gas ports and a plurality of vacuum ports. The plurality of gas ports are configured to transmit one or more gas flows to the substrate 60, and the plurality of vacuum ports are disposed between each gas port. It is configured to convey a gas flow outside the processing chamber 20. As shown in FIG. 4, the gas distribution plate 30 may include a first precursor syringe 420, a second precursor syringe 430, and a purge gas syringe 440. The injectors 420, 430, 440 may be controlled by a system computer (not shown) (eg, a host), or by a chamber-specific controller (eg, a programmable logic controller). The precursor injector 420 may be configured to inject a continuous or pulsed stream of the reactive precursor of the compound A into the processing chamber 20 through a plurality of gas ports 425. The precursor injector 430 may be configured to inject a continuous or pulsed stream of a reactive precursor of the compound B into the processing chamber 20 through a plurality of gas ports 435. The purge gas injector 440 may be configured to inject a continuous or pulsed stream of non-reactive or purge gas through the plurality of gas ports 445 into the processing chamber 20. The purge gas may be configured to remove reaction materials and reaction byproducts from the processing chamber 20. The purge gas is typically an inert gas, such as nitrogen, argon, and helium. The gas port 445 may be disposed between the gas port 425 and the gas port 435 to separate the precursor of the compound A from the precursor of the compound B, thereby avoiding cross-contamination between the precursors.

In another aspect, a remote plasma source (not shown) may be connected to the precursor injector 420 and the precursor injector 430 before the precursor is injected into the processing chamber 20. The plasma of the reactive material can be generated by applying an electric field to a compound in a remote plasma source. Any power source capable of activating the desired compound can be used. For example, power sources using DC, RF, and microwave discharge technologies can be used. If an RF power source is used, it can be coupled capacitively or inductively. Activation can also be generated by thermal-based technology, gas dissociation technology, high-intensity light sources (eg, ultraviolet light sources), or exposure to x-ray sources.

The system 400 may further include a pumping system 450 connected to the processing chamber 20. The pumping system 450 may be generally configured to evacuate a gas flow outside the processing chamber 20 through one or more vacuum ports 455. A vacuum port 455 may be disposed between each gas port to evacuate the gas flow outside the processing chamber 20 after the gas flow reacts with the substrate surface, and further limit cross-contamination between precursors.

The system 400 may include a plurality of partitions 460 disposed on the processing chamber 20 and between each port. The lower portion of each partition may extend close to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61). In this manner, the lower portion of the partition 460 may be separated from the substrate surface by a distance sufficient to allow the gas flow to flow around the lower portion and toward the vacuum port 455 after the gas flow reacts with the substrate surface. Arrow 498 indicates the direction of the gas flow. Since zone 460 is operable as a physical barrier to gas flow, zone 460 can also limit cross-contamination between precursors. The configurations shown are merely illustrative and should not be considered as limiting the scope of the technology. Those of ordinary skill in the art will understand that the gas distribution system shown is only one possible distribution system, and other types of sprinklers may be used.

In operation, the substrate 60 can be delivered (eg, by a robot) to the loading gate chamber 10 and can be placed on a shuttle 65. After the isolation valve 15 is opened, the shuttle 65 can be moved along the rail 70. Once the shuttle 65 enters the processing chamber 20, the isolation valve 15 may be closed to seal the processing chamber 20. The shuttle 65 can then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a linear path.

As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 may be repeatedly exposed to the precursor of the compound A from the gas port 425 and the precursor of the compound B from the gas port 435 with the gas port 445 in between. Purge gas. The purge gas injection can be designed to remove unreacted material from the previous precursor before exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas stream can be evacuated by the pumping system 450 through the vacuum port 455. Since vacuum ports can be provided on both sides of each gas port, the gas flow can be evacuated through the vacuum ports 455 on both sides. Therefore, the gas flow can flow vertically downward from the individual gas ports toward the first surface 61 of the substrate 60, span the first surface 410 and surround the lower portion of the partition 460, and finally face the vacuum port 455 upward. In this manner, each gas can be uniformly distributed across the substrate surface 61. The substrate 60 may also be rotated when exposed to various gas flows. The rotation of the substrate may be useful to prevent the formation of stripes in the formed layer. The rotation of the substrate can be a continuous or separate step.

The degree to which the substrate surface 61 is exposed to each gas can be determined by, for example, the flow rate of each gas from the gas port and the movement rate of the substrate 60. In one embodiment, the flow rate of each gas may be configured without removing absorbed precursors from the substrate surface 61. The width between each partition, the number of gas ports provided on the processing chamber 20, and the number of times the substrate may be transferred back and forth may also determine the degree to which the substrate surface 61 is exposed to various gases. Therefore, the quantity and quality of the deposited film can be optimized by changing the above factors.

In another embodiment, the system 400 may include a precursor injector 420 and a precursor injector 430 without a purge gas injector 440. Therefore, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the precursor of the compound A and the precursor of the compound B without being exposed to the purge gas therebetween.

The embodiment shown in FIG. 4 includes a gas distribution plate 30 above the substrate. Although embodiments have been described and illustrated for this upright orientation, it should be understood that the opposite orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downward, and the gas flowing toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate.

In some embodiments, the shuttle 65 may be a base 66 for carrying the substrate 60. Generally, the pedestal 66 may be a carrier that helps to form a uniform temperature across the substrate. The base 66 can be moved in the left-to-right and left-to-right directions between the loading lock chamber 10 and the processing chamber 20 relative to the arrangement of FIG. 4. The base 66 may have a top surface 67 for carrying the substrate 60. The pedestal 66 may be a heated pedestal such that the substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by a radiant heat source 90, a heating plate, a resistance coil, or other heating device disposed below the susceptor 66. Although illustrated as a lateral conversion, an embodiment of the system 400 can also be used in a rotary system where the wheels can be rotated clockwise or counterclockwise to continuously process one or more substrates below the illustrated gas distribution system. It should be similarly understood that additional modifications are included in the present technology.

FIG . 5 illustrates a method 500 of forming a semiconductor structure, many of which can be performed in, for example, the aforementioned chambers 200 and 400. The method 500 may include one or more operations before starting the method, and include front-end processing, deposition, etching, grinding, cleaning, or any other operation that may be performed before the operations. The method may include a number of selectable operations as shown in the drawings, which may or may not be specifically associated with a method according to the present technology. For example, many operations are described in order to provide a wider range of structure formation, but are not critical to the technology or can be performed by alternative methods, which will be discussed further below. Method 500 is described first. 6A through 6C schematically illustrated in FIG operation of the method 500 in conjunction with the operation described in the description. It should be understood that FIG. 6 illustrates only a partial schematic diagram, and the substrate may include any number of transistor sections having a state as shown in the drawing.

The method 500 may involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate including a region further developed to produce a 3D NAND structure. As shown in FIG. 6A, a portion of the processed structure 600 including the substrate 605 is illustrated, and may have a plurality of stacked layers covering the substrate, and may be silicon, germanium silicide, or other substrate materials. The layers may include a memory for producing a dielectric material 610 (which may be an oxide (eg, silicon oxide)) including an alternating layer having a metallic material 620 (which may be tungsten, cobalt, or other low-resistivity metal). Body node layer. Although only 7 layers of material are illustrated, the exemplary structure may include any number of layers, such as up to or greater than about 10, greater than or about 15, greater than or about 20, greater than or about 25, greater than or about 30, greater than or about 35 , Greater than or about 40, greater than or about 45, greater than or about 50, greater than or about 55, greater than or about 60, greater than or about 65, greater than or about 70, greater than or about 80, greater than or about 90, greater than or about one Hundreds or more layers of material.

The channel 630 (which may be a memory hole) may be defined to a level of the substrate 605 through a stacked structure. The channel 630 may be defined by a sidewall 632, and the sidewall 632 may be composed of alternating layers of a dielectric material 610 and a metal material 620. Although the rest of the disclosure will discuss tungsten and silicon oxide, any other known material with similar operating characteristics can replace one or more layers. Some or the owners of these operations may be performed in the aforementioned chamber or system tool, or may be performed in different chambers on the same system tool, and the system tool may include a chamber to perform the operations of method 400.

The method 500 may initially include the step of recessing the metallic material 620 as shown in FIG. 6B. The metallic material 620 may be recessed in an etching chamber similar to the chamber 200 described previously. In some embodiments, wet etching or other dry etching may be performed. However, the following describes one possible process for laterally removing tungsten or metallic materials from within the memory holes. Once positioned within the processing region of the semiconductor processing chamber, the method may include forming a plasma of a fluorine-containing precursor in a distal plasma region of the processing chamber at operation 505. The distal plasma region can be fluidly coupled to the processing region, but can be physically separated to confine the plasma at the substrate level, which can damage exposed structures or materials.

The effluent of the plasma may flow into the processing area and may be in contact with the semiconductor substrate at operation 510. At operation 515, the metallic material may be selectively etched laterally with respect to the exposed area of the dielectric material 610. The lateral etch may be performed through a channel (eg, a memory hole) and may occur along the exposed portion of each layer of the metallic material 620 (eg, tungsten) on the sidewalls within the channel. In some embodiments, the lateral etch may be selectively performed on the metal material layer and may substantially maintain an intervening layer of silicon oxide or other dielectric material. Further, as shown, etching may be performed on multiple surfaces of the metal material 620 (eg, opposite sides in and out of multiple channels or memory holes). Prior to the end of the lateral etch operation, the method 500 may etch the metal material laterally from the sidewalls of the channel and between the exposed layers of the dielectric material 610 to less than 50 nm in an exemplary operation. In some embodiments, the method 500 may etch a metal material laterally less than or about 45 nm, less than or about 40 nm, less than or about 35 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or About 10nm, less than or about 9nm, less than or about 8nm, less than or about 7nm, less than or about 6nm, less than or about 5nm, less than or about 4nm, less than or about 3nm, less than or about 2nm, less than or about 1nm, or more small.

The method 500 may involve reducing the etch rate to allow more complete diffusion to occur while helping to provide a more uniform etch from top to bottom. Without the technique described below, regions of metallic material at or near the top of the channel may begin to etch before the bottom region. This may then create a profile within the channel, such as a V-shaped profile of the metal material layer from the top to the bottom of the channel. This can happen, for example, when the amount of fluorine in the mixture increases or the temperature increases.

In the case of using a conventional dry technique, a V-shaped profile may be unavoidable because a high aspect ratio of a channel or a memory hole that can perform lateral etching. The diameter or width of an exemplary channel may be tens of nanometers or less, while the height of the channel may be several micrometers or more. This may result in an aspect ratio greater than 20: 1, greater than 50: 1, greater than 75: 1, greater than 100: 1, or even greater, or a height-to-width ratio. Therefore, in embodiments, more than 25 layers, more than 50 layers, more than 75 layers, or more than one hundred layers of alternating metal materials and dielectric materials can be formed and processed in each channel.

Because dry or gaseous etchant can travel a greater length, the top area of the trench may be exposed to a significant amount of etchant even before the etchant has reached the bottom of the trench. In this way, the metal material located in the upper region of the channel may be etched more than a portion at the bottom of the channel. Although the wet etching technology can etch the metal material layer more uniformly, due to the nature and dwell time of the etchant, the etching may not be smaller than, reach, or about 10 or more nanometers. Therefore, unlike this technique, conventional techniques may not be able to finely etch a certain amount of material from each metal material layer (for example, only a few nanometers), and may not produce a flat or substantially similar etched metal material in the entire channel. profile. However, the present technique can compensate for larger diffusion paths by restricting the etchant in any manner discussed to allow more uniform etch processing to occur.

Processing conditions may also affect operations performed in the method 500 and other etching methods according to the present technology. Each of the operations of method 500 may be performed during a constant temperature in an embodiment, and in some embodiments, the temperature may be adjusted during different operations. For example, in an embodiment, the substrate, pedestal, or chamber temperature during the lateral etching operation 515 may be maintained between about -100 ° C and about 100 ° C. The temperature can also be maintained below or about 80 ° C, below or about 60 ° C, below or about 40 ° C, below or about 20 ° C, below or about 0 ° C, below or about -20 ° C, below Or about -40 ° C, or lower. Temperature can affect the etch process itself, while higher temperatures can result in higher etch rates, increased etch, or other effects. Similarly, lower temperatures can slow the etch operation and allow improved diffusion. Therefore, in some embodiments, maintaining a temperature below or about 50 ° C or below or about 0 ° C may provide a more uniform amount of etched metal material at the top of the channel and at the bottom of the channel. As the temperature increases, the etch operation can additionally begin to affect the dielectric region and can cause exposed corners or slightly rounded regions of the dielectric material (eg, silicon oxide).

The pressure in the chamber can also affect the operations performed, and in embodiments, the chamber pressure can be maintained below about 10 Torr, below about 5 Torr, or below about 1 Torr. In embodiments, pressures below or about 1 Torr may allow precursors or plasma effluents to flow more easily into channels or memory holes. However, when the pressure decreases below about 0.5 Torr, the distal plasma may be affected and may have reduced stability or may become unstable. As mentioned earlier, the remote plasma may include an RPS unit, and may also be an area or portion of a chamber that is physically separated from the processing area of the chamber to limit or eliminate the plasma at the substrate level. In some embodiments using an RPS unit, for plasma stability with lower pressure in the chamber, a choke can be used to maintain higher pressure in the RPS unit for improving precursors or plasma effluent Flowing in the channel. Therefore, a turbomolecular pump can be used in the chamber to allow the chamber pressure to be reduced to a few milli Torr while the RPS is maintained above 0.6 Torr or about 0.6 Torr.

Chamber conditions, flow rate ratios, and other operating characteristics can be adjusted to perform controlled etching of metallic materials. For example, depending on the thickness of the material to be deposited, each region of the metallic material from the channel sidewalls can be etched laterally to a distance or depth of less than or about 10 nm, or any of the foregoing thicknesses. In an embodiment, each layer of the metal material may be etched to a depth or distance from the channel sidewall between about 1 nm and about 7 nm, or between about 2 nm and about 6 nm.

By performing an operation according to the present technology, the etching power can be reduced relative to the diffusion ability of the etchant material, which can allow a more uniform, substantially uniform, execution at each metal material region exposed within the channel or memory hole. Or substantially uniform etching. In an embodiment, a region of metallic material at or near the top of a channel or memory hole (eg, within 2 layers, 4 layers, 6 layers, 8 layers, Within 10 layers, or more), the amount of etched material measured from the side wall may be at or near the bottom of the channel of the memory hole, or a metal material layer or region (eg, from the bottom) 2 floors, 4 floors, 6 floors, 8 floors, 10 floors, or more).

Depending on the total number of stacked layers of etched channels or memory holes in the structure, the two layers compared may be at least 1 layer, at least 5 layers, at least 11 layers, at least 21 layers, at least 51 layers, or more Many and separate. As far as the upper layer is etched, the lateral etching of the two layers being compared may differ by less than or about 30%, and not more than 30% from the lower layer. In addition, the present technology can perform lateral etching of two layers such that the difference between the amounts of metal materials etched between the two layers is less than or about 25%, less than or about 20%, less than or about 15%, less than or About 10%, less than or about 5%, less than or about 1%, or zero difference. In this case, the two regions of the metal material are etched to an equal depth or distance from the sidewall of the channel. The substrate 605 may exhibit a minimum etch at the bottom of the channel 630, and may reduce an amount of less than or about 5 nm, and may reduce an amount of less than or about 3 nm, an amount of less than or about 2 nm, an amount of less than or about 1 nm, or may The metal material remains substantially unchanged during the lateral etching operation.

At optional operation 520, the substrate may be transferred from the etching chamber to the deposition chamber. The transfer can be performed under vacuum, and both chambers can reside on the same cluster tool to allow the transfer to take place in a controlled environment. For example, vacuum conditions can be maintained during transfer, and transfer can be performed without breaking the vacuum. Once in a deposition chamber (such as the above-mentioned chamber 400), at operation 525, a capping material may be formed or deposited on the recessed metal material 620. As shown in FIG. 6C, the cover material 625 (which may be a barrier material) may be directly formed on or in contact with the recessed metal material 620. The deposition operation may be selective deposition, where the capping material is preferably formed on the metallic material 620 relative to the exposed dielectric material 610. In contrast to conventional techniques, which may include additional masking operations, operation 525 may directly perform subsequent etching operations 515.

Although substrate transfer can be performed, other substrate processing may not be performed between selective etching and selective deposition. As will be explained in further detail below, although substrate transfer between operations may be performed in embodiments, and selective deposition may include multiple operations, the entire deposition process may be performed directly after a set of etching operations. Since blanket deposition or formation of the cover material 625 may require additional masking and removal techniques, by performing selective etching and selective deposition according to the method 500, the queue time can be significantly reduced compared to conventional techniques.

Various materials can be used in the process, and etching and deposition can be selective for multiple parts. Therefore, the present technology may not be limited to a single set of materials. For example, as mentioned above, the metal material 620 may be several conductive substances used in semiconductor processing. The metal material 620 may be or may include tungsten, cobalt, or any other conductive metal that may serve as a metal layer in the memory structure. The dielectric material 610 may also include an insulating material, and may also include a silicon-containing material, an oxygen-containing material, a carbon-containing material, or some combination of these materials (for example, silicon oxide or silicon oxycarbide). The cover material 625 may include one or more dielectric materials, insulating materials, ceramic materials, or barrier materials.

The cover material 625 can be used on tungsten for a variety of purposes. In some embodiments, titanium nitride can be used as the cover material 625, but it should be understood that similar materials can be used, including other metal nitrides, oxides, or dielectric materials. Titanium nitride can be used as a barrier on tungsten. However, in many conventional depositions, a capping material can also be formed on the dielectric material 610, which can then allow connections between separate nodes or layers. Therefore, an etch-back process can be performed. When the material is recessed from the dielectric, the treatment can be similar to tungsten or metallic materials to reduce the cover material due to minimal coverage or bonding, and tungsten can be exposed.

Subsequent operations to form the memory structure may include depositing additional core materials, and may include a barrier layer (eg, alumina). Although alumina can be deposited on dielectric materials, tungsten and other metals may have low adhesion capabilities, while alumina may not be easily deposited on this material, which may cause voids in the barrier layer. The formation of aluminum oxide on exposed tungsten can also oxidize metals and increase resistance. Titanium nitride and other barrier layer materials can adhere to tungsten as a barrier layer and allow aluminum oxide to be formed along the sidewalls. Therefore, by using a cap material 625 (for example, a titanium nitride barrier layer), an oxide metal NAND structure can be more easily produced.

Etching operations may involve additional precursors along with specific fluorine-containing precursors. In some embodiments, nitrogen trifluoride can be used to generate a plasma effluent. Additional or alternative fluorine-containing precursors can also be used. For example, the fluorine-containing precursor can flow into the remote plasma region, and the fluorine-containing precursor can include a group selected from atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, six At least one precursor of the group of sulfur fluoride and xenon difluoride. The distal plasma region can be in a different module from the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the RPS unit 201 and the first plasma region 215 can be used as the remote plasma region. The RPS may allow dissociation of the plasma effluent without damaging other chamber components, while the first plasma region 215 may provide a shorter path length to the substrate during which reorganization may occur.

Additional precursors can also be delivered to the distal plasma area to enhance fluorine-containing precursors. For example, carbon and hydrogen containing precursors or hydrogen precursors can be delivered with fluorine containing precursors. For example, the additional precursor may also be a fluorine-containing precursor (eg, fluoromethane). Hydrogen-containing or carbon- and hydrogen-containing precursors may be included to maintain a specific H: F atomic ratio for the plasma effluent. In an embodiment, the etching may be performed with a H: F ratio greater than 1, which may provide increased selectivity to tungsten or other metals relative to the dielectric materials described above. In an embodiment, the H: F atomic flow ratio can be maintained greater than 2: 1 or greater than 3: 1, which can be controlled by adjusting the relative flow rates of the fluorine-containing precursor and the hydrogen-containing precursor.

When the method is performed, the etching selectivity of tungsten relative to other components exposed on the surface of the substrate may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 50: 1, or greater than or About 100: 1 or more for various materials formed on a substrate and can be exposed to plasma effluent. In the disclosed embodiment, the etch selectivity of tungsten relative to (poly) silicon may be greater than or about 100: 1, greater than or about 150: 1, greater than or about 200: 1, or greater than or about 250: 1. In an embodiment, the etch selectivity of tungsten relative to silicon oxide may be greater than or about 15: 1, greater than or about 25: 1, greater than or about 30: 1, or greater than or about 40: 1. In an embodiment, the etch selectivity of tungsten relative to silicon oxycarbide may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 30: 1, or greater than or about 40: 1. In an embodiment, the etch selectivity of tungsten relative to tungsten oxide may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 50: 1, or greater than or about 100: 1.

Therefore, depending on the feature size, tungsten can be removed from the surface of the substrate, while other exposed materials can be reduced by less than 1 nm. In an embodiment, the depth of the recess for the metal material 620 may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. Due to this etch depth, the minimum amount of dielectric material can be removed, can be less than or about 3 nm, less than or about 1 nm, less than or about 0.5 nm, or the material can be maintained substantially or substantially unchanged. Therefore, the tungsten etching with respect to the dielectric material and the substrate may be characterized by any of the above-mentioned selectivities of materials for each structure.

The selective deposition may be performed in a chamber capable of deposition and capable of atomic layer deposition, including the chamber 400 described above. The deposition may be preset to selectively deposit an insulating material on a metal material relative to another insulating material. For example, the cover material 625 may be formed substantially on the metal material 620 while being minimally formed on or limited by the dielectric material 610. Selective deposition may be performed by a variety of operations, including forming a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting the formation of a dielectric on other dielectric materials.

Self-assembled monolayers can be formed on areas of the structure to tune the deposition. For example, a first self-assembled monolayer may be formed on the structure and then exposed to remove the monolayer from the metallic material 620. A single layer may be maintained on the dielectric material 610. A monolayer may have a capped portion that may repel or fail to interact with a precursor that is subsequently delivered. For example, in embodiments, the capped portion may be hydrophobic and may be capped with a hydrogen-containing portion (eg, methyl), which may not interact with additional precursors. The second self-assembled monolayer may be formed on the metal material 620 and may be hydrophilic or react with one or more precursors used to generate the cover material 625. Because the material can be repelled from the first self-assembled single layer or can be selectively stretched to the element, the second self-assembled single layer can be selectively formed on the metallic material 620. The second self-assembling monolayer can be terminated with a hydroxyl group or other hydrophilic portion, or can be terminated with a portion that specifically interacts with additional precursors used to form the cover material 625.

Atomic layer deposition may then be performed using two or more precursors to develop the cover material 625. The deposited precursor may include a metal-containing precursor and include a precursor configured to interact with a portion of the capped second self-assembled monolayer (instead of the first self-assembled monolayer). For example, when using a hydrophilic and hydrophobic capping monolayer, one of the atomic layer deposition precursors can include water or some other precursor to develop a cover material that can be hydrophilic. In this way, the deposition may not be formed on the first self-assembled monolayer, which may be hydrophobic. If the cap material includes a metal oxide (for example, titanium oxide or titanium nitride), the precursor for atomic layer deposition may include a titanium-containing precursor and water or a nitrogen-containing precursor. Then, during a half-reaction with water or other precursors, water may not be able to interact with the first self-assembled monolayer formed on the dielectric material 610, and therefore the deposition will not be formed on the first self-assembled monolayer. In this way, the cover material 625 can be selectively formed on the metal material 620 without forming a mask layer that can be chemically etched.

After the cover material 625 has been formed to a suitable height, the first self-assembled monolayer may be exposed to, for example, UV light and removed from the substrate in one example. Therefore, the first self-assembled monolayer can be formed directly after selective etching of the metallic material, or after being transferred to the additional chamber but before the additional processing operation, and the structure can be used without chemical removal or etching. Attach a mask layer. Similarly, after selective deposition, the cover material 625 may not be etched to ensure that the cover material 625 is selectively formed on the metal material. In this way, multiple operations used in conventional formation can be eliminated, which can significantly reduce queue time (eg, several hours).

Additional selective deposition techniques (which can include alternative mechanisms) can also be used for selective deposition of dielectric materials (eg, nitrogen-containing materials). For example, a nitrogen-containing material may serve as one of the self-assembled monolayers on the material used for deposition to occur (eg, one of the capped portions of the monolayer), but may allow attraction for A specific precursor of one or more of the materials. Other techniques can take advantage of temperature differences to enhance deposition on metal relative to silicon oxide. For example, atomic layer deposition using a titanium-containing precursor and a nitrogen-containing precursor may be performed at a temperature higher than or about 500 ° C, and may be higher than or about 750 ° C, higher than or about 900 ° C, higher than It is performed at a temperature of about 1000 ° C, or at, above, or about 1100 ° C.

As the temperature increases in this range, deposition can occur on tungsten at a higher rate than on silicon oxide. A selective etch of nitrogen may then be performed to remove the first dielectric material from the silicon oxide surface. Although it is also possible to reduce the first dielectric material on the surface of the metal material, since the thickness can be many times greater than the thickness on the silicon oxide, it can be completely removed on the silicon oxide while maintaining the thickness on the metal material.

Embodiments may also use an inhibitor to selectively form the capping material 625 on the metal material 620 without forming the capping material 625 on the dielectric material 610. For example, an inhibitor may be applied on the dielectric material. The inhibitor may be any number of materials, and the materials may be characterized by a siloxane backbone (eg, siloxane) or a tetrafluoroethylene backbone (eg, PTFE), as well as other oily or surfactant materials. Material may be applied to cover exposed portions of the dielectric material 610. The inhibitor material can prevent the adhesion or adsorption of materials that can be normally formed or deposited on the metal material 620. A cover material 625 is then formed, and a remover can be applied to the substrate to remove the inhibitor material. The remover may be a wet etchant, a reactant, or a surfactant cleaner, and may remove a residual inhibitor material that exposes the underlying dielectric material 610. Therefore, the inhibitor may be applied directly after selective etching, or after substrate transfer, but before other processing operations affecting the substrate. Utilizing an inhibitor may allow a cover material to be formed in a defined area without the need for subsequent patterning and / or etching definitions of the blanket film. By removing previous and subsequent patterning operations, processing can further reduce the queue time for conventional processing.

The inhibitor can also be a poisoning agent, or the product of a plasma application that can neutralize the surface of the substrate or render the surface of the substrate inert. For example, the modified plasma may be formed from one or more precursors, and may include inert precursors. Plasma may be applied to the surface of the substrate, which may change the surface of the dielectric material 610, but may not affect the metal material 620. In one possible example, a nitrogen-containing precursor (which may be nitrogen) may be delivered to a plasma processing area of a plasma-generating processing chamber. Plasma effluent (which may include nitrogen-containing plasma effluent) may be delivered to the substrate and a nitrided surface may be formed along the dielectric material 610.

Plasma effluent may not affect the metallic material 620, which may maintain a neat or unreacted surface. The capping material 625 may then be formed using one or more deposition techniques, which may include atomic layer deposition or other vapor or physical deposition. For example, atomic layer deposition techniques can be used, followed by plasma effluent treatment. After each cycle of deposition, the nitrogen-containing plasma may be reapplied to the substrate (eg, on the dielectric material 610). In this manner, the surface of the dielectric material 610 may be passivated to prevent or limit the formation of the cover material 625 on those areas. Other plasma or non-plasma materials can also be used to modify or poison the dielectric material 610, and the dielectric material 610 can also be processed to repel one or more precursors that can be used to form the cover material 625. Utilizing these plasma effluents on the non-recessed portions of the substrate may allow a cover material to be formed in a defined area without the need for subsequent patterning and / or etching definitions of the blanket film. By removing previous and subsequent patterning operations, processing can further reduce the queue time for conventional processing.

With respect to one or more non-metallic, dielectric, or insulating regions, any of these techniques can selectively deposit or form a dielectric or insulating material on a silicon-containing metal region. The selectivity may be complete, that is, the cover material may be formed only on the metal material 620 or the intermediate layer, and the cover material may not be formed on the dielectric material 610 at all. In other embodiments, the selectivity may not be complete, and the ratio of the deposition on the metal-containing material to the dielectric or insulating material may be greater than about 2: 1. Selectivity can also be greater than or about 5: 1, greater than or about 10: 1, greater than or about 15: 1, greater than or about 20: 1, greater than or about 25: 1, greater than or about 30: 1, greater than or about 35 : 1, greater than or about 40: 1, greater than or about 45: 1, greater than or about 50: 1, greater than or about 75: 1, greater than or about 100: 1, greater than or about 200: 1, or more.

The cover material may be formed to the aforementioned thickness, the thickness may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Therefore, a selectivity below 50: 1 may be acceptable to completely deposit the capping material 625 while forming a limited amount of material or substantially no material on the dielectric material 610. A slight etch-back operation may be performed in the chamber 200 after deposition to ensure complete removal of the cover material 625 from the dielectric material 610 to ensure complete node separation. Because the covering can be done in the recessed area of the metallic material 620, the etchback may not affect the deposited material, or the edges or sidewalls may be cleaned to produce a smooth surface. Since the deposition on the metal material 620 may be larger, any amount that may be deposited on the dielectric material 610 can be compensated by the slightly longer deposition time on the metal material 620, and then it can be recessed to the thickness of the recess and the dielectric can be cleaned The sidewall of the electrical material 610.

The deposition operation may be performed at any of the foregoing temperatures or pressures, and may be performed at a temperature greater than or about 50 ° C, and may be greater than or about 100 ° C, greater than or about 150 ° C, greater than or about 200 ° C, greater than or about 250 ° C, greater or about 300 ° C, greater than or about 350 ° C, greater than or about 400 ° C, greater than or about 450 ° C, greater than or about 500 ° C, greater than or about 600 ° C, greater than or about 700 ° C, greater than or about 800 ° C , Or higher. For example, during an atomic layer deposition operation, temperatures greater than or about 400 ° C can be used to activate the precursors to interact with each other as the material layer is formed. Compared with the conventional technology, by using this technology, manufacturing can be performed with more selective formation and removal, which can reduce the queue time by several hours compared with the conventional processing. By performing recess operations other than barrier formation, node separation can be more clearly defined, and subsequent processing or formation within the memory holes can be more easily performed. These processes can also achieve new structures, by forming selective layers to ensure that the metal material is protected, while the nodes remain separated in the memory structure.

In the additional method included in the present technology, the depression of the metal material may not be performed. Turning to FIG . 7 , a schematic cross-sectional view of an exemplary substrate 700 according to an embodiment of the present technology is illustrated. The substrate 700 may be similar to the substrate 600 previously described and illustrated in FIG. 7A, and may include similar materials or other materials as described above, and may have any of the dimensions or other characteristics described above. For example, the structure 700 may include a substrate 605 and alternating layers of a dielectric material 610 and a metal material 620. Memory holes or channels 630 may be formed within the structure and may have features of the sidewall 632.

Unlike the method 500 including the recessed metal material 620, as shown in FIG. 7B, additional structures can be formed by this technique. As shown, the recessed metal material 620 may not be performed. The illustrated method can deposit cap material 625 directly on metal material 620 after forming a memory hole or channel 630. A similar method or operation of the aforementioned selective deposition of a cap material may be performed, and the cap material (which may be a barrier material) may be any of the aforementioned materials (for example, including titanium nitride).

The cover material may be formed to extend outward from the metal material 620 and extend inside the channel 630. Similar to the previously described structure, the cover material 625 may not be formed on the dielectric material 610, or may not be continuous across the dielectric material 610 to create a separation between each cell. After the cover material 625 is formed, additional operations may be performed (including cleaning any residual formations on the dielectric material 610, as well as formations of the barrier layer (such as alumina) and additional core formations). By performing a method without pitting, queue time can be reduced, and surface roughening and other etching side effects can be limited.

In the foregoing description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the technology. However, it will be apparent to those of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

Several embodiments have been disclosed, but it should be understood that those skilled in the art can use various modifications, alternative constructions, and equivalents without departing from the spirit of the embodiments. Moreover, to avoid unnecessarily obscuring the technology, many known processes and components are not described. Therefore, the above description should not be considered as limiting the scope of the technology.

When a range of values is provided, it should be understood that, unless the context clearly indicates otherwise, each intermediate value between the upper and lower limits of the range is specifically disclosed to the smallest part of the lower limit unit. Any narrower range between any stated value or unstated intervening value in the stated range and any other stated or intervening value in that stated range is encompassed. Unless the range has any specific exclusions, the upper and lower limits of these smaller ranges may be independently included or excluded from the range, and either or both of the upper and lower limits may or may not be included in the smaller Each of the ranges is also included in the technology. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

As used herein and in the scope of the accompanying patent application, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "precursor" includes reference to one or more precursors and their equivalents known to those having ordinary knowledge in the field, and so on.

In addition, when the words "including", "including", "containing", "containing", "including", and "including" are used in this specification and the following claims, it is intended to specify the features, the whole, The presence of a component, or operation, but does not exclude the presence or addition of one or more other features, wholes, components, operations, actions, or groups.

10‧‧‧ Loading lock chamber

15‧‧‧ isolation valve

20‧‧‧Processing chamber

30‧‧‧Gas distribution board

60‧‧‧ substrate

61‧‧‧first surface

65‧‧‧ Shuttle

70‧‧‧ track

90‧‧‧ radiant heat source

100‧‧‧treatment system

102‧‧‧ front opening uniform pod

104‧‧‧ robot arm

106‧‧‧Support area

108a‧‧‧Processing chamber

108b‧‧‧Processing chamber

108c‧‧‧Processing chamber

108d‧‧‧Processing chamber

108e‧‧‧Processing chamber

108f‧‧‧Processing chamber

109a‧‧‧ Tandem Section

109b‧‧‧ Tandem Section

109c‧‧‧ Tandem Section

110‧‧‧Second robot arm

200‧‧‧ chamber

201‧‧‧RPS unit

203‧‧‧ cooling plate

205‧‧‧Gas inlet assembly

210‧‧‧ fluid supply system

214‧‧‧on board

215‧‧‧The first plasma area

216‧‧‧Lower plate

217‧‧‧ Panel

218‧‧‧Volume

219‧‧‧first fluid channel

220‧‧‧Insulation ring

221‧‧‧Second fluid channel

223‧‧‧Ion Eliminator

225‧‧‧Sprinkler

233‧‧‧Substrate processing area

240‧‧‧ Power Supply

253‧‧‧Detailed view

255‧‧‧ substrate

258‧‧‧Gas supply area

259‧‧‧ porosity

265‧‧‧ pedestal

325‧‧‧ sprinkler

365‧‧‧through hole

375‧‧‧small hole

400‧‧‧ chamber

420‧‧‧Syringe

425‧‧‧Gas port

430‧‧‧syringe

435‧‧‧Gas port

440‧‧‧Syringe

445‧‧‧Gas port

450‧‧‧ pumping system

455‧‧‧vacuum port

460‧‧‧Division

498‧‧‧arrow

500‧‧‧method

505‧‧‧Operation

510‧‧‧ Operation

515‧‧‧ operation

520‧‧‧operation

525‧‧‧operation

600‧‧‧ Structure

605‧‧‧ substrate

610‧‧‧ Dielectric material

620‧‧‧metal materials

625‧‧‧ cover material

630‧‧‧channel

632‧‧‧ side wall

700‧‧‧ Structure

A further understanding of the nature and advantages of the disclosed technology can be achieved by reference to the remainder of the description and drawings.

FIG. 1 illustrates a top plan view of an exemplary processing system according to an embodiment of the present technology.

FIG. 2A illustrates a schematic cross-sectional view of an exemplary processing chamber according to an embodiment of the present technology.

FIG. 2B illustrates a detailed view of an exemplary showerhead according to an embodiment of the present technology.

FIG. 3 illustrates a bottom plan view of an exemplary showerhead according to an embodiment of the present technology.

FIG. 4 illustrates a schematic cross-sectional view of an exemplary processing chamber according to an embodiment of the present technology.

FIG. 5 illustrates selected operations in a method of forming a semiconductor structure according to an embodiment of the present technology.

6A to 6C illustrate schematic cross-sectional views of an exemplary substrate according to an embodiment of the present technology.

7A to 7B illustrate schematic cross-sectional views of an exemplary substrate according to an embodiment of the present technology.

Several lines in the diagram are included as schematic diagrams. It should be understood that the drawings are for illustration purposes only and should not be considered to scale unless specifically stated to have a scale. In addition, the diagrams are provided as illustrations to aid understanding, and may not include all aspects or information compared to actual representations, and may include exaggerated materials for illustrative purposes.

In the accompanying drawings, similar components and / or features may have the same element symbols. In addition, various parts of the same type can be distinguished by using letters after the component symbol to distinguish similar parts. If only the frontmost component symbol is used in the description, the description applies to any similar component having the same frontmost component symbol, regardless of the letter.

Domestic hosting information (please note in order of hosting institution, date, and number) None

Information on foreign deposits (please note in order of deposit country, institution, date, and number) None

Claims (20)

A method for forming a semiconductor structure includes the following steps: forming a plasma containing a fluorine precursor in a distal plasma region of a processing chamber; and contacting a semiconductor substrate with an effluent of the plasma Wherein the semiconductor substrate is contained in a processing region of the processing chamber; a metal material is selectively etched laterally between exposed regions of a dielectric material on the semiconductor substrate; and subsequently deposited on the metal material A cover material, wherein the cover material is selectively deposited on the metal material with respect to an exposed area of the dielectric material. The method for forming a semiconductor structure according to claim 1, wherein the etching step is performed in a first processing chamber, and the deposition step is performed in a second processing chamber. The method for forming a semiconductor structure according to claim 2, further comprising the steps of: transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without destroying the vacuum Case. The method for forming a semiconductor structure according to claim 1, wherein the metallic material comprises tungsten or cobalt. The method for forming a semiconductor structure according to claim 1, wherein the dielectric material comprises silicon oxide. The method for forming a semiconductor structure according to claim 1, wherein the cover material comprises a metal nitride or a metal oxide. The method for forming a semiconductor structure according to claim 1, wherein the metal material is etched laterally from the sidewalls of the channel to less than 10 nm. The method for forming a semiconductor structure according to claim 1, wherein the etching step is performed using a selectivity of the metal material relative to the dielectric material of greater than or about 10: 1. The method for forming a semiconductor structure according to claim 1, wherein the deposition is performed using a selectivity of the metal material relative to the dielectric material of greater than or about 2: 1. The method for forming a semiconductor structure according to claim 1, wherein the step of selectively depositing the cover material comprises the following steps: inhibiting the growth of the cover material on the dielectric material. A method for forming a semiconductor structure includes the following steps: forming a plasma containing a fluorine precursor in a distal plasma region of a processing chamber; and contacting a semiconductor substrate with an effluent of the plasma Wherein the semiconductor substrate is contained in a processing region of the processing chamber; a layer of a metallic material is selectively etched laterally between exposed layers of a dielectric material on the semiconductor substrate; and subsequently the metallic material is A capping material is deposited thereon, wherein the capping material is selectively deposited on the metal material relative to the exposed area of the dielectric material. The method for forming a semiconductor structure as described in claim 11, wherein the layers of silicon nitride are etched laterally from the sidewalls of the channel to less than 10 nm. The method for forming a semiconductor structure according to claim 12, wherein the dielectric material comprises silicon oxide. The method for forming a semiconductor structure according to claim 13, wherein the cover material comprises a metal nitride or a metal oxide. The method for forming a semiconductor structure according to claim 14, wherein the metal nitride comprises titanium nitride. The method for forming a semiconductor structure according to claim 11, wherein the etching step is performed in a first processing chamber, and the deposition step is performed in a second processing chamber. The method for forming a semiconductor structure according to claim 11, further comprising the steps of: transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without breaking a vacuum. Case. The method for forming a semiconductor structure according to claim 11, wherein the semiconductor substrate defines a plurality of channels, and wherein the metal material is etched on a plurality of surfaces. The method for forming a semiconductor structure according to claim 11, wherein the etching step is performed using a selectivity of the metal material relative to the dielectric material of greater than or about 10: 1. The method for forming a semiconductor structure according to claim 11, wherein the depositing is performed using a selectivity of the metal material relative to the dielectric material of greater than or about 2: 1.