TW201737384A - System and method for defect classification based on electrical design intent - Google Patents

Abstract

A method for automatically classifying one or more defects based on electrical design properties includes receiving one or more images of a selected region of a sample, receiving one or more sets of design data associated with the selected region of the sample, locating one or more defects in the one or more images of the selected region of the sample by comparing the one or more images of the selected region of the sample to the one or more sets of design data, retrieving one or more patterns of interest from the one or more sets of design data corresponding to the one or more defects, and classifying the one or more defects in the one or more images of the selected region of the sample based on one or more annotated electrical design properties included in the one or more patterns of interest.

Description

System and method for defect classification based on electrical design intent

The present invention relates generally to wafer inspection and inspection, and more particularly to classifying defects based on electrical design intent during wafer inspection and inspection.

Fabricating semiconductor devices, such as logic and memory devices, typically involves processing a substrate (such as a semiconductor wafer) using a large number of semiconductor processes to form various features and levels of the semiconductor device. The plurality of semiconductor devices can be fabricated in a single semiconductor wafer and then the plurality of semiconductor devices can be separated into individual semiconductor devices. Semiconductor devices can develop defects during the process. The inspection process is performed at various steps during a semiconductor process to detect the same defects. Inspection processes are an important part of the fabrication of semiconductor devices, such as integrated circuits, which become even more important for the successful manufacture of acceptable semiconductor devices as the size of semiconductor devices is reduced. For example, when the size of a semiconductor device is reduced, detection of defects is highly desirable because even relatively small defects can cause undesirable deviations in the semiconductor device. Accordingly, it would be desirable to provide a solution for improved wafer inspection and defect classification to address manufacturing issues and provide improved wafer inspection capabilities.

In accordance with one or more embodiments of the present invention, a system for automatically classifying one or more defects based on electrical design properties is disclosed. In an illustrative embodiment, the system includes an imaging tool. In another illustrative embodiment, the system includes a user interface. In another illustrative embodiment, the user interface includes a display and a user input device. In another illustrative embodiment, the system includes a controller. In another illustrative embodiment, the controller includes one or more processors configured to execute a set of program instructions stored in a memory. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to receive one or more images of a selected region of a sample. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to receive one or more sets of design material associated with the selected region of the sample. In another illustrative embodiment, a set of design materials includes one or more layers. In another illustrative embodiment, a layer comprises one or more sets of shapes. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to compare the one or more images of the selected region of the sample with the one or more sets of design data And locating one or more defects in the one or more images of the selected region of the sample. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to draw one or more attentions from the one or more sets of design data corresponding to the one or more defects pattern. In another illustrative embodiment, the one or more patterns of interest comprise one or more labeled electrical design properties. In another illustrative embodiment, the pattern of interest is represented by one or more shapes. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to classify the one or more of the selected regions of the sample based on the one or more annotation electrical design properties The one or more defects in the image. In accordance with one or more embodiments of the present invention, a system for using electrical design properties for defect classification to label one or more sets of design materials is disclosed. In an illustrative embodiment, the system includes a user interface. In another illustrative embodiment, the user interface includes a display and a user input device. In another illustrative embodiment, the system includes a controller. In another illustrative embodiment, the controller includes one or more processors configured to execute a set of program instructions stored in a memory. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to receive one or more sets of design materials. In another illustrative embodiment, a set of design materials includes one or more layers. In another illustrative embodiment, a layer comprises one or more sets of shapes. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to receive one of the one or more sets of design data from the user input device to select one of the patterns of interest. In another illustrative embodiment, the pattern of interest is represented by one or more shapes. In another illustrative embodiment, the program instructions are configured to cause the one or more processors to label the one or more groups using one or more electrical design properties associated with the selected pattern of interest The pattern of interest in the design data. In accordance with one or more embodiments of the present invention, a method for automatically classifying one or more defects based on electrical design properties is disclosed. In an illustrative embodiment, the method can include, but is not limited to, receiving one or more images of a selected region of a sample. In another illustrative embodiment, the method can include, but is not limited to, receiving one or more sets of design materials associated with the selected region of the sample. In another illustrative embodiment, the one or more sets of design data correspond to the selected area of the sample. In another illustrative embodiment, a set of design materials includes one or more layers. In another illustrative embodiment, a layer comprises one or more sets of shapes. In another illustrative embodiment, the method can include, but is not limited to, positioning the sample by comparing the one or more images of the selected region of the sample with the one or more sets of design data. One or more defects in the one or more images of the selected area. In another illustrative embodiment, the method can include, but is not limited to, extracting one or more patterns of interest from the one or more sets of design data corresponding to the one or more defects. In another illustrative embodiment, the pattern of interest is represented by one or more shapes. In another illustrative embodiment, the one or more patterns of interest comprise one or more labeled electrical design properties. In another illustrative embodiment, the method can include, but is not limited to, classifying the one or more of the one or more images of the selected region of the sample based on the one or more labeled electrical design properties Defects. In accordance with one or more embodiments of the present invention, a method for labeling one or more sets of design materials for use in defect classification using electrical design properties is disclosed. In an illustrative embodiment, the method can include, but is not limited to, receiving one or more sets of design materials. In another illustrative embodiment, a set of design materials includes one or more layers. In another illustrative embodiment, a layer comprises one or more sets of shapes. In another illustrative embodiment, the method can include, but is not limited to, receiving, from the user input device, one of the one or more sets of design materials to select one of the patterns of interest. In another illustrative embodiment, the pattern of interest is represented by one or more shapes. In another illustrative embodiment, the method can include, but is not limited to, annotating the one of the one or more sets of design materials using one or more electrical design properties associated with the selected pattern of interest. pattern. It is to be understood that the foregoing [invention] and the following [embodiments] are merely illustrative and illustrative and are not intended to limit the invention. The subject matter of the present invention is incorporated in the specification, and is in the The description and drawings together illustrate the principles of the invention.

This application is based on 35 U. S. C.  § 119(e) claims Prathanti Uppaluri, entitled "METHOD FOR DEFECT CLASSIFICATION BASED ON ELECTRICAL DESIGN INTENT", which was filed on May 26, 2016. Thirupurasundari Jayaraman, Ardis Liang and Srikanth Kandukuri as inventors of US Provisional Patent Application No. 62/341, Priority 765, The entire contents of this application are incorporated herein by reference.  Reference will now be made in detail to the subject matter disclosed. The subject matter is illustrated in the accompanying drawings.  Referring generally to Figures 1A through 3, A system and method for wafer electrical design property labeling and defect classification is disclosed in accordance with the present invention.  Embodiments of the present invention relate to a system and method for labeling design data using electrical design signals, Wherein the electrical design property is attributed to one or more defect characteristics and is used to determine the importance (degree of harm) of a defect to the electrical device or interconnection.  For the purposes of the present invention, As used herein, the terms "design" and "design data" generally refer to the physical design (layout) of an integrated circuit (IC) and are derived from the physical design through complex simulations or simple geometric and Boolean operations. Information. E.g, The entity design can be stored in a data structure (such as a graphical data system (GDS) file, Any other standard machine readable file, Any other suitable file and design database known in the art). Provide IC layout data or wafer design data in a variety of formats, Includes (but is not limited to) GDSII and OASIS formats. A GDSII file is one of the files used to design a representation of layout data. Other examples of such files include (but are not limited to) GL1 and OASIS files and proprietary file formats (such as, Main reticle design file (RDF) data, It is KLA-Tencor, Milpitas, Calif ("KT") is exclusive). Using specific wafer fabrication, Logical and electrical intent coding design data. Design data can be exported to one of the Electronic Design Automation (EDA) tools. E.g, The design data output from the EDA tool can be processed by the analysis software and converted to the RDF format.  It should be noted in this article, One of the main reticle images and/or derivatives thereof obtained by a main reticle inspection system can be used as one of the "agents" or "several agents" for the design. This primary reticle image or one of its derivatives can be used as an alternative to the design layout in any of the embodiments described herein using a design. The design may include Section 7 of the U.S. Patent No. 7, issued on August 4, 2009 by Zafar et al. 570, No. 796 and U.S. Patent No. 7, issued by Kulkarni et al., March 9, 2010, 676, Any other design information or design information agent described in No. 077, The entire contents of both of these are incorporated herein by reference. In addition, The design data can be standard cell library materials, Integrate layout information, Design data for one or more layers, Derivatives of the design data and all or part of the wafer design information.  Further note in this article, The simulated or acquired image from a wafer or main reticle can be used as a proxy for design. Image analysis can also be used as a proxy for design analysis. E.g, A polygon that can be self-printed on one of the wafers and/or one of the main reticle designs. It is assumed that the image of the wafer and/or the main reticle is taken at sufficient resolution to adequately image the design polygon.  The extraction of electrical intent from the design data of the wafer may be automated or manual based on the type of design material available to a user. A rule-driven EDA tool class, such as a layout comparison circuit diagram (LVS), can be used to automatically extract electrical intent from the design data. E.g, LVS tools require all design layers, Contains a text layer, And connection rules to automatically extract the electrical intent of the wafer design. In the case where a complete set of design layers is not available to the user, A user driven solution is available. however, In case a rule drive or user driver is not available, The electrical intent of the design information cannot be used for extraction. thus, It will be desirable to use the design's electrical intent to label design data to provide information to a user or a controller for use during wafer inspection and inspection processes.  A further embodiment of the invention relates to a system and method for receiving sample detection images and classifying defects found in the sample detection images. The defect can be classified by comparing a defect with a design data that is annotated using electrical design properties. The electrical design properties include the nature of the defect and the importance of the defect. The importance of a defect is defined by its location. Important structural defects affect the electrical integrity of the device. Classification of defects based on defect characteristics and important levels of the semiconductor wafer facilitates proper classification of defects after manufacture, A situation in which most or all of an electrical pattern is lost from the semiconductor wafer.  For the purposes of the present invention, A defect can be classified as a gap, Short circuit, Granules, Residual, Residual film or any other defect known in the art. Defects can be classified as interference (defects with low importance) or material failures (defects of high importance). The importance of a defect is defined by its location and the electrical intent at that location. E.g, Defects in redundant electrical structures that are set for better manufacturability (which do not affect the electrical integrity of the device) are less important than defects in a single electrical structure (eg, material failure) ( For example, interference). E.g, A defect in or on a floating net may be less important than a defect in or on a power line or ground line.  In some cases where one of the defects is present, A wafer can lose an electrical structure (for example, All or a large part of a path or a contact). In this situation, A user may not have sufficient information about the electrical structure to correctly determine the effect of the defect by visual inspection, Because the defect can be located in an empty area without any shape. therefore, The user can misclassify the defect. E.g, Loss of shape or portion of one of the shapes may be erroneously classified as a disturbance rather than a material error due to the lack of shape data in the layer under inspection. Or vice versa. This misclassification can result in a loss of revenue for the manufacturer. Replacement and compensation of wafers that are affected by interference defects in the form of unnecessary reprinting of the interfering wafer or material failure. thus, It would be desirable to provide an electrical intent for comparison within the design data during the inspection and inspection process to provide the detector with an additional resource for determining the importance of a defect.  For the purposes of the present invention, Terminology, Electrical design intent, Electrical properties, Electrical design properties and electrical patterns represent synonymous terms.  FIG. 1 illustrates a system 100 for sample testing in accordance with one or more embodiments of the present invention. In one embodiment, System 100 includes an imaging tool 102. In another embodiment, System 100 includes a sample 104 disposed on a sample stage 106. In another embodiment, System 100 includes a controller 110. In another embodiment, System 100 includes a user interface 120.  In another embodiment, Imaging tool 102 is configured to detect defects on sample 104. E.g, Imaging tool 102 can include any suitable characterization tool known in the art. Such as (but not limited to) a detection tool or inspection tool. E.g, Imaging tool 102 can include, but is not limited to, an electron beam detection or inspection tool (eg, SEM system). By another example, Imaging tool 102 can include, but is not limited to, an optical inspection tool. E.g, The optical inspection tool can include a wideband plasma (BBP) detection tool. Includes, but is not limited to, a laser based plasma maintenance (LSP) detection tool. In another case, The optical detection tool can include a narrowband detection tool. Such as (but not limited to) a laser scanning detection tool. In addition, In the case of optical inspection, Imaging tool 102 can include, but is not limited to, a bright field imaging tool or a dark field imaging tool. It should be noted in this article, Imaging tool 102 can include a configuration configured to detect surface reflection from a sample 104, scattering, Any optical system that illuminates with diffraction and/or radiation. An example of an imaging tool is generally described in U.S. Patent No. 7, issued on August 8, 2006. 092, No. 082; US Patent Case No. 6, issued on September 16, 2003, 621, No. 570; And U.S. Patent No. 5, issued on September 9, 1998, 805, In number 278, The entire contents of each of these are incorporated herein by reference. An example of an imaging tool is also generally described in U.S. Patent No. 8, issued on April 4, 2014.  No. 594, US Patent Case No. 8, issued on April 8, 2014, 692, 204, US Patent Case No. 8, issued on April 15, 2014, 698, No. 093, US Patent Case No. 8, issued on May 6, 2014, 716, No. 662, US Patent Application No. 14/699, filed on April 29, 2015, No. 781, US Patent Application No. 14/667, filed on March 24, 2015, U.S. Patent Application Serial No. 235, filed on Aug. 13, 2014, In No. 155, The entire contents of each of these are incorporated herein by reference.  In another embodiment, Although not shown, The imaging tool 102 can include an illumination source, a detector and various optical components for performing the detection (for example, lens, Beam splitter and the like). E.g, The illumination source of imaging tool 102 can include any illumination source known in the art. E.g, The illumination source can include, but is not limited to, a broadband source or a narrowband source. In addition, The illumination source can be configured to direct light to the surface of the sample 104 disposed on the sample stage 106 (via various optical components). Further, The various optical components of imaging tool 102 can be configured to direct light reflected and/or scattered from the surface of sample 104 to the detector of imaging tool 102. By another example, The detector of imaging tool 102 can include any suitable detector known in the art. E.g. The detector can include, but is not limited to, a photomultiplier tube (PMT), Charge coupled device (CCD), Time-delay integration (TDI) cameras and the like. In addition, The output of the detector can be communicatively coupled to one of the controllers 110 as described in further detail herein.  In one embodiment, Sample 104 contains a wafer. E.g, Sample 104 can include, but is not limited to, a semiconductor wafer. As used throughout the invention, The term "wafer" generally refers to a substrate formed of a semiconductor material or a non-semiconductor material. E.g, A semiconductor or semiconductor material can include, but is not limited to, a single crystal germanium, Gallium arsenide and indium phosphide.  In another embodiment, Sample 104 is manufactured based on one or more sets of design data. In another embodiment, A set of design materials contains one or more sets of layers. E.g, Such layers may include, but are not limited to, a resist, a dielectric material, A conductive material and a half conductive material. Many different types of such layers are known in the art. And the term wafer as used herein is intended to encompass a wafer on which all of these layers can be formed. By another example, The one or more layers formed on the wafer may be repeated one or more times within the wafer. The formation and processing of such material layers can ultimately result in the completion of the device. Many different types of devices can be formed on a wafer. And the term wafer as used herein is intended to encompass a wafer on which any type of device known in the art is fabricated.  In another embodiment, A layer contains one or more sets of shapes. E.g, The one or more sets of shapes can be repeated one or more times within the layer. By another example, A set of shapes can be regular or irregular. In another embodiment, A shape is a polygon. The implementation of the polygon in detecting the design information of a device is generally described in the US Patent Case No. 8 of December 30, 2014. 923, 600 and US Patent Application No. 14/178 of February 12, 2014, In No. 866, The entire contents of each of these are incorporated herein by reference.  In another embodiment, The one or more sets of design materials include one or more patterns of interest. E.g, The one or more patterns of interest may be repeated one or more times within the one or more sets of design materials. In another embodiment, A pattern of interest can be represented by one or more sets of shapes. In another embodiment, The pattern of interest may be a unit defined within the one or more sets of design materials. It should be noted in this article, A pattern of interest may correspond to a particular electrical intent of one of the one or more sets of design materials. As per the user of the present invention, The electrical intent of the one or more sets of design data includes (but is not limited to) a power line, a grounding wire, a time series, One word line, One yuan line, a data line, A logical line and the like.  FIG. 1B illustrates one or more layers of a set of design data for sample 104 in accordance with the present invention. In one embodiment, The set of design materials includes a layer 130. In another embodiment, Layer 130 contains one or more polygons. E.g, Layer 130 can have repeating polygons. E.g, Layer 130 can have a set of repeating polygons 132. In addition, Layer 130 can have a set of repeating polygons 134. By another example, Layer 130 can have a single polygon. E.g, Layer 130 can have a single polygon 136. In addition, Layer 130 can have a single polygon 138. By another example, Layer 130 can have one or more additional polygons 139. In another embodiment, A user can mark the one or more polygons using one or more electrical properties. In one example, The one or more polygons may be labeled using an electrical design property for an SRAM bit cell. E.g, The user can mark the set of repeating polygons 132 as a voltage source. In addition, The user can mark the set of repeating polygons 134 as a ground. Further, The user can mark the polygon 136 as a word line. Further, The user can mark the polygon 138 as a one-dimensional line.  It should be noted in this article, One or more polygons 132 may be labeled using the same or different electrical design properties, 134, 136, 138, 139. Further note in this article, Additional or alternative polygons on layer 130 may be labeled using one or more electrical design properties. E.g. One or more polygons 132, 134, 136, 138, 139 does not require the use of one or more electrical properties. By another example, A user may use one or more electrical design properties to label any of the polygons depicted in FIG. 1B. therefore, The above description should not be construed as limiting the invention, but only as an illustration.  In another embodiment, The set of design data for sample 104 includes one or more additional sets of polygons on one or more additional layers. E.g, The set of design data for the sample 104 can include a set of polygons 140 on one layer. By another example, The set of design data for the sample 104 can include a set of polygons 150 on a layer. By another example, The set of design data for the sample 104 can include a set of polygons 160 on one layer. By another example, The set of design data for the sample 104 can include a set of polygons 170 on one layer.  In another embodiment, Polygon 140, 150. 160, 170 groups can be on separate layers. however, It should be noted in this article, Polygon 140, 150. 160, One or more of the 170 groups may be on the same layer. In addition, It should be noted in this article, Polygon 140, 150. 160, One or more of the 170 groups may be on layer 130, Layer 130 includes a polygon 132, 134, 136, 138, 139. therefore, The above description should not be construed as limiting the invention, but only as an illustration.  Referring again to Figure 1A, In another embodiment, Sample stage 106 can comprise any suitable mechanical and/or machine assembly known in the art. E.g, The sample stage 106 can be configured to actuate the sample 104 to a selected position or orientation. E.g, The sample stage 106 can include or can be mechanically coupled to one or more actuators (such as a motor or servo system), The actuator is configured to translate or rotate for positioning, according to a selected detection or metrology algorithm, Sample 104 is focused and/or scanned (some of which are known in the art).  In one embodiment, The controller 110 includes one or more processors 112 and a memory medium 114. In another embodiment, One or more sets of program instructions 116 are stored in the memory medium 114. In another embodiment, One or more processors 112 are configured to execute the set of program instructions 116 to perform one or more of the various steps described throughout the present invention.  In another embodiment, User interface 120 is communicatively coupled to one or more processors 112 of controller 110. In another embodiment, The user interface 120 includes a display device 122. In another embodiment, User interface 120 includes a user input 124.  In another embodiment, Controller 110 is configured to receive and/or retrieve data or information from other systems or subsystems by transmitting media that may include one of wired and/or wireless portions (eg, One or more sets of information from the imaging tool 102 or any of the components from the imaging tool 102 or one or more user inputs via the user interface 120). In another embodiment, The controller 110 of the system 100 is configured to transmit data or information by transmitting media over one of the wired and/or wireless portions (eg, The output of one or more processes disclosed herein is transmitted to one or more systems or subsystems (eg, One or more commands to the imaging tool 102 or to any of the components of the imaging tool 102 or displayed on the user interface 120 one or more outputs). In this regard, The transmission medium can be used as a data link between the controller 110 and other subsystems of the system 100. In another embodiment, Controller 110 is configured to communicate via a transmission medium (eg, Network connection) and send data to the external system.  In one example, One of the imaging tools 102 can be detected in any suitable manner (eg, Coupling to the controller 110 by one or more transmission media indicated by the dashed lines shown in FIG. The controller 110 is enabled to receive the output generated by the detector. By another example, If the imaging tool 102 includes more than one detector, Controller 110 can then be coupled to the plurality of detectors as described above. It should be noted in this article, Controller 110 can be configured to use detection data collected and transmitted by imaging tool 102, Any one or more defects on the sample 104 are detected using any method and/or algorithm known in the art to detect defects on the wafer. E.g, Imaging tool 102 can be configured to accept instructions from another subsystem of system 100 including, but not limited to, controller 110. Once the instructions from the controller 110 are accepted, The imaging tool 102 can perform a detection process (ie, a detection protocol) at the locations of the samples 104 identified in the provided instructions, The results of the detection process are transmitted to the controller 110.  In one embodiment, The set of program instructions 116 are programmed to cause the one or more processors to use electrical design properties to label one or more sets of design data. E.g, The set of program instructions 116 can be programmed to cause the one or more processors to receive one or more sets of design materials. By another example, The set of program instructions 116 can be programmed to cause the one or more processors to receive one of the one of the one or more sets of design materials to be selected. By another example, The set of program instructions 116 can be programmed to cause the one or more processors to mark the selected pattern of interest using one or more electrical design properties. By another example, The set of program instructions 116 can be programmed to cause the one or more processors to use the one or more electrical design properties to annotate one or more of the selected patterns of interest.  It should be noted in this article, The controller 110 can use the electrical design properties stored in the memory 114 or use the user input electrical design properties to label the patterns of interest with one or more sets of design data. Further note in this article, The controller 110 can automatically mark the pattern of interest. Or, instead, the following patterns of interest from a user's feedback via the user interface 120 are noted.  In another embodiment, The set of program instructions 116 are alternatively or additionally programmed to cause the one or more processors to analyze sample detection results from the imaging tool 102 and to classify one or more defects within the results. E.g, The set of program instructions 116 can be programmed to cause the one or more processors to receive one or more images of a selected area of a sample. By another example, The set of program instructions 116 can be programmed to cause the one or more processors to receive one or more sets of design material associated with the selected area of the sample. By another example, The set of program instructions 116 can be programmed to cause the one or more processors to locate one or more defects in the one or more images of the selected region of the sample. By another example, The set of program instructions 116 can be programmed to cause the one or more processors to retrieve one or more corresponding patterns of interest using the electrical design properties from the one or more sets of design data. By another example, The set of program instructions 116 can be programmed to cause the one or more processors to classify the one or more of the one or more images of the selected region of the sample based on the one or more labeled electrical design properties Multiple defects.  It should be noted in this article, Controller 110 can automatically classify the defects based on the electrical design properties of the one or more sets of design data. In addition, The controller 110 can classify the defects based on the electrical design properties of the one or more sets of design data from a user feedback from the user interface 120.  In one embodiment, One or more processors 112 of controller 110 include any one or more of the processing elements known in the art. In this sense, The one or more processors 112 can include any microprocessor device configured to perform algorithms and/or instructions. E.g, One or more processors 112 may be from a desktop computer, Host computer system, workstation, Video computer, Parallel processor, Vehicle onboard computer, Handheld computer (for example, tablet, A smart phone or tablet phone) or other computer system configured to execute a program configured with one of the operating systems 100 (eg, Network computer), As described throughout the present invention. Should be aware that The steps described throughout the present invention can be carried out by a single computer system or alternatively a multi-computer system. In general, The term "processor" is broadly defined to encompass any device having one or more processing elements. It executes program instructions 116 from a non-transitory memory medium (e.g., memory 114). In addition, Different subsystems of system 100 (eg, The imaging tool 102 or user interface 120) may comprise a processor or logic element adapted to perform at least a portion of the steps described herein. therefore, The above description should not be construed as limiting the invention, but only as an illustration.  In one embodiment, The memory medium 114 of the controller 110 includes any storage medium known in the art suitable for storing program instructions 116 executable by the associated processor(s) 112. E.g, The memory medium 114 can include a non-transitory memory medium. E.g, The memory medium 114 can include, but is not limited to, a read-only memory, a random access memory, a magnetic or optical memory device (such as a disk), a tape, A solid state disk and the like. In another embodiment, It should be noted in this article, The memory 114 is configured to provide display information to a display device 122 and/or the output of the various steps described herein. Further attention should be paid to The memory 114 can be housed in a common controller housing having one or more processors 112. In an alternate embodiment, The memory 114 can be located remotely relative to the physical locations of the processor 112 and the controller 110. E.g, One or more processors 112 of the controller 110 are accessible through a network (eg, Internet, The internal network and the like) access one of the remote memories (such as a server). In another embodiment, The memory medium 114 stores program instructions 116 for causing one or more processors 112 to perform the various steps described throughout the present invention.  In one embodiment, Display device 122 includes any of the display devices known in the art. E.g, The display device can include, but is not limited to, a liquid crystal display (LCD). By another example, The display device can include, but is not limited to, an organic light emitting diode (OLED) based display. By another example, The display device can include, but is not limited to, a CRT display. Those skilled in the art should be aware that A variety of display devices may be suitable for implementation in the present invention and the particular choice of display device may depend on a variety of factors. It includes, but is not limited to, the size of the appearance, Cost and similar. In a general sense, Capable with user input devices (for example, Touch screen, Panel mounting interface, keyboard, mouse, Any of the display devices integrated with the track pad and the like are suitable for implementation in the present invention.  In one embodiment, User input device 124 includes any user input device known in the art. E.g, User input device 124 can include, but is not limited to, a keyboard, Keypad, Touch screen, lever, Knob, Wheel, Trackball, switch, Dial, Slider, Rolling rod, Sliding parts, handle, Touch pad, pedal, steering wheel, Joystick, Panel input device or the like. In the case of a touch screen interface, Those skilled in the art should be aware that A large number of touch screen interfaces are suitable for implementation in the present invention. E.g, The display device 122 can be coupled to a touch screen interface (such as, but not limited to) a capacitive touch screen, a resistive touch screen, a touch screen based on surface acoustic waves, An infrared-based touch screen or similar) is integrated. In a general sense, Any touch screen interface that can be integrated with the display portion of a display device is suitable for implementation in the present invention. In another embodiment, User input device 124 can include, but is not limited to, a panel mounting interface.  These embodiments of the system 100 illustrated in Figure 1 can be further configured as described herein. In addition, System 100 can be configured to perform any of the other steps of any of the method embodiments described herein.  2 depicts a process flow diagram depicting a method 200 for an electrical property for defect classification to label one or more sets of design data. The method can also include any other steps that can be performed by the output acquisition subsystem and/or computer subsystem or the system described herein. These steps may be performed by one or more computer systems that may be configured in accordance with any of the embodiments described herein. It should be noted in this article, These steps of method 200 may be implemented in whole or in part by system 100. however, Should be aware that Method 200 is not limited to system 100, Because additional or alternative system level embodiments may perform all or part of such steps of method 200.  In a step 202, Receive one or more sets of design materials. E.g, The one or more sets of design data may be in RDF format. In one embodiment, A set of design materials contains one or more sets of layers. In another embodiment, A layer contains one or more sets of shapes. In another embodiment, A shape is a polygon. In another embodiment, The one or more sets of design data are displayed on the user interface 120.  In a step 204, Receiving one of the one of the one or more sets of design materials, a selection of a pattern of interest (POI). In one embodiment, Analyze each area within one or more sets of design data. E.g, The one or more sets of design data can be displayed on the display device 122 of the user interface 120. By another example, A user can zoom in and out of the one or more sets of design data via user input 124 of user interface 120. In another embodiment, Identifying one or more patterns of interest within the one or more sets of design materials. In another embodiment, A particular pattern of interest is selected from the one or more patterns of interest. E.g, The particular pattern of interest can be selected by the user via user input 124 of user interface 120. By another example, The particular pattern of interest may include a particular macro, A subject of interest or an arbitrary pattern of interest. By another example, The pattern of interest can be represented by one or more polygons. In another embodiment, The selected pattern of interest is displayed on the user interface 120.  In a step 206, The selected pattern of interest is labeled using one or more electrical design properties. In one embodiment, A user analyzes the selected pattern of interest. E.g, The user can zoom in and out of the selected pattern of interest to view one or more of its polygons. In another embodiment, The user selects a portion of the polygons of the selected pattern of interest. In another embodiment, The user selects one or more electrical design properties to label the selected portion of the polygons of the selected pattern of interest. E.g, The one or more electrical design properties can be stored in the memory 114 of the controller 110 and displayed on the display 122 of the user interface 120. E.g, The stored one or more electrical design properties can include all of the possible electrical design properties for any of the wafer designs known in the art. In addition, The stored one or more electrical design properties may be based on the nature selected by the prior user, A compressed list of pre-programmed instructions implemented in response to the identification of the controller 110 of the selected pattern of interest or the identification of a particular wafer design. By another example, The one or more electrical design properties may be entered by the user via user input 124 of user interface 120. In another embodiment, The one or more electrical design properties are displayed on the user interface 120. In another embodiment, The annotation-affected pattern is stored in the one or more sets of design materials.  In an optional step 208, The one or more electrical design properties are used to label one or more of the selected instances of the selected pattern of interest. In one embodiment, A pattern search function analyzes the one or more sets of design data for repeated instances of the previously selected pattern of interest. In another embodiment, The pattern search function labels the repeating instances using the one or more electrical design properties previously labeled. In another embodiment, The one or more repeating instances of the selected pattern of interest are displayed on the user interface 120. In another embodiment, The one or more electrical design properties of the one or more repeating instances of the selected pattern of interest are displayed on the user interface 120. In another embodiment, The one or more repeated instances of the noted pattern are stored in the one or more sets of design data. In another embodiment, The results of the analysis of the pattern search function are stored in the one or more sets of design data. It should be noted in this article, If the image of interest is a macro or a unit of interest, Then the pattern search is not needed. However, the pattern search can still be performed by process 200 as needed.  It should be noted that These steps of repeat 200 can be repeated for additional patterns of interest within the one or more sets of design materials.  Further attention should be paid to The pattern search function can be implemented prior to storing the labeled electrical design properties of the selected pattern of interest. In this regard, All instances of the selected pattern of interest will be labeled prior to storing the labels in the one or more sets of design materials. therefore, The above description should not be construed as limiting the invention, but only as an illustration.  One of the selected patterns of interest within one or more sets of design data is used to provide one or more electrical design properties for use in determining a defective configuration during wafer inspection. In one embodiment, The isoelectric design property includes a defect type characteristic (ie, Void, Short circuit, Tight or similar) Design sub-features (ie, a power line, a grounding wire, a timing function, a data function or the like) and an important level of the design (ie, harmless, interference, Materials and similar terms; a weighting scale system; Or any of them.  3 depicts a process flow diagram depicting one method 300 for automatically classifying one or more defects based on electrical design properties. The method can also include any other steps that can be performed by the output acquisition subsystem and/or computer subsystem or the system described herein. These steps may be performed by one or more computer systems that may be configured in accordance with any of the embodiments described herein. It should be noted in this article, These steps of method 300 may be implemented in whole or in part by system 100. however, Should be aware that Method 300 is not limited to system 100, Because additional or alternative system level embodiments may perform all or part of such steps of method 300.  In a step 302, Receiving one or more images of a selected area of a sample. In one embodiment, The one or more images comprise an image of one or more of the selected regions of the sample. In another embodiment, The one or more images comprise images of one or more shapes within one of the selected regions of the sample. In another embodiment, The one or more images are received by the controller 110 from the imaging tool 102. however, It should be noted that The one or more results from a previous wafer inspection may instead be uploaded to the controller 110 by a user. In this regard, The controller 110 can be communicatively coupled to or detached from the imaging tool 102. In another embodiment, The one or more images of one or more of the selected regions of the sample are displayed on the user interface 120.  In a step 304, Receiving one or more sets of design data associated with the selected area of the sample. E.g, The one or more sets of design data may be retrieved from the memory 114. By another example, The one or more sets of design materials may be received from a user. In one embodiment, The one or more sets of design materials are labeled using one or more electrical design properties. In another embodiment, The one or more sets of design data are displayed on the user interface 120.  In a step 306, Positioning one or more defects in the one or more images of the selected region of the sample. In one embodiment, The controller 110 compares the one or more images of the selected region of the sample to the one or more sets of design data. In another embodiment, The controller 110 identifies a difference between the one or more images from the one or more sets of design data as one of the one or more images. In another embodiment, The one or more defects are displayed on the user interface 120.  It should be noted in this article, Positioning the defects in the one or more images of the selected region of the sample without comparing the one or more images with the one or more sets of design data, Alternatively, the process positioning can be detected and viewed in step 306 by any other wafer known in the art. therefore, The above description should not be construed as limiting the invention, but only as an illustration.  In a step 308, One or more corresponding patterns of interest are drawn from the one or more sets of design data using electrical design properties. For the purposes of the present invention, One of the electrical design property annotations corresponds to the design of the desired pattern. In another embodiment, The one or more design wafers are represented by one or more polygons surrounding the location of the one or more defects in the one or more images of the selected region of the sample. In another embodiment, The one or more design wafers have a range from 0. One or more sizes from 250 microns to 10 microns. For example, the area of the design wafer can be 0. 250 micron x0. 250 microns. By way of another example, the area of the design wafer can be 1 micron x 1 micron. By way of another example, the design wafer can have an area of 10 microns x 10 microns. It should be noted herein that the shape of the design wafer may not be square, but instead may be any regular or irregular shape known in the art. Therefore, the above description should not be taken as limiting the invention, but only as an illustration. In another embodiment, the one or more electrical design properties are displayed on the user interface 120. In another embodiment, the one or more design wafers comprise one or more labeled electrical properties. For example, the marked electrical properties may include, but are not limited to, a defect type characteristic, a design secondary characteristic, or an important level to the design. In a step 310, the one or more defects in the one or more images of the selected region of the sample are classified based on the one or more labeled electrical design properties. For example, using one or more defect type characteristics (ie, voids, shorts, tight bundles, or the like), designing secondary characteristics (ie, a power line, a ground line, a timing function, a data function, or the like) and An important level of design (ie, harmless, interference, materials, and the like; a weighting scale system; or the like) to classify the one or more defects. It should be noted that these steps of repeating 300 may be repeated for additional defects within the one or more images of the selected region of the sample and corresponding patterns of interest. It should also be noted that classifying one or more defects in the one or more images resulting from wafer inspection based on defect type characteristics and design sub-characteristics may help to use one by prioritizing yield killer defects. The source of the defect rate is found, thus potentially reducing the time required for detection. In one embodiment, a defect design sub-characteristic enables a user to connect the defect to one of the wafer functionalities. Examples of perceptual problems include, but are not limited to, electrical intent of a defect location (eg, a defect on a power line or ground line), a lost electrical structure, including but not limited to a contact or a path, or an important clock Tight online. For example, in the case where the selected pattern of interest is an SRAM bit cell, a defect can be characterized as a "gap" and sub-characterized as "a gap in one of the bit lines in an SRAM region." In addition, a defect can be characterized as "tight bundle" and sub-characterized as "tightening on an important clock network". Here, the design sub-feature can help a user to more quickly associate a "tight bundle" defect with a wafer timing failure. It should further be noted that these definitional deficiencies minimize product waste and potential damage to both the consumer and the manufacturer or retailer in terms of the importance of the design. For example, a defect can be considered as a material failure or an interference depending on how the function of a wafer is affected. In properly assessing the importance of a defect, one of the wafers with one of the interference defects can be processed differently from the wafer having one of the material defects of the manufacturer or retailer. For example, a wafer with one of the interference defects can be sold to a desired market at a lower price, rather than being scrapped in bulk with a wafer containing a material defect. In the contemplated embodiment, controller 110 requires input from a user during classification process 300. For example, the user can switch between the one or more sets of design data and the one or more images of the selected area of the sample via the user input 124 on the display 122. For example, display 122 may display both the one or more images of the sample and one or more sets of design data for side-to-side comparison during positioning of one or more defects. Additionally, display 122 can display the one or more images and one or more sets of design data for the sample in an overlay graphic window. By way of another example, the controller 110 can display a corresponding defect pattern and a corresponding attention pattern with the marked electrical property information on the display 122 in response to a user attempt. By way of another example, controller 110 may, prior to continuing classification process 200 (including (but not limited to) an "annotation", "saving" or "continue" attempt), in a defect and marked by one or more electrical design properties The input from the user is required after the display of the corresponding attention pattern. Therefore, the above description should not be taken as limiting the invention, but only as an illustration. While the invention has been described with respect to the specific embodiments of the present invention, it is understood that various modifications and embodiments of the invention may be made without departing from the scope and spirit of the invention. Accordingly, the scope of the invention should be limited only by the scope of the appended claims.

100‧‧‧ system
102‧‧‧ imaging tools
104‧‧‧ samples
106‧‧‧Sample table
110‧‧‧ Controller
112‧‧‧ processor
114‧‧‧Memory Media
116‧‧‧Program Instructions
120‧‧‧User interface
122‧‧‧ display device
124‧‧‧User input
130‧‧ layers
132‧‧‧ polygon
134‧‧‧ polygon
136‧‧‧ polygon
138‧‧‧ polygon
139‧‧‧ polygon
140‧‧‧ Polygon
150‧‧‧ Polygon
160‧‧‧Poly
170‧‧‧ polygon
200‧‧‧ method
202‧‧‧Steps
204‧‧‧Steps
206‧‧‧Steps
208‧‧‧Steps
300‧‧‧ method
302‧‧‧Steps
304‧‧‧Steps
306‧‧‧Steps
308‧‧‧Steps
310‧‧‧Steps

A person skilled in the art can better understand the advantages of the present invention by referring to the accompanying drawings, in which: Figure 1A is a block diagram of one of the systems for wafer inspection in accordance with the present invention. 1B illustrates a set of design data comprising one or more layers in accordance with the present invention. 2 illustrates a process flow diagram of a method for labeling one or more sets of design data for use in defect classification using one or more electrical design properties in accordance with the present invention. 3 illustrates a process flow diagram of one of the methods for automatically classifying one or more defects based on electrical design properties in accordance with the present invention.

300‧‧‧ method

302‧‧‧Steps

304‧‧‧Steps

306‧‧‧Steps

308‧‧‧Steps

310‧‧‧Steps

Claims (39)

A system for automatically classifying one or more defects based on electrical design properties, comprising: an imaging tool; a user interface, wherein the user interface includes a display and a user input device; and a controller Exciting one or more processors configured to execute a set of program instructions stored in the memory, wherein the program instructions are configured to cause the one or more processors to: receive one of the samples Selecting one or more images of the region; receiving one or more sets of design data associated with the selected region of the sample, wherein the set of design materials comprises one or more layers, one of the layers comprising one or more sets of shapes; Locating one or more defects in the one or more images of the selected region of the sample by comparing the one or more images of the selected region of the sample with the one or more sets of design data; Retrieving one or more patterns of interest in the one or more sets of design data for the one or more defects, wherein the one or more patterns of interest comprise one or more annotation design properties, wherein the pattern of interest is comprised of One Or a plurality of shape representations; and classifying the one or more defects in the one or more images of the selected region of the sample based on the one or more annotation electrical design properties. A system for automatically classifying one or more defects based on electrical design properties, as claimed in claim 1, wherein the imaging tool comprises one or more of the following: an optical inspection tool or an SEM inspection tool. A system for claim 1 for automatically classifying one or more defects based on electrical design properties, wherein one shape is a polygon. A system for claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the program instructions are further configured to cause the one or more processors to: display the classified one or more defect. A system for claim 1, wherein the one or more patterns of interest have at least one dimension ranging from 0.250 microns to 10 microns. A system for claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the one or more annotation electrical properties comprise a defect type characteristic, a design secondary characteristic, and an important level to the design At least one of them. The system of claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the program instructions are further configured to cause the one or more processors to: receive one or more sets of design materials, One set of design data includes one or more layers, wherein one layer includes one or more sets of shapes; receiving, from the user input device, one of the one or more sets of design materials, one of the patterns of interest selected, wherein the pattern of interest Represented by one or more shapes; and annotating the pattern of interest in the one or more sets of design materials using one or more electrical design properties associated with the selected pattern of interest. A system for automatically classifying one or more defects based on electrical design properties, as in claim 1, wherein the program instructions are further configured to cause the one or more processors to: perform a pattern search function, wherein The pattern search function uses the one or more electrical design properties to mark one or more repetitions of the pattern of interest. A system for claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the program instructions are further configured to cause the one or more processors to: the one or more sets of design data Displayed on the display of the user interface. A system for claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the program instructions are further configured to cause the one or more processors to: display one or more electrical design properties . The system of claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the program instructions are further configured to cause the one or more processors to: receive the one or more displayed One of the choices of electrical design properties. A system for claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the program instructions are further configured to cause the one or more processors to: store the annotated pattern of interest. The system of claim 1 for automatically classifying one or more defects based on electrical design properties, wherein the program instructions are further configured to cause the one or more processors to: store the annotation of the pattern of interest One or more repetitions. A system for labeling one or more sets of design data using electrical design properties for defect classification, comprising: a user interface, wherein the user interface includes a display and a user input device; and a controller Requiring one or more processors configured to execute a set of program instructions stored in a memory, wherein the program instructions are configured to cause the one or more processors to: receive one or more sets of designs Data, wherein a set of design data includes one or more layers, wherein one layer comprises one or more sets of shapes; receiving, from the user input device, one of the one or more sets of design materials, one of the patterns of interest, wherein the The attention pattern is represented by one or more shapes; and the one of the one or more sets of design materials is labeled with one or more electrical design properties associated with the selected pattern of interest. A system for claiming one or more sets of design data, wherein the program instructions are further configured to cause the one or more processors to: implement a pattern search function, wherein the pattern search function uses the one Or multiple electrical design properties to mark one or more repetitions of the pattern of interest. A system for claiming one or more sets of design data, wherein the program instructions are further configured to cause the one or more processors to: display the one or more sets of design data to the user interface On the display. A system for claiming one or more sets of design data, wherein the program instructions are further configured to cause the one or more processors to: display one or more electrical design properties. A system for claiming one or more sets of design data, wherein the program instructions are further configured to cause the one or more processors to: receive one of the displayed one or more electrical design properties . A system for claiming one or more sets of design data, wherein the one or more electrical design properties are stored in a memory. A system for claiming one or more sets of design data, wherein the one or more electrical design properties are received from a user. A system for claiming one or more sets of design data, wherein the one or more electrical design properties comprise at least one of a defect type characteristic, a design secondary characteristic, and an important level to the design. A system for claiming one or more sets of design data, wherein the program instructions are further configured to cause the one or more processors to: store the annotated pattern of interest. A system for claiming one or more sets of design data, wherein the program instructions are further configured to cause the one or more processors to: store the one or more iterations of the annotation of the pattern of interest. A method for automatically classifying one or more defects based on electrical design properties, comprising: receiving one or more images of a selected region of a sample; receiving one of the selected regions associated with the sample Or a plurality of sets of design data, wherein the one or more sets of design data correspond to the selected area of the sample, wherein a set of design data comprises one or more layers, wherein one layer comprises one or more sets of shapes; by comparing the samples The one or more images of the selected area and the one or more sets of design data to locate one or more defects in the one or more images of the selected area of the sample; The one or more sets of design data of the plurality of defects are taken from one or more patterns of interest, wherein the pattern of interest is represented by one or more shapes, wherein the one or more patterns of interest comprise one or more labels Designing properties; and classifying the one or more defects in the one or more images of the selected region of the sample based on the one or more labeled electrical design properties. A method of claim 24 for automatically classifying one or more defects based on electrical design properties, further comprising: displaying the classified one or more defects. The method of claim 24 for automatically classifying one or more defects, further comprising: receiving one or more sets of design materials, wherein the set of design materials comprises one or more layers, one of the layers comprising one or more sets of shapes Receiving, from the user input device, one of the one or more sets of design materials selected by the one of the patterns of interest, wherein the pattern of interest is represented by one or more shapes; and using a pattern associated with the selected pattern of interest One or more electrical design properties to mark the pattern of interest in the one or more sets of design materials. A method for automatically classifying one or more defects, as claimed in claim 24, further comprising: implementing a pattern search function, wherein the pattern search function uses the one or more electrical design properties to mark one of the patterns of interest Or multiple repetitions. The method of claim 24 for automatically classifying one or more defects, further comprising: displaying the one or more sets of design data on the display of the user interface. A method for automatically classifying one or more defects, as in claim 24, further comprising: displaying one or more electrical design properties. The method of claim 24 for automatically classifying one or more defects, further comprising: receiving one of the displayed one or more electrical design properties. A method for automatically classifying one or more defects, as in claim 24, further comprising: storing the annotated pattern of interest. A method for automatically classifying one or more defects, as in claim 24, further comprising: storing the one or more iterations of the annotation of the pattern of interest. A method for labeling one or more sets of design materials using electrical design properties for defect classification, comprising: receiving one or more sets of design materials, wherein a set of design materials includes one or more layers, one of which includes a Or a plurality of sets of shapes; receiving, by the user input device, one of the one or more sets of design materials selected by the one of the patterns of interest, wherein the pattern of interest is represented by one or more shapes; and using the selected The pattern is associated with one or more electrical design properties to mark the pattern of interest in the one or more sets of design materials. A method for claiming one or more sets of design data using electrical design properties, as in claim 33, comprising: implementing a pattern search function, wherein the pattern search function uses the one or more electrical design properties to mark the attention One or more of the patterns are repeated. The method of claim 33 for labeling one or more sets of design data using electrical design properties, further comprising: displaying the one or more sets of design data on the display of the user interface. A method for claiming one or more sets of design materials using electrical design properties, as in claim 33, further comprising: displaying one or more electrical design properties associated with the selected pattern of interest. The method of claim 33 for labeling one or more sets of design materials using electrical design properties, further comprising: receiving one of the displayed one or more electrical design properties associated with the selected pattern of interest . A method for claiming one or more sets of design materials using electrical design properties, as in claim 33, further comprising: storing the annotated pattern of interest. The method of claim 33 for labeling one or more sets of design materials using electrical design properties, further comprising: storing the one or more iterations of the annotation of the pattern of interest.