TW201714084A - Register error protection through binary translation - Google Patents
Register error protection through binary translationInfo
- Publication number
- TW201714084A TW201714084A TW105121003A TW105121003A TW201714084A TW 201714084 A TW201714084 A TW 201714084A TW 105121003 A TW105121003 A TW 105121003A TW 105121003 A TW105121003 A TW 105121003A TW 201714084 A TW201714084 A TW 201714084A
- Authority
- TW
- Taiwan
- Prior art keywords
- register value
- error protection
- binary translation
- register error
- life
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/52—Binary to binary
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Debugging And Monitoring (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2011/068051 WO2013101165A1 (en) | 2011-12-30 | 2011-12-30 | Register error protection through binary translation |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201714084A true TW201714084A (en) | 2017-04-16 |
TWI603192B TWI603192B (zh) | 2017-10-21 |
Family
ID=48698399
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101149321A TWI551982B (zh) | 2011-12-30 | 2012-12-22 | 透過二進制轉譯之暫存器錯誤保護技術 |
TW106127133A TW201820138A (zh) | 2011-12-30 | 2012-12-22 | 透過二進制轉譯之暫存器錯誤保護技術 |
TW105121003A TWI603192B (zh) | 2011-12-30 | 2012-12-22 | 透過二進制轉譯之暫存器錯誤保護技術 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101149321A TWI551982B (zh) | 2011-12-30 | 2012-12-22 | 透過二進制轉譯之暫存器錯誤保護技術 |
TW106127133A TW201820138A (zh) | 2011-12-30 | 2012-12-22 | 透過二進制轉譯之暫存器錯誤保護技術 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9405647B2 (zh) |
TW (3) | TWI551982B (zh) |
WO (1) | WO2013101165A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10558437B1 (en) * | 2013-01-22 | 2020-02-11 | Altera Corporation | Method and apparatus for performing profile guided optimization for high-level synthesis |
US9448788B1 (en) * | 2014-01-22 | 2016-09-20 | SecondWrite LLC | Binary rewriting system |
GB2539455A (en) * | 2015-06-16 | 2016-12-21 | Nordic Semiconductor Asa | Memory watch unit |
US10296464B2 (en) | 2016-12-09 | 2019-05-21 | Intel Corporation | System, apparatus and method for dynamic profiling in a processor |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6185667B1 (en) * | 1998-04-09 | 2001-02-06 | Teranex, Inc. | Input/output support for processing in a mesh connected computer |
US7219167B2 (en) | 2003-09-25 | 2007-05-15 | Intel Corporation | Accessing configuration registers by automatically changing an index |
USRE45632E1 (en) * | 2005-01-03 | 2015-07-28 | O'shantel Software L.L.C. | Memory-controller-embedded apparatus and procedure for achieving system-directed checkpointing without operating-system kernel support |
US7392433B2 (en) * | 2005-01-25 | 2008-06-24 | International Business Machines Corporation | Method and system for deciding when to checkpoint an application based on risk analysis |
US7689804B2 (en) * | 2006-12-20 | 2010-03-30 | Intel Corporation | Selectively protecting a register file |
US7757040B2 (en) * | 2007-01-30 | 2010-07-13 | International Business Machines Corporation | Memory command and address conversion between an XDR interface and a double data rate interface |
US8352812B2 (en) * | 2007-08-03 | 2013-01-08 | Intel Corporation | Protecting data storage structures from intermittent errors |
US8381032B2 (en) * | 2008-08-06 | 2013-02-19 | O'shantel Software L.L.C. | System-directed checkpointing implementation using a hypervisor layer |
US8397133B2 (en) * | 2008-11-26 | 2013-03-12 | Arizona Board Of Regents For And On Behalf Of Arizona State University | Circuits and methods for dual redundant register files with error detection and correction mechanisms |
US8464035B2 (en) * | 2009-12-18 | 2013-06-11 | Intel Corporation | Instruction for enabling a processor wait state |
US8560924B2 (en) * | 2010-01-05 | 2013-10-15 | International Business Machines Corporation | Register file soft error recovery |
US8966027B1 (en) * | 2010-05-24 | 2015-02-24 | Amazon Technologies, Inc. | Managing replication of computing nodes for provided computer networks |
US9043580B2 (en) * | 2011-04-07 | 2015-05-26 | Via Technologies, Inc. | Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA) |
US8826257B2 (en) * | 2012-03-30 | 2014-09-02 | Intel Corporation | Memory disambiguation hardware to support software binary translation |
-
2011
- 2011-12-30 US US13/994,697 patent/US9405647B2/en not_active Expired - Fee Related
- 2011-12-30 WO PCT/US2011/068051 patent/WO2013101165A1/en active Application Filing
-
2012
- 2012-12-22 TW TW101149321A patent/TWI551982B/zh not_active IP Right Cessation
- 2012-12-22 TW TW106127133A patent/TW201820138A/zh unknown
- 2012-12-22 TW TW105121003A patent/TWI603192B/zh not_active IP Right Cessation
-
2016
- 2016-08-02 US US15/226,854 patent/US20160342495A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US9405647B2 (en) | 2016-08-02 |
TWI551982B (zh) | 2016-10-01 |
WO2013101165A1 (en) | 2013-07-04 |
TW201820138A (zh) | 2018-06-01 |
US20160342495A1 (en) | 2016-11-24 |
TW201346533A (zh) | 2013-11-16 |
TWI603192B (zh) | 2017-10-21 |
US20130318401A1 (en) | 2013-11-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |