TW201445735A - Improved structure of fin-type field effect transistor and manufacturing method thereof - Google Patents

Abstract

The present invention provides an improved structure of fin-type field effect transistor and manufacturing method thereof. The structure comprises a silicon substrate, a silicon fin, an insulation layer, and an epitaxial layer. The silicon fin is formed on the silicon substrate by etching. The cross-sectional width of the silicon fin is smaller than or equal to 5 nm. As a result, Ge or III-V group semiconductor material can be stably formed as an epitaxial layer on the silicon fin directly in a selective manner. The epitaxial layer has a higher critical thickness and lower dislocation density, and the device has the advantages of high carrier mobility and small current leakage because the device junction contains partial silicon material.

Description

Improved structure of fin field effect transistor and manufacturing method thereof

The invention relates to a fin field effect transistor and a manufacturing method thereof, in particular to an improved structure and a manufacturing method of a fin field effect transistor which reduces the width of the fin, enables the epitaxial layer to stably adhere, and improves the performance of the element.

Since the development of integrated circuits in the 1960s, the component density has increased significantly so far. As the component density of integrated circuits increases, the size of components continues to shrink, especially the thickness and source of the gate. The length of the channel between (source)/drain, whose required size has entered the micrometer to nanometer level. As the semiconductor industry progresses to the nanotechnology process node, in order to pursue higher device density, higher performance, and lower cost, it faces challenges in manufacturing and design, and thus develops a three-dimensional design.

For example, Fin Field-Effect Transistor (FinFET), which is a novel metal-oxide-semiconductor (MOS) transistor, is a well-known field effect transistor (Field-effect). Transistor) developed. The structure of the fin field effect transistor includes a base layer, a fin, an oxide layer and a gate formed on the base layer, the oxide layer is formed on the base layer, surrounding the fin Finally, the gate is disposed on the fin and the oxide layer, and further forms a source and a drain.

In the structure of the conventional field effect transistor, the gate through which the current is controlled can only control the on and off of the circuit on one side of the gate, which is a planar structure; compared with the planar structure, the fin field effect transistor The structure of the gate is a fish-like 3D structure that controls the switching on and off of the circuit on both sides of the circuit, thereby enabling better control of current while reducing leakage and dynamic power consumption.

Semiconductor materials such as germanium (Ge) and III-V have good high carrier mobility, and are suitable as epitaxial layers of fin field effect transistors, but the fin material is germanium, and pure germanium and III-V. When the family material is formed on the fin, it is not easy to be stably combined with the crucible, and there is a problem of lattice mismatch and stress. In order to solve this disadvantage, the conventional technique is to grow the Si _1-x Ge _x gradient buffer layer into the crucible.锗 or III-V materials to solve the problem of lattice constant mismatch; but although the yttrium or III-V material is more stably combined with the fin, the buffer layer with high defect density will be included in the component Within the junction structure, the junction leakage of the fin field effect transistor is large. In addition, the Si _1-x Ge _x graded buffer layer is usually very thick and less suitable for component design and fabrication.

Another method for forming ruthenium on the skeg is to make the thickness of the ruthenium layer extremely thin, less than the critical thickness above the ruthenium, about 1 nm thick, but the ruthenium layer of this thickness is not practical. Efficacy exists and lacks the value of application.

Since the prior art is still unable to perfect such problems, it is necessary to break through and solve them. Therefore, how to improve convenience, practicability and economic benefits is a key project that the industry should strive to solve and overcome.

Therefore, the inventor of the present invention has developed a solution that is more convenient, practical, and economical in view of the fact that the conventional fin-type field-effect transistor is not ideal, that is, to develop a solution that is more convenient, practical, and economical. The improved structure of the crystal is intended to promote the development of society, and the present invention has been produced by the idea of a long time.

The object of the present invention is to provide an improved structure of a fin field effect transistor, which is capable of elastically deforming the skeg by reducing the width of the skeg, and directly utilizing the physical properties under the width of the section to allow the epitaxial The layer grows on the skeg, and the ridge has a higher critical thickness and less difference in density due to elastic deformation.

Another object of the present invention is to provide an improved structure of a fin field effect transistor, which directly epitaxially crystallizes a material such as pure germanium or a III-V compound onto a skeg, without using Si _1-x Ge _x or the like. The buffer layer has the advantage of less leakage.

A further object of the present invention is to provide a method for fabricating an improved structure of a fin field effect transistor, which can be selectively formed by a selective epitaxial technique in a conventional thiol-based field effect transistor structure during the manufacturing process. Complete, without the need to use complex technology and excessively increase the cost of the process.

In order to achieve the above-mentioned various purposes and effects, the present invention discloses an improved structure of a fin field effect transistor and a method of fabricating the same, the structure comprising: a germanium base layer having a fin fin (Si Fin) located therein An insulating layer disposed on the base layer and exposing the fin; and an epitaxial layer covering the surface of the fin, the material of the epitaxial layer being selected from the group consisting of One of the group consisting of III-V compounds; wherein the skeletal fin is elongated and has a shape of a narrow upper and a lower width. Thus, by narrowing the cross-sectional width of the skeg, the physical phenomenon of the crystal lattice is easily pulled apart, so that the lattice constant is close to the lattice constant of the epitaxial layer material, so that the lattice does not match. The problem was solved.

10. . . Base layer

12. . . Etch tank

20. . . Fins

twenty two. . . Section width

30. . . Insulation

40. . . Epitaxial layer

50. . . Gate

55. . . Gate insulation

First: it is a schematic structural view of a preferred embodiment of the present invention;
Second: it is a side view of the structure of the preferred embodiment of the present invention;
Figure 3A is a flow chart showing the manufacturing steps of the improved structure of the present invention;
FIG. 3B is a flow chart showing the steps of setting the insulating layer of the present invention; and FIG. 4 is a schematic view showing the structure of the ruthenium base layer after etching according to the present invention.

In order to provide a better understanding and understanding of the features and the efficacies of the present invention, the preferred embodiment and the detailed description are as follows:

Although germanium (Ge) and III-V metals have high carrier mobility, they are suitable as channels for high-performance fin field effect transistors (FinFETs), but because of the large difference between lattice constant and germanium, it is very difficult to Directly integrated on a Si Fin transistor.

First, please refer to the first figure and the second figure, which are a schematic structural view and a side view of a preferred embodiment of the present invention; as shown in the figure, the embodiment includes a base layer 10, a fin 20, and a An insulating layer 30 and an epitaxial layer 40; wherein the skeg 20 is etched through the ruthenium base layer 10, and a plurality of elongated fins having a narrow upper and lower width are formed on the ruthenium base layer 10, such as The cross-sectional width 22 of the fin 20 is less than or equal to 5 nm. As for the insulating layer 30, it is disposed on the ruthenium base layer 10, but it does not completely cover the skeg 20, but exposes the skeg 20 so that the lei is exposed. The layer 40 is coated thereon.

Next, please refer to the third A figure, which discloses the step flow of the foregoing structure at the time of manufacture, which includes the steps:
Step S1: etching a base layer to have a plurality of etching grooves;
Step S2: providing an insulating layer on the ruthenium base layer, partially filling the etched grooves, and exposing a portion of the ruthenium base layer to form a plurality of skegs having a cross-sectional width of less than or equal to 5 nm; S3: growing an epitaxial layer on the skeg, and the material of the epitaxial layer is selected from the group consisting of strontium and a group III-V compound.

Please refer to FIG. 3B, which is a flow chart of the steps of setting the insulating layer; wherein the step of partially filling the etching grooves and exposing a portion of the base layer to form a plurality of fins comprises:
Step S20: filling the etching groove and covering the skegs;
Step S22: chemical mechanical planarization (CMP) of the insulating layer; and step S24: etching the insulating layer after polishing.

In the present invention, the cross-sectional width 22 of the skeg 20 formed by etching is critical, and the cross-sectional width refers to a position at which the surface of the insulating layer is half height, which is substantially less than or equal to 5 nm, and preferably ranges from 4 to 4 ~5nm. The lattice constant of 矽 is 5.43A. However, the thinner the film formed by yttrium, the easier it tends to be elastic deform. At this time, the lattice constant of 矽 will slightly increase in the vertical direction. That is, the length of the lattice side perpendicular to the surface of the insulating layer is slightly pulled apart, so that the lattice constant is greater than 5.43 A, so that there are completely different application results.

Generally speaking, the atoms inside the crystal are regularly arranged in a certain order, and each atom in the crystal is regarded as a point, which represents the vibration center of the atom, and the points are connected by imaginary lines to obtain a The space lattice structure, called the lattice, the smallest geometric unit of the lattice is called the unit cell, the length of each edge in the unit cell is called the lattice constant, and the lattice constant is the basic structural parameter of the crystalline substance. The binding energy between atoms has a direct relationship, and the change in lattice constant reflects changes in the composition and stress state of the crystal.

In the present invention, the epitaxial layer 40 which is overlying the skeg 20 and is coated is a pure ruthenium or a III-V compound; and in the case of pure ruthenium, the lattice constant is 5.65 A, which is equivalent to a standard ruthenium. The lattice constant 5.43A has a 4% difference, so in the general case, the original lattice mismatch between the two causes the germanium to not be well-plated. Further, if the pure germanium epitaxial layer 40 is forcibly formed on the skeg 20, after the two heterogeneous materials are combined, the accumulation of stress may occur due to the mismatch of the lattice parameters, with the epitaxial layer 40 being The thicker the thickness, the greater the accumulated stress. When the material grows beyond a critical thickness, the material can no longer withstand this stress, and the energy is released in the form of a poor displacement.

As mentioned above, the so-called difference row is a kind of line defect, which is a crystal defect caused by irregular arrangement of atoms. The crystal defects are divided into point defects, line defects and surface defects. The difference row discussed in the present invention is also called For line defects, it forms a closed loop in the crystal or terminates on the surface of the crystal, and the difference is divided into a blade row, a spiral row, and a mixed row. As long as the crystal is in a poor row, it will cause an electrical component. The leakage and the carrier mobility decrease.

As described above, since the skeg 20 has been prepared in a very fine form, the lattice constant of yttrium is liable to increase due to elastic deformation, and the lattice constant of yttrium or III-V is lowered by elastic deformation, so that both lattices The constants are matched with each other, and naturally there is no problem of the difference between the rows. Therefore, as long as the etching process is performed by etching the germanium base layer 10 by etching, the etching layer 12 is formed by etching (refer to the fourth drawing), and the insulating layer 30 is exposed to expose the insulating layer 30. The elongated fins 20 can complete the channel structure on a simple epitaxial or III-V semiconductor material to obtain a small-sized, high-mobility thiol-type field effect transistor.

The material of the insulating layer 30 is yttrium oxide for isolation of components, but the material is not limited to the use of yttrium oxide. In addition, on the epitaxial layer 40, a gate 50 is further disposed to control the opening or closing of the channel of the fin 20 from a source to a drain current, wherein the epitaxial layer 40 There is a gate insulating layer 55 between the gate 50 and the gate 50.

Thereby, the epitaxial layer 40 can be easily integrated on the skeg 20, which has good compatibility with the original skeletal transistor process, and has the advantages of small component leakage and high carrier mobility. When the epitaxial layer 40 is grown on the skeg 20, it will deform simultaneously with the skeg 20, and has a higher critical thickness and less difference in density. In addition, the thickness of the epitaxial layer 40 itself can be freely adjusted as needed. The thickness of the epitaxial layer 40 of the epitaxial layer of the present invention is 3 to 15 nm under consideration of practical application value.

In summary, the present invention reduces the skeletal fins in the samarthyl fin field effect transistor to 5 nm or less, so that a semiconductor material such as germanium or a III-V compound can be stably bonded directly through the epitaxial manner. Above the skeletal fins, mass production is not required through complicated technology, and the integration of bismuth or III-V materials with bismuth is better realized, which eliminates the doubts of the prior art that there is a large amount of line difference in this structure, which is undoubtedly An improved structure and manufacturing method of a fin field effect transistor having both practical and economic value.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.

10. . . Base layer

20. . . Fins

30. . . Insulation

40. . . Epitaxial layer

50. . . Gate

55. . . Gate insulation

Claims (10)

A structure of a fin field effect transistor, the system comprising:
a base layer having a fin (Si Fin) thereon;
An insulating layer disposed on the ruthenium base layer and exposing the skeg; and an epitaxial layer overlying the surface of the skeg, the material of the epitaxial layer being selected from the group consisting of 锗 and III- One of a group consisting of a group V compound;
Wherein, the skeletal fin is elongated and has a shape of a narrow upper and a lower width. The structure of the fin field effect transistor according to claim 1, wherein the material of the insulating layer is yttrium oxide. The structure of the fin field effect transistor according to claim 1, wherein the skeg has a cross-sectional width of less than or equal to 5 nm. The structure of the fin field effect transistor according to claim 1, wherein the thickness of the epitaxial layer is 3 to 15 nm. The structure of the fin field effect transistor according to claim 1, wherein the vertical direction lattice constant of the skeg is greater than 5.43A. The structure of a fin field effect transistor according to claim 1, wherein the skeletal fin is formed by etching the ruthenium base layer. The structure of the fin field effect transistor according to claim 1, wherein the epitaxial layer further has a gate. The structure of the fin field effect transistor according to claim 7, wherein the epitaxial layer and the gate further have a gate insulating layer. A method for manufacturing a structure of a fin field effect transistor, comprising the steps of:
Etching a base layer to have a plurality of etching grooves;
An insulating layer is disposed on the ruthenium base layer, partially filling the etched grooves, and exposing a portion of the ruthenium base layer to form a plurality of skegs having a cross-sectional width of less than or equal to 5 nm; and growing an epitaxial The layer is formed on the skeg, and the material of the epitaxial layer is selected from the group consisting of ruthenium and a group III-V compound. The method for manufacturing a structure of a fin field effect transistor according to claim 9, wherein the step of partially filling the etching grooves and exposing a portion of the base layer to form a plurality of fins comprises:
Filling the etching groove and covering the fins;
The insulating layer is chemically mechanically polished; and the insulating layer is etched back after grinding.