TW201324479A - Active matrix multi-stable display apparatus and method for driving display panel thereof - Google Patents

Abstract

An active matrix multi-stable display apparatus and a method for driving a display panel thereof are provided. The method includes the following steps. A frame is divided for including a resetting phase, a first gray phase and a second gray phase. In the resetting phase, a reset voltage is provided into a pixel of the display panel for driving the pixel into homotropic state. In the first gray phase, a first gray voltage is provided into the pixel. In the second gray phase, a second gray voltage is provided into the pixel.

Description

Active matrix multi-stable display device and driving method thereof

The present invention relates to a multi-stable display device, and more particularly to an active matrix (AM) multi-stable display device, and driving of an active matrix multi-stable display panel therein method.

Compared with passive matrix (PM) Cholesteric Liquid Crystal (Ch-LC) displays, active matrix (AM) cholesteric liquid crystal displays have cross-talk and are achievable Video rate and other advantages. However, while pursuing the video rate, the update speed is fast, and the time for charging and discharging the liquid crystal is not sufficient, so that the display screen cannot be optimized. In terms of gray-scale driving, the current gray-scale control technology can be divided into pulse-width modulation (PWM) and voltage modulation. The pulse width modulation gray scale control method causes large power consumption due to fast signal switching. The voltage modulation is limited by the number of voltage levels that drive the integrated circuit. When the number of voltage levels is smaller, the number of gray levels that the display can present is also less. When the number of voltage levels is larger, although the number of gray scales can be achieved, the cost of driving the integrated circuit is also increased.

The present disclosure provides an active matrix (AM) multi-stable display device and a driving method thereof for driving an active matrix multi-stable display panel with a data driver having less voltage level. The active matrix multi-stable display panel exhibits more gray scale numbers.

The embodiment of the present disclosure provides a driving method for an active matrix multi-stable display panel, including: dividing a frame period into at least one resetting phase, a first grayscale period, and a second During the reset period, a reset voltage is supplied to a pixel of the active matrix multi-stable display panel to drive the pixel to a homogenous state; During a grayscale period, a first grayscale voltage is provided to the pixel; and during the second grayscale period, a second grayscale voltage is provided to the pixel.

The disclosed embodiment provides an active matrix multi-stable display device, including an active matrix multi-stable display panel, a scan driver, a data driver, and a controller. The active matrix multi-stable display panel has at least one scan line, at least one data line and at least one pixel, wherein the pixel is coupled to the scan line and the data line. A scan driver is coupled to the scan line. A data driver is coupled to the data line. The controller is coupled to the scan driver and the data driver. The controller divides a frame period into at least one reset period, a first gray scale period, and a second gray scale period. During the reset period, the controller controls the data driver to provide a reset voltage to the pixel to drive the pixel to a homogeneous state. During the first grayscale period, the controller controls the data driver to provide a first grayscale voltage to the pixel. During the second grayscale period, the controller controls the data driver to provide a second gray scale voltage to the pixel.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a functional block diagram illustrating an active matrix (AM) multi-stable display device 100 in accordance with an embodiment of the present disclosure. The display device 100 includes an active matrix multi-stable display panel 110, a scan driver 120, a data driver 130, and a controller 140. The active matrix multi-stable display panel 110 can be an active array display panel of any bi-stable or multi-stable display medium, such as a cholesteric liquid crystal (Ch-LC) display panel or Other bistable display media display panels. The active matrix multi-stable display panel 110 has a plurality of scan lines Y1, Y2, Y3, Y4, ..., Yn and a plurality of data lines X1, X2, X3, X4, ..., Xm. The scan driver 120 is coupled to the scan lines Y1 Y Yn. The data driver 130 is coupled to the data lines X1 to Xm. The controller 140 is coupled to the scan driver 120 and the data driver 130.

One pixel is arranged at the intersection of each scan line and each data line. For example, the pixel 111 is disposed at the intersection of the scan line Y1 and the data line X1. Here, the pixel 111 is taken as an illustrative example, and other pixels may refer to the related description of the pixel 111. Each pixel (eg, pixel 111) includes a switching element SW, a storage capacitor Cst, and a pixel capacitor Cp, as shown in FIG. The switching element SW may be a thin film transistor (TFT) or other controlled switch. The first end of the switching element SW is coupled to the data line X1, and the control end of the switching element SW is coupled to the scan line Y1. The pixel capacitor Cp and the first end of the storage capacitor Cst are coupled to the second end of the switching element SW, and the pixel capacitor Cp and the second end of the storage capacitor Cst are coupled to the same or different reference voltages. For example, in this embodiment, the second end of the pixel capacitor Cp and the second end of the storage capacitor Cst are coupled to a common voltage Vcom. In other embodiments, the second end of the pixel capacitor Cp and the second end of the storage capacitor Cst are respectively coupled to different reference voltages. For example, the second end of the pixel capacitor Cp is coupled to the common voltage Vcom, and the storage capacitor Cst The second end is coupled to a ground voltage.

While the switching element SW is turned on, the data driver 130 outputs the driving voltage Vc to the pixel capacitance Cp and the storage capacitance Cst. After the switching element SW is turned off, the driving voltage Vc is held in the pixel 111, wherein the driving voltage Vc and the common voltage Vcom form a voltage difference ΔV between the two electrodes of the pixel capacitance Cp. A multi-stable display medium such as cholesteric liquid crystal (Ch-LC) is disposed between the two electrodes of the pixel capacitor Cp. Taking cholesterol liquid crystal as an example, FIG. 2 illustrates a schematic diagram of an ideal curve of a reflectance-voltage curve of a cholesteric liquid crystal. The horizontal axis of Fig. 2 represents the voltage difference ΔV (absolute value) between the two electrodes of the pixel capacitance Cp, and the vertical axis represents the light reflectance of the multi-stable pixel (pixel capacitance Cp). The solid line in FIG. 2 indicates that the initial state of the liquid crystal molecule is a planar state (planar, or reflective state, the bright state), and the broken line indicates that the initial state of the liquid crystal molecule is a focal conic, or a non-reflective state. Characteristic curve of the dark state). If the initial state of the pixel is a bright state (refer to the solid line in FIG. 2), as the voltage amplitude between the electrodes increases from VA to VB, the state of the pixel will shift from a bright state to a dark state. If the voltage amplitude between the electrodes continues to rise, as the voltage amplitude increases from VC to VD, the state of this pixel will shift from the Homotropic state to the bright state. If the initial state of the pixel is a dark state (please refer to the broken line in FIG. 2), the state of the pixel remains in the dark state during the rise of the voltage amplitude from VA to VB between the electrodes. If the voltage amplitude between the electrodes continues to increase, as the voltage amplitude increases from VC to VD, the dark state pixel will transition from a homogeneous state to a bright state pixel.

The controller 140 stores and processes the screen information. The controller 140 outputs the screen information to the data driver 130, and controls the data driver 130 to output the screen information to the active matrix multi-stable display panel 110 through the data lines X1 to Xm. At the same time, the controller 140 controls the scan driver 120 to synchronously output a scan signal to drive the switching element SW of each pixel (for example, the pixel 111) through the scan lines Y1 to Yn.

FIG. 3 is a schematic diagram showing a signal timing diagram of the display device 100 of FIG. 1 according to an embodiment of the present disclosure. In this example, a frame period FP is at least divided into a resetting phase RP, a first grayscale period GP1, a second grayscale period GP2, and a discharge phase DCP. In this embodiment, the two gray-scale periods GP1 and GP2 are taken as an example. However, the implementation manner of this embodiment is not limited thereto. According to the teachings of the present embodiment, those skilled in the art can determine the number of gray period periods p in a frame period FP according to their design requirements.

In the reset period RP, the controller 140 drives the scan lines Y1 to Yn through the scan driver 120 to simultaneously turn on the switching elements SW of the pixels of each of the scan lines Y1 to Yn. While the switching element SW of the pixel is turned on, the controller 140 controls the data driver 130 to supply the reset voltage (Vcom+Vh) or (Vcom-Vh) to the data line X1~Xm of the active matrix multi-stable display panel 110. In order to write the reset voltage to the pixel capacitance Cp of all pixels. All pixels of the active matrix multi-stable display panel 110 are driven to a Homotropic state based on the reset voltage.

After the end of the reset period, the RP enters the first gray level period GP1. During the first grayscale period GP1, the controller 140 sequentially drives the scan lines Y1~Yn through the scan driver 120, as shown in FIG. In conjunction with the scan timing of the scan lines Y1~Yn, the controller 140 outputs the first gray scale voltage to the data lines X1~Xm through the data driver 130 to write the first gray scale voltage to the turned-on pixels on the scan lines Y1~Yn. . For example, if the pixel is to be set to a bright state, a bright state voltage (Vcom+Vp) or (Vcom-Vp) is applied to the pixel when the pixel is scanned during the first grayscale period GP1. To set the pixel to the dark state, when the pixel is scanned during the first grayscale period GP1, a dark state voltage (Vcom+Vfc) or (Vcom-Vfc) is applied to the pixel. The voltage value Vp is less than or approximately equal to the voltage VA shown in FIG. 2, and the voltage value Vfc is approximately between the voltage VB and the voltage VC shown in FIG. The above voltage values Vp and Vfc are both smaller than the voltage value Vh.

After the end of the first gray scale period GP1, the second gray scale period GP2 is entered. During the second grayscale period GP2, the controller 140 sequentially drives the scan lines Y1 to Yn through the scan driver 120, as shown in FIG. In conjunction with the scan timing of the scan lines Y1~Yn, the controller 140 outputs the first gray scale voltage to the data lines X1~Xm through the data driver 130, so as to write the second gray scale voltage to the turned-on pixels on the scan lines Y1~Yn. . The second gray scale voltage may be the same as the first gray scale voltage, or may be different from the first gray scale voltage. For example, the data driver 130 provides a bright state voltage (Vcom+Vp) (ie, a first grayscale voltage) to the pixel during the first grayscale period GP1, and provides a dark state voltage (Vcom) during the second grayscale period GP2. +Vfc) (ie, the second grayscale voltage) is at the pixel, and the pixel exhibits a grayscale state between the bright state and the dark state during the frame period. Therefore, even if the data driver 130 can only output two driving voltage levels (bright state voltage and dark state voltage), by operating the driving method of the active matrix multi-stable display panel according to the embodiment, the active matrix type is stable. Each pixel of the state display panel 110 can exhibit 2*2=4 gray scales.

The pixel 111 is driven by a positive polarity signal as an example. In the reset period RP, the controller 140 controls the data driver 130 to supply the reset voltage (Vcom+Vh) to the data line X1 of the active matrix multi-stable display panel 110 to write the reset voltage (Vcom+Vh). The pixel capacitance Cp of the pixel 111 is entered such that the pixel 111 is driven to a homogeneous state. To set the pixel 111 to the bright state, the GP2 data driver 130 applies a bright state voltage (Vcom+Vp) to the pixel 111 during the first grayscale period GP1 and the second grayscale period. To set the pixel 111 to the dark state, the data driver 130 applies a dark state voltage (Vcom+Vfc) to the pixel 111 during both the first gray scale period GP1 and the second gray scale period GP2. To set the pixel 111 to the first gray state between the bright state and the dark state, the data driver 130 applies the dark state voltage (Vcom+Vfc) to the pixel 111 during the first grayscale period GP1, and During the second gray scale, GP2 applies a bright state voltage (Vcom + Vp) to the pixel 111. To set the pixel 111 to the second gray state between the bright state and the dark state, the data driver 130 applies the bright state voltage (Vcom+Vp) to the pixel 111 during the first grayscale period GP1, and During the second gray scale, GP2 applies a dark state voltage (Vcom + Vfc) to the pixel 111.

The pixel 111 is driven by a negative polarity signal as an example. In the reset period RP, the data driver 130 writes the reset voltage (Vcom-Vh) to the pixel capacitance Cp of the pixel 111 via the data line X1, so that the pixel 111 is driven to the homogeneous state. To set the pixel 111 to the bright state, the data driver 130 applies a bright state voltage (Vcom-Vp) to the pixel 111 during both the first gray scale period GP1 and the second gray scale period GP2. To set the pixel 111 to the dark state, the data driver 130 applies a dark state voltage (Vcom-Vfc) to the pixel 111 during both the first gray scale period GP1 and the second gray scale period GP2. To set the pixel 111 to the first gray state between the bright state and the dark state, the data driver 130 applies the dark state voltage (Vcom-Vfc) to the pixel 111 during the first grayscale period GP1, and During the second gray scale, GP2 applies a bright state voltage (Vcom-Vp) to the pixel 111. To set the pixel 111 to the second gray state between the bright state and the dark state, the data driver 130 applies the bright state voltage (Vcom-Vp) to the pixel 111 during the first grayscale period GP1, and During the second gray scale, GP2 applies a dark state voltage (Vcom-Vfc) to the pixel 111.

Therefore, if the data driver 130 can output s kinds of driving voltage levels, since the frame period FP has two gray-scale periods GP1 and GP2, by driving the driving method of the active matrix multi-stable display panel according to the embodiment, multi-stable active matrix display each pixel of the panel 110 may be presented s * s = s ^ 2 species (i.e., s ² species) grayscale. Similarly, if the data driver 130 can output s kinds of driving voltage levels, and the frame period FP has p gray scale periods, by driving the driving method of the active matrix multi-stable display panel according to the embodiment, Each pixel of the active matrix multi-stable display panel 110 can exhibit s^p (ie, s ^p ) gray scales. Therefore, the present embodiment can use the data driver 130 with lower cost (less driving voltage level) to achieve more gray scale display, which is greatly helpful for the improvement of the active matrix CMOS liquid crystal driving screen.

After the end of the second gray level period GP2, it enters the DCP during discharge. In the DCP during discharge, the controller 140 drives the scan lines Y1 to Yn through the scan driver 120 to simultaneously turn on the switching elements SW of the pixels of each of the scan lines Y1 to Yn. While the switching element SW of the pixel is turned on, the controller 140 controls the data driver 130 to supply the common voltage Vcom to the data lines X1 to Xm of the active matrix multi-stable display panel 110 to write the common voltage Vcom to all the pixels. Pixel capacitance Cp. Therefore, the voltage difference across the pixel capacitance Cp is discharged to near 0 volts. Since the voltage difference across all pixels of the DCP during discharge of the FP during this frame has been discharged to near 0 volts, a reset voltage (Vcom+Vh) is applied to all pixels during the reset during the next frame or ( In the case of Vcom-Vh), the present embodiment can avoid the impact of the reset voltage and burn the switching element SW in the pixel.

FIG. 4 is a schematic diagram showing a signal timing diagram of the display device 100 of FIG. 1 according to another embodiment of the present disclosure. The embodiment shown in FIG. 4 can refer to the related description of FIG. 3. Different from the embodiment shown in FIG. 3, in the first gray scale period GP1 in the embodiment shown in FIG. 4, a pre-charge operation is also performed. Referring to FIG. 4, the first gray scale period GP1 is divided into at least n scan line periods SLP_1, SLP_2, SLP_3, ..., SLP_n. During one of the scan line periods SLP_1 S SLP_n during the scan line period SLP_i, the scan driver 120 turns on the scan line Y1 in advance in addition to the pixels on one of the n scan lines Y1 YYn. ~Yn One of the pixels on the other scan line Y(i+1).

For example, the scan driver 120 turns on the pixels on the first scan line Y1 during the scan line period SLP_1 so that the data driver 130 writes the gray scale voltage to the pixels of the scan line Y1. In the same scan line period SLP_1, the scan driver 120 also turns on the pixels on the other scan line Y2 in advance, so that the data driver 130 writes the gray scale voltage of the pixel on the scan line Y1 to the pixels of the scan line Y2, so that the scan line The pixel of Y2 completes the precharge operation. Next, the data driver 130 writes the gray scale voltage of the pixel on the scan line Y2 to the pixels of the scan lines Y2 and Y3 during the scan line period SLP_2. By analogy, the data driver 130 writes the gray scale voltage of the pixel on the scan line Yi to the pixels of the scan lines Yi and Y(i+1) during the scan line period SLP_i.

Therefore, the pixels of the display panel 110 can be precharged during the first gray scale period GP1, so that the pixel capacitor Cp has sufficient time to be charged and discharged in advance, and the RC loading issue is compensated for the address time. The problem of charging and discharging speed is not fast enough.

FIG. 5 is a schematic diagram showing a signal timing diagram of the display device 100 of FIG. 1 according to still another embodiment of the present disclosure. The embodiment shown in FIG. 5 can refer to the related description of FIG. 3. Different from the embodiment shown in Fig. 3, in the embodiment shown in Fig. 5, the reset period RP and the discharge period DCP. Scan driver 120 (or controller 140) groups scan lines Y1~Yn of active matrix multi-stable display panel 110, with each group containing one or more scan lines. The reset period RP contains multiple reset sub-periods. During the first reset period of the reset period RP, the pixels of the first scan line group of the scan lines Y1 to Yn are reset to the homogeneous state. During the second reset period of the reset period RP, the pixels of the second scan line group of the scan lines Y1 to Yn are reset to the homogeneous state. In this embodiment, the first reset sub-period does not overlap the second reset sub-period.

For example, the embodiment shown in FIG. 5 divides the scan lines Y1~Yn into n groups, wherein each scan line group includes one scan line. During the first reset sub-period RSP1 of the reset period RP, the scan driver 120 turns on the pixels on the scan line Y1 (the first scan line group), and the data driver 130 resets the pixels of the scan line Y1 to the homogeneous state. During the second reset sub-time period RSP2, the scan driver 120 turns on the pixels on the scan line Y2 (the second scan line group), and the data driver 130 resets the pixels of the scan line Y2 to the homogeneous state. The rest is like this.

Similarly, the DCP during discharge contains multiple periods of electron discharge. During the first electron discharge period of the DCP during discharge, the data driver 130 supplies the common voltage Vcom to the pixels of the first scan line group of the scan lines Y1 to Yn. During the second electron discharge period of the DCP during discharge, the data driver 130 supplies the pixels of the second scan line group of the common voltage Vcom to the scan lines Y1 to Yn. For example, referring to FIG. 5, during the first discharge period DSP1 of the DCP during discharge, the scan driver 120 turns on the pixels on the scan line Y1 (the first scan line group), and the data driver 130 supplies the common voltage Vcom to the scan line Y1. Pixel. During the second electron discharge period DSP2, the scan driver 120 turns on the pixels on the scan line Y2 (the second scan line group), and the data driver 130 supplies the pixels of the common voltage Vcom to the scan line Y2. The rest is like this.

FIG. 6 is a schematic diagram showing a signal timing diagram of the display device 100 of FIG. 1 according to still another embodiment of the present disclosure. The embodiment shown in FIG. 6 can refer to the related description of FIGS. 3 to 5. Different from the embodiment shown in FIG. 5, in the embodiment shown in FIG. 6, the reset period RP, the first gray scale period GP1, and the discharge period DCP. The portion of the first gray scale period GP1 can be referred to the relevant description of FIG. In the present embodiment, the two reset sub-periods that are temporally adjacent in the reset period RP overlap each other. For example, the first reset sub-period RSP1 of the reset period RP in FIG. 6 partially overlaps the second reset sub-period RSP2. In addition, the two electron-releasing periods adjacent in time series in the DCP during discharge also overlap each other. For example, during the first discharge period of the DCP during the discharge in FIG. 6, the DSP1 partially overlaps the second discharge period DSP2. Therefore, the pixels of the display panel 110 can be precharged during the reset period RP, the first gray scale period GP1, and the discharge period DCP, so that the pixel capacitor Cp has sufficient time to be charged and discharged in advance, thereby compensating for the resistance and capacitance load problem. (RC loading issue) causes the problem that the charging and discharging speed is not fast enough during the address time.

FIG. 7 is a timing diagram showing waveforms of the common voltage shown in FIG. 1 according to an embodiment of the present disclosure. In Fig. 7, the horizontal axis represents time and the vertical axis represents voltage. Here, the pixel 111 is taken as an illustrative example, and other pixels may refer to the related description of the pixel 111. Referring to FIGS. 1 and 7, as the voltage of the scan line Y1 turns on the timing of the switching element SW, the data driver 130 can output the driving voltage Vc to the pixel capacitor Cp and the storage capacitor Cst. After the switching element SW is turned off, the driving voltage Vc is held in the pixel 111.

Figure 7 illustrates the FP during two complete frames, and the remaining frames can be analogized with reference to the description of Figure 7. Referring to the left frame period FP of FIG. 7 , in the reset period RP and the first gray scale period GP1 , the controller 140 adjusts the common voltage Vcom of the active matrix multi-stable display panel 110 to the voltage level V1 . When the voltage of the scan line Y1 turns on the switching element SW, the data driver 130 may output the reset voltage (Vcom+Vh) and the bright state voltage (Vcom+Vp) to the pixel during the reset period RP and the first gray scale period GP1, respectively. Capacitor Cp. Therefore, the data driver 130 drives the pixels 111 with positive polarity during the reset period RP and the first gray scale period GP1.

In the second gray scale period GP2, the controller 140 adjusts the common voltage Vcom to the voltage level V2. The voltage level V2 is greater than the voltage level V1. For the application of the active matrix multi-stable display panel 110 driven by the polarity inversion technique, since the current frame period (ie, the full frame period FP on the left side of FIG. 7) drives the pixel 111 with a positive polarity, the next frame During the period (ie, the full frame period FP on the right side of FIG. 7), the pixel 111 is driven in a negative polarity. In the present embodiment, in the reset period RP and the first gray scale period GP1 of the next frame period (ie, the full frame period FP on the right side of FIG. 7), the controller 140 adjusts the common voltage Vcom to be greater than the voltage level V1. With the voltage level V3 of V2, the negative polarity drive is performed. Since the common voltage Vcom has been previously adjusted to the voltage level V2 before entering the next frame period, the swing of the common voltage Vcom is reduced, thereby avoiding the reset voltage burnout switch when entering the reset period RP. The problem with component SW. Therefore, compared with the embodiment shown in Figs. 3 to 6, the present embodiment can omit the DCP during discharge.

The modulation mode of the common voltage Vcom in the FP during the complete frame period on the right side of FIG. 7 can be analogized with reference to the related description of the FP in the complete frame period on the left side of FIG. 7 . Referring to the full frame period FP on the right side of FIG. 7, in the reset period RP and the first gray scale period GP1, the controller 140 adjusts the common voltage Vcom to the voltage level V3, and in the second gray level period GP2, controls The controller 140 adjusts the common voltage Vcom to a voltage level V2 that is less than the voltage level V3.

FIG. 8 is a timing diagram showing waveforms of the common voltage shown in FIG. 1 according to another embodiment of the present disclosure. Similarly to FIG. 7, the horizontal axis and the vertical axis in FIG. 8 represent time and voltage, respectively, and the pixel 111 is still exemplified. Referring to the left frame period FP of FIG. 8, in the reset period RP, the controller 140 adjusts the common voltage Vcom to the voltage level V1. When the voltage of the scanning line Y1 turns on the switching element SW during the reset period RP, the data driver 130 can output the reset voltage (Vcom+Vh) to the pixel capacitance Cp. During the first grayscale period GP1, the controller 140 adjusts the common voltage Vcom to a voltage level V2 that is greater than the voltage level V1. When the voltage of the scanning line Y1 turns on the switching element SW during the first gray scale period, the data driver 130 can output the bright state voltage (Vcom+Vp) to the pixel capacitance Cp. Therefore, the data driver 130 drives the pixels 111 with positive polarity during the reset period RP and the first gray scale period GP1. In the second gray scale period GP2, the controller 140 adjusts the common voltage Vcom to a voltage level V3 greater than the voltage level V2. At this time, the data driver 130 drives the pixel 111 with a negative polarity during the second gray scale period GP2.

Since the common voltage Vcom has been gradually adjusted to the voltage level V3 in advance before entering the next frame period, the swing of the common voltage Vcom at the time of polarity switching is reduced, thereby avoiding resetting when entering the reset period RP. The voltage burns down the problem of the switching element SW. Therefore, compared with the embodiment shown in Figs. 3 to 6, the present embodiment can omit the DCP during discharge.

The modulation mode of the common voltage Vcom in the FP during the complete frame period on the right side of FIG. 8 can be analogized with reference to the related description of the FP during the complete frame on the left side of FIG. Referring to the full frame period FP on the right side of FIG. 8, in the reset period RP, the controller 140 adjusts the common voltage Vcom to the voltage level V3. During the first grayscale period GP1, the controller 140 adjusts the common voltage Vcom to a voltage level V2 that is less than the voltage level V3. During the second gray scale period GP2, the controller 140 adjusts the common voltage Vcom to a voltage level V1 that is less than the voltage level V2.

FIG. 9 is a timing diagram showing waveforms of the common voltage shown in FIG. 1 according to still another embodiment of the present disclosure. Similarly to FIG. 7, the horizontal axis and the vertical axis in FIG. 9 represent time and voltage, respectively, and the pixel 111 is still exemplified. Referring to the left frame period FP of FIG. 9, in the reset period RP, the controller 140 adjusts the common voltage Vcom to the voltage level V1, and the data driver 130 outputs the reset voltage (Vcom+Vh) to the pixel capacitance Cp. During the first grayscale period GP1, the controller 140 maintains the common voltage Vcom at the voltage level V1, and the data driver 130 outputs the bright state voltage (Vcom+Vp) to the pixel capacitor Cp. Therefore, the data driver 130 drives the pixels 111 with positive polarity during the reset period RP and the first gray scale period GP1. During the second gray scale period GP2, the controller 140 adjusts the common voltage Vcom to a voltage level V2 that is greater than the voltage level V1. At this time, the data driver 130 drives the pixel 111 with a negative polarity during the second gray scale period GP2.

Referring to the full frame period FP on the right side of FIG. 8, in the reset period RP, the controller 140 adjusts the common voltage Vcom to the voltage level V3, and the data driver 130 outputs the negative polarity reset voltage (Vcom-Vh) to the pixel. Capacitor Cp. During the first grayscale period GP1, the controller 140 adjusts the common voltage Vcom to a voltage level V2 that is less than the voltage level V3, and the data driver 130 outputs a negative polarity bright state voltage (Vcom-Vp) to the pixel capacitance Cp. During the second gray-scale period GP2, the controller 140 adjusts the common voltage Vcom to a voltage level V1 that is less than the voltage level V2, and the data driver 130 outputs a positive-state bright state voltage (Vcom+Vp) to the pixel capacitance Cp. Since the common voltage Vcom has been progressively adjusted to the voltage level V1 before entering the next frame period, the swing of the common voltage Vcom at the time of polarity switching is reduced, thereby avoiding resetting when entering the reset period RP. The voltage burns down the problem of the switching element SW. Therefore, compared with the embodiment shown in FIGS. 3 to 6, the present embodiment can also omit the DCP during discharge.

In summary, the embodiments of the present disclosure employ a multi-subframe driving waveform architecture, that is, a plurality of grayscale periods are configured in a FP during a frame period. The driving waveform is written to the same pixel in multiple stages in one frame during FP, so that more gray scale numbers than the voltage level of the data driver 130 can be generated. Through the driving method of the embodiments of the present disclosure, the driver 130 with less voltage reference digits can be used to achieve more display gray scales, especially for the improvement of the active matrix cholesteric liquid crystal driving screen. In some embodiments, the pixels are precharged to allow the liquid crystal to have sufficient time to charge and discharge in advance, compensating for the problem of insufficient charge and discharge times during the address time due to the RC loading issue.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Display device

110. . . Active matrix multi-stable display panel

111. . . Pixel

120. . . Scan drive

130. . . Data driver

140. . . Controller

Cp. . . Pixel capacitance

Cst. . . Storage capacitor

DCP. . . During discharge

DSP1, DSP2. . . Electron discharge

FP. . . Frame period

GP1, GP2. . . Gray period

RP. . . Reset period

RSP1, RSP2. . . Reset period

SLP_1~SLP_n. . . Scan line period

SW. . . Switching element

Vc. . . Driving voltage

Vcom. . . Common voltage

X1~Xm. . . Data line

Y1~Yn. . . Scanning line

FIG. 1 is a schematic diagram of functional modules of an active array multi-stable display device according to an embodiment of the present disclosure.

Fig. 2 is a view showing an ideal curve of a reflectance-voltage characteristic curve of a cholesteric liquid crystal.

FIG. 3 is a schematic diagram showing signal timing of the display device of FIG. 1 according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram showing signal timing of the display device shown in FIG. 1 according to another embodiment of the present disclosure.

FIG. 5 is a schematic diagram showing signal timing of the display device shown in FIG. 1 according to still another embodiment of the present disclosure.

FIG. 6 is a schematic diagram showing signal timing of the display device shown in FIG. 1 according to still another embodiment of the present disclosure.

FIG. 7 is a timing diagram showing waveforms of the common voltage shown in FIG. 1 according to an embodiment of the present disclosure.

FIG. 8 is a timing diagram showing waveforms of the common voltage shown in FIG. 1 according to another embodiment of the present disclosure.

FIG. 9 is a timing diagram showing waveforms of the common voltage shown in FIG. 1 according to still another embodiment of the present disclosure.

DCP. . . During discharge

DSP1, DSP2. . . Electron discharge

FP. . . Frame period

GP1, GP2. . . Gray period

RP. . . Reset period

RSP1, RSP2. . . Reset period

SLP_1~SLP_n. . . Scan line period

Vcom. . . Common voltage

X1~Xm. . . Data line

Y1~Yn. . . Scanning line

Claims (24)

A driving method for an active matrix multi-stable display panel, comprising: dividing a frame period into at least one reset period, a first gray level period and a second gray level period; during the reset period, providing Resetting a voltage to a pixel of the active matrix multi-stable display panel to drive the pixel to a homogeneous state; during the first gray scale period, providing a first gray scale voltage to the pixel; During the second gray level period, a second gray scale voltage is provided to the pixel. The driving method of the active matrix multi-stable display panel according to claim 1, wherein all pixels of the active matrix multi-stable display panel are simultaneously reset to the homogeneous state during the reset period. The driving method of the active matrix multi-stable display panel according to claim 1, further comprising: grouping the plurality of scan lines of the active matrix multi-stable display panel; During a reset period, pixels of a first scan line group of the scan lines are reset to the homogeneous state; and during a second reset period of the reset period, one of the scan lines is The pixels of the second scan line group are reset to the homogeneous state. The driving method of the active matrix multi-stable display panel according to claim 3, wherein the first reset sub-period partially overlaps the second reset sub-period. The driving method of the active matrix multi-stable display panel according to claim 1, further comprising: dividing the first gray scale period into at least n scan line periods SLP_1 S SLP_n; during the scan lines SLP_1 ~SLP_n one of the scan line periods SLP_i, turning on the pixels of one of the n scan lines Y1 YYn of the active matrix type multi-stable display panel; and pre-turning on the scan lines during the current scan line period SLP_i The other pixel of Y1~Yn scan line Y(i+1). The driving method of the active matrix multi-stable display panel according to claim 1, wherein the frame period further comprises a discharge period, the driving method further comprising: providing a common voltage to the discharge period The pixel. The driving method of the active matrix multi-stable display panel according to claim 6, further comprising: grouping the plurality of scan lines of the active matrix multi-stable display panel; a first during the discharging period Providing the common voltage to pixels of a first scan line group of the scan lines during electron discharge; and providing a second scan of the common voltage to the scan lines during a second discharge period during the discharge The pixels of the line group. The driving method of the active matrix multi-stable display panel according to claim 7, wherein the first electron discharging period partially overlaps the second electron discharging period. The driving method of the active matrix multi-stable display panel according to claim 1, further comprising: adjusting a common voltage of the active matrix multi-stable display panel to a first during the resetting period a voltage level; the common voltage is adjusted to a second voltage level during the first gray level period, wherein the second voltage level is greater than the first voltage level; and during the second gray level period And adjusting the common voltage to a third voltage level, wherein the third voltage level is greater than the second voltage level. The driving method of the active matrix multi-stable display panel according to claim 1, further comprising: adjusting a common voltage of the active matrix multi-stable display panel to a first during the resetting period a voltage level; the common voltage is adjusted to a second voltage level during the first gray level period, wherein the second voltage level is less than the first voltage level; and during the second gray level period And adjusting the common voltage to a third voltage level, wherein the third voltage level is less than the second voltage level. The driving method of the active matrix multi-stable display panel according to claim 1, further comprising: one of the active matrix multi-stable display panels during the reset period and the first gray scale period The common voltage is adjusted to a first voltage level; and during the second gray level period, the common voltage is adjusted to a second voltage level, wherein the second voltage level is greater than the first voltage level. The driving method of the active matrix multi-stable display panel according to claim 1, further comprising: one of the active matrix multi-stable display panels during the reset period and the first gray scale period The common voltage is adjusted to a first voltage level; and during the second gray level period, the common voltage is adjusted to a second voltage level, wherein the second voltage level is less than the first voltage level. An active matrix multi-stable display device includes: an active matrix multi-stable display panel having at least one scan line, at least one data line and at least one pixel, wherein the pixel is coupled to the scan line and the data line a scan driver coupled to the scan line; a data driver coupled to the data line; and a controller coupled to the scan driver and the data driver; wherein the controller divides at least one frame period a reset period, a first gray scale period and a second gray scale period; during the reset period, the controller controls the data driver to provide a reset voltage to the pixel to drive the pixel to a pixel a state in which the controller controls the data driver to provide a first gray scale voltage to the pixel; and during the second gray scale period, the controller controls the data driver to provide a The second gray scale voltage is at the pixel. The active matrix multi-stable display device of claim 13, wherein all pixels of the active matrix multi-stable display panel are simultaneously reset to the homogeneous state during the reset period. The active matrix multi-stable display device of claim 13, wherein the scan driver groups the scan lines of the active matrix multi-stable display panel; a first weight during the reset period During the setting, the controller controls the data driver to reset pixels of a first scan line group of the scan lines to the homogeneous state; and during a second reset period during the reset, the control The device controls the data driver to reset pixels of a second scan line group of the scan lines to the homogeneous state. The active matrix multi-stable display device of claim 15, wherein the first reset sub-period partially overlaps the second reset sub-period. The active matrix multi-stable display device according to claim 13, wherein the controller divides the first gray scale period into at least n scan line periods SLP_1 S SLP_n; during the scan lines SLP_1~ SLP_n one of the scan line periods SLP_i, the controller controls the scan driver to turn on the pixels of one of the n scan lines Y1 YYn of the active matrix multi-stable display panel; and during the current scan line period SLP_i, The controller controls the scan driver to pre-turn on the pixels of the other scan line Y(i+1) of the scan lines Y1~Yn. The active matrix multi-stable display device of claim 13, wherein the frame period further comprises a discharge period; during the discharging period, the controller controls the data driver to provide a common voltage to the Pixel. The active matrix multi-stable display device of claim 18, wherein the scan driver groups the plurality of scan lines of the active matrix multi-stable display panel; a first release during the discharge During the electronic period, the controller controls the data driver to provide the common voltage to the pixels of a first scan line group of the scan lines; and during a second discharge period during the discharge, the controller controls the data driver to provide The common voltage is to a pixel of a second scan line group of the scan lines. The active matrix multi-stable display device of claim 19, wherein the first electron discharging period partially overlaps the second electron discharging period. The active matrix multi-stable display device of claim 13, wherein the controller adjusts a common voltage of the active matrix multi-stable display panel to a first voltage during the reset period Level during the first gray level period, the controller adjusts the common voltage to a second voltage level greater than the first voltage level; and during the second gray level period, the controller The common voltage is adjusted to a third voltage level greater than the second voltage level. The active matrix multi-stable display device of claim 13, wherein the controller adjusts a common voltage of the active matrix multi-stable display panel to a first voltage during the reset period Level during the first gray level period, the controller adjusts the common voltage to a second voltage level that is less than the first voltage level; and during the second gray level period, the controller The common voltage is adjusted to a third voltage level that is less than the second voltage level. The active matrix multi-stable display device according to claim 13 , wherein during the resetting period and the first gray scale period, the controller shares the active matrix multi-stable display panel The voltage is adjusted to a first voltage level; and during the second gray level period, the controller adjusts the common voltage to a second voltage level greater than the first voltage level. The active matrix multi-stable display device according to claim 13 , wherein during the resetting period and the first gray scale period, the controller shares the active matrix multi-stable display panel The voltage is adjusted to a first voltage level; and during the second gray level period, the controller adjusts the common voltage to a second voltage level that is less than the first voltage level.