TW201232742A - Integrated circuit pattern and method - Google Patents

Integrated circuit pattern and method Download PDF

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Publication number
TW201232742A
TW201232742A TW100103131A TW100103131A TW201232742A TW 201232742 A TW201232742 A TW 201232742A TW 100103131 A TW100103131 A TW 100103131A TW 100103131 A TW100103131 A TW 100103131A TW 201232742 A TW201232742 A TW 201232742A
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Taiwan
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portions
line
integrated circuit
main line
parallel
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TW100103131A
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Chinese (zh)
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TWI506754B (en
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Shih-Hung Chen
Hang-Ting Lue
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Macronix Int Co Ltd
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Abstract

An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least three times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Description

201232742 » 1 ύ t ^ vm λ & 6. Description of the invention: [Reciprocal reference material for other applications] This application is related to the US Patent Application No. 12981121, the filing date is 12/29/2; 1〇, the name is “Multiple Patterning Method”, and the agent case number is MXIC 1949-1. [Technical field to which the invention pertains]

SUMMARY OF THE INVENTION The present invention relates to integrated circuit patterns and their fabrication, including the use of multiple patterning methods to fabricate integrated circuits whereby the access of the material lines is facilitated. [Prior Art] A snubber circuit is generally used to fabricate a variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of the integrated circuit, which increases the cost of the side components and thus increases the versatility of the hybrid circuit. The smallest secret of the accumulation (the minimum distance between the two (4) types of the (four) type of near structure (such as the same point between two adjacent gate conductors) is often used as a representative of the density of this circuit. The increase is often limited by the resolution of the lithographic apparatus that can be obtained. The minimum size of a feature and space that can be produced by a given calibrating device is related to its resolution capability, which can be generated by using a predetermined optical job. The sum of the minimum feature width and the width of 丫 = is the minimum distance that can be produced for this device. = The feature width is often equal to the minimum space width, so the minimum spacing that can be produced with a given lithographic apparatus is roughly equal to Produces twice the minimum feature width. A method of reducing the distance between integrated circuit devices to a finely generated minimum of 201232742 TW6498PA small pitch is based on double or quadruple patterning (here sometimes multiple The use of a patterned representation. In this way, a single mask is typically used to construct a series of parallel material lines on a substrate. Different methods can then be used. Transforming each parallel material line into multiple parallel material lines. Various methods typically use a series of deposition and etching steps to do this. Different methods are discussed in Xie, Peng and Smith, Bruce W., "About sub-32 nm lithography. Analysis of the division between higher levels", 〇ptical

Microlithography XXII, Proc. 〇f SPIE Vol. 7274, 72741Y, c 2〇〇9 SPIE. One method discussed in the following example uses self-aligning sidewalls, which are constructed to form approximately two or four parallel lines of material from each of the lines of material constructed from the original reticle. SUMMARY OF THE INVENTION The problematic knife ▲ is constructed by reducing the pitch to the size of the secondary lithography. That is, the # between the material lines may be the second time; when engraved, the demand for the access line (the 肊u component) can not be completely different from the sub-lithography size:; by: such as; In terms of size, it is the size required for the lithographic light = the chip access area of the plug. The tolerance of the misalignment of the force hood is increased and the γ direction is the length of the X-direction portion of the γ-direction, and the γ-direction portion has a _#, 帛 spacing, and the Υ direction portion. Line - line 201232742 contains the end area. The end region of the γ-direction portion includes a main line portion and an offset portion. The biasing portion includes a biasing element spaced from the main line portion and electrically connected to the main line portion. The offset portion defines the contact area for use by subsequent pattern transfer procedures. In some examples, the 'offset portion is in the end region and the second pitch is at least three times greater than the first pitch. In some examples, the lines are lithographically formed lines, and the first pitch has an underlying lithography dimension. In some examples, the 主^ main line portion is located in the path offset portion of the main line portion, and the contact portion is along the -related main line portion 2 in the middle - offset ^ ^ 并 and includes substantially parallel to the correlation : The main line portion extends and is approximately perpendicular to the associated 2. In some examples, some of the offset portions are located in the lateral shift region. % I knife to the circuit between the axes of the multi-® solution method - example The receiving field for subsequent __ shift program use, line. The set of parallel-material line-series J is an Ai material line-definition pattern, which has a length of - χ & 1 above the length of each first material portion is substantially greater than the first material line containing Tp, degrees long. Parallel line pattern selection step package S. Select a first spacing to the X square ^" direction portion " two spacing two distance =::: 201232742,

TW6498PA is parallel and parallel to the gamma direction. At least two second material lines are formed parallel to each of the first material lines to construct parallel X-direction portions of the second material line and parallel Υ-direction portions of the second material line. The Υ direction portion of the second material line includes an end region. The second material line forming step includes: forming a Υ direction portion having a main line portion and a bias portion. The biasing portion includes a biasing element that is integral with the main line portion and electrically connected to the main line portion. The offset portion defines the contact area for use by subsequent pattern transfer procedures. In some examples, the offset portion is formed in the end region. In some examples, the step of forming the Υ direction portion includes forming a continuous loop biasing portion that contacts the main line portion and is located on one side of the main line portion. In some examples, the step of forming the Υ direction portion includes forming a biasing portion that includes at least one biasing element extending laterally from the main portion. In some examples, the step of forming the Υ direction portion includes forming an offset portion disposed along the main line portion and including an element extending substantially parallel to the main line portion and substantially perpendicular to the main line portion. In some examples, the step of forming the Υ direction portion includes forming a lateral shifting region along the main line portion and at least some of the offset portion is located in the lateral shifting region. In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows: [Embodiment] Figures 1-33 and below related to those figures The description is from U.S. Patent Application Serial No. 12,981,121, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all 6 201232742 λ * * w > ^ wa χ » We understand and understand that the process steps and construction benefits described here do not describe the complete manufacturing process for the manufacture of the circuit. The present invention may be practiced in conjunction with a variety of different integrated circuit fabrication techniques that have traditionally been used in the art of the art or are developed in the future. The following description will generally refer to specific embodiments of the embodiments and methods. It is to be understood that the invention is intended to be limited to the details of the embodiments and methods disclosed herein, but the invention may be practiced by using other features, elements, methods and embodiments. The preferred embodiments are shown to illustrate the invention and are not intended to limit the scope of the invention as defined by the scope of the claims. Those skilled in the art will recognize various equivalent changes to the accompanying description. The same elements in the various embodiments and examples are generally indicated by the same reference numerals. The various examples discussed below are generally referred to as procedures using lithography and lithography, which involve transferring a pattern from one object to the next, typically by using a reticle and photoresist. The circuit was broken during the manufacturing period. However, the invention is not limited thereto, but may instead include, for example, a process of writing a pattern directly onto a substrate or possibly using other techniques (e.g., electron beam) = other materials that will be constructed in the future. Lithography programs and other pattern writing or transfer techniques are sometimes referred to as pattern transfer programs. Figures 1-8 show the first part of the four-fold patterning process in a simplified version. A plan view of a circular first material line 12 of a nest-like set of 1G, which is constructed from a corresponding suitable reticle having a parallel X-direction portion 16 and a parallel gamma-direction portion on a substrate 14. The spacing 20 between the X-direction portions 16 is less than the γ direction 201232742, t

The spacing between the TW6498PA sections 18 is 22. Preferably, the spacing 22 is at least 2 times greater than the spacing 22, more preferably at least 3 times greater than the spacing 22, and even more preferably 4 times the spacing 22. The length 24 of the X-direction portion 16 is substantially greater than the length 26 of the Y-direction portion 18, typically a few digits, such as at least 30 times larger. However, for the purpose of illustration, the length 24 of the X-direction portion 16 is not drawn to scale, but is greatly reduced. In this example, the width 28 of each of the X-direction portions 16 may be, for example, about 60 nm, and the width 30 of each of the Y-direction portions 18 may be, for example, about 150 nm. Since the spacing 22 is greater than the spacing 20, such additional width for the Y-direction portion 18 can be accommodated. Fig. 2 shows the formation of a spacer layer 32 on each of the X-direction portion 16 and the Y-direction portion 18 of the first material line 12 of Fig. 1. The spacer layer 32 acts as a set of second material lines 32. This effectively utilizes the inevitable reduction in spacing to double the linear density relative to the density of the first material line 12. In a subsequent processing step, the X-direction portion 16 and the Y-direction portion 18 of the first material line 12 are removed leaving only the spacer layer 32 as the second material line. Figure 3 shows the construction of a spacer layer 34 on each side of the second material line 32 of Figure 2, whereby the linear density is quadrupled from the line density of Figure 1 by a certain reduction in spacing. As with portions 16 and 18, the second material line 32 is removed during subsequent processing steps leaving only the spacer layer 34 as the third material line 34. Figure 4 is a top plan view of the reticle 36 for use with the construction of Figure 3. The mask 36 is used to cover the portion of the Y-direction portion 38 of the spacer layer 34 of Fig. 3; in this example, the *X-direction portion 40 is not changed by using the mask 36 as shown in Fig. 5. The use of a reticle 36 allows for the removal of portions of the Y-direction portion 38 of the spacer layer 34 by 201232742 i vv v*t7〇i r\. The result of this removal (shown in Figure 6) constructs the end region 42 along the Y-direction portion 38. Figure 7 is a plan view of a reticle 44 to be used with the construction of Figure 6 to construct a supplemental feature. In this example, the supplemental features include contact pads and circuit interconnects to be applied to the end regions 42 of the Y-direction portion 38. Figure 8 shows the results of using the reticle 44 and appropriate post-processing steps (e.g., exposure and etching steps) to construct the complementary features, particularly the contact pads 46 along the Y-direction portion 38 at the end regions 42 and Circuit interconnect 48. Preferably, the distance between the Y-direction portions 38 is sufficient for the lithographically fabricated pads and alignment tolerances, and the X-direction portions 40 are not pressed by these problems and may therefore be photolithographic. The increased spacing between the end regions 42 of the Y-direction portion 38 is important when compared to the distance between the X-direction portions 40, as it allows for the use of conventional dimensionally lithographic contacts that are otherwise formed. A pad 46 or a larger pad is provided to provide a dimensioned sub-lithographically fabricated and spaced apart X-direction portion 40 of the third material line 34. The third material • the material line 34 is generally used as a word line or a bit line, and the X direction portion 40 and the Y direction portion 38 are generally referred to as an X pointing word/bit line portion 40 and a Y pointing word/bit, respectively. Line portion 38. By providing sufficient space between the innermost X-direction portions 40 of such material lines 34, circuit interconnects 48 can be placed between the innermost X-direction portions as shown in FIG. In other examples, circuit interconnects 48 may be disposed outside of the outermost X-direction portions 40 of such material lines 34. Circuit interconnects 48 may be lines fabricated by photolithography or sublithography. Figure 9-16 shows a second example of a four-fold patterning process in a simplified version 201232742.

TW6498PA sub, which is similar to the first example of the four times patterning process of Figures 1-8. Therefore, this second example will not be described in detail. However, the main differences are as follows. The nested, looped material line 12 of the set 10 is present in the form of an L-shaped section 52. Thus, a plurality of pairs of L-shaped sections 52 construct the nested, looped material line. The reticle 54 of Fig. 12 is sized to cover not only the portion of the Y-direction portion 38 but also the portion of the X-direction portion 40. Referring to Fig. 13, the 间隔 enables the adjacent spacer layer 34 not to pass through FIG. The terminal elements 56 are shown electrically connected to each other. Figures 17A-17C show three additional examples of a plurality of sets of 10 nested, looped material lines 12. The contact pad will be formed at position 55 along the Y-direction portion 56. Figure 18 is a simplified flow chart showing the basic procedure implemented by the multiple patterning method of the present invention. Beginning at 68, a set of parallel line patterns for a set of 10 parallel first material lines 12 is selected, typically a nested loop pattern. The first material line 12 has parallel X-direction portions 16, which may be substantially longer than the parallel Y-direction portions 18, for example 100 or 1000 times longer. Next, at 62, the first and second pitches 20, 22 for the X and Y direction portions 16, 18 are selected. Such spacing is selected such that the second spacing 22 is greater than the first spacing 20, such as 4-8 times larger. At 64, the parallel first material lines 12 of the set 10 are formed on a substrate 14. Two second material lines 32 are formed at 66. The second material line 32 is parallel to the first material line 12. At 68, two third material lines 34 are formed parallel to each of the second material lines 32. This allows for the construction of parallel X-direction portions 40 and parallel Y-direction portions 38 for the third material line. The Y-direction portion 38 of the second material line 34 includes an end region 42. At 70, a complementary feature is constructed, 201232742 1 vv wr^oi r\ such as the enlarged contact pad 46 and the circuit interconnect 48 at the end region 42. Figures 19-32 show a manufacturing flow for an example of self-surveying quasi-interval patterning using BE_s〇N〇s WL four times. BE-SONOS stands for charge-capture memory unit. Figure 19 shows a substrate 76 comprising first to eighth layers 78-92 and a photoresist line 94 formed on the first layer 78. In this example, the first, third and sixth layers 78, 82 and 88 are composed of polycrystalline germanium (generally denoted by poly) and the second and fourth layers 8 and 84 are composed of si 2 . The sixth layer 86 is composed of WS1. The eighth layer 92 is Si. The seventh layer 90 is a composite of five layers for use as a charge storage structure for BE-SONOS having alternating Si〇2 and SiN layers, wherein the Si〇2 layer is the first calculated from above. Third and fifth floors. The first, second and third layers 78, 80 and 82 are considered to be sacrificial layers because they are completely removed during the patterning process. Other materials and materials can also be used. Referring to Fig. 20, photoresist line 94 is used to etch first layer 78 to construct structure 96, which corresponds to first material line 12 of Figure 1. Fig. 21 shows the result of depositing the SiN layer 98 on the structure of Fig. 20. The 22nd reference shows the result of anisotropic etching of this layer 98, which removes those portions of layer 98 that cover the structure 96 other than layer 80. Doing so will leave the sidewall spacers 100 on each side of the structure 96, wherein the sidewall spacers correspond to the spacer layer 32 of Figure 2. Figure 23 shows the result of etching structure 96 leaving sidewall spacers 100. Fig. 24 shows the configuration of Fig. 23 after the film 1〇2 of the polycrystalline silicon has been deposited thereon. In Fig. 25, the film 102 over the sidewall spacers 100 and covering portions of the second layer 80 is removed, thereby leaving the polysilicon sidewall spacers 104 on each side of the SiN sidewall spacers 100. on. 201232742

TW6498PA In Figure 26, the photoresist mask 106 is used to cover portions of the configuration of Figure 25 that have not been removed. The mask 1 〇 6 can be regarded as the opposite of the reticle 36 of Fig. 4. Figure 27 shows the removal of the polycrystalline sidewall spacer 104 that is not protected by the photoresist mask 1〇6 and the subsequent removal of the photoresist mask 1

result. Figure 28 shows the result of etching portions of the SiN sidewall spacers 1 and the second layer 80 that are not covered by the sidewall spacers 104; doing so causes the polysilicon/Si 2 stack 108 to remain in the third layer 82. on. The stack 1 〇 8 contains the upper polysilicon portion 107 and the lower Si 〇 2 portion 1 〇 9. Comparing the two structures 96 on the right-hand side of the construction of Fig. 20 with the polysilicon/Si〇2 stacks 1〇8 on the right-hand side of the construction of Fig. 28, we can see that the number of vertical structures has changed from 2 4 times and become 8.

Fig. 29 shows the construction of the photoresist mask 11 of Fig. 28, which corresponds generally to the mask 44 of Fig. 7. Figure 30 shows the construction of Figure 29 after the portions of the third layer 82 that are not covered by the stack 108 or the mask 11 has been etched. The upper polysilicon portion 1〇7 is removed leaving the stack 112. Stack 112 includes an upper si〇2 portion 113 fish-lower polycrystalline dream portion 114. In Fig. 30, the photoresist mask 11〇: also: the skin is removed. Figure 31 shows the result of the oxide etch which removes the upper portion 113 from the fourth portion that is not covered by the polysilicon portion 114 and can form the stack 116. The stack Μ includes a knives U4 and SiO2 portion 118. 1 and 32 show that the layer 86, _ minute 118 f, which is not covered by the stack ΐ6, is removed except for the polycrystalline stone portion 114 and the partial removal S 丨 0 2 is 曰 having the engraved elements 122, 124 (generally I, respectively) The memory cells 12 of one of the columns are formed together to form a word line 124 of 12 201232742, and the word and line 124 are above the charge storage area 128. In this example, the memory unit 12 is formed into a NAND string. In this example, the surname program also constructs a string selection line 130 that extends in the same direction as the word line 124. Since the thickness of the fourth layer 84 is generally greater than that of the seventh layer, a portion of the SiO 2 portion 118 may remain after the entire seventh layer 9 is etched through. Figure 33 is a block diagram showing the closely spaced X pointing word line county 40 and the wider spaced Y pointing word line portion 38 in the word line region 132. In a typical memory circuit, there will typically be thousands of word lines 124. In this example, two different contact regions 134 are disposed adjacent to word line region 132 and to word line region 132. Contact 46 is disposed within contact area 134 along a wider spaced (larger pitch) y pointing to word line portion 38. Peripheral circuit driver area 136 is disposed between contact areas 134 and to contact area 134. The configuration of this type described below provides an effective layout of the actual area of the integrated circuit to the high density memory. (1) the word line is in the word line area 132; (2) the word line area 132 if one or more contacts Region 134 includes contacts 46 along gamma pointing wordline portion 38, and (3) one or more associated peripheral circuit driver regions 136 contact regions 134. The following discussion of Figures 34-55 will illustrate various modifications to the above described methods and configurations for constructing contact regions in the Y-direction portion. The examples of Figures 34-51 use a double patterning approach with a fourfold patterning understanding used with the examples of Figures 52-55, or a larger pattern can be used. Figure 34 shows the Y-direction portion 18, which contains adjacent to the main gamma

201232742 TW6498PA A relatively short Y-direction partial section 150 of direction section 152. Section 150 is sometimes referred to as an island section 150. Figure 35 shows that a conductive spacer layer 34 is formed on either side of section 152 and around section 15A. Figure 36 shows the configuration of Figure 35 after the removal of sections 150, 152, by which the left-hand direction portion 154 is included, which includes main line portions 156, 158 and offset portion 160. The biasing portion 16A includes a biasing element 162 (separated from the main line portion 158 and substantially parallel to the main line portion 158) and a plurality of connecting elements 164 (which electrically connect the biasing element ι 62 to the main line portion 158). The Υ direction portion 154 constructs a contact region 46 for use in subsequent lithography procedures. The distance 166 between the 方向 direction partial sections 15 〇, 152 is preferably greater than the width 168 of the main line portions 156, 158 < 5 distance 166 is also preferably less than three times the width 168. This type of pattern is sometimes referred to as an I-shaped design for double patterning because of the I-shape of the island section 15 . Figures 37-39 relate to a double I-shaped design for double patterning. The Υ direction portion 18 includes γ-direction partial sections 17A, 171 which are disposed adjacent to the main gamma-direction partial section 172. The main Υ direction portion 172 has first and second lateral f-bit regions 174, 175 connected by a connection region 176. Figure 38 shows that a conductive spacer layer 34 is formed on either side of the region k 172 and surrounds the island segment, m. The first graph shows the configuration of the %th map after the removal of the segments 17A, m and 172, thereby leaving the gamma direction portion 178, which includes the main line portions i8G, ΐ8ι, and the 偏 bias f portions 182, 183. The biasing portions 182, 183 each comprise a bias (separated from the main line portion, 181, and substantially parallel to the main: car, 181) and a plurality of connecting elements 186 (the biasing element 184 is electrically connected to each main line portion (10) , (8)). The gamma direction portion 178 constructs 201232742 a τ* ι~\ contact area 46 for use in subsequent lithography procedures. Figures 40-42 show alternatives to the examples of Figures 37-39, in which like elements are designated by like reference numerals. Figures 43-45 relate to an E-shaped design for double patterning. Figure 43 shows a Y-direction portion 18 comprising three relatively short, laterally directed segments 188 extending laterally from a major section 190 and generally perpendicular to the main section 190. Figure 44 shows conductive spacer layer 34 formed on either side of section 190 and surrounding section 188. Fig. 45 shows the configuration of Fig. 44 in which the Y-direction portion 192 of the main line portion 194, 196 and the offset portion 198 are left in the removal region # segment 188, 190. The biasing portion 198 includes a biasing element 200 spaced from the main wire portion 196 and the connecting member 202 and generally parallel to the main wire portion 196 and the connecting member 202, wherein the connecting member 202 electrically connects the biasing member 200 to the main wire portion 196. The Y-direction portion 192 constructs a contact region 46 for use in subsequent lithography procedures. In this example, contact region 46 includes portions of both bias portion 198 and main line portions 194, 196; in other examples, contact region 46 cannot include a portion of main line portion 194. The distance 222 between the Y-direction partial sections 188 is preferably greater than or equal to the width 224 of the main line portions 194,196. The distance 222 is also preferably less than 4 times the width 224. These dimensions typically have similar designs, such as those shown in Figures 46-49 and 49-51. Figures 46-48 show alternatives to the examples of Figures 43-45, in which like elements are designated by like reference numerals. Figures 49-51 relate to a double F-shaped design for double patterning. Figure 49 shows a Y-direction portion 18 comprising one of the main segments 206 having a first and a second 15 201232742 connected by a connection region 212,

TW6498PA lateral shifting area 208, 210. Portion 18 also includes two relatively short laterally directed sections 204 extending laterally from main section 206 and generally perpendicular to main section 206. Figure 50 shows conductive spacer layer 34 formed on either side of section 206 and surrounding section 204. Figure 51 shows the configuration of Figure 47 after removal of sections 204, 206, thereby leaving a Y-direction portion 214 comprising main line portions 216, 218 and offset portions 220 extending laterally from main line portions 216, 218. . The biasing portion 220 is electrically connected to the main line portions 216, 218. The Y-direction portion 214 constructs a contact area 46 associated with each of the main line portions 216, 218 for use in subsequent lithography procedures. Figures 52-55 relate to a dual P-shaped design for quadruple patterning. Figure 52 shows a Y-direction portion 18 comprising a main section 230 having first and second lateral shifting regions 232, 234 connected by a connecting region 236. Portion 18 also includes two relatively short island sections 238 spaced apart from main section 230. A hole 240 is formed in the connection region 236. Fig. 53 shows the configuration of Fig. 52 after the spacer layer 32 is formed along the edge of the Y-direction portion 18. Fig. 54 shows the formation of the conductive spacer layer 34 along the edge of the spacer layer 32 after the removal of the Y-direction portion 18. Figure 55 shows the configuration of Figure 54 after removal of spacer layer 32, thereby leaving a Y-directional portion 242 that includes mainline portions 244, 245, 246, 247 and offsets extending laterally from their associated mainline portions. Portions 248, 249, 250, 251. Each biasing portion 248-251 includes a biasing element 254 that is electrically coupled to its associated mainline portion by a connecting member 256. The Y-direction portion 242 constructs a set of four contact regions 46 for use in subsequent lithography procedures. Within each biasing portion is a 201232742 1 vvun:7〇m conductive element that does not need to be electrically connected to any other configuration but does help to provide mechanical stability to the resulting contact area 46. The distance 258 between the fox island section 238 and the region 232 of the main section 230 is preferably greater than or equal to twice the width 260 of the main line portions 244-247, and preferably less than or equal to five times the main line portion 244- 247 has a width of 260. The dimension 262 is preferably greater than or equal to the width 260 of the mainline portions 244-247, and is preferably less than or equal to three times the width 260 of the mainline portions 244-247. The invention discussed above with reference to Figures 34-55 can be used in general semiconductor devices (including memory and logic elements) to construct various features other than the metallization patterns discussed above (e.g. Asked very much). The invention is also applicable to a variety of different integrated circuit processing techniques, including shallow trench isolation. Reference is made to any of the above patents, patent applications and publications for reference. In view of the above, the present invention has been disclosed in the above preferred embodiments, which are not intended to limit the invention. Those skilled in the art having the knowledge of the present invention can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple description of the diagram] Figures 1-8 show the first example of the four-fold patterning process in a simplified version. Figure 1 is a top plan view of a nested, looped material line constructed from a correspondingly shaped reticle within a substrate having parallel x-direction portions and parallel Y-direction portions, in the X-direction portion. The distance between 17 201232742,.

The TW6498PA is smaller than the distance between the Y-direction sections. Figure 2 shows the construction of the spacer layer on each side of the material line of Figure 1, whereby the density is doubled by the subsequent reduction in the spacing. Fig. 3 shows the construction of the spacer layer on each side of the material line of Fig. 2, whereby the line density of Fig. 1 is quadrupled by the subsequent reduction in the distance between the lines. Figure 4 shows a top plan view of the reticle used with the construction of Figure 3. Fig. 5 is a view showing the alignment of the structure of Fig. 4 and the structure of Fig. 3 covering a portion of the Υ direction portion. Fig. 6 shows the result of the removal of the portion of the ridge direction portion covered by the reticle of Fig. 4 which establishes the end region of the material line. Figure 7 is a plan view of a reticle to be used with the construction of Figure 6 to construct a supplemental feature. Figure 8 shows the results of using the reticle of Figure 7 and appropriate subsequent processing steps, such as exposure and etching, to construct additional features, particularly contact pads and lands in the end regions along the Υ direction portion. Line or word line. Figures 9-16 show a second example of a four-fold patterning process similar to the process of Figures 1-8 in a simplified version, but in which the nested, looped material lines are in the form of L-shaped segments. Figures 17A-17C show three additional examples of multiple sets of nested, looped material lines. Figure 18 is a simplified flow chart showing the basic procedure implemented using the multiple patterning method of the present invention discussed above with reference to Figures 1-17. 201232742 1 vv r\ Figure 19-32 shows the use of BESNOS WL quadruple pattern An example of the manufacturing process. Figure 33 is a block diagram schematically showing the relationship between the word line area, the contact area, and the peripheral circuit driver area. Figures 34-36 show the biasing portion of the directional portion of the patterning process during the double patterning process. The biasing portion includes the biasing element and the component that connects the biasing element to the mainline portion. Figures 37-39 show a process similar to the 34th National I, An &, a Le 36 diagram but using a double I-shaped design during the double patterning process. = 40-42 shows a process similar to the process of Figure 37_39. Figures 43-45 show a process similar to the process of the 3rd Acer music 34-36 but using an E-shaped design during the double patterning process. Ganhe H group Figure 46-48 shows a process similar to 坌4 Figure 49-51 shows a process similar to the process of Figure i5. In the case of the process of using the double F-shaped design, the process of the dual-figure design is shown in Fig. 52-55, which is similar to the process of using the double P design in the process of the king. [Description of main component symbols] 10: Group 12: First material line W: Substrate 16: X-direction part 18: Y-direction part 201232742

TW6498PA 20: first pitch 22: second pitch 24: length 26: length 28: width 30: width 32: second material line/spacer layer 3 4. second material line 34: third material line/spacer layer 36: Photomask 38: Y pointing word/bit line portion 40: X-direction portion 42: End region 44: reticle 46: contact pad/contact/contact region 48: circuit interconnection 52: L-shaped segment 54: Mask 55: Position 56: Y-direction portion/end member 60-70: Method step 76: Substrate 78: First layer 80: Second layer 82: Third layer 20 201232742 1 VT ν*Τ^ΟΧ i~v

84: fourth layer 86: sixth layer 90: seventh layer 92: eighth layer 94: photoresist line 96: structure 98: SiN layer 100: sidewall spacer layer 102: film 104: sidewall spacer layer 106: mask 107 : polysilicon portion 108 : stack 109 : SiO 2 portion 110 : reticle 112 : stack 113 : SiO 2 portion 114 : polysilicon portion 116 : stack 118 : SiO 2 portion 120 : memory unit 122 : etched element 124 : word line / etched Element 128: charge storage area 130: string selection line 21 201232742

TW6498PA 132: Word Line Area 134: Contact Area 136: Peripheral Circuit Driver Area 150: Section 152: Section 154: Y Direction Section 156: Main Line Section 158: Main Line Section 160: Offset Section 162: Biasing Element 164: Connection Element 166: Distance 168: Width 170, 171, 172: Section 174, 175: Lateral displacement region 176: Connection region 178: Y-direction portion 180, 181: Main line portion 182, 183: Offset portion 184: Biasing element 186: connecting element 188: section 190: main section 192: Y-direction section 194, 196: main line section 22 201232742 1 ττ vr^ui γλ 198: offset section 200: biasing element 202: connecting element 204: section 206 : Main section

208, 210: first and second lateral shifting regions 212: connecting regions 214: Y-direction portions 216, 218: main line portion 220: offset portion 222: distance 224: width 230: main segments 232, 234: lateral shift Bit area 236: connection area 2 3 8 . island section 240: hole 242: Y direction section 244, 245, 246, 247: main, line 咅p 248, 249, 250, 251: offset part 254: offset Element 256: Connecting element 258: distance 260: width 262: size

Claims (1)

  1. 201232742 TW6498PA VII, the scope of application for patents: 1 rigging circuit pattern ^ w —| /|, · - group material line 'located above a substrate' of these material line boundaries /, multiple lines, which have multiple X directions Partial and multiple Y-direction parts of the eight " =: the length of the part is substantially the heart of the part of the ¥ direction
    The second direction of the warfare direction has a second γ y tool having a second pitch, the second pitch being greater than the first pitch; ° parallel to the x-direction portions being parallel to each other, and the γ-direction portion of the axis γ-direction portion includes a plurality of The end regions; and the gamma end regions of the direction portions include a plurality of main line portions and a bias portion, the bias portions including a plurality of biasing elements, which are directly spaced and connected to the domain portions, The offset knife borders multiple contact areas for subsequent pattern transfer procedures. The integrated circuit pattern according to claim 1, wherein the offset portions are located at the end regions. 3. The integrated circuit pattern of claim 1, wherein the lengths of the X-direction portions are at least 30 times the lengths of the direction portions. The integrated circuit pattern of claim 1, wherein the second pitch is at least twice as large as the first pitch. 5. The integrated circuit pattern according to claim 1, wherein the second spacing of 5 hai is at least 4 times larger than the first pitch. 6. The integrated circuit pattern according to claim 1, wherein the X-direction portions are substantially perpendicular to the Y-direction portions in 24 201232742 Λ ww V/-r^ V4 4 E . In the middle of the patent, the integrated circuit pattern described in item 1 of the patent range is referred to as a plurality of word lines or a plurality of bit lines. The integrated circuit pattern as described in claim 1 is a line formed by photolithography, the first pitch having a sub-lithographic dimension and the third pitch having a photolithographic dimension. 9· Please request the integrated circuit pattern described in item 1 of the patent scope, the basin • row = ¥ direction section and the χ direction sections define a set of nested ring flats. 10. As claimed in the patent scope! In the integrated circuit pattern described in the section, the phase stop line is a line formed by photolithography, and the contact areas have a multi-jLJ size. As in the integrated circuit pattern described in the item i of the patent application, the two gamma direction portions include a continuous loop biasing portion which contacts the k main line portion and is located on one side of the main line portion. Spring 12. The integrated circuit pattern of claim 5, wherein the offset portions comprise at least one biasing element extending laterally from the main line portions. 13. The integrated circuit pattern of claim 1, wherein the offset portion is disposed along an associated main line portion and includes a plurality of pieces. The element extends substantially parallel to the associated main line portion and is substantially perpendicular to the associated main line portion. I': (5) applying the integrated circuit pattern described in item i of the patent scope, 匕3 varnishing a plurality of lateral shift regions of the domain portions, at least some of the offset portions/knife being located in the lateral shifts Bit area. 25 I 201232742 TW6498PA Use: To raise: multi-method, make the =' field for the subsequent pattern transfer program during the integrated circuit process - group parallel - material - select - group into the group of parallel Touching on the substrate, the first line boundary has a pattern of the X-direction portion and a plurality of first material lines of the first direction material lines, and the plurality of the direction lines of the material line: The selection step of the length substantially longer than the plurality of parallel line patterns includes: for the X:,: the first: and the selection for the ¥ direction portions - the second line is flat with each other = the first: ::::^:===- The material line is in the γ direction portion, and the second materials ": the γ-square material portion includes a plurality of end regions; and the Υ direction portion includes: forming one main line a plurality of biasing direction portions, the biasing portions enclosing a main line portion, the partial main line portions being spaced apart and electrically connected to the pattern transfer programs for use. Defining a plurality of contact regions for subsequent pseudo-forces Applying the method described in item 15 of the patent scope, a deviation in a: 7-point formation The method of claim, wherein the forming step comprises forming a continuous loop biasing portion 26 201232742 contacting the main line portion and located on one side of the main line portion Wherein, the method according to the second aspect of the invention is as described above, wherein the step of forming the ρ: comprises forming a biasing portion >" The main portion is a laterally extending biasing element. Υ * The main line of the method of claim 15; the forming step of the crucible comprises: forming a biasing portion along the main line portion and substantially perpendicular to The wire member extends substantially parallel to the method of item 15, wherein the lateral displacement regions include: forming a plurality of bit regions along the main line portions. - at least some of the offset portions are located in the lateral directions Moving the second === the method described, wherein the two fewer methods, wherein the two additional material lines are formed, parallel to each of the first material lines; and 23 to the first material line 'It's parallel to each of this extra Parallel wire Η / The method of claim 15 wherein the nested shape is parallel line pattern. Remove at least part of the application = 7; the square mentioned in item 15 ^ ^ 2, the two-way direction portion to construct the end regions. 'As claimed in the patent application 帛 15 item, wherein the 27 201232742, TW6498PA <> f: the material line of the strip defines at least the following a person--continuous length=shape'-a rectangular shape having a rectangular shape along the gaps of the Y-directions, having a gap along the γ/minutes and a rectangular shape, It only fits in one direction. 26. The method of claim 15, wherein the lengths of the direction portions are at least 30 times greater than the ¥ direction portions. A method of claim 15, wherein the whistle-to-pitch is at least twice the first-pitch. The method of claim 15, wherein the spacing is at least four times the first spacing. The first
    28
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555082B (en) * 2015-05-15 2016-10-21 力晶科技股份有限公司 Patterning method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7183205B2 (en) * 2004-06-08 2007-02-27 Macronix International Co., Ltd. Method of pitch dimension shrinkage
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
KR100675282B1 (en) * 2005-09-12 2007-01-29 삼성전자주식회사 Forming methods of fine patterns, and forming methods of trench isolation layers using the same
US7351666B2 (en) * 2006-03-17 2008-04-01 International Business Machines Corporation Layout and process to contact sub-lithographic structures
US8106519B2 (en) * 2008-04-22 2012-01-31 Macronix International Co., Ltd. Methods for pitch reduction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555082B (en) * 2015-05-15 2016-10-21 力晶科技股份有限公司 Patterning method

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