TW201214183A - Method and apparatus for automated validation of semiconductor process recipes - Google Patents

Method and apparatus for automated validation of semiconductor process recipes Download PDF

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Publication number
TW201214183A
TW201214183A TW100128569A TW100128569A TW201214183A TW 201214183 A TW201214183 A TW 201214183A TW 100128569 A TW100128569 A TW 100128569A TW 100128569 A TW100128569 A TW 100128569A TW 201214183 A TW201214183 A TW 201214183A
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Taiwan
Prior art keywords
rule
semiconductor process
semiconductor
rules
rule set
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TW100128569A
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Chinese (zh)
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TWI479352B (en
Inventor
Charles Hardy
Roger Alan Lindley
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Applied Materials Inc
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    • GPHYSICS
    • G16INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS
    • G16ZINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS, NOT OTHERWISE PROVIDED FOR
    • G16Z99/00Subject matter not provided for in other main groups of this subclass
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/048Interaction techniques based on graphical user interfaces [GUI]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00Computing arrangements using knowledge-based models
    • G06N5/02Knowledge representation; Symbolic representation
    • G06N5/022Knowledge engineering; Knowledge acquisition
    • G06N5/025Extracting rules from data

Abstract

Methods and apparatus for automated validation of semiconductor process steps are provided herein. In some examples, a method for validating a semiconductor process recipe includes: selecting a rule set describing an operating window for a semiconductor process tool; checking parameter values defined by steps in the semiconductor process recipe against limit-checking rules of the rule set to produce first results; determining step types from the steps in the semiconductor process recipe using step definition rules of the rule set to produce second results; checking transitions between the step types against step transition rules of the rule set to produce third results; and generating, using the computer, validation data for use of the semiconductor process recipe with the semiconductor process tool based on the first, the second, and the third results.

Description

201214183 六、發明說明: 【發明所屬之技術領域】 本發明之實施例大體而言係關於—種用於自動驗證半 導體製程製作方法之方法及設備。 【先前技術】 製造半導體裝置之製程可需要許多連續步驟,該等連 續步驟可產生成百上千乃至成千上萬的製程變體。此 外實施製程步驟u具具有各種規格限制及要 求’從而進一步增加了制& π你 了Μ的可變性。因此,製程工程 =出半導體製程製作方法(「製作方法」),以指定製程 :定如何針對用於製程之每-個工具執行此種步 不正確的製作方法可產生 理中的何體晶圓。給定^=果’甚至可能損壞處 明確而十分複雜的。蓉於此種广午知作視窗可為定義 誤地建立製作方法, :雜性,製程工程師可錯 者超出工具之定義操作視窗範圍。因此,::不正確或 於製造過程中之前,必須驗證該等製作方·^作方法用 一通常,手動驗證製作方法,藉此製… 定工具之規格及操作視窗之上王師以詳述特 動驗證製作方法為勞乂又引用製作方法 勞力㈣型的且易出錯。通常,試圖手 201214183 實現自動驗證製作方法製程之努力集中在使用試算表來 驗證製作方法參數屬於允許限产 旰隈度内。儘管此舉提供某種 程度之驗證,但若在涉及若4 右干參數之組合的複雜狀況 下,則此種製程可為不充分的。语m他 个兄刀的更困難的為,驗證製作 方法步驟之次序及類型符合給定 订σ、〇疋工具之操作視窗要求。 因此,本發明人提供了一猶用 J 裡用於自動驗證半導體製程 步驟之改進的方法及設備。 【發明内容】 本文提供了用於自動驗證半導體製程步驟之方法及設 備。在-些實施例中,-種用於驗證半導體製程製作方 法之方法(及一種儲存用於執行該方法之指令之電腦可 讀取媒體)包括以下步驟:選擇規則集,該規則集描述 半導體製私工具之刼作視窗;核對參數值與該規則集之 限制核對規則以產生第一結果,該等參數值係由該半導 體製程製作方法步驟定義;使用該規則集之步驟定義規 則’根據該半導體製程製作方法之該等步驟決定步驟類 型’以產生第二結果;核對該等步驟類型之間的轉變與 該規則集之步驟轉變規則,以產生第三結果;以及基於 該等第一結果、該等第二結果及該等第三結果,使用該 電腦產生驗證資料,以供與該半導體製程工具一起使用 該半導體製程製作方法。 201214183 在—些實施例中,一種用於驗證半導體製程製作方法 之設備包括:記憶體’該記憶體經配置為儲存製作方法 核對軟體及複數個規則集,該等規則集描述半導體製程 工具,操作視窗;以及處理器,該處理器耗接至該記憶 體’該處理器經配置為執行該製作方法核對軟體以:自 該複數個規則集選擇規則集,該等規則集用於描述半導 體製程工具;核對參數值與該規則集之限制核對規則以 產生第-結果’該等參數值係由該半導體製程製作方法 步驟定義;使用該規則集之步驟定義規則,根據該半導 體製程製作方法之該等步驟決定步驟類型,以產生第二 結果"玄對該等步冑類型<間的轉變與該規則集之步驟 轉變規則,以產生第三結果;以及基於該等第一結果、 該等第二結果及該等第三結果,產生驗證資料,以供與 «亥半導體製程工具一起使用該半導體製程製作方法。 本發明之其他及另外實施例描述如下。 【實施方式】 第1圖為圖不計算系統1 〇〇之示例性實施例之方塊 圖°十异系統100包括:處理器1 〇2、記憶體! 〇4、各種 支援電路106 ' I/O介面1〇8及顯示器1〇9。本文中所稱 作之電腦」可至少包括處理器系統1 02及記憶體1 04。 通常’處理器102可包括一或更多中央處理單元^⑶㈣ processing units; CPUs)。CPU包括電路,該電路經配置 201214183 為執行程式指令(「軟體」)。處理器102之支援電路1〇6 包括:習知快取記憶體、電源、時脈電路、資料暫存器、 I/O介面等。I/O介面108可直接耦接至記憶體1〇4或經 由處理器102搞接。I/O介面108可耦接至顯示器ι〇9及 工/0裝置UW/0裝置可包括各種輸入/輸出裝置(例如, 鍵盤' 滑鼠等)。記憶體104可包括以下中之一或更多者·· 隨機存取記憶體、唯讀記憶體、磁阻讀寫記憶體、光學 讀寫記憶體、快取記憶體、磁性讀寫記憶體等。 記憶體104儲存軟體110’軟體11〇包括程式指令,該 等程式指令經配置以由處理器1〇2執行。軟體ιι〇可包 括作業系統(operating system; 〇s) 112及半導體製程製 作方法核對工具(「製作方法核對器m」)。0SU2可提 供製作方法核對器114與計算系统1〇〇之間的介面。可 使用本領域已知之各種作業系統實施os 112。在0SU2 的控制下’可由處理器102執行製作方法核對器ιΐ4,以 執灯驗證半導體製程製作方法,如下文詳細描述。 在-些實施例中,計算系統1〇〇可經由ι/〇介面⑽ 麵接至半導體製程工具15〇。因此,電腦系201214183 VI. Description of the Invention: [Technical Field of the Invention] Embodiments of the present invention generally relate to a method and apparatus for automatically verifying a semiconductor manufacturing process. [Prior Art] The process of fabricating a semiconductor device can require a number of sequential steps that can result in hundreds or even thousands of process variations. In addition, the process steps u have various specifications and requirements' to further increase the variability of the system & π. Therefore, process engineering = semiconductor manufacturing method ("manufacturing method") to specify the process: how to perform this step for each tool used in the process. The incorrect fabrication method can produce the wafer. Given ^=fruit' may even be damaged and clear and complex. In this kind of wide-time knowledge window, it is possible to create a production method for the definition. Miscellaneous, the process engineer can go wrong beyond the defined operating window of the tool. Therefore, :: is incorrect or before the manufacturing process, it is necessary to verify that the producers use a normal, manual verification method, which is used to determine the specifications of the tool and the operating window. The special verification production method is labor and reference to the production method labor (four) type and error-prone. In general, efforts to implement the automated verification method in 201214183 focus on using spreadsheets to verify that production method parameters are within allowable limits. Although this provides some degree of verification, such a process may be insufficient if it involves a complex combination of parameters such as 4 right-hand parameters. It is more difficult for him to verify that the order and type of steps in the production method are in accordance with the operational window requirements of the given σ and 〇疋 tools. Accordingly, the inventors have provided an improved method and apparatus for automatically verifying semiconductor process steps in J. SUMMARY OF THE INVENTION Methods and apparatus for automatically verifying semiconductor fabrication steps are provided herein. In some embodiments, a method for verifying a semiconductor fabrication process (and a computer readable medium storing instructions for performing the method) includes the steps of selecting a rule set describing a semiconductor system a window of the private tool; checking the parameter value and the constraint checking rule of the rule set to generate a first result, the parameter value being defined by the semiconductor manufacturing method step; using the rule set step to define a rule according to the semiconductor The steps of the process making method determine the step type 'to generate a second result; check the transition between the step types and the step set of the rule set to generate a third result; and based on the first result, the Waiting for the second result and the third result, the computer is used to generate verification data for use with the semiconductor process tool for the semiconductor process fabrication method. 201214183 In some embodiments, an apparatus for verifying a semiconductor fabrication process includes: a memory configured to store a fabrication method collation software and a plurality of rule sets, the rule sets describing semiconductor process tools, operations a window; and a processor consuming the memory to the memory 'the processor is configured to execute the production method check software to: select a rule set from the plurality of rule sets, the rule set is used to describe a semiconductor process tool Checking the parameter values and the constraint checking rules of the rule set to generate a first-result 'the parameter values are defined by the semiconductor process fabrication method steps; using the rule set steps to define rules according to the semiconductor process fabrication method The step determines a step type to generate a second result " a transition between the step type < and a step transition rule of the rule set to generate a third result; and based on the first result, the first The second result and the third result, the verification data is generated for use with the «Heil Semiconductor process tool Guide system processes production methods. Other and additional embodiments of the invention are described below. [Embodiment] FIG. 1 is a block diagram of an exemplary embodiment of a computing system 1 图. The system 100 includes: processor 1 〇 2, memory! 〇4, various support circuits 106' I/O interface 1〇8 and display 1〇9. The computer referred to herein may include at least a processor system 102 and a memory 104. Typically, processor 102 may include one or more central processing units ^ (3) (four) processing units; CPUs). The CPU includes circuitry that is configured to execute program instructions ("software") in 201214183. The support circuit 1〇6 of the processor 102 includes: a conventional cache memory, a power supply, a clock circuit, a data register, an I/O interface, and the like. The I/O interface 108 can be directly coupled to the memory 1〇4 or interfaced by the processor 102. The I/O interface 108 can be coupled to the display ι 9 and the work/0 device UW/0 device can include various input/output devices (eg, a keyboard 'mouse, etc.). The memory 104 may include one or more of the following: a random access memory, a read-only memory, a magnetoresistive read/write memory, an optical read/write memory, a cache memory, a magnetic read/write memory, and the like. . The memory 104 storage software 110' software 11 includes program instructions that are configured to be executed by the processor 1〇2. The software ιι〇 may include an operating system (〇s) 112 and a semiconductor manufacturing method verification tool ("production method checker m"). The 0SU2 provides an interface between the authoring method checker 114 and the computing system. The os 112 can be implemented using a variety of operating systems known in the art. The fabrication method verifier ι 4 can be executed by the processor 102 under the control of 0SU2 to perform the lamp verification semiconductor fabrication process, as described in detail below. In some embodiments, the computing system 1 can be interfaced to the semiconductor process tool 15 via the ι/〇 interface (10). Therefore, the computer department

尤其,由製作方法核對器114所產生之輸出)可有二 地用以控制半導體製藉丁目1C 導體製程…5。…、150以執行半導體處理。半 體裝置之㈣類型工且 已知用於處理且製造半導 第 圖。 2圖為圖示製作方法核對器 製作方法核對器114可包括: Π 4之實施例之方塊 規則引擎202、規則資 201214183 料庫2〇4、輸入介面(「輸入IF 2〇6」)及輸出介面(「輸 出IF 208」)。規則資料庫204可包括複數個規則集21 6。 輸入IF 206經配置為接收一或更多製作方法21〇及工具 配置資料(「工具配置2丨4」)。輸入IF 2 06將製作方法(多 個)210及工具配置214耦接至規則引擎2〇2。規則引擎 2 02經配置為存取規則資料庫204以獲得一或更多規則 集216。規則引擎202產生驗證資料212,該驗證資料212 係經由輸出IF 208提供作為輸出。輸入IF2〇6及輸出Ιρ 208可為使用者介面中之_部分諸如圖形使用者介面 (grapMCaluserinterface;Gui)116,圖形使用者介面 ιι6 可圖示於計算系統100之顯示器1〇9上。 社料中’製作方法(多個)21〇描述一或更多半導體 製程製作方法。製作方、车< 夕2 忐裝作方去(多個)21〇可為任何電子格式, 諸如普通正文檔案、可延伸標示語言(咖心職_ language; XML)檔案等。 半導體製程工具(c方法描述-系列待由 4il. ^ 八」)在半導體晶圓上執行之 處理步驟(「步驟)。 義。「扑八h + 步驟可由-或更多指令定 紙 知令」描述待由1目_ 相择㈣夕+ 具執仃之動作及/或與製程工具 相關聯之-或更多參數配置。例 具之特定參數之數值賦值 7 了描述I程工 可執行各種動作,諸如韻刻:沈:f知,製程工具 可設定為不同數值之各種參數,力母主一個動作包括 製程氣流、製程氣屋等。因此/源功率 '偏壓功率、 因此,製作方法步驟可實行動 201214183 作及/或設定製程 程。 工具之各種參數 以達成所要半導體製 母-個製程工具包括「操作視窗」,該「操作視窗」定 義關於各種動作及參數(例如,最小,最大參數值、需要 且允許動作及動作順序等)《限制。規則資料庫204包 括=數個製程工具之規則集216。每一個規則集216描述 特定製程工具之操作視窗(或製程工具之版本,若製程 工具具有多個版本或配置)。通常,規則引擎2〇2核對製 作方法(多個)21〇與規則集216,卩決定製作方法(多 個)210對製作方法210之預定製程工具是否有效。工具 配置214提供特定製程工具之配置資料。規則引擎逝 可使用工具配置214白招日丨丨a, 直4自規則集216選擇特定規則集,該 特定規則集對應於如所配置之彼特定製程工具。 規則集216包括各種規則,該等規則定義如所配置之 製程工具之操作視窗。規則集216可包括不同類型之規 則規則」疋義與製程工具之參數及/或動作相關聯之 _。規則可包括優先順序。例如,規則可定義為「嚴 苛」,原因在於違反此種規則可對製程工具及/或半導體 晶圓造成損壞。規則可定義$「警示」,原因在於違反此 種規則為不推薦而有可能的。熟習此項技術者將瞭解, 額外及/或不同類型之優先順序可分配給該等規則。 在一些實施例中,規則集216包括限制核對規則。「限 制核對規則」可定義製程工具之特定可變參數之限制。 例如,一個限制核對規則可定義在處理期間維持於製程 201214183 工具腔至中之最小壓力。另一個限制核對規則可定義此 I y士 敢大值。另一個限制核對規則可定義最小/最大 轧抓。熟習此項技術者將瞭解,各種限制核對規則可為 特定製祆工具之各種參數而形成。 在些貫施例中,規則集2 16包括步驟定義規則。「步 驟定義規則」可定義步驟類型之一組要求。「步驟類型」 為可由製程工具所執行之動作。例如,蝕刻腔室可執行 源蝕刻步驟、偏壓蝕刻步驟、沖洗步驟、清潔步驟等。 藉由°又定工具之特定參數及分配給此種參數之數值,來 :義每—種步驟類型。由步驟定義規則所定義之要求指 疋那些參數及參數值會產生特定步驟類型。例如「X」 瓦特源功率'、」瓦特偏壓功率及「z」seem氣流可分 類為源姓刻步驟類型’目此可設定步驟定義規則之要 f。、」瓦特源功率、「b」瓦特偏壓功率及「c」sccm 礼流可分類為偏壓則步驟類型,因此可設定步驟定義 規則之要求。熟習此項技術者將瞭解,給定製程工具可 ^有各種步驟類型且步驟定義規則可經定義以分類此種 步驟類型。 -些實施例中,規則集216包括步驟轉變規則。「 驟轉變規則」可定牛剧^s Λ,丨a 0曰y 制 J疋義步驟類型之間允許且需要的轉變 程工具可執行各種步驟類型 進行。製程工且… 要按任何順 製ί具之刼作視窗可定義步驟類型之間允許2 或需要的轉變。例如,步驟轉變規則可定義,允許步驟 10 201214183 跟隨步驟Ad-個步驟轉變規則可定義,不允許步驟E 跟隨步驟C’而必須在步驟C與步驟£之間執行步驟D。 熟習此項技術者將瞭解’規則集216可包括上述^ 的限制核對、步驟定義及步驟轉變規則之各種實施例: 例如’可以製程工具之不同變體之不同規則配置任何規 則。可以相依資訊配置任何規則,例如,若製程工具具 有某—特徵,則必須相應地配置彼特徵。 在操作中,規則引擎202針對合㈣規則集216摩用 每-個製作方法21〇,以決定製作方法21〇是否有效。在 一些實施例中’規則引$ 2G2核對由製作方法步驟所定 義之參數值與限制核對規則’以產生第一結果,該等第 —結果指示違反此種規則(若有)。隨後,規則引擎202 可使用步驟定義規則來決定製作方法之步驟類型,以產 生第二結果,該等第二結果將製作方法步驟分成特定步 驟類型。隨後’規_ 202可核對步驟類型之間的轉 變與步驟轉變規則,以產生第三結果,該等第三 示違反此種規則(若有)。然後,基於第一結果、第二^ 果及第三結果,規則引擎2〇2可產生驗證資料Η?,以供 與如所配置之特定製程工具一起使用製作方法。 ’、 驗證資料212可指示錯誤(多個)(若有),該(等) 錯誤描述違反應用規則集中之至少一個規則。在一些實 施例中’錯誤指不(多個)可進一步描述製作方法之修 (夕個)’該(等)修改為消除違規所必需。驗證資料 212係經由輸出if 208提供作為輸出。例如,驗證資料 11 201214183 212可經由GUI而向伟宙本舶- 叩使用者顯不,因此使用者 規及產生有效製作方法所需要之潛在修改。 ’、 在一些實施例中,製作方法核對器114包括製作 減輕模組2 1 8。製作方法、、ά @ z 眾忭万去減輕模組218經配 資料2U及製作方法21〇(多 收驗。且 製作方法減輕模組2 1 8 經配置為修改已被指+ & & /已被“為無效之製作方法(多個)。例 如,製作方法減輕模組?s π 士 , , 18可有利地識別違規及驗證資 料2 1 2之推薦修改,且自叙攸并、五 且自動修改違反了的製作方法,以 消除运規。製作方法減輕模 可猎由改變參數值、 插入步驟、移除步驟、重新 垔新佈置步驟專而進行修改, 使製作方法將滿足特定庫 " ⑴產生修改後的製作 咸“‘、且 、夕個;220,以作為輪屮。 第3圖$圖示驗證製 ^ 的流程圖。可由上述計算系方法咖之實施例 ’、統〇 〇來執行方法3 0 0。方法 300始於步驟3〇1。在步 法 仕,驟302,選擇規則隼 體製程工具之操作視窗。在 J集朿…導 配置資料來選擇規則集。 了基於八 也丨/驟304,核對由丰導體贺栽 製作方法之步驟所定義之參 則,以產生第一結果。在步驟值”規則集之限制核對規 步驟306,使用規則隼之步驟宏 義規則,根據半導體製程 則集之/驟疋 型,以產生第二結果。在步之步驟決定步驟類 轉變與規則集之步驟轉變規則,核對步驟類型之間的 驟310,基於第一結果、第二社要以產生第三結果。在步 一、、,°果及第三結果,有利地產 12 201214183 具—起使用半導體製 生驗證資料,以供與半導體製程 程製作方法。 方法3”包括步驟312,在步驟312中使用 在顯示器上顯示驗證資 .概也貝科,該顯示器耦接 300可包括步驟314至316 方法…“ 至步驟316。在步驟3M,判定製作 方法疋否被指示為有效。若是, 〇QQ _ , 彳方去30〇結束於步驟 利地佟貝1,方法3〇0行進至步驟316。在步驟316,有 二半導體製程製作方法’,以消除錯誤(多個),該 (專)錯誤由驗證資料所描述。隨後,方* 3〇〇可返回 至步驟304且進行重複。 口本發明之態樣實施為與電腦系統一起使用之程式產 品。程式產品之(多個)定義實施例之功能且該⑷ 程式可包含於各種電腦可讀取媒體上,包括(但不限 於)·⑴資訊’該資訊永久儲存於不可寫入儲存媒體(例 如,電腦内之唯讀記憶體裝置’諸如可由cd_r〇m驅動 或DVD驅動讀取之CD-R〇M磁碟或dvd r〇m磁碟) 上;以及(ii)可改寫資訊,該可改寫資訊儲存於可寫入儲 存媒體(例如’磁片驅動或硬碟驅動内之軟式磁碟或可 喂寫CD或可讀寫dvd )上。當此種電腦可讀取媒體攜 帶電腦可讀取指令時,此種電腦可讀取媒體表示本發明 之實施例’其中該等指令指示本發明之功能。 儘管上文係針對本發明之實施例,但在不脫離本發明 之基本範疇之情況下可設計本發明之其他及另外實施 例。 13 201214183 【圖式簡單說明】 上文簡要概述且下文更詳細論述之本發明之實施例可 參照本發明之說明性實施例進行轉,本發明之說明性 實施例圖示於附加圖式中。然而,應注意,附加圖式僅 圖示本發明之典型實施例,因此不欲視為本發明範疇之 限制,因為本發日月可允許其他时有效之實施例。 第1圖為圖示計算系統之示例性實施例之方塊圖; 第2圖為圖示製作方法核對器之實施例之方塊圖;以 及 第3圖為圖示驗證製程製作方法之方法實施例之流程 為了促進理解,為· r月b之情況下,相同元件符號茯矣 諸圖所共有之相同元徠 琥代表 件。諸圖未按比例繪製且為清楚起 見了予以簡化。預细 . J ~個實施例之元件及特徵結構可有 利地併入其他實施彳 有 包例中而無需進一步敍述。 14 201214183 【主要元件符號說明】 100 計算系統 102 處理器 104 記憶體 106 支援電路 108 I/O介面 109 顯示器 110 軟體 111 I/O裝置 112 作業系統 114 製作方法核對器 150 半導體製程工具 202 規則引擎 204 規則資料庫 206 輸入介面 208 輸出介面 210 製作方法 212 驗證資料 214 工具配置 216 規則集 218 製作方法減輕模組 220 修改後的製作方法 300 方法 301 步驟 302 步驟 304 步驟 306 步驟 308 步驟 310 步驟 3 12 步驟 3 14 步驟 316 步驟 399 步驟 15In particular, the output produced by the fabrication method verifier 114 can be used to control the semiconductor system. ..., 150 to perform semiconductor processing. The type (4) of the half-body device is known and used to process and fabricate a semi-conducting map. 2 is a diagram of the production method verification method verification method checker 114 may include: 方块 4 embodiment of the block rule engine 202, rule capital 201214183 library 2 〇 4, input interface ("input IF 2 〇 6") and output Interface ("Output IF 208"). The rules repository 204 can include a plurality of rule sets 216. The input IF 206 is configured to receive one or more production methods 21 and tool configuration data ("Tool Configuration 2" 4). The input IF 2 06 couples the production method (multiple) 210 and the tool configuration 214 to the rules engine 2〇2. The rules engine 202 is configured to access the rules repository 204 to obtain one or more rule sets 216. The rules engine 202 generates a verification material 212 that is provided as an output via the output IF 208. The input IF2 〇 6 and the output Ι ρ 208 may be part of the user interface such as a graphical user interface (GrapMCaluser interface; Gui) 116, and the graphical user interface ιι6 may be illustrated on the display 1 〇 9 of the computing system 100. In the community, the manufacturing method(s) 21〇 describes one or more semiconductor manufacturing methods. Producer, car < 夕 2 忐 作 去 ( 多个 多个 多个 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 。 。 。 。 。 。 。 。 Semiconductor process tool (c method description - series to be 4il. ^ eight) processing steps performed on the semiconductor wafer ("steps". Meaning. "Push eight h + steps can be ordered by - or more orders" Describe the configuration to be performed by 1 item _ 相 (4) + + 仃 及 and/or associated with the process tool - or more parameter configuration. The numerical value assignment of the specific parameters of the example 7 describes the I process can perform various actions, such as rhyme: Shen: f know, the process tool can be set to various parameters of different values, the main action of the force master includes process airflow, process gas House and so on. Therefore, the source power 'bias power, therefore, the manufacturing method steps can be implemented 201214183 and / or set the process. The various parameters of the tool to achieve the desired semiconductor master-process tool include an "operation window" that defines various actions and parameters (eg, minimum, maximum parameter values, required and allowed actions, and sequence of actions, etc.) limit. The rules repository 204 includes a set of rules 216 for a number of process tools. Each rule set 216 describes the operational window of a particular process tool (or the version of the process tool if the process tool has multiple versions or configurations). In general, the rules engine 2〇2 collates the production method(s) 21〇 with the rule set 216, and determines whether the production method(s) 210 are valid for the predetermined process tool of the production method 210. Tool Configuration 214 provides configuration information for a particular process tool. The rule engine may use the tool configuration 214 to select a particular rule set from the rule set 216, the particular rule set corresponding to the particular process tool as configured. Rule set 216 includes various rules that define the operational window of the process tool as configured. Rule set 216 may include different types of rule rules" _ associated with the parameters and/or actions of the process tool. Rules can include prioritization. For example, rules can be defined as "stringent" because violations of such rules can cause damage to process tools and/or semiconductor wafers. Rules can define $"alerts" because it is possible to violate this rule as not recommended. Those skilled in the art will appreciate that additional and/or different types of prioritization may be assigned to such rules. In some embodiments, rule set 216 includes a restriction check rule. The Limit Check Rule defines the limits of specific variable parameters of the process tool. For example, a limit check rule can define the minimum pressure to maintain the process chamber 201214183 during processing. Another restriction check rule can define this I y dare to be big. Another restriction check rule can define a minimum/maximum roll. Those skilled in the art will appreciate that various restriction checking rules can be formed for various parameters of a particular manufacturing tool. In some embodiments, rule set 2 16 includes step definition rules. The Step Definition Rule defines one of the group requirements for the step type. The "step type" is an action that can be performed by the process tool. For example, the etch chamber may perform a source etch step, a bias etch step, a rinsing step, a cleaning step, and the like. By means of ° specific parameters of the tool and the values assigned to such parameters, each type of step is defined. The requirements defined by the step definition rules refer to those parameters and parameter values that result in a particular step type. For example, "X" Watt source power', "Watt bias power and "z" seem airflow can be classified as source name step type". This can be set to define the rule f. The watt source power, the "b" watt bias power, and the "c" sccm ritual can be classified as the bias step type, so the requirements of the step definition rules can be set. Those skilled in the art will appreciate that there are various step types for custom programming tools and that step definition rules can be defined to classify such step types. In some embodiments, rule set 216 includes a step transition rule. The "change rules" can be used to determine the number of step types that can be performed between the step types of the steps. The process and... You can define the allowable 2 or desired transitions between the step types by pressing any of the following windows. For example, the step transition rule can be defined, allowing step 10 201214183 to follow the step Ad-step transition rule can be defined, step E is not allowed to follow step C' and step D must be performed between step C and step £. Those skilled in the art will appreciate that the rule set 216 can include various embodiments of the restriction check, step definition, and step transition rules described above: For example, any rule can be configured for different rules of different variations of the process tool. Any rules can be configured with dependent information. For example, if a process tool has a feature, then the feature must be configured accordingly. In operation, the rules engine 202 uses each of the production methods 21 for the (four) rule set 216 to determine if the production method 21 is valid. In some embodiments, the 'rule introduces $2G2 to check the parameter values and limit checking rules defined by the method steps to produce a first result that indicates violation of such rules, if any. Subsequently, the rules engine 202 can use the step definition rules to determine the type of steps in the method of production to produce a second result that divides the method steps into specific step types. The "regulation> 202 may check for transitions between step types and step transition rules to produce a third result that violates such rules, if any. Then, based on the first result, the second result, and the third result, the rules engine 2〇2 can generate a verification data for use with the production method as configured by the particular process tool. ', the verification material 212 may indicate an error (multiple) (if any) that the description of the violation violates at least one rule in the application rule set. In some embodiments, the error means that the modification of the production method may further describe the modification of the production method (the same) is necessary to eliminate the violation. The verification data 212 is provided as an output via the output if 208. For example, the verification data 11 201214183 212 can be displayed to the Weizhou-Boss user via the GUI, so the user can make potential modifications required to produce an effective production method. In some embodiments, the fabrication method verifier 114 includes a fabrication mitigation module 2 18 . Production method, ά @z 忭 忭 去 减轻 减轻 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 218 / has been "ineffective production method (multiple). For example, the production method to reduce the module?s π,, 18 can be used to identify the violations and verification data 2 1 2 recommended modifications, and self-deprecating, and Automatically modify the production method that violates the rules to eliminate the operation rules. The production method can be modified by changing the parameter values, inserting steps, removing steps, and re-arranging the new steps to make the production method meet the specific library. (1) Produce the modified production salt "', and, the evening; 220, as the rim. Figure 3, the flow chart of the verification system ^. The embodiment of the above-mentioned calculation system method", the reconciliation Execution method 300. Method 300 begins with step 3〇1. In step, step 302, select the operation window of the rule system tool. In the J set... guide configuration data to select the rule set.丨/骤304, check by Feng The parameters defined by the steps of the method of making the plant are used to generate the first result. In the step value "rule set restriction check step 306, the rule is used in the macro rule, according to the semiconductor process set/squeeze type, To generate a second result. In the step of step, the step transition rule of the step class transition and the rule set is determined, and the step 310 between the step types is checked, based on the first result, the second community is to generate the third result. , and the third result, the beneficial real estate 12 201214183 uses the semiconductor production verification data for the semiconductor manufacturing process. The method 3" includes a step 312, in which the verification resource is displayed on the display. In addition, the display coupling 300 may include steps 314 to 316 ... "to step 316. In step 3M, it is determined whether the production method is indicated as valid. If so, 〇QQ _ , the 去方 goes to 30 〇 In the step of the mussel 1, the method 3〇0 proceeds to step 316. In step 316, there are two semiconductor manufacturing methods 'to eliminate the error (multiple), the (special) error test The information is described. Subsequently, the method can be returned to step 304 and repeated. The aspect of the invention is implemented as a program product for use with a computer system. The function of the defined embodiment(s) of the program product And the (4) program can be included on various computer readable media, including (but not limited to) (1) information 'This information is permanently stored in a non-writable storage medium (eg, a read-only memory device in a computer) such as cd_r 〇m drive or DVD drive to read CD-R〇M disk or dvd r〇m disk); and (ii) rewritable information, the rewritable information is stored in a writable storage medium (eg 'magnetic disk Drive or drive the hard disk in the hard drive or feed the CD or read and write dvd). When such computer readable medium carries computer readable instructions, such computer readable medium represents an embodiment of the present invention' wherein the instructions indicate the functionality of the present invention. While the above is directed to embodiments of the present invention, other and additional embodiments of the present invention may be devised without departing from the basic scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention, which are briefly described above and discussed in more detail below, may be described with reference to the illustrative embodiments of the invention, which are illustrated in the accompanying drawings. However, it is to be noted that the appended drawings are merely illustrative of the exemplary embodiments of the invention, and are not intended to 1 is a block diagram showing an exemplary embodiment of a computing system; FIG. 2 is a block diagram illustrating an embodiment of a manufacturing method verifier; and FIG. 3 is a block diagram illustrating a method of manufacturing a verification process In order to promote understanding, in the case of r r b, the same component symbol is the same as that represented by the figures. The figures are not drawn to scale and are simplified for clarity. The components and features of the embodiments can be advantageously incorporated into other embodiments without further elaboration. 14 201214183 [Description of main component symbols] 100 Computing system 102 Processor 104 Memory 106 Support circuit 108 I/O interface 109 Display 110 Software 111 I/O device 112 Operating system 114 Production method checker 150 Semiconductor process tool 202 Rule engine 204 Rule Database 206 Input Interface 208 Output Interface 210 Production Method 212 Validation Data 214 Tool Configuration 216 Rule Set 218 Production Method Light Reduction Module 220 Modified Production Method 300 Method 301 Step 302 Step 304 Step 306 Step 308 Step 310 Step 3 12 Step 3 14 Step 316 Step 399 Step 15

Claims (1)

201214183 七、申請專利範圍: 1. 一種驗證一半導體製程製作方法之電腦實施方法,該方 法包含以下步驟: 選擇一規則集,該規則集描述一半導體製程工具之一操作 視窗; 核對參數值與該規則集之限制核對規則以產生第一結果, 該等參數值係由該半導體製程製作方法步驟定義; 使用該規則集之步驟定義規則,根據該半導體製程製作方 法之S亥等步驟決定步驟類型,以產生第二结果; 核對該等步驟類型之間的轉變與該規則集之步驟轉變規 則,以產生第三結果;以及 基於該等第一結果、該等第二結果及該等第三結果,使用 該電腦產生驗證資料’以供與該半導體製程工具—起使 用該半導體製程製作方法。 2.如請求項1所述之方法,其中 邊擇步驟包含以下步 獲得該半導體製程工具之配置資料;以及 基於該配置資料,自複數個規則集選擇該規則集。 3.如請求項1所述之方法,其中 半導體製程工具之可變參數之限制 該等限制核對規則定義該 4·如請求们㈣之方法,其中該等步驟定義規則定義 16 201214183 等步驟類塑中之各步驟類型之一組要求。 5.如請求項1所述之方法’其中該等步驟轉變規則定義步 驟類型之間允許且需要的轉變。 6·如請求項1所述之方法,其中該驗證資料包括至少一個 錯誤指示器’該錯誤指示器描述違反該規則集中之至少 一個規則。 7. 如請求項6所述之方法’其中該至少一個錯誤指示進一 步描述該半導體製程製作方法之至少一個修改,以消除 該違規。 8. 如明求項6所述之方法,該方法進一步包含以下步驟: 使用该電腦修改該半導體製程製作方法,以消除該違規, 該違規由該至少一個錯誤指示器所描述。 9·如請求項8所述之方法’其中該修改步驟包含以下步驟: 在該半導體製程製作方法之該等步驟之中插入新步驟。 10.如請求項1所述之方法,該方法進一步包含以下步驟: 使用圖形使用者介面(graphical user interface; GUI)在一 顯不器上顯示該驗證資料,該顯示器耦接至該電腦。 17 201214183 ιι·一種用於驗證一半導體製程製作方法之設備,該設備包 含: 一記憶體,該記憶體經配置為儲存製作方法核對軟體及複 數個規則集,該等規則集描述半導體製程工具之操作視 窗;以及 —處理器,該處理器㉟接至該記憶體,該處理器經配置為 執行該製作方法核對軟體以: 自該複數個規則集選擇-規則集’該等規則集用於描述 一半導體製程工具; 核對參數值與該規則集之限制核對規則以產生第一結 果,該等參數值係由該半導體製程製作方法步驟定 義; 使用該規則集之步驟定義規則,根據該半導體製程製作 方法之該等步驟決定步驟類型,以產生第二結果; 核對該等步驟類型之間的轉變與該規則集之步驟轉變規 則’以產生第三結果;以及 基於該等第-結果、該等第:結果及該等第三結果,產 生驗證資料,以供與該半導體製程工具一起使用該半 導體製程製作方法。 12.如明求項11所述之設備,其中該記憶體經配置為儲存 該等半導體製程工具中之各半導體製程工具之配置資 料並且其中該處理器經配置為,基於該半導體處理器 工具之該配置資料自該複數個規則集選擇該規則集。 18 201214183 13. 如二求g u所述之設備,其中該等限制核對規則定義 該半導體製程卫具之可變參數之限制,其㈣等步驟定 義規則定義該等步驟類型中之各步驟類型之—組要求, 並且其中該等步驟轉變規則定義㈣類型之間允許且需 要的轉變。 14. 如請求㉟U所述之設備,其中該驗證資料包括至少一 個錯誤指示器,該錯誤指示器描述違反該規則集中之至 少一個規則。 15·如請求g Η所述之設備’其中該處理器經進一步配置 以: 使用:電腦修改該半導體製程製作方法,以消除該違規, 該堤規由該至少一個錯誤指示器所描述。 16. 如請求項η所述之設備,該設備進—步包含: -顯示器,該顯示器麵接至該處理器,該顯示器經配置為 使用-圖形使用者介面(GUI)來顯示該驗證資料。 17. 人種電腦可讀取媒體,該電腦可讀取媒體上健存有指 令’當該等指令由一處理器執行時使該處理器執行―: 驗證-半導體製程製作方法之方法,該方法包含以下步 19 201214183 選擇一規則集,該規則集描述一半導體製程工具之一操作 視窗; 核對參數值與該規則集之限制核對規則,以產生第一結 果,該等參數值係由該半導體製程製作方法步驟定義: 使用該規則集之步驟定義規則,根據該半導體製程製作方 法之該等步驟決定步驟類型,以產生第二妹果. 核對該等步驟類型之間的轉變與該規則集之步驟轉變規 則’以產生第三結果;以及 基於該等第-結果、該等第二結果及該等第三結果,使用 該電腦產生驗證資料,以供與該半導體製程工具一起使 用該半導體製程製作方法。 18. 如請求項17所述之電腦可讀取媒體,#中該等限制核 對規則定義該半導體製程工具之可變參數之限制,其中 該等步驟定義規則定義該等步驟類型中之各步驟類型之 -組要求’並且其中該等步驟轉變規則定義步驟類型之 間允許且需要的轉變。 19. 如請求項17所述之電腦可讀取媒體,丨中該驗證資料 包括至少-個錯誤指示器,該錯誤指示器描述違反該規 則集中之至少-個規則’並且其中該至少—個錯誤指示 進一步描述該半導體製程製作方法之至少-個修改,以 消除該違規。 20 201214183 ’其中該驗證資料 示器福述違反該規 方法進一步包含以 20.如叫求項17所述之電腦可讀取媒體 包括至少—個錯誤指示器,該錯誤指 則集中之至少一個規則,並且其中該 下步驟: Λ 使用該電腦修改該半導體製裎製作方、 該違規由該至少一個錯誤指-^以消除該違規, 曰不器所描述。 21201214183 VII. Patent application scope: 1. A computer implementation method for verifying a semiconductor manufacturing method, the method comprising the following steps: selecting a rule set, the rule set describing an operation window of a semiconductor process tool; checking the parameter value and the Restricting the collation rules of the rule set to generate a first result, the parameter values are defined by the steps of the semiconductor manufacturing method; using the rules of the rule set to define rules, determining the type of the step according to the steps of the semiconductor manufacturing method Generating a second result; checking a transition between the types of step types and a step transition rule of the rule set to generate a third result; and based on the first result, the second result, and the third result, The use of the computer to generate verification data 'for use with the semiconductor process tool to use the semiconductor process fabrication method. 2. The method of claim 1, wherein the step of selecting comprises the step of obtaining configuration data of the semiconductor process tool; and selecting the rule set from the plurality of rule sets based on the configuration data. 3. The method of claim 1, wherein the variable parameter of the semiconductor process tool limits the restriction checking rules to define the method of the request (4), wherein the step defines the rule definition 16 201214183, etc. One of the various step types in the requirement. 5. The method of claim 1 wherein the step transition rules define allowed and required transitions between step types. The method of claim 1, wherein the verification data includes at least one error indicator 'the error indicator describes violation of at least one rule in the rule set. 7. The method of claim 6, wherein the at least one error indicates to further describe at least one modification of the semiconductor process fabrication method to eliminate the violation. 8. The method of claim 6, the method further comprising the step of: modifying the semiconductor process fabrication method using the computer to eliminate the violation, the violation being described by the at least one error indicator. 9. The method of claim 8 wherein the modifying step comprises the step of: inserting a new step among the steps of the semiconductor fabrication process. 10. The method of claim 1, the method further comprising the step of: displaying the verification data on a display using a graphical user interface (GUI) coupled to the computer. 17 201214183 ιι. A device for verifying a semiconductor fabrication process, the device comprising: a memory configured to store a production method collation software and a plurality of rule sets describing semiconductor process tools An operating window; and a processor, the processor 35 coupled to the memory, the processor configured to execute the authoring method of collating the software to: select from the plurality of rule sets - a rule set 'the rule sets are used to describe a semiconductor process tool; verifying a parameter value and a constraint checking rule of the rule set to generate a first result, wherein the parameter value is defined by the semiconductor process manufacturing method step; using the rule set step to define a rule, according to the semiconductor process The steps of the method determine the type of the step to produce a second result; the transition between the step types and the step of the rule set transition rule ' to generate a third result; and based on the first result, the first : the results and the third results, generating verification data for the semiconductor process The drive system using the semiconductor device manufacturing method together. 12. The device of claim 11, wherein the memory is configured to store configuration data for each of the semiconductor process tools in the semiconductor process tool and wherein the processor is configured to be based on the semiconductor processor tool The configuration data selects the rule set from the plurality of rule sets. 18 201214183 13. The device as described in claim 2, wherein the restriction checking rule defines a limitation of a variable parameter of the semiconductor process tool, and (4) a step defining rule defines a type of each step in the step type. The group requirements, and where the step transition rules define (4) allow and require transitions between types. 14. The device of claim 35, wherein the verification material includes at least one error indicator that describes violation of at least one rule in the set of rules. 15. The device of claim </RTI> wherein the processor is further configured to: use a computer to modify the semiconductor process fabrication method to eliminate the violation, the bank gauge being described by the at least one error indicator. 16. The device of claim η, the device further comprising: - a display, the display being interfaced to the processor, the display being configured to display the verification data using a graphical user interface (GUI). 17. A human computer readable medium, the computer readable medium having instructions for causing the processor to execute when the instructions are executed by a processor - a method of verifying - a semiconductor process manufacturing method The following steps are included: 19 201214183 Selecting a rule set describing an operation window of a semiconductor process tool; checking a parameter value and a restriction check rule of the rule set to generate a first result, the parameter value is determined by the semiconductor process Manufacturing method step definition: using the rules of the rule set to define rules, according to the steps of the semiconductor manufacturing method, determining the type of the step to generate a second sister. The transition between the types of steps and the steps of the rule set Transforming the rules to generate a third result; and using the computer to generate verification data for use with the semiconductor process tool based on the first results, the second results, and the third results . 18. The computer readable medium of claim 17, wherein the restriction checking rules define restrictions on variable parameters of the semiconductor process tool, wherein the step definition rules define each of the step types in the step types The -group requirement' and wherein the step transition rules define the transitions that are allowed and required between the step types. 19. The computer readable medium of claim 17, wherein the verification data includes at least one error indicator describing violation of at least one rule of the rule set and wherein the at least one error The indication further describes at least one modification of the semiconductor fabrication process to eliminate the violation. 20 201214183 'where the verification information device violates the rules further includes 20. The computer readable medium as claimed in claim 17 includes at least one error indicator, at least one rule of the error indication set And wherein the next step: Λ using the computer to modify the semiconductor maker, the violation is described by the at least one error-^ to eliminate the violation. twenty one
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