TW201205748A - Ball grid array package - Google Patents

Ball grid array package Download PDF

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Publication number
TW201205748A
TW201205748A TW99124790A TW99124790A TW201205748A TW 201205748 A TW201205748 A TW 201205748A TW 99124790 A TW99124790 A TW 99124790A TW 99124790 A TW99124790 A TW 99124790A TW 201205748 A TW201205748 A TW 201205748A
Authority
TW
Taiwan
Prior art keywords
substrate
ball
pads
power
solder
Prior art date
Application number
TW99124790A
Other languages
Chinese (zh)
Other versions
TWI476881B (en
Inventor
Wen-Jeng Fan
Original Assignee
Powertech Technology Inc
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Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW099124790A priority Critical patent/TWI476881B/en
Publication of TW201205748A publication Critical patent/TW201205748A/en
Application granted granted Critical
Publication of TWI476881B publication Critical patent/TWI476881B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Disclosed is a BGA package comprising a substrate, a chip disposed on the substrate, and a plurality of solder balls under the substrate. The substrate has a plurality of ball pads and a solder mask having openings to expose the ball pads. Among the ball pads, there are two or more power/ground pads. The solder mask have a groove connecting the power/ground pads and solder material is filled in the groove to bond with the solder balls on the power/ground pads. Thereby, the voltages of the power/ground pads can be balanced. It is a way to save power/ground metal layer in the substrate so that package thickness is thinned and substrate cost is reduced.

Description

201205748 • 六、發明說明： • 【發明所屬之技術領域】 纟發明係有關於半導體裝置，特別係有關於一種球柵 陣列封裝構造。 【先前技術】 球柵陣列封裝構造（BGA package)已為相當普遍的積 胃電路產^ ’内設有半導體晶片’並㈣複數個在基板 下呈多排格狀陣列之銲球（s〇lder ba⑴接合至一外部印 _ 刷電路板，相較於早期延伸在封膠體兩側之外引腳，更 具有小尺寸與高密度之優點。 球柵陣列封裝構造主要結構可分為三部分：基板、晶 片和封膠體。通常基板之一表面為表面接合面，另一相 對表面為晶片的安裝面。基板是一種線路特別精細的印 刷線路板，I了符合封裝要求的較多輸出端子數或是基 板微小化，通常為多層板，其内部設有位在不同層之信 φ號佈線層、電源層與接地層。 如第1與2圖所示，一種習知球格陣列封裝構造主要 包含有一基板110、複數個銲球13〇以及一内密封有晶 片之封膠體160。該基板11〇係具有一第一表面1U與 一第二表面112。該第一表面1U係為被該封膠體16〇 覆蓋之表面，該第二表面112係為顯露於該封膠體16〇 之外且相對於該第一表面U1之外表面。該基板n〇係 作為晶片載體與電性傳遞介面，内部形成有信號佈線 層、接地層118與電源層119»在該第二表面112之佈 201205748201205748 • VI. Description of the Invention: • Technical Field of the Invention The invention relates to a semiconductor device, and more particularly to a ball grid array package structure. [Prior Art] The ball grid array package structure (BGA package) has been used for the production of semiconductor wafers in a fairly common gastrointestinal circuit and (4) a plurality of solder balls in a multi-row grid array under the substrate (s〇lder) The ba(1) is bonded to an external printed circuit board, which has the advantages of small size and high density compared with the pins extending on both sides of the sealing body. The main structure of the ball grid array package structure can be divided into three parts: the substrate , wafer and encapsulant. Usually one surface of the substrate is a surface joint surface, and the other opposite surface is a mounting surface of the wafer. The substrate is a printed circuit board with particularly fine lines, and the number of output terminals that meet the packaging requirements is The substrate is miniaturized, usually a multi-layer board, and has a signal layer, a power layer, and a ground layer, which are located in different layers. As shown in FIGS. 1 and 2, a conventional ball grid array package structure mainly includes a substrate 110. a plurality of solder balls 13A and a sealant 160 sealed with a wafer. The substrate 11 has a first surface 1U and a second surface 112. The first surface 1U is the sealant. a 16 〇 covered surface, the second surface 112 is exposed outside the encapsulant 16 且 and opposite to the outer surface of the first surface U1. The substrate n 〇 is used as a wafer carrier and an electrical transfer interface, and the inside is formed There is a signal wiring layer, a ground layer 118 and a power layer 119» on the second surface 112. 201205748

線層係以一銲罩層114覆蓋，該銲罩層114係具有複數 個開孔114 A以顯露出該佈線層之複數個接球墊113。該 些銲球130係回焊連接在對應之該些接球墊113。利用 該些銲球13 0使該球柵陣列封裝構造可接合至一外部印 刷電路板。該基板110内更設有複數個導通孔（via)U7 或可稱為錄通孔（Ρ ΤΗ)，該些接球墊丨13中的多個接地墊 (對應到vss的腳位）與多個電源墊（對應到vcc的腳位） 係經由對應之導通孔117分別電性連接至該接地層118 與該電源層119,達到電壓平衡，故可降低因接地電流 回流及電源輸送產生的封裝電感，進而降低電磁波干 擾。然而’如第3圖所示，因基板的多層數而具有較高 的基板成本與較大的基板厚度。 有人曾在覆晶封裝構造中提出一種改善結構，例如我 國專利公告第555 1 52號所揭示者，基板與晶片更設有一 面積大於接球墊的矩形或條狀凸塊墊，作為電源晶片墊 或是接地晶片墊，並以體積遠大於銲球凸塊之大銲料凸 塊接合基板與晶片之大面積凸塊墊，即為使多個銲球凸 塊溶合成大尺寸非球狀凸塊之型態。雖可改善電性效能 與傳導散熱性’但在回料Α尺寸銲料凸塊的高度與表 面張力不利於表面接合，銲球凸塊有假焊之虞。此外， 大面積凸塊墊會影響基板與晶片之高密度線路佈局與對 流散熱性。 【發明内容】 有蓉於此，本發明之主要 目的係在於提供一種球柵陣 201205748 列封裝構造，能縮減基板内部的金屬層又不會影響電性 效能與對流散熱性，從而使半導體封裝構造更為薄化並 能使基板成本更為降低。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種球栅陣列封裝構造，包含 一基板、-晶片以及複數個銲球。該基板係具有一第一 表面與-第二表面，該基板更具有複數個接球墊以及形 成於該第二表面之一銲覃《，兮名日里θ β 〇丄The wire layer is covered by a solder mask layer 114 having a plurality of openings 114 A for revealing a plurality of ball pads 113 of the wiring layer. The solder balls 130 are reflow soldered to the corresponding ball pads 113. The ball grid array package construction can be bonded to an external printed circuit board using the solder balls 130. The substrate 110 further includes a plurality of vias U7 or may be referred to as recording vias (Ρ ΤΗ), and a plurality of ground pads (corresponding to vss pins) of the ball pads 13 A power pad (corresponding to the pin of vcc) is electrically connected to the ground layer 118 and the power layer 119 via the corresponding via holes 117 to achieve voltage balance, thereby reducing the package generated by ground current reflow and power supply. Inductance, which in turn reduces electromagnetic interference. However, as shown in Fig. 3, there is a high substrate cost and a large substrate thickness due to the number of layers of the substrate. Some people have proposed an improved structure in the flip chip package structure. For example, as disclosed in Japanese Patent Publication No. 555 1 52, the substrate and the wafer are further provided with a rectangular or strip-shaped bump pad having a larger area than the ball pad as a power chip pad. Or grounding the wafer pad and bonding the large-area bump pads of the substrate and the wafer with a large solder bump having a volume much larger than the solder ball bumps, that is, the plurality of solder ball bumps are dissolved into the large-sized non-spherical bumps. Type. Although the electrical performance and the conduction heat dissipation can be improved, but the height and surface tension of the solder bumps in the reed type are not conducive to surface bonding, the solder bumps have a false solder joint. In addition, large-area bump pads can affect the high-density line layout and convection heat dissipation of the substrate and the wafer. SUMMARY OF THE INVENTION The main object of the present invention is to provide a ball grid array 201205748 column package structure, which can reduce the metal layer inside the substrate without affecting electrical performance and convection heat dissipation, thereby making the semiconductor package structure It is thinner and can reduce the cost of the substrate. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a ball grid array package structure comprising a substrate, a wafer, and a plurality of solder balls. The substrate has a first surface and a second surface, the substrate further has a plurality of ball pads and one of the solder pads formed on the second surface, and the θ β 〇丄

杆旱層該銲罩層係具有複數個開The dry layer of the weld layer has a plurality of openings

孔以顯露出該些接球墊，該此接社I 邊二接球墊係包含兩個或兩個 以上之電源/接地塾。辞日η及 0日曰片係S又置於該基板。該些銲球 係接合至該基板之該些接球墊。其中，該鋅罩層係具有 -連通該些電源/接地墊之溝槽，該溝槽内係填入銲料， 以連接該些電源/接地執 登上的如球’藉使該些電源/接地 墊為電壓平衡。 本發明的目的及鉉、、t k 解决其技術問題還可採用以下技術 措施進—步實現。 在前述的球栅陣列# J封裝構造中，該銲料與該些銲球係 可*為相同材質。 在前述的球栅陣 一 封裝構造中，該些接球墊係可設於 該第二表面，且該澧揭 ^ 槽係為雷射切痕而不貫穿該銲罩層。 在刖述的球栅陣列 封裝構造中，該些接球墊係可設於 該笫一表面，且該溝 ^ 再僧係貫穿該銲罩層。 在則述的球柵陣列 Μ 封裝構造中，該些電源/接地墊之 中心點距離等於該4b —媒球墊之平均間距，且該溝槽係可 201205748 呈直條狀。 在前述的球柵陣列封裝構造中，該晶片之一主動面係 可貼附至該基板之該第一表面’該基板係可更具有一貫 穿槽孔，以顯露該晶片複數個位於該主動面之銲墊。 在前述的球柵陣列封裝構造中，可另包含複數個穿過 該貫穿槽孔之電性連接元件，以電性連接該 在前述的球柵陣列封裝構造中，可另包含一封膠體， 係形成於該基板之該第—表面，以密封該晶片。 在前述的球栅陣列封裝構造中，該些電源/接地墊之 周邊係可被該銲罩層所覆蓋。 在前述的球栅陣列封裝構造中，該溝槽之深度係可不 超過該些電源/接地墊之銲球接合表面。 又 在前述的球柵陣列封裝構造中，該基板之該第二表面 係可更設有-被該銲罩層覆蓋之訊號跡線，係穿過該些 • 該些電源/接地墊之間，但不連接至該些電源/接地墊。 由以上技術方案可以看出，本發明之球柵陣列封裝構 4，具有以下優點與功效： 一、可藉由在銲罩層之溝槽内填入銲料並連接電源/接地 墊上的銲球作為其中之一技術手段’使電源/接地墊 為電壓平衡，故能縮減基板内部的電源/接地金屬層 又不會影響電性效能與對流散熱性，從而使半導體 封裝構ie更為薄化並能使基板成本更為降低。 一、可藉由在銲罩層之溝槽内填入銲料並連接電源/接地 201205748 塾上的銲球作為其中之—技術手段，為基板外免用 大銲塊的立體電性連接的結構，可在同一回焊製程 同時形成銲料並使銲球固著於接球墊上，以降低封 裝製造成本並符合基板高密度佈線的要求。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之70件與組合關係’圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製’某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 據本發月之第一具體實施例，一種球柵陣列封裝構 造舉例說明於第4、5圖之截面示意圖、“圖之局部底 面示意圖與第7圖之局部底面立體圖。該球柵陣列封裝 構& 2〇0主要包含-基板210、-晶4 220以及複數個 銲球230。在本實施例第4圖中，雖以窗口型球柵陣列 封裝型態為例’但不受局限地，本發明亦可運用在其它 已知的球柵陣列封裝架構或是覆晶封裝架構。 明參閱第4圖所示，該基板2丨〇係用以提供電性連接 並作為該球柵陣列封裝構造200之晶片載體，通常是為 印刷電路板，亦可為陶瓷載板或是電路薄膜。該基板21〇 係具有一第一表面211與-第二表面212,該第一表面 201205748 211通常係為晶片設置面’並可為被封膠體覆蓋之表面， 而該第二表面212係為顯露於封膠體之外且相對於該第 一表面211之外表面，作為該些銲球23〇的安裝面。該 基板210更具有複數個接球墊213以及形成於該第二表 面212之一銲罩層214。該些接球墊213可形成於該第 二表面212或第一表面211。如第4與5圖所示，在本 實施例中’該些接球墊213係設於該基板21〇之該第二 表面2 12，以方便顯露。該銲罩層2丨4係具有複數個開 孔2 14 A，以顯露出該些接球墊2丨3，該些接球墊2丨3係 包含兩個或兩個以上之電源/接地墊2丨3 A，可電性連接 至該晶片220，以作為供電電壓端或是接地的參考電 位。該些接球墊213係可多排陣列排列在該基板21〇之 該第二表面212，其形狀可例如是圓形之接球墊，該些 電源/接地墊2 1 3 A之形狀與大小係可相同於該些接球墊 2 13之其它訊號塾，而該些電源/接地塾2丨3 a係可排列 在該基板210之角隅、側邊或中央位置。在本實施例中， 如第4圖所示，該些電源/接地墊213A係相互緊鄰排列， 並可鄰近於該基板210之中央位置。 該銲罩層2 1 4係可為一保護線路防止銲料污染之絕 緣性表面塗層，可稱之為綠漆，或可為其它具防銲特性 之表面保護層。該銲罩層214可提供該基板21〇表面絕 緣保護，能防止線路及基板核心層外露而被污染。具體 而言，如第5圖所示，該銲罩層214之開口 214A直徑 係可小於該些接球墊包含該些電源/接地塾2nA之直 201205748 徑’即該些電源/接地墊213A之周邊係可被該銲罩層214 * 所覆蓋，而與該基板210有著較佳的固著力，故該些電 源/接地塾213A係為鲜罩界定塾（s〇lder Mask Defined， SMD)。在本實施例中，該基板2 1 〇之該第二表面2 1 2係 可更設有一被該銲罩層214覆蓋之訊號跡線216，其係 穿過該些該些電源/接地墊213A之間，但不是連接至該 些電源/接地墊213A’而是連接至該些接球塾之訊號 墊，以符合基板高密度線路佈局的要求。 鲁 再如第4圖所示，在本實施例中，該晶片220係設置 於該基板210之該第一表面211上。該晶片220係為形 成有積體電路（integrated circuit, 1C)之半導體元件，例 如：記憶體、邏輯元件或特殊應用積體電路（ASIC)，其 係由一晶圓(wafer)分割而出。在本實施例中，該晶片220 之一主動面221係可貼附至該基板210之該第一表面 2 11，該基板2 1 0係更具有一貫穿槽孔2丨5，以顯露該晶 癱 片220複數個位於該主動面221之銲墊222。該貫穿槽 孔215係可位於該基板21〇之中央位置，該些銲墊222 係分佈排列於該晶片220之該主動面22 1之中央，即中 央型銲墊（central pad)。該晶片220係可利用一非液態黏 b曰層，例如膠帶、b階黏勝（B-stage adhesive)或是晶片 貼附物質（Die Attach Material，DAM)，以黏接該晶片220 之該主動面221至該基板210之第一表面211。該基板 2 1 〇在該貫穿槽孔2 1 5之兩側可設置複數個接指，利用 跡線電性連接至該些接球墊213包含該些電源/接地墊 201205748 213A。此外，在該球栅陣列封裝構造2〇〇中，可另包含 ' 複數個穿過該貫穿槽孔215之電性連接元件250,以電 性連接該些銲墊222至該基板210。在本實施例中，該 些電性連接元件250係為打線形成之銲線（b〇nding wires)，可為金線或銅線，係連接該晶片22〇之該些銲 塾222與該基板2 1 0之接指。在另一變化實施例中，該 些電性連接元件250亦可為基板内部延伸出之引線 (lead)。該球柵陣列封裝構造2〇〇可另包含一封膠體 籲 26〇’其係形成於該基板210之該第一表面211，以密封 該晶片220。該封膠體260係為一環氧模封化合物（Ep〇xy Molding Compound，EMC)，以轉移成形方式（transfer molding)覆蓋於該基板210之該第一表面21卜在本實施 例中，該封膠體260係可更形成於該基板21〇之該貫穿 槽孔215與部分之該第二表面212，以密封該些電性連 接元件250，提供適當的封裝保護以防止電性短路與塵 埃污染。 請再參閱第4圖所示，該些銲球23〇係接合至該基板 210之該些接球墊213包含該些電源/接地墊213A上。 每一接球墊213(包含該些電源/接地墊213A)係接合有一 銲球230,用於與外界電性連通。特別的是，如第5圖 所示，該銲罩層214係具有一連通該些電源/接地墊213A 之溝槽214B，該溝槽214B内係填入銲料24〇，以連接 該些電源/接地墊213A上的銲球23〇，藉使該些電源/接 地墊213A為電壓平衡。更細部而言，如第5與7圖所 10 201205748 不，該溝槽214B係可為雷射切痕而不貫穿該銲罩層 214’即可利用雷射光裝置在該銲罩層214上形成該溝槽 214B。較佳地，該溝槽214B之深度係可不超過該些電 源/接地墊213A之銲球接合表面，而不會穿透位在該第 一表面212之訊號跡線216。細部而言，如第5圖所示， 該溝槽2 14B之底部與該訊號跡線2丨6之間係可形成有 一間隙厚度，而未直接相互接觸連通。該溝槽214b之 深度係可介於該銲罩層214之厚度30%〜80%，約在1〇〜40 微米。如銲罩層214之厚度不足，則可多次塗刷銲罩材 料在該基板210之該第二表面212上。而該溝槽214B 之寬度應不大於該些接球墊213(包含該些電源/接地墊 2 1 3 A)之半控。此外，在一較佳實施例中，如第4與6 圖所示’該些電源/接地墊213A之中心點距離係等於該 些接球墊2 1 3之平均間距’且該溝槽2 14B係可呈直條 狀而不彎曲，藉由將該溝槽214B形成在最短距離之該 些電源/接地墊213A上’能降低接地造成的浮遊容量附 著。 具體而言，該些銲球2 3 0係可利用植球、網版印刷 (screen printing)或鋼版印刷（stencil printing)等方法將 銲球先放置在或是以銲料塗施在該些接球墊21 3(包含該 些電源/接地墊213 A)上，其中以自動植球技術配合將助 焊式銲料預先印刷的製程較為可行，以使個別銲球能沾 附在該些接球墊213(包含該些電源/接地墊213 A)上以及 回焊前銲料能填入在該銲罩層214之溝槽214B内。之 11 201205748 後經過一高溫回焊（reflow)製程’以使該些銲球23〇永久 接合至該些接球墊213(包含該些電源/接地墊213A)上。 或者，該些接球墊213與該些電源/接地塾213A上可直 接塗佈助焊劑（flux)，另以塗劃方式使回焊前銲料填入該 溝槽2 1 4B内。 因此’本發明利用上述在銲罩層之溝槽内填入銲料並 連接電源/接地墊上的銲球之技術手段再結合對應的封 裝結構，能縮減該基板21 0内部的電源/接地金屬層，又 參 不會影響電性效能與對流散熱性，從而使該球柵陣列封 裝構造200更為薄化並能使該基板2丨〇成本更為降低。 在另一較佳實施例中，該銲料24〇與該些銲球23〇 係可為相同材質，可在同一回焊製程同時形成銲料並使 銲球固著於該些接球墊213(包含該些電源/接地墊2i3a) 上，以降低封裝製造成本並符合基板高密度佈線的要 求。例如，可沿用既有的銲球形成方法，先將助焊劑形 # 成在該些接球墊213(包含該些電源/接地墊213A)上與該 溝槽214B内，再塗佈在回焊前銲料或放置回焊前銲球。 在回焊製程時，將封裝構造置人在—加㈣統中，此時 銲料或銲球經過熔融而為液態並具有流動性，因該溝槽 214B内係亦塗佈有助焊劑，以利熔融的銲料導流入該溝 槽214B内。在回焊製程之後，在該溝槽21化内的鋒料 240便能連接至在該些電源/接地墊2i3A上之銲球 使該些電源/接地墊213A係經由該基板21〇外部之銲球 23 0與在該溝槽214B内之該銲料24〇電性連接故成為 12 201205748 在該基板210之外免用大銲塊的立體電性連接的結構， 不需要再使用基板内的電源/接地金屬層以及内部跡線。 請參閱第8圖所示，在本實施例中，該基板21〇係具 有單層線路結構’該基板2 1 0内部不具有電源/接地金屬 層，可省去電性佈局之複雜度與製程困擾，以達到訊號 處理尚速化’並降低基板之製作成本。但不受限地，在 其他之具體實施例中’該基板210係可為雙面導通的印 刷電路板。 ® 依據本發明之第二具體實施例’另一種球桃陣列封裝 構造說明於第9、10圖之截面示意圖。該球柵陣列封裝 構造3 00主要包含一基板210、一晶片220以及複數個 銲球230。其中與第一實施例相同的主要元件將以相同 符號標示，故可理解亦具有上述之相同作用，在此不再 予以贅述。. 如第9與10圖所示’在本實施例中，該些接球墊213 0 包含該些電源/接地墊213A係設於該基板210之該第一 表面211，而對應連接的跡線等信號佈線層亦可設於該 第一表面211。並且’該銲罩層214係具有對準於該些 接球墊2 1 3之開孔2 1 4A ’並且該溝槽3 1 4B係貫穿該鲜 罩層214，其中，所稱之「貫穿」係指該溝槽314B之形 成係可顯露出該基板210之該第二表面212(即顯露出基 板核心層），也就是說，該溝槽314B之底部即是連通至 該基板210之該第·一表面212。因不需要考慮溝槽深度 的深淺對跡線的影響’可便於利用機械加工、網印圖案 13 201205748The holes are used to reveal the ball pads, and the two ball pads of the two sides of the port include two or more power/ground ports. The η and 0 系 系 S are placed on the substrate again. The solder balls are bonded to the ball pads of the substrate. Wherein, the zinc cap layer has a trench connecting the power/ground pads, and the trench is filled with solder to connect the power/grounding such as a ball to enable the power/ground The pad is voltage balanced. The object of the present invention and the technical problems of k, t k can be further realized by the following technical measures. In the aforementioned ball grid array # J package structure, the solder and the solder balls can be the same material. In the above-described ball grid array structure, the ball pads may be disposed on the second surface, and the ridges are laser cuts without penetrating the solder mask layer. In the ball grid array package structure described above, the ball pads may be disposed on the surface of the ball, and the groove is further passed through the solder mask layer. In the ball grid array package structure described above, the center point distance of the power/ground pads is equal to the average spacing of the 4b-media pad, and the groove can be straight in the shape of 201205748. In the foregoing ball grid array package configuration, an active surface of the wafer can be attached to the first surface of the substrate. The substrate can have a through hole to expose a plurality of the active surface of the wafer. Solder pad. In the foregoing ball grid array package structure, a plurality of electrical connection elements passing through the through-holes may be further included to electrically connect the ball grid array package structure, and may further comprise a gel. Formed on the first surface of the substrate to seal the wafer. In the ball grid array package construction described above, the periphery of the power/ground pads can be covered by the solder mask layer. In the ball grid array package construction described above, the depth of the trench may not exceed the solder ball bonding surface of the power/ground pads. In the foregoing ball grid array package structure, the second surface of the substrate may further include a signal trace covered by the solder mask layer, and pass between the power/ground pads. But not connected to these power/ground pads. It can be seen from the above technical solution that the ball grid array package 4 of the present invention has the following advantages and effects: 1. The solder ball can be filled in the trench of the solder mask layer and connected to the solder ball on the power/ground pad. One of the technical means is to make the power/ground pad voltage balanced, so that the power/ground metal layer inside the substrate can be reduced without affecting the electrical performance and convection heat dissipation, thereby making the semiconductor package thinner and capable of thinning The substrate cost is further reduced. 1. The structure of the three-dimensional electrical connection of the large solder bumps outside the substrate can be obtained by filling the solder in the trench of the solder mask layer and connecting the solder ball on the power supply/grounding 201205748 作为 as a technical means. Solder can be formed at the same time in the same reflow process and the solder balls are fixed on the ball pad to reduce the manufacturing cost of the package and meet the requirements of high-density wiring of the substrate. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only 70 items and combinations related to the case are displayed. 'The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. 'Several size ratios and other related size ratios are exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. According to a first embodiment of the present month, a ball grid array package structure is illustrated in a cross-sectional view of FIGS. 4 and 5, a partial bottom view of the figure, and a partial bottom view of the seventh figure. The ball grid array structure & 2〇0 mainly includes a substrate 210, a crystal 4 220, and a plurality of solder balls 230. In the fourth embodiment of the present embodiment, the window type ball grid array package type is taken as an example 'but without limitation, The present invention can also be applied to other known ball grid array package structures or flip chip package structures. As shown in FIG. 4, the substrate 2 is used to provide electrical connection and serve as the ball grid array package structure. The wafer carrier of 200 is usually a printed circuit board, and may also be a ceramic carrier board or a circuit film. The substrate 21 has a first surface 211 and a second surface 212, and the first surface 201205748 211 is usually The wafer mounting surface ′ may be a surface covered by the encapsulant, and the second surface 212 is exposed outside the encapsulant and opposite to the outer surface of the first surface 211 as a mounting surface of the solder balls 23〇 The substrate 210 has a plurality of a ball pad 213 and a solder mask layer 214 formed on the second surface 212. The ball pads 213 may be formed on the second surface 212 or the first surface 211. As shown in Figures 4 and 5, in this embodiment In the example, the ball pads 213 are disposed on the second surface 211 of the substrate 21 to facilitate exposure. The solder mask layer 2 丨 4 has a plurality of openings 2 14 A to reveal the Ball pad 2丨3, the ball pad 2丨3 includes two or more power/ground pads 2丨3 A, which can be electrically connected to the chip 220 as a power supply voltage terminal or ground The reference pads 213 are arranged in a plurality of rows on the second surface 212 of the substrate 21, and may be, for example, a circular ball pad, and the power/ground pads 2 1 3 A The shape and size can be the same as the other signals 该 of the ball pads 2 13 , and the power/ground 塾 2 丨 3 a can be arranged at the corner, side or central position of the substrate 210. In an embodiment, as shown in FIG. 4, the power/ground pads 213A are arranged next to each other and adjacent to a central position of the substrate 210. The solder mask layer 2 1 The 4 series can be an insulating surface coating for protecting the circuit from solder contamination, which can be called green paint, or can be other surface protection layer with solder resistance. The solder mask layer 214 can provide surface insulation of the substrate 21 The protection can prevent the circuit and the core layer of the substrate from being exposed and contaminated. Specifically, as shown in FIG. 5, the diameter of the opening 214A of the solder mask layer 214 can be smaller than the ball pads including the power/grounding layer 2nA. Straight 201205748 diameter 'that is, the periphery of the power/ground pads 213A can be covered by the solder mask layer 214*, and has a better fixing force with the substrate 210, so the power/grounding 213A is fresh罩 Mask Mask Mask 。 (SMD). In this embodiment, the second surface 2 1 2 of the substrate 2 1 is further provided with a signal trace 216 covered by the solder mask layer 214 , which passes through the power/ground pads 213A. Instead of being connected to the power/ground pads 213A', they are connected to the signal pads of the balls to meet the requirements of the substrate high-density circuit layout. Further, as shown in FIG. 4, in the embodiment, the wafer 220 is disposed on the first surface 211 of the substrate 210. The wafer 220 is a semiconductor element formed with an integrated circuit (1C), such as a memory, a logic element, or an application specific integrated circuit (ASIC), which is divided by a wafer. In this embodiment, an active surface 221 of the wafer 220 can be attached to the first surface 211 of the substrate 210. The substrate 210 has a through hole 2丨5 to expose the crystal. The cymbal plate 220 has a plurality of pads 222 located on the active surface 221 . The through hole 215 is located at a central position of the substrate 21, and the pads 222 are distributed in the center of the active surface 22 of the wafer 220, that is, a central pad. The wafer 220 can utilize a non-liquid adhesive layer such as tape, B-stage adhesive or Die Attach Material (DAM) to bond the active of the wafer 220. The face 221 is to the first surface 211 of the substrate 210. The substrate 2 1 可 can be provided with a plurality of fingers on both sides of the through slot 2 1 5 , and the power pads/ground pads 201205748 213A are electrically connected to the ball pads 213 by using traces. In addition, in the ball grid array package structure 2, a plurality of electrical connection elements 250 passing through the through holes 215 may be further included to electrically connect the pads 222 to the substrate 210. In this embodiment, the electrical connection elements 250 are formed by wire bonding, which may be gold wires or copper wires, and the solder pads 222 and the substrate connected to the wafer 22 2 1 0 finger. In another variant embodiment, the electrical connection elements 250 can also be leads that extend inside the substrate. The ball grid array package structure 2 can further comprise a glue body 形成 其 其 formed on the first surface 211 of the substrate 210 to seal the wafer 220. The encapsulant 260 is an epoxy molding compound (EMC), and the first surface 21 of the substrate 210 is covered by transfer molding. In this embodiment, the seal is used. The colloid 260 can be formed on the through hole 215 of the substrate 21 and a portion of the second surface 212 to seal the electrical connection elements 250 to provide proper package protection to prevent electrical short circuits and dust pollution. Referring to FIG. 4 again, the ball pads 213 that are soldered to the substrate 210 include the power/ground pads 213A. Each of the ball pads 213 (including the power/ground pads 213A) is coupled to a solder ball 230 for electrical communication with the outside. In particular, as shown in FIG. 5, the solder mask layer 214 has a trench 214B connecting the power/ground pads 213A, and the trench 214B is filled with solder 24A to connect the power sources/ The solder balls 23 on the ground pad 213A are such that the power/ground pads 213A are voltage balanced. In more detail, as shown in FIGS. 5 and 7 201205748, the groove 214B may be a laser cut without passing through the solder mask layer 214', and may be formed on the solder mask layer 214 by using a laser light device. The trench 214B. Preferably, the depth of the trench 214B does not exceed the solder ball bonding surface of the power/ground pads 213A without penetrating the signal traces 216 located at the first surface 212. In detail, as shown in Fig. 5, a gap thickness may be formed between the bottom of the trench 2 14B and the signal trace 2 丨 6 without being in direct contact with each other. The depth of the trench 214b may be between 30% and 80% of the thickness of the solder mask layer 214, and is about 1 to 40 microns. If the thickness of the solder mask layer 214 is insufficient, the solder mask material may be applied to the second surface 212 of the substrate 210 a plurality of times. The width of the trench 214B should be no more than half of the ball pads 213 (including the power/ground pads 2 1 3 A). In addition, in a preferred embodiment, as shown in FIGS. 4 and 6, the center distance of the power/ground pads 213A is equal to the average pitch of the ball pads 2 1 3 and the trenches 2 14B It can be straight without bending, and by forming the trench 214B on the power/ground pads 213A at the shortest distance, the floating capacity adhesion caused by the ground can be reduced. Specifically, the solder balls 230 may be placed on the solder balls by soldering, screen printing, or stencil printing, or may be applied to the solder by soldering. The ball pad 21 3 (including the power/ground pads 213 A), wherein the process of pre-printing the solder solder with the automatic ball placement technology is more feasible, so that the individual solder balls can adhere to the ball pads. Solder can be filled into the trench 214B of the solder mask layer 214 on 213 (including the power/ground pads 213 A) and before reflow. After 201205748, a high temperature reflow process is performed to permanently bond the solder balls 23A to the ball pads 213 (including the power/ground pads 213A). Alternatively, the ball pads 213 and the power/grounding pads 213A may be directly coated with a flux, and the solder before reflowing may be filled into the trenches 2 1 4B by a coating method. Therefore, the present invention can reduce the power/ground metal layer inside the substrate 21 by using the above-mentioned technical means of filling the solder in the trench of the solder mask layer and connecting the solder ball on the power/ground pad to the corresponding package structure. In addition, the electrical performance and convection heat dissipation are not affected, so that the ball grid array package structure 200 is thinner and the substrate cost can be further reduced. In another preferred embodiment, the solder 24 can be made of the same material as the solder balls 23, and solder can be formed simultaneously in the same reflow process to fix the solder balls to the ball pads 213 (including These power/ground pads 2i3a) are used to reduce package manufacturing costs and meet the requirements of high-density wiring of substrates. For example, the existing solder ball forming method may be used, and the flux shape may be formed on the ball pad 213 (including the power/ground pads 213A) and the trench 214B, and then coated in the solder reflow. The solder is placed before the solder or placed before reflow. In the reflow process, the package structure is placed in the system, in which the solder or solder ball is molten and liquid and fluid, because the groove 214B is also coated with flux to facilitate The molten solder is conducted into the trench 214B. After the reflow process, the front material 240 in the trench 21 can be connected to the solder balls on the power/ground pads 2i3A so that the power/ground pads 213A are soldered through the substrate 21 The ball 23 0 is electrically connected to the solder 24 in the trench 214B, so that 12 201205748 is free from the three-dimensional electrical connection of the large solder bump outside the substrate 210, and the power supply in the substrate is not required to be used. Ground metal layer and internal traces. Referring to FIG. 8 , in the embodiment, the substrate 21 has a single-layer circuit structure. The substrate 2 10 has no power/ground metal layer inside, which can eliminate the complexity and process of the electrical layout. Troubled to achieve faster signal processing and reduce the cost of manufacturing substrates. However, without limitation, in other embodiments, the substrate 210 can be a two-sided conductive printed circuit board. ® In accordance with a second embodiment of the present invention, another spherical peach array package configuration is illustrated in cross-sections in Figures 9 and 10. The ball grid array package structure 300 mainly includes a substrate 210, a wafer 220, and a plurality of solder balls 230. The same elements as those in the first embodiment will be denoted by the same reference numerals, and it is understood that they have the same functions as described above and will not be described again. As shown in FIGS. 9 and 10, in the present embodiment, the ball pads 213 0 include the power/ground pads 213A disposed on the first surface 211 of the substrate 210, and the correspondingly connected traces. An equal signal wiring layer may also be disposed on the first surface 211. And the solder mask layer 214 has an opening 2 1 4A ' aligned with the ball pads 2 1 3 and the groove 3 1 4B extends through the fresh cover layer 214, wherein the so-called "through" Means that the formation of the trench 314B can expose the second surface 212 of the substrate 210 (ie, the substrate core layer is exposed), that is, the bottom of the trench 314B is connected to the substrate 210. A surface 212. Since it is not necessary to consider the influence of the depth of the groove depth on the traces, it is easy to use mechanical processing and screen printing patterns 13 201205748

或是曝光顯影方式形成。具體而言，該基板210係具有 竣數個貫孔317，其係貫穿該第一表面211至該第二表 面212，以顯露該些接球墊213包含該些電源/接地墊 213A。該些銲球23 0係設置在該些接球墊213，故該些 電源/接地墊2 1 3 A上亦設置有銲球，以供連接至外部之 印刷電路板。該晶片220之主動面221係背向該基板 210’並以該些電性連接元件250連接至該基板21〇之該 第一表面211，故該基板210之該第二表面212係可不 設有信號佈線層。詳細而言，該些貫孔3丨7係可利用雷 射或機械鑽孔形成。Or exposure development method is formed. Specifically, the substrate 210 has a plurality of through holes 317 extending through the first surface 211 to the second surface 212 to reveal that the ball pads 213 include the power/ground pads 213A. The solder balls 230 are disposed on the ball pads 213. Therefore, the power/ground pads 2 1 3 A are also provided with solder balls for connection to an external printed circuit board. The active surface 221 of the substrate 220 is opposite to the substrate 210 ′ and is connected to the first surface 211 of the substrate 21 by the electrical connecting elements 250. Therefore, the second surface 212 of the substrate 210 may not be provided. Signal wiring layer. In detail, the through holes 3丨7 can be formed by laser or mechanical drilling.

如第1 0圖所示，在本實施例中，由於該溝槽3丨4B 係可貫穿該銲罩層214’而使該溝槽314B具有較深之深 度亦不會有馨穿到訊號佈線層之情況發生。在銲球2 3 0 的回焊製程中，銲料240可更輕易地回流至該溝槽3ΐ4β 内’而連接該些電源/接地墊213A上的銲球230，藉此 使該些電源/接地墊213A為電壓平衡，並縮減基板内部 的電源/接地金屬層，又不會影響電性效能與對流散熱 性。 ’、、、 依據本發明之第三具體實施例，另一種球柵陣列封 構以說月於第11圖之截面示意圖。該球柵陣列封裝構 400主要包含—基板21〇、—晶片22〇以及複數個辉 23〇 ’可運用於封裝件堆叠結構（paekage孤 pop)，例如該球柵陣列封裝構造400可作為p〇p的底 封裝件。纟中與第-實施例相同的主要元件將以相同 14 201205748 號標示，故可理解亦具有上述之相同作用，在此不再予 • 以贅述。 在本實施例中，該晶片220係設置於該基板210之該 第二表面212上，該晶片220與該基板210之間的電性 連接方式係採用覆晶結合，可省略以往的打線電性連接 步驟。該些銲墊222係分佈排列於該晶片220之該主動 面221，每一銲墊222係設置有一凸塊470，該晶片220 係可利用該些凸塊470電性連接至該基板210。該些凸 鲁 塊470係可為銲料凸塊（s〇ider bump)，其尺寸可小於該 些銲球230。在其他具體實例中，該些凸塊470係可為 柱狀導電凸塊。另外，可以一底部填充膠（underfill material)4 80填充於該晶片220與該基板210之間隙，以 包覆該些凸塊470並保護該晶片220之該主動面221。 本發明雖不受局限地可運用到各式不同半導體封裝 類型，然該實施例之特徵仍在於，形成在該基板21〇之 φ 第二表面212之該銲罩層214係具有一連通該些電源/ 接地墊213A之溝槽214B，該溝槽214B内係填入銲料 以連接該些電源/接地墊213A上的銲球230，藉使 該些電源/接地墊213A為電壓平衡。以在基板表面上的 電性立體連接結構可省略基板内部的金屬層數，故該球 栅陣列封裝構造400具有較薄之封裝厚度，又不會影響 電性效能。 以上所述，僅是本發明的較佳實施例而已並非對本 發明作任㈣式上的㈣，耗本發明已讀佳實施例 15 201205748 揭露如上，然而並非 術者，/ 非用以限定本發明’任何熟悉本 佟故也 技術範圍内，所作的任何簡單 U改、專效性變化盥铬 早 内。 、^ ，句仍屬於本發明的技術範圍 【圖式簡單說明】 第1圖：―㈣知球柵陣列封裝構造之局部放大截面示 意圖。 第2圖 第3圖 第4圖 習知球栅陣列封裝構造之局部底面示意圖。 習知球栅陣列封裝構造之基板之局部放大截面 示意圖。 第 依據本發明之第-具體實施例的-種球栅陣列 封裝構造之截面示意圖。. 圖 第 據本發明之第一具體實施例的球柵陣列封裝 構造之局部放大截面示意圖。又 依據本發明之第一具體實施例的球柵陣列封裝 構造之局部底面示意圖。 圖.依據本發明之第一具體實施例的球栅陣列封裝 構造之局部底面立體圖。 、 第8圖.依據本發明之第一具體實施例的球柵陣列封裝 構造之基板之局部放大截面示意圖。 第9圖·依據本發明之第二具體實施例的-種球柵陣列 封裝構造之截面示意圖。 第1〇圖.依據本發明之第二具體實施例的-種球柵陣列 封裝構造之局部放大截面示意圖。 m 16 201205748 第11圖：依據本發明之第三具體實施例的一種球柵陣列 " 封裝構造之截面示意圖。 【主要元件符號說明】 110 基板 111 第一表面 112 第二表 113 接球墊 114 銲罩層 114Α 開孔 117 導通孔 118 接地層 119 電源層 130 銲球 160 封膠體 200 球柵陣列封裝構造 210 基板 211 第一表面 212 第二表 213 接球塾 213Α .電源/接地墊 214 銲罩層 214Α .開孔 214Β 溝槽 215 貫穿槽孔 216 訊號跡線 220 晶片 221 主動面 222 銲墊 230 銲球 240 銲料 250 電性連接元件 260 封膠體 300 球柵陣列封裝構造 3 14B ί溝槽 3 17 貫孔 4 0 0球柵陣列封裝構造 480底部填充膠 470 凸塊As shown in FIG. 10, in the present embodiment, since the trench 3丨4B can penetrate the solder mask layer 214', the trench 314B has a deeper depth and does not have a clear signal wiring. The situation of the layer occurs. In the solder reflow process of the solder ball 230, the solder 240 can be more easily reflowed into the trench 3ΐ4β' to connect the solder balls 230 on the power/ground pads 213A, thereby making the power/ground pads The 213A is voltage balanced and reduces the power/ground metal layer inside the substrate without affecting electrical performance and convection heat dissipation. In accordance with a third embodiment of the present invention, another ball grid array is illustrated in a cross-sectional view in Fig. 11. The ball grid array package 400 mainly includes a substrate 21 〇, a wafer 22 〇, and a plurality of 〇 23 〇 ' can be applied to a package stack structure (paekage orphan pop), for example, the ball grid array package structure 400 can be used as a p 〇 The bottom package of p. The main elements in the same manner as in the first embodiment will be denoted by the same reference numeral 14 201205748, so that it is understood that the same functions as described above are also omitted. In this embodiment, the wafer 220 is disposed on the second surface 212 of the substrate 210. The electrical connection between the wafer 220 and the substrate 210 is a flip chip connection, which can omit the conventional wire bonding property. Connection steps. The pads 222 are disposed on the active surface 221 of the wafer 220. Each of the pads 222 is provided with a bump 470. The wafer 220 can be electrically connected to the substrate 210 by using the bumps 470. The bumps 470 can be solder bumps that are smaller in size than the solder balls 230. In other embodiments, the bumps 470 can be columnar conductive bumps. In addition, an underfill material 480 may be filled in the gap between the wafer 220 and the substrate 210 to cover the bumps 470 and protect the active surface 221 of the wafer 220. The present invention is not limited to the various semiconductor package types, but the embodiment is further characterized in that the solder mask layer 214 formed on the second surface 212 of the substrate 21 has a connection therebetween. The trench 214B of the power/ground pad 213A is filled with solder to connect the solder balls 230 on the power/ground pads 213A, such that the power/ground pads 213A are voltage balanced. The electrical three-dimensional connection structure on the surface of the substrate can omit the number of metal layers inside the substrate, so the ball grid array package structure 400 has a thin package thickness without affecting electrical performance. The above is only the preferred embodiment of the present invention and is not the fourth (4) of the present invention. The preferred embodiment 15 201205748 is disclosed above, but it is not an operator, and is not intended to limit the present invention. 'Anything that is familiar with this and is also within the technical scope, any simple U change, special effect change 盥 chrome early. The sentence is still within the technical scope of the present invention. [Simplified description of the drawings] Fig. 1 is a partial enlarged cross-sectional view showing the structure of the ball grid array package. Fig. 2 Fig. 3 Fig. 4 Schematic diagram of a partial bottom surface of a conventional ball grid array package structure. A schematic partial enlarged cross-sectional view of a substrate of a conventional ball grid array package structure. A schematic cross-sectional view of a ball grid array package structure in accordance with a first embodiment of the present invention. Figure 2 is a partially enlarged cross-sectional view showing the configuration of a ball grid array package in accordance with a first embodiment of the present invention. Further, a partial bottom plan view of a ball grid array package structure in accordance with a first embodiment of the present invention. Fig. A partial bottom perspective view of a ball grid array package structure in accordance with a first embodiment of the present invention. Figure 8 is a partially enlarged cross-sectional view showing a substrate of a ball grid array package structure according to a first embodiment of the present invention. Figure 9 is a cross-sectional view showing a package structure of a ball grid array according to a second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partially enlarged cross-sectional view showing a package structure of a ball grid array according to a second embodiment of the present invention. m 16 201205748 FIG. 11 is a cross-sectional view showing a ball grid array " package structure according to a third embodiment of the present invention. [Main component symbol description] 110 substrate 111 first surface 112 second table 113 ball pad 114 solder mask layer 114 Α opening 117 via hole 118 ground layer 119 power layer 130 solder ball 160 encapsulant 200 ball grid array package structure 210 substrate 211 first surface 212 second table 213 ball 塾 213 Α power/ground pad 214 solder mask layer 214 Α opening 214 沟槽 trench 215 through slot 216 signal trace 220 wafer 221 active surface 222 pad 230 solder ball 240 solder 250 Electrical connection component 260 Sealant 300 Ball grid array package construction 3 14B 沟槽 Trench 3 17 Through hole 4 0 0 Ball grid array package construction 480 Underfill 470 Bump

Claims (1)

201205748 七、申請專利範圍： 1、一種球柵陣列封裝構造，包含： 基板’係具有一第一表面與一第二表面，該基板 更具有複數個接球墊以及形成於該第二表面之一 鲜罩層’該鲜罩層係具有複數個開孔以顯露出該 二接球塾’該些接球墊係包含兩個或兩個以上之 電源/接地整；201205748 VII. Patent application scope: 1. A ball grid array package structure, comprising: a substrate having a first surface and a second surface, the substrate further having a plurality of ball pads and one of the second surfaces a fresh cover layer 'the fresh cover layer has a plurality of openings to reveal the two balls 塾'. The ball pads comprise two or more power/groundings; 曰日片’係設置於該基板；以及 複數個銲球，係接合至該基板之該些接球墊； 其中，該銲罩層係具有一連通該些電源/接地墊之溝 槽，該溝槽内係填入銲料，以連接該些電源/接地 2、a plurality of solder balls are attached to the ball pads of the substrate; wherein the solder mask layer has a trench connecting the power/ground pads, the trench The solder is filled in the slot to connect the power/ground 2 4、 墊上的銲球’藉使該些 根據申請專利範圍第1項 中該銲料與該些銲球為相 根據申請專利範圍第1項 中該些接球墊係設於該第 射切痕而不貫穿該銲罩層 根據申請專利範圍第1項 中該些接球墊係設於該第 該銲罩層。 電源/接地塾為電壓平衡。 之球栅陣列封裝構造，其 同材質。 之球栅陣列封裝構造，其 二表面，且該溝槽係為雷 P 之球柵陣列封裝構造，其 一表面，且該溝槽係貫穿 、根據申請專利範圍第1項之球柵陣列封裝構造，其 中該些電源/接地墊之中心點距離等於該些接球墊 之平均間距，且該溝槽係呈直條狀。 6、根據申請專利範圍第1項之球柵陣列封裝構造，其 m 18 201205748 中該晶片之—士&品在日卜 主動面係貼附至該基板之該第一表 面該基板係更且有^一嘗定Μ 尺具有貧穿槽孔，以顯露該晶片複 數個位於該主動面之銲墊。 7 根據申請專利範圈第6項夕1+、i 钝圍笫項之球柵陣列封裝構造，另 包含複數個穿過穿擔 牙過該貫穿糟孔之電性連接元件，以電 性連接該些銲墊至該基板。 根據申請專利範圍第1、 靶園弟 2、3、4、5、ό或7項之4, the solder ball on the pad 'But according to the solder in the first paragraph of the patent application and the solder ball according to the scope of the patent application, the ball pad is set in the first shot The welding cap layer is not penetrated. According to the first aspect of the patent application, the ball pad is attached to the first welding cap layer. The power/ground 塾 is voltage balanced. The ball grid array package structure is the same material. a ball grid array package structure having two surfaces, and the trench is a ball grid array package structure of a ray P, one surface thereof, and the trench is penetrated, and the ball grid array package structure according to claim 1 The central point distance of the power/ground pads is equal to the average spacing of the ball pads, and the grooves are straight. 6. The ball grid array package structure according to claim 1, wherein in the m 18 201205748, the substrate of the wafer is attached to the first surface of the substrate, and the substrate is further attached to the first surface of the substrate. There is a hole that has a poor penetration slot to reveal a plurality of pads on the active surface of the wafer. 7 The ball grid array package structure according to the sixth embodiment of the patent application section 1+, i blunt enclosure, further comprising a plurality of electrical connection elements passing through the through-holes to electrically connect the electrical connection elements Some pads are applied to the substrate. According to the scope of the patent application, the target park brother 2, 3, 4, 5, ό or 7 球柵陣列封裝構造，另包 « ^ ^ ^ 封膠體’係形成於該 9 土 該第—表面，以密封該晶片。 根據_請專利範圍第.卜2、3、4、5 球栅陣列封裝構造，其中該此電^ /項之 被兮經s a 二電源/接地墊之周邊係 被該銲罩層所覆蓋。 1〇、根據申請專利範圍第1、2、3、4、5、6或 球柵陣列封裝構造， / 項之 ^ ^ 丹T该溝槽之深度係不趙讽分 些電源/接地墊之銲球接合表面。 °" "、根據申請專利範圍第1〇項之球柵 ^該基板之該第二表面係更設有-被該辉=覆 之訊號跡線，係穿過該些該些電源/接地墊 仁不連接至該些電源/接地墊。 1 【S] 19The ball grid array package structure, the other package « ^ ^ ^ sealant body" is formed on the first surface of the soil to seal the wafer. According to the patent scope of the second, third, fourth, and fifth ball grid array package structure, the periphery of the electric/ground layer is covered by the solder mask layer. 1〇, according to the patent application scope 1, 2, 3, 4, 5, 6 or ball grid array package structure, / ^ ^ 丹 T the depth of the groove is not sarcasm to some power / ground pad welding The ball engages the surface. °""<", according to the patent application scope of the first aspect of the ball grid ^ the second surface of the substrate is further provided with - the signal trace of the glow, through the power / ground pad Ren is not connected to these power/ground pads. 1 [S] 19
TW099124790A 2010-07-27 2010-07-27 Ball grid array package TWI476881B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720013A (en) * 2014-12-02 2016-06-29 力成科技股份有限公司 Stereoscopic Stacking Method for Semiconductor Packages Preventing Intermediary Conductor Bridging

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7214566B1 (en) * 2000-06-16 2007-05-08 Micron Technology, Inc. Semiconductor device package and method
KR20020065045A (en) * 2001-02-05 2002-08-13 삼성전자 주식회사 Semiconductor chip package comprising enhanced pads

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720013A (en) * 2014-12-02 2016-06-29 力成科技股份有限公司 Stereoscopic Stacking Method for Semiconductor Packages Preventing Intermediary Conductor Bridging

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