201143079 六、發明說明： 【發明所屬之技術領域】 本發明，係有關於記憶元件及記億方法。 【先前技術】 現今，使用有發揮穿隧磁阻（Tunneling Magneto-Resistive ) 效 果之磁 性多層 膜的記 憶元件 （ 穿隧磁 阻元件 )，係被應用在MRAM等之非揮發性記憶體等之中。 穿隧磁阻元件之多層膜，係具備有2層的磁性層、和 被挾持在2層的磁性層間之絕緣層。絕緣層之膜厚係爲薄 ，若是爲了使其作爲記憶元件來動作，而流動與膜面垂直 之感測電流，則藉由穿隧效果，會通過絕緣層而流動有穿 隧電流。 當2層的磁性層之磁化方向互爲逆方向（反平行）時 ，電阻値係爲大，而當相同方向時（平行），電阻値係爲 小。藉由使大小之電阻値與「〇」「1」相對應，係能夠實 現非揮發性地將2値的資訊作記憶之記憶元件。 作爲對於穿隧磁阻元件而將資料作寫入之方法，例如 ，在專利文獻1中，係揭示有：藉由在磁性層之膜面上而 平行地流動電流，來使身爲在磁性層內之互爲逆方向的磁 區之邊界的磁壁作移動，以進行寫入之方法。 在先前技術所採用之穿隧磁阻元件的形狀中，基本上 ，由於係僅能夠得到2層的磁性層之磁化方向的關係爲平 行或者是反平行之狀態，因此，電阻係爲高電阻和低電阻 -5- 201143079 之2種類，而只能夠藉由使大小之電阻値和「0」「1」相 對應，來進行由2値所致之資訊的記憶。 不論是在現今之正進行硏究開發的非揮發性記憶體之 MR AM中，或者是在已被量產並且細微化係更加地進展的 DRAM中，成爲資訊之基本構成的位元，亦係將「0」 Μ 」之2個的狀態作爲基礎。因此，不論其爲揮發性或者是 非揮發性，在容量之觀點上來說，均並不存在有優越性。 爲了增加記憶容量，除了將記憶元件之個數（密度） 增加以外，係並沒有其他的答案，因此，除了藉由細微化 來追求進步以外，係並沒有其他的方法，但是，在記億元 件的細微化中，也是有所極限。故而，係需要一種藉由細 微化以外之方法來將記錄密度提升的手段。 〔先前技術文獻〕 〔專利文獻〕 〔專利文獻1〕國際公開第2007/ 020823號 【發明內容】 〔發明所欲解決之課題〕 本發明，係爲了解決上述先前技術之問題而創作者， 其目的，係在於提供一種使用穿隧磁阻效果而記憶3値或 者是4値之資訊的記憶元件以及記憶方法。 〔用以解決課題之手段〕 爲了解決上述問題，本發明，係爲一種3値記憶元件 -6 - 201143079 ，係具備有：帶狀之自由磁性層；和密著於前述自由磁性 層之表面上的絕緣層；和密著於前述絕緣層之表面上’並 相互分離地被作配置’且被磁化爲相同方向之第〗、第2固 定層部，若是將在前述絕緣層中，表面與前述第1、第2固 定層部作了密著的部分之從前述表面起直到背面爲止的部 分，稱爲第1、第2絕緣層部，並將在前述自由磁性層中’ 表面與前述第1、第2絕緣層部作了密著的部分之從前述表 面起直到背面爲止的部分，稱爲第1、第2自由層部’則係 藉由前述第1自由層部和前述第1絕緣層部以及前述第1固 定層部，來形成通過前述第1絕緣層部而流動有穿隧電流 之第1元件，並藉由前述第2自由層部和前述第2絕緣層部 以及前述第2固定層部，來形成通過前述第2絕緣層部而流 動有穿隧電流之第2元件，若是將前述第1、第2固定層部 之磁化方向設爲固定方向，則前述第1、第2元件之流動有 前述穿隧電流時的電阻値，係設爲：當前述第1、第2自由 層部之磁化方向爲與前述固定方向同方向時而會變小’且 當爲反方向時而變大，將前述第1、第2元件之電阻値的雙 方均爲大時，作爲第1狀態，並將前述第1、第2元件之電 阻値的其中一方爲大而另外一方爲小時，作爲第2狀態， 且將前述第1、第2元件之電阻値的雙方均爲小時，作爲第 3狀態，而區別之，該3値記憶元件，其特徵爲：若是將前 述自由磁性層之前述第1、第2自由層部之間的部分設爲中 間部，並將身爲前述自由磁性層中之前述中間部與前述第 1、第2自由層部間的外部且與前述第1、第2自由層部作了 201143079 接觸的部分設爲第1、第2端部，則在前述自由磁性層內’ 係被形成有身爲磁化方向互爲相異之區域的邊界之磁壁’ 前述磁壁，係經由在前述自由磁性層處而於帶狀之長邊方 向上流動的寫入電流而被作移動，並成爲位置在前述第1 端部和前述第2端部以及前述中間部之其中一處。 本發明，係爲一種3値記億元件，其中，前述第1、第 2固定層部之磁化方向、和前述第1、第2自由層部之磁化 方向，係均爲與膜厚方向相垂直之方向。 本發明，係爲一種3値記憶元件，其中，前述第1、第 2固定層部之磁化方向、和前述第1、第2自由層部之磁化 方向，係均爲與膜厚方向相平行之方向。 本發明，係爲一種3値記憶元件，其中，在前述第1、 第2端部處，係分別被電性連接有第1、第2電極，前述磁 壁，係被配置在前述第1、第2電極之間的部分，前述寫入 電流，係構成爲在前述第1、第2電極間流動。 本發明，係爲一種記憶元件，係爲3値之記憶元件， 並具備有：帶狀之下部自由磁性層；和密著於前述下部自 由磁性層之表面的一部份上之下部絕緣層：和背面之一部 份爲密著於前述下部絕緣層之表面上的帶狀之上部自由層 ;和密著於前述上部自由層之表面的一部份處上之上部絕 緣層；和密著於前述上部絕緣層之表面，並被磁化爲一方 向之固定層，若是將在前述上部絕緣層中，前述表面與前 述固定層部作了密著的部分之從前述表面起直到背面爲止 的部分，稱爲上部絕緣層部，並將在前述上部自由磁性層 -8 - 201143079 中，前述表面與前述上部絕緣層部作了密著的部分之從前 述表面起直到前述背面爲止的部分，稱爲第1上部自由胃 部，將前述背面與前述下部絕緣層部作了密著的部分之從 前述背面起直到前述表面爲止的部分，稱爲第2上部自由 層部，且將前述下部自由磁性層中，前述表面與前述下部 絕緣層作了密著的部分之從前述表面起直到背面爲止的部 分，稱爲下部自由層部，則係藉由前述固定層和前述上部 絕緣層部以及前述第1上部自由層部，來形成通過前述上 部絕緣層部而流動有穿隧電流之第1元件，並藉由前述第2 上部自由層部和前述下部絕緣層以及前述下部自由層部， 來形成通過前述下部絕緣層而流動有穿隧電流之第2元件 ，前述第1元件之流動有前述穿隧電流時的電阻値，係設 爲：當前述第1上部自由層部之磁化方向爲與前述固定層 之磁化方向同方向時而會變小，且當爲反方向時而變大， 前述第2元件之流動有前述穿隧電流時的電阻値，係設爲 :當前述第2上部自由層部之磁化方向爲與前述下部自由 層部之磁化方向同方向時而會變小，且當爲反方向時而變 大，將前述第1、第2元件之電阻値的雙方均爲大時，作爲 高電阻狀態，並將前述第1、第2元件之電阻値的其中一方 爲大而另外一方爲小時，作爲中間電阻狀態，且將前述第 1、第2元件之電阻値的雙方均爲小時，作爲低電阻狀態， 而區別之，該3値記憶元件，其特徵爲：若是將前述上部 自由磁性層之身爲前述第1上部自由層部的外部且爲前述 第2上部自由層部之外部並且被與前述上部自由磁性層之 201143079 帶狀的長邊方向之互爲相異的端部作了連接的部分，設爲 第1、第2上方端部，而將身爲前述下部自由磁性層中之前 述下部自由層部的外部並且與前述下部自由層之帶狀的長 邊方向之互爲相異的端部作了連接的部分設爲第1、第2下 方端部，則在前述上部自由磁性層內，係被形成有身爲磁 化方向互爲相異之區域的邊界之上方磁壁，並且在前述下 部自由磁性層內，係被形成有身爲磁化方向互爲相異之區 域的邊界之下部磁壁，前述上部磁壁，係經由在前述上部 自由磁性層處而於前述長邊方向上流動的上部寫入電流而 被作移動，並成爲位置在前述第1上方端部和前述第2上方 端部之其中一處，前述下部磁壁，係經由在前述下部自由 磁性層處而於前述長邊方向上流動的下部寫入電流而被作 移動，並成爲位置在前述第1下方端部和前述第2下方端部 之其中一處，而記憶有3値。 本發明，係爲一種記憶元件，其中，除了前述高電阻 狀態、前述低電阻狀態之外，亦將前述第1元件之電阻値 爲大且前述第2元件之電阻値爲小時，設爲第1中間電阻狀 態，且將前述第1元件之電阻値爲小且前述第2元件之電阻 値爲大時，設爲第2中間電阻狀態，藉由此來作區別，並 記憶4値。 本發明，係爲一種記憶元件，其中，前述固定層之磁 化方向和前述第1、第2上部自由層部之磁化方向以及前述 下部自由層部之磁化方向’係均爲與膜厚方向相垂直之方 向。 -10- 201143079 本發明，係爲一種記憶元件，其中，前述固定層之磁 化方向和前述第1、第2上部自由層部之磁化方向以及前述 下部自由層部之磁化方向，係均爲與膜厚方向相平行之方 向。 本發明，係爲一種記憶元件，其中，在前述第1、第2 上方端部處，係分別被電性連接有第1、第2上部寫入電極 ’前述上部磁壁，係被配置在前述第1、第2上部寫入電極 之間的部分處，前述上部寫入電流，係構成爲在前述第1 、第2上部寫入電極間流動，在前述第〗、第2下方端部處 ’係分別被電性連接有第1、第2下部寫入電極，前述下部 磁壁’係被配置在前述第1、第2下部寫入電極之間的部分 處’前述下部寫入電流，係構成爲在前述第1、第2下部寫 入電極間流動。 本發明，係爲一種記憶方法，係將2個元件作並聯連 接’該元件，係具備有：自由層部；和密著於前述自由層 部之表面上的絕緣層；和密著於前述絕緣層之表面上，並 被磁化爲一方向之固定層，藉由前述自由層部和前述絕緣 層以及前述固定層，來形成通過前述絕緣層而流動穿隧電 流之元件，在流動有前述穿隧電流時之電阻値，係設爲： 當前述自由層部之磁化方向爲與前述固定層之磁化方向同 方向時而會變小，且當爲反方向時而會變大，該記憶方法 ’係對於2個的前述元件之電阻値的雙方均爲大時、和其 中一方之前述元件之電阻値爲大而另外一方之前述元件之 電阻値爲小時、以及2個的前述元件之電阻値的雙方均爲 -11 - 201143079 小時，此3種的電阻値作判別，並記憶3値，該記億方法， 其特徵爲：將2個的前述元件之前述自由層部，形成在相 同之帶狀的自由磁性層內之於長邊方向上相分離了的互爲 相異之位置處，若是將前述自由磁性層中之2個的前述自 由層部之間的部分設爲中間部，並將前述中間部與2個的 前述自由層部的外側設爲第1、第2端部，則在前述自由磁 性層內，形成身爲磁化方向互爲相異之區域的邊界之磁壁 ，並使前述磁壁在前述自由磁性層處而於前述長邊方向上 移動，且使其位置在前述第1端部和前述第2端部以及前述 中間部之其中一處。 本發明，係爲一種記憶方法，其中，在前述第1、第2 端部處，係分別被電性連接有第1、第2電極，使前述磁壁 ，位置在前述第1、第2電極之間的部分，在前述第1、第2 電極間，流動寫入電流，而使前述磁壁移動。 本發明，係爲一種記憶方法，係將2個元件作串聯連 接，該元件，係具備有：自由層部；和密著於前述自由層 部之表面上的絕緣層：和密著於前述絕緣層之表面上，並 被磁化爲一方向之固定層，藉由前述自由層部和前述絕緣 層以及前述固定層，來形成通過前述絕緣層而流動穿隧電 流之元件，在流動有前述穿隧電流時之電阻値，係設爲： 當前述自由層部之磁化方向爲與前述固定層之磁化方向同 方向時而會變小，且當爲反方向時而會變大，該記憶方法 ，係對於2個的前述元件之電阻値的雙方均爲大時、和其 中一方之前述元件之電阻値爲大而另外一方之前述元件之 -12- 201143079 電阻値爲小時、以及2個的前述元件之電阻値的雙方均爲 小時，此3種的電阻値作判別，並記億3値’該記憶方法， 其特徵爲：將其中一方之前述元件的前述自由層部，形成 在帶狀之下部自由磁性層內，並將該其中一方之前述元件 的前述固定層和另外一方之前述元件的前述自由層部’形 成在相同的帶狀之上部自由磁性層內，若是將前述上部自 由磁性層中之身爲該其中一方之前述元件的前述固定層之 外側且爲該另外一方之前述元件的前述自由層部之外側’ 設爲第1、第2上方端部，而將前述下部自由磁性層中之該 其中一方之前述元件的前述自由層部之外側’設爲第i、 第2下方端部，則係在前述上部自由磁性層內，形成身爲 磁化方向互爲相異之區域的邊界之上部磁壁’並且在前述 下部自由磁性層內，形成下部磁壁，而使前述上部磁壁在 前述上部自由磁性層處而於前述長邊方向上移動，並使其 成爲位置在前述第1上方端部和前述第2上方端部之其中一 處，且使前述下部磁壁在前述下部自由磁性層處而於前述 長邊方向上移動，並使其成爲位置在前述第1下方端部和 前述第2下方端部之其中一處。 本發明，係爲一種記憶方法，其中，係對於2個的前 述元件之電阻値的雙方均爲大時、和其中一方之前述元件 之電阻値爲大而另外一方之前述元件之電阻値爲小時、和 該其中一方之前述元件之電阻値爲小而該另外一方之前述 元件之電阻値爲大時、以及2個的前述元件之電阻値的雙 方均爲小時，此4種的電阻値作判別，並記憶4値。 -13- 201143079 本發明，係爲一種記憶方法，其中，在前述第1、第2 上方端部處’係分別被電性連接有第1、第2上部寫入電極 ，使前述上部磁壁位置在前述第1、第2上部寫入電極之間 的部分處’並在前述第1、第2上部寫入電極間流動寫入電 流，而使前述上部磁壁移動，在前述第1、第2下方端部處 ，係分別被電性連接有第1、第2下部寫入電極，使前述下 部磁壁位置在前述第1、第2下部寫入電極之間的部分處， 並在前述第1、第2下部寫入電極間流動寫入電流，而使前 述下部磁壁移動。 〔發明之效果〕 由於係能夠藉由1個元件來記憶3値或者是4値之資訊 ，因此，並不需藉由細微化，便能夠使記億元件之記錄密 度提升。 【實施方式】 對於身爲本發明之多値記憶元件的第1例之3値記憶元 件的構造作說明。 圖1，係爲本發明之3値記億元件1的平面圖，圖2係對 於同A-A線切斷剖面圖作展示。在圖1中，係將層間絕緣膜 2a、2b省略° 3値記憶元件1，係具備有平面形狀爲帶狀之自由磁性 層13。參考圖1，於此，自由磁性層13之平面形狀，係被 形成爲從長方形而將一邊作了除去後的形狀，並具備有： -14- 201143079 具備寬幅和較寬幅而更長之長邊方向的帶狀之自由磁性層 中央部13a、和以被連接在自由磁性層中央部13a之長邊方 向的互爲相異之端部處並且在與自由磁性層中央部13 a之 寬幅方向相平行的同一方向上而延伸的方式所形成之帶狀 的第1、第2自由磁性層端部13b、13c。 自由磁性層13內之磁化方向（磁矩之方向），係如同 後述一般，成爲朝向與帶狀之長邊方向相平行的方向。圖 1、圖2之箭頭，係代表磁化方向。 參考圖2，在自由磁性層中央部13a之表面上，係密著 配置有絕緣層12，在絕緣層12表面上，係密著有第1、第2 固定層部11!、112，並在自由磁性層中央部13a之長邊方向 上而相互分離地被作配置。 第1、第2固定層部11,、112之磁化方向（磁極之朝向 )，係被朝向相同方向，並被固定。以下，將第1、第2固 定層部11!、112之磁化方向，稱爲固定方向。於此，固定 方向，係與自由磁性層中央部13a之長邊方向相平行，圖2 之符號Fqi，係代表固定方向。 於此，如圖1、圖2中所示一般，第1、第2固定層11, 、112係分別密著在相異之絕緣層12的表面上，但是，本 發明，係並不被限定於此，亦可使其密著在1枚之絕緣層 12的表面上之互爲相異的位置處。 在絕緣層1 2中，將與第1、第2固定層部1 1 ^、1丨2相密 著了的部分之從表面起直到背面爲止的部分，稱作第1、 第2絕緣層部1 2 !、1 2 2，並將自由磁性層1 3中之與第1、第2 -15- 201143079 絕緣層部12,、122相密著了的部分之從表面起直到背面爲 止的部分，稱作第1、第2自由層部13,、132。 如同上述一般，由於第1、第2固定層部lh、112係相 互分離，因此，第1、第2自由層部13,、132亦係相互分離 地作配置。 圖2之符號FM、F21，係代表第1、第2自由層部13】、 132之磁化方向。如同後述一般，第1、第2自由層部13!、 1 3 2之磁化方向F , ,、F2 i，係被構成爲能夠經由在自由磁性 層13處而於帶狀之長邊方向上流動的寫入電流來使其反轉 〇 藉由第1自由層部13!和第1絕緣層部12!以及第1固定層 部11!，而形成第1元件1〇!，藉由第2自由層部132和第2絕 緣層部122以及第2固定層部112，而形成第2元件102。 在第1、第2固定層部1 1 i、1 12上，係分別被電性連接 有第1、第2上部電極15,、152，在第1、第2自由磁性層端 部13b、13c處，係分別被電性連接有第1、第2下部電極（ 第1、第2電極）1 4a、1 4b。 若是在第1、第2上部電極15!、152和第1、第2下部電 極1 4 a、1 4b之間施加電壓，則由於第1、第2絕緣層部1 2 , 、122之膜厚係爲薄，因此，藉由穿隧效果，在第1、第2 元件10,、1〇2內，係通過第1、第2絕緣層部12!、122而流 動有穿隧電流。穿隧電流，由於其電流量係較寫入電流更 小，因此，就算是流動有穿隧電流，後述之磁壁1 9亦成爲 並不會移動。 -16- 201143079 第1、第2元件1 〇,、1 〇2之流動有穿隧電流時的電阻値 ’係藉由穿隧磁阻效果，而當第1、第2自由層部i3l、132 之磁化方向Fu、F21爲與第1、第2固定層部11,、112之磁 化方向（固定方向）F(h相同方向時而變小，並當反方向 時而變大。 在3値憶兀件1內，係被構成有將第1、第2元件10! 、1〇2作了並聯連接之並聯連接電路，並如同後述一般， 將第1'第2元件lOi、1〇2之電阻値雙方均爲大時作爲第1狀 態’並將第1、第2元件10,、1〇2之其中一方的電阻値爲大 而另外一方爲小時作爲第2狀態，且將第1、第2元件1 0 ,、 1 〇2之電阻値雙方均爲小時作爲第3狀態，以作區分。 接者’針對桌1、第2自由層部13丨、13〗之磁化方向F!i 、F21的變化作說明。 首先’作爲磁化方向之初期化，如圖3 ( a )或者是圖 3(c)中所示一般’從與自由磁性層13之膜面相平行並且 與第1、第2自由磁性層端部13b、13c之長邊方向相平行的 方向來施加外部磁場Η，而將第1、第2自由磁性層端部1 3 b 、13c磁化爲與外部磁場Η相同之方向。符號Fb、Fc，係分 別代表第1、第2自由磁性層端部1 3 b、1 3 c之磁化方向》 接著，在將外部磁場Η除去後，於此，若是從第2下部 電極14b來朝向第1下部電極14a來流動初期化電流1()，則藉 由從傳導電子所對於磁矩之自旋轉移（Spin-Transfer)效 果（旋轉角動量之授受）’當如同圖3(c)所示一般，第 1自由磁性層端部13b之磁化方向Fb係與初期化電流1〇之方 -17- 201143079 向.相同的情況時’如同圖3(d)所示一般，自由磁性層中 央部1 3 a之磁化方向F a亦係朝向與初期化電流〗Q之方向相同 的方向，而’當如同圖3(a)所示一般，第1自由磁性層 端部13b之磁化方向Fb係與初期化電流Iq之方向相反的情 況時，如同圖3(b)所示一般，自由磁性層中央部13a之 磁化方向Fa亦係朝向與初期化電流1〇之方向相反的方向， 因此，在自由磁性層中央部13a和第2自由磁性層端部13c 之間的邊界處，係被形成有身爲磁化方向互爲相異之區域 的邊界之磁壁19。換言之，磁壁19，係位置在磁化方向爲 與在自由磁性層13之長邊方向上流動的初期化電流之方向 相同方向的順部分、和相異方向之逆部分，此兩者之間。 亦可在將外部磁場Η除去後，從第1下部電極14a來朝 向第2下部電極1 4b而流動初期化電流1〇，並在自由磁性層 中央部13a和第1自由磁性層端部13b之間的邊界處形成磁 壁1 9。 圖4(a)〜（c)，係對相對於固定方向FQ1之第1、第 2自由層部13,、132之磁化方向Fu、F21的變化作展示。 將第1、第2元件1 0 ,、1 〇2之電導的最小値分別設爲C 1 、C2，並將最大値分別設爲C1+AC1' C2+z\C2(電導値 係爲電阻値之倒數）。 於此，首先，如圖4 ( a )中所示一般，磁壁1 9，係位 置在第2下部電極14b和第2自由層部132之間的區域（以下 ，稱爲第2端部18c)處，第1、第2自由層部13!、132之磁 化方向Fu、F21，係雙方均爲與固定方向F(n相同之方向， • 18 - 201143079 3値記憶元件1之電導，係成爲以C1+C2+AC1 + AC2來表示 的最大値。 接著，如圖4(b)中所示一般，若是從第1下部電極 14a來朝向第2下部電極14b而流動預先所制訂之脈衝寬幅 的寫入電流Iw，則藉由從傳導電子所對於磁矩之自旋轉移 效果，磁壁19係從第2端部18c起而移動至第1自由層部13, 和第2自由層部1 3 2之間的區域（以下，稱作中間部1 8b ) 處，亦即是，只有第2自由層部132之磁化方向F21會反轉， 3値記憶元件1之電導値，係成爲C1+C2+AC1。 接著，如圖4(c)中所示一般，若是從第1下部電極 1 4 a來朝向第2下部電極1 4 b而流動預先所制訂之脈衝寬幅 的寫入電流Iw，則磁壁1 9係從中間部1 8b起而移動至第1自 由層部13,和第1下部電極l4a之間的區域（以下，稱作第1 端部18a)處，亦即是，第1自由層部13i之磁化方向Fll亦 會反轉，3値記憶元件1之電導値’係成爲最小値C 1 + C 2。 接著，若是從第2下部電極l4b來朝向第1下部電極14a 而流動預先所制訂之脈衝寬幅的寫入電流Iw，則磁壁1 9係 從第1端部18 a起而移動至第2端部18 c處’第1、第2自由層 部1 3 !、1 3 2之磁化方向F , ,、F2 ,之雙方係再度反轉，並如 同圖4(a)中所示一般地而再度回到電導値爲最大値 C1+C2+AC1 + AC2 之狀態。 如此這般，3値記憶元件1之電導’係成爲最大値 C 1 +C2+ Δ C 1 + Δ C2 ' 中間値C1+C2+/\C1、最小値C1+C2 之 3種的電導値。 -19- 201143079 在最大値和中間値之間設置第1基準値，並在中間値 與最小値之間設置第2基準値，而藉由對於最大値、最小 値、中間値之3種的電導値作判別，來得到3値之記億元件 1 ° 在上述說明中，雖係藉由寫入電流Iw之脈衝寬幅來對 於磁壁19之移動量作控制，但是，亦可藉由寫入電流Iw之 脈衝的數量來對於磁壁19之移動量作控制。 本發明，係亦可如同圖1 4之剖面圖中所示一般，除了 第1、第2下部電極14a、14b之外，亦在第1、第2自由層部 13!、132處另外電性連接有第1、第2讀出下部電極16,、 162。若是在第1、第2上部電極15,、152和第1、第2讀出下 部電極16,、162之間被施加有電壓，則在第1、第2元件10! 、1〇2中係流動有穿隧電流。穿隧電流，由於係在自由磁 性層13內而於膜厚方向上流動，因此，係並不會有由於穿 隧電流而使磁壁19移動之虞。 本發明之自由磁性層13，例如係由CoFeB層所成，絕 緣層12，係由MgO層所成，第1、第2固定層部11,、112, 係由在絕緣層12上而依序將CoFeB層、Ru層、CoFe層、 PtMn層和Ta層作了層積之多層膜所成。 本發明之自由磁性層13的平面形狀，係並不被限定於 如同上述一般之從長方形而將其中一邊去除後的形狀，亦 可如圖16中所示一般，形成爲在自由磁性層中央部13a之 長邊方向的其中一端處而將帶狀之自由磁性層端部13 c以 朝向與自由磁性層中央部13 a之寬幅方向相平行的方向而 -20- 201143079 延伸的方式所作了連接的「L」字狀。 當本發明之自由磁性層13的平面形狀爲從長方形而將 其中一邊去除了的形狀之情況時，第1、第2元件10,、1〇2 係並不被限定於位置在自由磁性層中央部13a處之構成， 亦可如圖6中所示一般，而構成爲分別位置在第1、第2自 由層端部13b、13c處。 進而，本發明之自由磁性層1 3的平面形狀，係亦可如 圖7中所示一般，設爲相較於上述之從長方形來將其中一 邊去除後的形狀而使自由磁性層中央部1 3 a之形狀在外側 來如同弓一般地作了彎曲的形狀一般之「U」字形狀。當 「U」字形狀之自由磁性層1 3的情況時，係如圖8中所示一 般，沿著第1、第2自由磁性層端部13b、13c之長邊方向而 施加外部磁場Η，並將自由磁性層1 3磁化爲與外部磁場Η 相同之方向，之後將外部磁場Η除去，藉由此，而在弓形 狀之自由磁性層中央部13a內形成磁壁19。 亦即是，本發明之自由磁性層1 3的平面形狀，係只要 是能夠在內部形成磁壁1 9之形狀即可。 本發明之第1、第2固定層部11!、112和第1、第2自由 層部1 3 !、1 3 2之磁化方向，係並不被限定於如同上述一般 之均被磁化爲與膜厚方向垂直之方向的情況，而亦可被與 膜厚方向相平行地來磁化。當被磁化爲與膜厚方向平行的 情況時，自由磁性層1 3之平面形狀，係並不被限定於如同 上述一般之從長方形來將其中一邊去除後的形狀或者是「 L」字形狀亦或是「U」字形狀。 -21 - 201143079 對於身爲本發明之多値記憶元件的第2例之3値或者是 4値記憶元件的構造作說明。 圖9，係爲本發明之記憶元件2 1的平面圖，圖1 0係對 於同B-B線切斷剖面圖作展示。在圖9中，係將層間絕緣膜 22a、22b、22c省略。 記憶元件2 1，係具備有平面形狀分別爲帶狀之上部自 由磁性層33和下部自由磁性層37。參考圖9，於此，上部 自由磁性層33之平面形狀，係被形成爲從長方形而將其中 一邊去除後的形狀，並具備有：帶狀之上部自由磁性層中 央部33a、和被連接於上部自由磁性層中央部33 a之長邊方 向的互爲相異之端部處，並且以在平行於上部自由磁性層 中央部33a之寬幅方向的同一方向上延伸的方式所形成之 帶狀的第1、第2上部自由磁性層端部33b、33c，下部自由 磁性層37之平面形狀，係被形成爲從長方形而將其中一邊 去除後的形狀，並具備有：帶狀之下部自由磁性層中央部 37a、和被連接於下部自由磁性層中央部37a之長邊方向的 互爲相異之端部處，並且以在平行於下部自由磁性層中央 部37a之寬幅方向的同一方向上延伸的方式所形成之帶狀 的第1、第2下部自由磁性層端部3 7b、37c。 上部、下部自由磁性層33、37內之磁化方向，係如同 t 前述一般，分別成爲朝向與帶狀之長邊方向相平行的方向 。圖9、圖1 0之箭頭，係代表磁化方向。 參考圖10，在下部自由磁性層中央部3 7a之表面，係 密著配置有下部絕緣層36，上部自由磁性層中央部33a之 -22- 201143079 背面’係密著配置在下部絕緣層36之表面上。在身爲被上 部自由磁性層3 3之背面和下部自由磁性層3 7之表面所挾持 的部分並且爲下部絕緣層3 6之外側處，係以作塡充的方式 而被配置有層間絕緣膜22b，在層間絕緣膜22b處，係成爲 並不會流動後述之穿隧電流。 在上部自由磁性層中央部3 3 a表面，係密著配置有上 部絕緣層32，在上部絕緣層32之表面，係密著配置有固定 層3 1。 固定層31之磁化方向，於此係被固定爲與上部、下部 自由磁性層中央部33a、3 7a之長邊方向相平行的方向。圖 10之符號F〇2，係代表固定層31之磁化方向。 將上部絕緣層32中之與固定層31作了密著的部分之從 表面起直到背面之間的部分，稱作上部絕緣層部3 2〇。又 ，在上部自由磁性層33中，將與上部絕緣層部3 2〇相密著 了的部分之從表面起直到背面之間的部分，稱作第1上部 自由層部3 3 !，並將與下部絕緣層3 6相密著了的部分之從 表面起直到背面之間的部分，稱作第2上部自由層部3 3 2 » 進而，將下部自由磁性層37中之與下部絕緣層36作了密著 的部分之從表面起直到背面之間的部分，稱作下部自由層 部 37〇。 圖10之符號F12、F22、F32，係分別代表第1、第2上部 自由層部33!、332和下部自由層部37〇之磁化方向。如同後 述一般，第1、第2上部自由層部33,、332之磁化方向Fl2、 F22，係被構成爲能夠經由在上部自由磁性層3 3處而於帶 -23- 201143079 狀之長邊方向上作流動的寫入電流（上部寫入電流）來作 反轉，下部自由層部37〇之磁化方向F32，係被構成爲能夠 經由在下部自由磁性層37處而於帶狀之長邊方向上作流動 的寫入電流（下部寫入電流）來作反轉。 藉由固定層31和上部絕緣層部3 2ο以及第1上部自由層 部33t，而形成第1元件30!，藉由第2上部自由層部332和下 部絕緣層36以及下部自由層部37〇，而形成第2元件3 02 » 在固定層31上，係被電性連接有上部電極35，在第1 、第2上部自由磁性層端部33b、33c處，係分別被電性連 接有第1、第2中間電極（第1、第2上部寫入電極）34a、 3 4b，在第1、第2下部自由磁性層端部37b、37c處，係分 別被電性連接有第1、第2下部電極（第1、第2下部寫入電 極）38a 、 38b 。 若是在上部電極35和第1、第2下部電極38a、38b之間 施加電壓，則由於上部、下部絕緣層32、36之膜厚係爲薄 ，因此，藉由穿隧效果，係通過上部、下部絕緣層32、36 而流動有穿隧電流。穿隧電流，由於其電流量係較寫入電 流更小，因此，就算是流動有穿隧電流，後述之上部、下 部磁壁39,、3 92亦成爲並不會移動。 第1元件3 0 i之流動有穿隧電流時的電阻値，係當第1 上部自由層部33,之磁化方向F12爲與固定層部31之磁化方 向（固定方向）F«)2相同方向時而變小，並當反方向時而 變大。第2元件302之流動有穿隧電流時的電阻値，係當下 部自由層部37〇之磁化方向F32爲與第2上部自由層部332之 -24- 201143079 磁化方向F22相同方向時而變小，並當反方向時而變大。 在記億元件21內，係構成將第1、第2元件30,、302作 了串聯連接之串聯連接電路。如同後述一般，將第1、第2 元件3 0 !、3 02之電阻値雙方均爲大時作爲高電阻狀態，並 將第1、第2元件3th、302之其中一方的電阻値爲大而另外 一方爲小時作爲中間電阻狀態，且將第1、第2元件3 0,、 3 〇2之電阻値雙方均爲小時作爲低電阻狀態，以作區分。 接者’參考圖11 (a)〜（d)，針對第1'第2上部自 由層部33,、3 3 2之磁化方向F12、F22和下部自由層部37〇之 磁化方向F32的變化作說明。 將第1、第2元件3 0 !、3 02之電阻的最小値分別設爲R 1 、R2，並將最大値分別設爲Rl + ARl、R2+AR2。 將上部自由磁性層33中之身爲第1上部自由層部33,的 外部並爲第2上部自由層部3 3 2的外部且與第1、第2中間電 極3 4a、3 4b作連接之區域，分別稱作第1、第2上方端部 41a、41b，並將下部自由層部37〇和第1、第2下部電極38a 、38b之間的區域，分別稱作第1、第2下方端部42a、42b ο 於此，藉由上述一般之磁化方向的初期化，如圖1 1 ( a )中所示一般，上部磁壁3 9 ,和下部磁壁3 9 2，係分別位置 在第2上方端部41b和第2下方端部斗“處，第i、第2上部自 由層部33!、332之磁化方向F12、F22和下部自由層部37〇之 磁化方向F32，係均爲與固定方向FQ2相同之方向，記憶元 件21之電阻値，係成爲以R1+R2所表現之最小値。 -25- 201143079 接著，如圖11 (b)中所示一般，若是從第1下部電極 38a來朝向第2下部電極38b而流動預先所制訂之脈衝寬幅 的寫入電流Iw，則下部磁壁3 92係從第2下方端部42b起而 移動至第1下方端部42a處，亦即是，僅有下部自由層部 37〇之磁化方向F32會反轉，記憶元件21之電阻値，係成爲 R1+R2+△ R2。 接著，如圖11 (c)中所示一般，若是從第1中間電極 34a來朝向第2中間電極34b而流動預先所制訂之脈衝寬幅 的寫入電流Iw，則上部磁壁3 9 ,係從第2上方端部4 1 b起而 移動至第1上方端部41 a處，亦即是，第1、第2上部自由層 部33!、3 3 2之磁化方向F12、F22亦會反轉，記憶元件21之 電阻値，係成爲R1+R2 + AR1。 接著，如圖11 (d)中所示一般，若是從第2下部電極 3 8b來朝向第1下部電極38a而流動預先所制訂之脈衝寬幅 的寫入電流Iw，則下部磁壁3 92係從第1下方端部42a起而 移動至第2下方端部42b處，亦即是，下部自由層部37〇之 磁化方向F32係再度反轉，記憶元件2 1之電阻値，係成爲 最大値 Rl+112+Δ R1+AR2。 如此這般，記億元件2 1之電阻，係成爲最大値 R1+R2+ Δ R1 + Δ R2 ' 第 1 中間値 R 1 +R2 + △ R 1、第 2 中間値 Rl+R2+A R2、以及最小値R1+R2之4種的電阻値。 當第1電阻差△ R1爲較第2電阻差△ R2更大的情況時（ Δ R1 > Δ R2 )，第1中間値係成爲較大的中間値，第2中間 値係成爲較小的中間値。當第1電阻差△ R1爲較第2電阻差 -26- 201143079 △ R2更小的情況時（△ R1 < △ R2 )，第2中間値係成爲較 大的中間値，第1中間値係成爲較小的中間値。 藉由在最大値和中間値之間設置第1基準値，並在中 間値與最小値之間設置第2基準値，而對於最大値、最小 値、中間値之3種的電阻値作判別，來得到3値之記憶元件 21 〇 進而，藉由除了第1、第2基準値以外，亦在較大的中 間値和較小的中間値之間設置第3基準値，而對於最大値 、較大之中間値、較小之中間値、最小値之4種的電阻値 作判別，能夠得到4値之記憶元件2 1。 在本發明中，亦可如同圖1 5之剖面圖中所示一般，除 了第1、第2下部電極38a、38b以外，亦在下部自由層部 3 7〇處另外電性連接有讀出下部電極44。若是在上部電極 3 5和讀出下部電極44之間被施加有電壓，則在第1、第2元 件3 0 ,、3 02中係流動有穿隧電流。由於穿隧電流係在上部 、下部自由磁性層33、37內而於膜厚方向上流動，因此， 並不會有由於穿隧電流而造成位置在第1、第2上方端部 41a、41b處之上方磁壁39,或者是位置在第1、第2下方端 部42a、42b處之下方磁壁3 92移動之虞。 在本發明之記憶元件2 1中，係並不被限定於如圖1 0中 所示一般之使第1、第2上部自由層部33 ,、3 3 2相互作重合 之構成，亦可如圖12中所示一般而構成爲使第1、第2上部 自由層部33,、332相互分離。當第1、第2上部自由層部33, 、3 3 2相互分離的情況時，係亦可使上部磁壁3^位置在第1 -27- 201143079 、第2上部自由層部33,、332之間的區域處。 又，當第1、第2上部自由層部33,、332相互分離的情 況時，係亦可如圖13中所示一般，設爲將其中一方之中間 電極（於此係爲第1中間電極3 4a )電性連接於第1、第2上 部自由層部33,、332之間的區域處之構成。 本發明之上部、下部自由磁性層33、3 7之平面形狀， 只要是能夠於內部而形成磁壁39!、3 9 2之形狀，則係並不 被限定於上述一般之從長方形而將其中一邊去除後的形狀 〇 本發明之固定層部31和第1、第2上部自由層部33,、 3 3 2以及下部自由層部37〇之磁化方向，係並不被限定於如 同上述一般之均被磁化爲與膜厚方向垂直之方向的情況， 而亦可被與膜厚方向相平行地來磁化。 接著，對於使用有本發明之多値記憶元件的記憶裝置 之構造作說明。圖5，係爲對於MR AM等之記憶裝置9的其 中一例作展示之剖面圖。於此，係以使用有3値記憶元件1 之構成爲代表來作說明。代替3値記憶元件1，亦可使用第 2例之記憶元件21。 記憶裝置9，係各具備有複數根之第1、第2配線4、5 。第1配線4，係空出有特定間隔地被相互平行地作配置， 第2配線5，係在與配置有第1配線4之平面相平行且相異的 平面內，以與第1配線4交叉的方式而被作配置》於此，第 1、第2配線4、5，係被埋設在層間絕緣膜2中。 在第1配線4和第2配線5之立體交叉位置的近旁處，係 -28- 201143079 被配置有本發明之3値記憶元件1。第1配線4和第2配線5之 交叉位置，由於係被配置爲行列狀，因此，3値記憶元件1 係被配置爲行列狀。 3値記憶元件1之第1、第2上部電極15!、152，係雙方 均爲被與在近旁處而交叉之第1配線4作電性連接，於此， 第1下部電極14a，係被與第2配線5作電性連接。 第1、第2配線4、5，係被與控制裝置7作連接，在控 制裝置7處，係被連接有測定裝置8。在將資訊讀出的情況 時，控制裝置7，係對於第1、第2配線4、5作選擇，並在 所期望之3値記億元件1中流動感測電流，測定裝置8，係 對於流動有感測電流之3値記憶元件1的電導作測定，並將 測定結果傳輸至控制裝置7處。 如同上述一般，本發明之3値記憶元件1的電導，係可 得到最大値、最小値、中間値之3種，在控制裝置7處，係 至少被設置有電導之最大値和最小値。 控制裝置7，係對於測定裝置8之測定結果和所設定之 電導的値作比較，並判斷出測定結果係相當於最大値、最 小値或者是最大値和最小値之間（中間値）之何者。控制 裝置7，係將所判斷出之結果分別與「〇」、「1」、「2」 等之資訊附加關連，並作爲資訊而讀出。 故而，在此記憶裝置9中，係藉由第1、第2配線4、5 ，和控制裝置7，以及測定裝置8，而構成將資訊讀出之讀 出手段。 接著，針對資訊之改寫作說明。在此記憶裝置9中， -29- 201143079 係沿著第2配線5之配線而延伸設置有第3配線6。 3値記憶元件1之第2下部電極14b ’係被與第3配線6作 電性連接。 控制裝置7，係對於第2、第3配線5、6作選擇，並使 寫入電流流動至所期望之3値記憶元件1處。 將3値記憶元件1之電導設爲最大値、最小値、中間値 之寫入電流的方向以及脈衝寬幅的長度之條件，係預先被 求取出來並被設定在控制裝置7中。 控制裝置7，係將所欲記憶之資訊和3値記憶元件1的 電導附加關連，並以設爲與電導附加了關連之値的通電條 件，來對第2、第3配線5、6流動電流，並將所期望之記憶 資訊作爲電導來記憶在3値記憶元件1中。 如此這般，藉由第2、第3配線5、6，和控制裝置7， 而構成將資訊作改寫之改寫手段。 在上述說明中，雖係對於電導値作測定並得到3値之 電導値，但是，亦可對於電阻値作測定並得到3値之電阻 値。 【圖式簡單說明】 〔圖1〕本發明之3値記憶元件的平面圖。 〔圖2〕本發明之3値記憶元件的A-A線切斷剖面圖。 〔圖3〕 （a)〜（d):用以對於從長方形而將一邊 除去後之形狀的自由磁性層的磁化方向之初期化作說明的 圖。 -30- 201143079 〔圖4〕 （a)〜（c):用以對於第1、第2自由層部 的磁化方向之變化作說明的圖。 〔圖5〕對於使用有3値記憶元件之記憶裝置之其中一 例作展示之剖面圖。 〔圖6〕用以對於第1、第2元件之配置的其中一例作 說明之平面圖。 〔圖7〕具備有「U」字形狀之自由磁性層的3値記億 元件之平面圖。 〔圖8〕用以對於「U」字形狀之自由磁性層的磁化方 向之初期化作說明的圖。 〔圖9〕本發明之3値或者是4値之記憶元件的平面圖 〇 〔圖10〕本發明之3値或者是4値之記憶元件的B-B線 切斷剖面圖。 〔圖11〕 （a)〜（d):用以對於第1、第2上部自由 層部以及下部自由層部的磁化方向之變化作說明的圖。 〔圖12〕第1、第2上部自由層部相互作了分離的記憶 元件之剖面圖。 〔圖13〕第1、第2上部自由層部相互作了分離的記億 元件之第2例的剖面圖。 〔圖1 4〕具備有讀出下部電極的3値記憶元件之剖面 圖。 〔圖15〕具備有讀出下部電極的3値或者是4値之記億 元件的剖面圖。 -31 - 201143079 〔圖16〕具備有「L」字形狀之自由磁性層的3値記憶 元件之平面圖。 【主要元件符號說明】 1 : 3値記憶元件 1〇|、3〇i:第1元件 1〇2、302 :第2元件 111、112:第1、第2固定層部 1 2 :絕緣層 12!、122 :第1、第2絕緣層部 1 3 :自由磁性層 13!、132:第1、第2自由層部 14a、14b:第1、第2電極（第1、第2下部電極） 18a、18c :第1、第2端部 18b :中間部 2 1 :記憶元件 31 :固定層 32 :上部絕緣層 32〇 :上部絕緣層部 3 3 :上部自由磁性層 33,、3 32 :第1、第2上部自申層部 34a、34b:第1、第2上部寫入電極（第1、第2中間電 極） 3 6 :下部絕緣層 -32- 201143079 37:下部自由磁性層 3 7〇 :下部自由層部 38a、38b:第1、第2下部寫入電極（第1、第2下部電 41a' 41b:第1、第2上方端部 42a、42b :第1、第2下方端部 -33-201143079 VI. Description of the Invention: [Technical Field to Be Invented by the Invention] The present invention relates to a memory element and a method of recording. [Prior Art] Nowadays, a memory element (a tunneling magnetoresistive element) having a magnetic multilayer film that exhibits a tunneling magneto-resistive effect is used in a non-volatile memory such as MRAM. . The multilayer film of the tunneling magnetoresistive element is provided with a magnetic layer having two layers and an insulating layer sandwiched between two magnetic layers. The thickness of the insulating layer is thin, and if it is operated as a memory element and flows a sensing current perpendicular to the film surface, a tunneling current flows through the insulating layer by the tunneling effect. When the magnetization directions of the two layers of magnetic layers are opposite to each other (anti-parallel), the resistance enthalpy is large, and when in the same direction (parallel), the resistance enthalpy is small. By making the resistor of the size correspond to "〇" and "1", it is possible to realize a memory element that non-volatilely memorizes information of 2 inches. As a method of writing data to a tunneling magnetoresistive element, for example, Patent Document 1 discloses that a current is applied in parallel on a film surface of a magnetic layer to cause a magnetic layer to be in a magnetic layer. The magnetic walls in the boundary between the magnetic regions in the opposite direction are moved to perform writing. In the shape of the tunneling magnetoresistive element used in the prior art, basically, since the relationship of the magnetization directions of the two layers of the magnetic layer is only parallel or anti-parallel, the resistance is high resistance and Low resistance -5 - 201143079 2 types, and can only remember the information caused by 2値 by matching the resistance of the size to "0" and "1". Whether it is in the MR AM of non-volatile memory that is being researched and developed today, or in the DRAM that has been mass-produced and the micro-system is more advanced, it is also the basic component of information. The basis of the two states of "0" is used as the basis. Therefore, whether it is volatile or non-volatile, there is no advantage in terms of capacity. In order to increase the memory capacity, there is no other answer than the increase in the number of memory elements (density). Therefore, there is no other way to pursue progress beyond miniaturization. In the subtlety, there are limits. Therefore, there is a need for a means to increase the recording density by means other than miniaturization. [Prior Art Document] [Patent Document 1] [Patent Document 1] International Publication No. 2007/020823 [Draft of the Invention] The present invention has been made in order to solve the problems of the prior art described above, and its object It is to provide a memory element and a memory method for memorizing the information of 3値 or 4値 using the tunneling magnetoresistance effect. [Means for Solving the Problems] In order to solve the above problems, the present invention is a 3-inch memory element-6 - 201143079, which is provided with a strip-shaped free magnetic layer; and is adhered to the surface of the aforementioned free magnetic layer An insulating layer; and a second fixed layer portion which is 'disposed and disposed apart from each other' on the surface of the insulating layer and magnetized in the same direction, if it is to be in the insulating layer, the surface is as described above The portions of the first and second fixed layer portions which are adhered from the surface to the back surface are referred to as first and second insulating layer portions, and the surface of the free magnetic layer is the first surface and the first surface. The portion from the surface to the back surface of the portion where the second insulating layer portion is adhered is referred to as the first and second free layer portions, and the first free layer portion and the first insulating layer are formed by the first free layer portion and the first insulating layer. And the first fixed layer portion forming a first element through which the tunneling current flows through the first insulating layer portion, and the second free layer portion, the second insulating layer portion, and the second fixed portion Layers, formed by the aforementioned second a second element through which a tunneling current flows in the edge layer portion, and when the magnetization directions of the first and second fixed layer portions are in a fixed direction, when the tunneling current flows through the first and second elements The resistance 値 is such that the magnetization direction of the first and second free layer portions becomes smaller when it is in the same direction as the fixed direction, and becomes larger when the direction is the opposite direction, and the first and second portions are formed. When both of the resistances of the elements are large, the first state is one of the first and second elements, and the other one is small, and the second state is the first state. In the third state, the resistance of the second element is small, and the three-dimensional memory element is characterized in that, between the first and second free layer portions of the free magnetic layer. Part of the intermediate portion is provided, and the portion between the intermediate portion of the free magnetic layer and the first and second free layer portions and the first and second free layer portions are in contact with 201143079 For the first and second end portions, in the free magnetic layer The magnetic wall formed by the boundary of the region in which the magnetization directions are different from each other is moved by the write current flowing in the longitudinal direction of the strip at the free magnetic layer, and becomes The position is at one of the first end portion, the second end portion, and the intermediate portion. The present invention is a three-dimensional element in which the magnetization directions of the first and second fixed layer portions and the magnetization directions of the first and second free layer portions are both perpendicular to the film thickness direction. The direction. The present invention is a three-turn memory device in which the magnetization directions of the first and second fixed layer portions and the magnetization directions of the first and second free layer portions are both parallel to the film thickness direction. direction. The present invention is a three-turn memory device in which the first and second electrodes are electrically connected to the first and second end portions, and the magnetic walls are disposed in the first and the first The portion between the electrodes, the write current, is configured to flow between the first and second electrodes. The present invention is a memory element, which is a memory element of 3 turns, and is provided with: a strip-shaped lower free magnetic layer; and a portion of the upper and lower insulating layers adhered to the surface of the lower free magnetic layer: And a portion of the back surface is a strip-shaped upper free layer adhered to the surface of the lower insulating layer; and an upper insulating layer adhered to a portion of the surface of the upper free layer; and is adhered to The surface of the upper insulating layer is magnetized into a fixed layer in one direction, and a portion of the upper insulating layer in which the surface and the fixed layer portion are adhered from the surface to the back surface, It is referred to as an upper insulating layer portion, and in the upper free magnetic layer -8 - 201143079, a portion of the surface from which the surface of the upper insulating layer is adhered from the surface to the back surface is referred to as a a portion of the upper free stomach portion, wherein the portion of the back surface and the lower insulating layer portion that are adhered from the back surface to the surface is referred to as a second upper free layer portion. In the lower free magnetic layer, a portion of the lower surface of the lower insulating layer that is adhered from the surface to the back surface is referred to as a lower free layer portion, and is insulated by the fixed layer and the upper portion. a layer portion and the first upper free layer portion to form a first element through which a tunneling current flows through the upper insulating layer portion, and the second upper free layer portion and the lower insulating layer and the lower free layer a second element through which a tunneling current flows through the lower insulating layer, and a resistance 时 when the tunneling current flows through the first element is a magnetization of the first upper free layer portion When the direction is the same as the magnetization direction of the fixed layer, the amount becomes smaller, and when the direction is the reverse direction, the resistance 値 when the tunneling current flows in the second element is: (2) The magnetization direction of the upper free layer portion becomes smaller when it is in the same direction as the magnetization direction of the lower free layer portion, and becomes larger when it is in the reverse direction, and the first and second elements are electrically When both of the barriers are large, the high resistance state is such that one of the resistances of the first and second elements is large and the other is small, and the intermediate resistance state is the first and second. The two-dimensional memory element is characterized in that the body of the upper free magnetic layer is outside the first upper free layer portion and is a low resistance state. a portion of the second upper free layer portion that is connected to an end portion of the upper free magnetic layer in the longitudinal direction of the band of 201143079, which is the first and second upper end portions. Further, the portion which is the outer portion of the lower free magnetic layer in the lower free magnetic layer and which is different from the end portion of the strip-shaped longitudinal direction of the lower free layer is first and second. In the lower end portion of the second portion, the upper magnetic layer is formed with a magnetic wall above the boundary of the region in which the magnetization directions are different from each other, and the magnetism is formed in the lower free magnetic layer. a magnetic wall below the boundary of the region in which the directions are different from each other, and the upper magnetic wall is moved by an upper writing current flowing in the longitudinal direction of the upper free magnetic layer, and the position is in the One of the upper end portion and the second upper end portion, the lower magnetic wall is moved by a lower write current flowing in the longitudinal direction of the lower free magnetic layer, and becomes a position At one of the first lower end portion and the second lower end portion, three turns are stored. The present invention is a memory device in which the resistance 値 of the first element is large and the resistance 値 of the second element is small, in addition to the high resistance state and the low resistance state. In the intermediate resistance state, when the resistance 値 of the first element is small and the resistance 値 of the second element is large, the second intermediate resistance state is set, thereby distinguishing and memorizing 4 値. The present invention is a memory element in which a magnetization direction of the fixed layer and a magnetization direction of the first and second upper free layer portions and a magnetization direction of the lower free layer portion are both perpendicular to a film thickness direction The direction. -10- 201143079 The present invention is a memory element in which the magnetization direction of the fixed layer and the magnetization direction of the first and second upper free layer portions and the magnetization direction of the lower free layer portion are both The direction of the thick direction is parallel. The present invention is a memory element in which the first and second upper writing electrodes 'the upper magnetic walls are electrically connected to the first and second upper end portions, respectively. 1. The portion between the second upper write electrodes, wherein the upper write current is configured to flow between the first and second upper write electrodes, and at the second and second lower ends Each of the lower write electrodes is electrically connected to the first and second lower write electrodes, and the lower magnetic wall is disposed at a portion between the first and second lower write electrodes. The first and second lower writing electrodes flow between the electrodes. The present invention is a memory method in which two elements are connected in parallel, the element is provided with: a free layer portion; and an insulating layer adhered to the surface of the free layer portion; and is closely adhered to the foregoing insulating layer a surface of the layer and magnetized into a fixed layer in one direction, and the element that flows through the insulating layer is formed by the free layer portion and the insulating layer and the fixed layer, and the tunneling is performed in the flow The resistance 値 at the time of current is set to be: when the magnetization direction of the free layer portion is in the same direction as the magnetization direction of the fixed layer, it becomes smaller, and when it is in the opposite direction, it becomes larger, and the memory method is When both of the resistances of the two elements are large, the resistance 値 of the one of the elements is large, and the resistance 値 of the other element is small, and both of the resistance 値 of the two elements are two. In the case of -11 - 201143079 hours, the three types of resistances are discriminated and the memory is 3 値. The method is characterized in that the free layer portions of the two aforementioned elements are formed in the same band. In the free magnetic layer, at a position different from each other in the longitudinal direction, if the portion between the free layer portions of the two free magnetic layers is the intermediate portion, When the outer side of the intermediate portion and the two free layer portions are the first and second end portions, a magnetic wall that is a boundary of a region in which magnetization directions are different from each other is formed in the free magnetic layer, and the magnetic wall is formed. The free magnetic layer moves in the longitudinal direction and is positioned at one of the first end portion, the second end portion, and the intermediate portion. The present invention is a memory method in which the first and second electrodes are electrically connected to the first and second end portions, and the magnetic wall is positioned at the first and second electrodes. In the inter-portion, a write current flows between the first and second electrodes to move the magnetic wall. The present invention is a memory method in which two elements are connected in series, the element is provided with: a free layer portion; and an insulating layer adhered to the surface of the free layer portion: and is insulated from the foregoing insulation a surface of the layer and magnetized into a fixed layer in one direction, and the element that flows through the insulating layer is formed by the free layer portion and the insulating layer and the fixed layer, and the tunneling is performed in the flow The resistance 値 at the time of current is set to be: when the magnetization direction of the free layer portion is in the same direction as the magnetization direction of the fixed layer, it becomes smaller, and when it is in the opposite direction, it becomes larger, and the memory method is When both of the resistances of the two elements are large, the resistance 値 of the one of the elements is large, and the other element is -12-201143079, and the resistance is 小时, and two of the aforementioned elements are When both sides of the resistor 均为 are small, the three kinds of resistors are used for discrimination, and the memory method is characterized in that the free layer portion of the aforementioned element is formed in a strip shape. In the lower free magnetic layer, the fixed layer of the element described above and the free layer portion of the other element are formed in the same strip-shaped upper free magnetic layer, if the upper free magnetic layer is The lower free magnetic layer is formed on the outer side of the fixed layer of the other element and the outer side of the free layer portion of the other element is the first and second upper end portions. When the outer side of the free layer portion of the element of the one of the elements is the i-th and second lower end portions, the boundary between the regions in which the magnetization directions are different from each other is formed in the upper free magnetic layer. The upper magnetic wall ′ and the lower magnetic layer are formed in the lower free magnetic layer, and the upper magnetic wall is moved in the longitudinal direction at the upper free magnetic layer, and is positioned at the first upper end. And one of the second upper end portions, wherein the lower magnetic wall moves in the longitudinal direction at the lower free magnetic layer, and A position in which a lower end wherein the first portion and the second portion of the lower end. The present invention is a memory method in which the resistance 値 of the two elements of the two elements is large, and the resistance 値 of the one of the elements is large, and the resistance 値 of the other element is small. And the resistance 値 of the one of the one of the elements is small, and the resistance 値 of the other element is large, and both of the resistance 値 of the two elements are small, and the four types of resistance are determined. And remember 4 値. -13-201143079 The present invention is a memory method in which the first and second upper writing electrodes are electrically connected to the first and second upper end portions, respectively, so that the upper magnetic wall position is a portion where the first and second upper write electrodes are between and a write current flows between the first and second upper write electrodes, and moves the upper magnetic wall to the first and second lower ends. The first lower portion and the second lower write electrode are electrically connected to each other, and the lower magnetic wall is located at a portion between the first and second lower write electrodes, and is in the first and second portions. A write current flows between the lower write electrodes to move the lower magnetic wall. [Effects of the Invention] Since it is possible to memorize 3 or 4 pieces of information by one element, it is possible to improve the recording density of the billion element without miniaturization. [Embodiment] A structure of a memory element of a first example of a multi-turn memory device of the present invention will be described. Fig. 1 is a plan view showing a three-dimensional element 1 of the present invention, and Fig. 2 is a cross-sectional view taken along the line A-A. In Fig. 1, the interlayer insulating films 2a and 2b are omitted from the memory element 1, and the free magnetic layer 13 having a planar shape in a strip shape is provided. Referring to Fig. 1, the planar shape of the free magnetic layer 13 is formed into a shape obtained by removing one side from a rectangular shape, and is provided with: -14- 201143079 having a wide width and a wider width and longer The strip-shaped free magnetic layer central portion 13a in the longitudinal direction and the mutually different end portions connected to the longitudinal direction of the central portion 13a of the free magnetic layer and in the central portion 13a of the free magnetic layer The strip-shaped first and second free magnetic layer end portions 13b and 13c formed to extend in the same direction in which the web directions are parallel. The magnetization direction (direction of the magnetic moment) in the free magnetic layer 13 is oriented in a direction parallel to the longitudinal direction of the strip as will be described later. The arrows in Fig. 1 and Fig. 2 represent the magnetization directions. Referring to Fig. 2, an insulating layer 12 is disposed on the surface of the central portion 13a of the free magnetic layer, and the first and second fixed layer portions 11!, 112 are adhered to the surface of the insulating layer 12, and The free magnetic layer central portion 13a is disposed apart from each other in the longitudinal direction. The magnetization directions (the directions of the magnetic poles) of the first and second fixed layer portions 11, 112 are oriented in the same direction and fixed. Hereinafter, the magnetization directions of the first and second fixed layer portions 11 and 112 are referred to as a fixed direction. Here, the fixing direction is parallel to the longitudinal direction of the central portion 13a of the free magnetic layer, and the symbol Fqi of Fig. 2 represents a fixed direction. Here, as shown in FIG. 1 and FIG. 2, the first and second fixing layers 11, and 112 are respectively adhered to the surfaces of the different insulating layers 12, but the present invention is not limited. Here, it may be adhered to the mutually different positions on the surface of one insulating layer 12. In the insulating layer 12, a portion from the surface to the back surface of the portion which is in close contact with the first and second fixed layer portions 1 1 ^ and 1 2 is referred to as a first insulating layer and a second insulating layer portion. 1 2 !, 1 2 2, and a portion of the portion of the free magnetic layer 13 that is adhered to the first and second -15-201143079 insulating layer portions 12, 122 from the surface to the back surface, It is called the first and second free layer parts 13, and 132. As described above, since the first and second fixed layer portions 1h and 112 are separated from each other, the first and second free layer portions 13 and 132 are also disposed apart from each other. The symbols FM and F21 in Fig. 2 represent the magnetization directions of the first and second free layer portions 13 and 132. As will be described later, the magnetization directions F, , and F2 i of the first and second free layer portions 13 and 13 2 are configured to be able to flow in the longitudinal direction of the strip via the free magnetic layer 13 . The write current is reversed, and the first free element 13! and the first insulating layer portion 12! and the first fixed layer portion 11! are formed to form the first element 1 〇!, by the second free The second portion 102 is formed by the layer portion 132, the second insulating layer portion 122, and the second fixed layer portion 112. The first and second upper electrodes 15 and 152 are electrically connected to the first and second fixed layer portions 1 1 i and 1 12, respectively, at the first and second free magnetic layer end portions 13b and 13c. The first and second lower electrodes (first and second electrodes) 14a and 14b are electrically connected to each other. When a voltage is applied between the first and second upper electrodes 15! and 152 and the first and second lower electrodes 14a and 14b, the film thickness of the first and second insulating layer portions 1 2 and 122 is increased. Since it is thin, a tunneling current flows through the first and second insulating layer portions 12! and 122 in the first and second elements 10, 1 and 2 by the tunneling effect. Since the tunneling current is smaller than the write current, even if a tunneling current flows, the magnetic wall 19 described later does not move. -16- 201143079 The first and second components 1 〇, 1 〇 2 flow has a tunneling current when the resistance 値 ' is through the tunneling magnetoresistance effect, and when the first and second free layer parts i3l, 132 The magnetization directions Fu and F21 are smaller than the magnetization directions (fixed directions) F of the first and second fixed layer portions 11 and 112 (the same direction is obtained when the direction is h, and becomes larger when the direction is reversed. In the element 1, a parallel connection circuit in which the first and second elements 10! and 1〇2 are connected in parallel is formed, and the resistance of the first 'second element 10i, 1〇2 is generally described later. In the first state, the resistance of one of the first and second elements 10, 1 and 2 is large, and the other is hour as the second state, and the first and second are used. The resistances of the elements 1 0 and 1 〇 2 are both in the third state for distinction. The receiver's magnetization directions F!i and F21 for the table 1 and the second free layer portions 13丨, 13 First, the initialization of the magnetization direction, as shown in Fig. 3 (a) or Fig. 3 (c), is generally parallel to the film surface of the free magnetic layer 13 and the first and second The external magnetic field 施加 is applied in a direction in which the longitudinal direction of the magnetic layer end portions 13b and 13c are parallel, and the first and second free magnetic layer end portions 1 3 b and 13c are magnetized in the same direction as the external magnetic field 。. Fc represents the magnetization direction of the first and second free magnetic layer end portions 1 3 b and 1 3 c respectively. Next, after the external magnetic field is removed, the second lower electrode 14b faces the second lower electrode 14b. 1 The lower electrode 14a flows the initializing current 1(), and the spin-transfer effect (rotation angular momentum imparting) from the conduction electrons to the magnetic moment is as shown in Fig. 3(c). Generally, the magnetization direction Fb of the first free magnetic layer end portion 13b is equal to the initial current of 1-17-17- 201143079. In the same case, as shown in Fig. 3(d), the magnetization direction F a of the central portion 13 a of the free magnetic layer is also oriented in the same direction as the direction of the initializing current Q, and 'when as in Fig. 3 ( In the case where the magnetization direction Fb of the first free magnetic layer end portion 13b is opposite to the direction of the initializing current Iq, the magnetization direction of the central portion 13a of the free magnetic layer is generally as shown in Fig. 3(b). Fa is also oriented in a direction opposite to the direction of the initializing current of 1 ,. Therefore, at the boundary between the central portion 13a of the free magnetic layer and the end 13c of the second free magnetic layer, the magnetization directions are formed to be mutually The magnetic wall 19 of the boundary of the distinct region. In other words, the magnetic wall 19 is positioned in the same direction as the direction of the initializing current flowing in the longitudinal direction of the free magnetic layer 13 and the opposite portion of the dissimilar direction. After the external magnetic field is removed, the initializing current 1 流动 flows from the first lower electrode 14a toward the second lower electrode 14b, and is in the free magnetic layer central portion 13a and the first free magnetic layer end portion 13b. A magnetic wall 19 is formed at the boundary between the two. 4(a) to 4(c) show changes in the magnetization directions Fu and F21 of the first and second free layer portions 13, 132 in the fixed direction FQ1. The minimum 値 of the conductance of the first and second elements 10, 1 and 2 is set to C 1 and C2, respectively, and the maximum 値 is set to C1 + AC1 ' C 2 + z \ C2 (the conductance is a resistance 値) Countdown). Here, first, as shown in FIG. 4(a), the magnetic wall 196 is located in a region between the second lower electrode 14b and the second free layer portion 132 (hereinafter referred to as a second end portion 18c). The magnetization directions Fu and F21 of the first and second free layer portions 13 and 132 are both in the same direction as the fixed direction F (n, • 18 - 201143079 3値, the conductance of the memory element 1 is The maximum 値 indicated by C1+C2+AC1 + AC2. Next, as shown in FIG. 4(b), generally, the pulse width of the predetermined width is flowed from the first lower electrode 14a toward the second lower electrode 14b. When the write current Iw is applied, the magnetic wall 19 moves from the second end portion 18c to the first free layer portion 13 and the second free layer portion 1 3 2 by the spin transfer effect of the conduction electrons with respect to the magnetic moment. The region between (hereinafter referred to as the intermediate portion 18b), that is, only the magnetization direction F21 of the second free layer portion 132 is reversed, and the conductance of the memory element 1 becomes C1+C2+. AC1. Next, as shown in Fig. 4(c), in general, a pulse width width set in advance is flowed from the first lower electrode 14a toward the second lower electrode 14b. In the write current Iw, the magnetic wall 19 moves from the intermediate portion 18b to the region between the first free layer portion 13 and the first lower electrode 14a (hereinafter referred to as the first end portion 18a). In other words, the magnetization direction F11 of the first free layer portion 13i is also reversed, and the conductance 値' of the memory element 1 becomes the minimum 値C 1 + C 2 . Then, from the second lower electrode 14b toward the first When the lower electrode 14a flows in a predetermined pulse width write current Iw, the magnetic wall 19 moves from the first end portion 18a to the second end portion 18c's first and second free layers. The magnetization directions F, , and F2 of the parts 1 3 ! and 1 3 2 are reversed again, and return to the conductance 一般 as the maximum 値C1+C2+AC1 as shown in Fig. 4(a). + The state of AC2. In this way, the conductance of the 3値 memory element 1 becomes the maximum 値C 1 +C2+ Δ C 1 + Δ C2 ' intermediate 値C1+C2+/\C1, the minimum 値C1+C2 Conductance 値 -19- 201143079 Set the first reference 値 between the maximum 値 and the middle 値, and set the second reference 在 between the middle 値 and the minimum 値, and by the maximum 値, the minimum 値, the middle 値Three types of conductance discrimination are used to obtain a 3 元件 亿 billion element 1 °. In the above description, although the amount of movement of the magnetic wall 19 is controlled by the pulse width of the write current Iw, it is also possible to borrow The amount of movement of the magnetic wall 19 is controlled by the number of pulses of the write current Iw. The present invention can also be generally as shown in the cross-sectional view of Fig. 14 except for the first and second lower electrodes 14a, 14b. Further, the first and second read lower electrodes 16, 162 are electrically connected to the first and second free layer portions 13 and 132, respectively. When a voltage is applied between the first and second upper electrodes 15 and 152 and the first and second read lower electrodes 16 and 162, the first and second elements 10 and 1 are connected to each other. The flow has a tunneling current. Since the tunneling current flows in the film thickness direction in the free magnetic layer 13, there is no possibility that the magnetic wall 19 moves due to the tunneling current. The free magnetic layer 13 of the present invention is formed, for example, of a CoFeB layer, and the insulating layer 12 is made of a MgO layer. The first and second fixed layer portions 11, 112 are sequentially formed on the insulating layer 12. A multilayer film in which a CoFeB layer, a Ru layer, a CoFe layer, a PtMn layer, and a Ta layer are laminated is formed. The planar shape of the free magnetic layer 13 of the present invention is not limited to the shape in which one side is removed from the rectangular shape as described above, and may be formed in the central portion of the free magnetic layer as shown in FIG. The strip-shaped free magnetic layer end portion 13 c is connected at one end in the longitudinal direction of 13a so as to extend in a direction parallel to the width direction of the central portion 13 a of the free magnetic layer, -20-201143079 The "L" shape. When the planar shape of the free magnetic layer 13 of the present invention is a shape in which one side is removed from a rectangular shape, the first and second elements 10, 1〇2 are not limited to the position in the center of the free magnetic layer. The configuration of the portion 13a may be configured to be positioned at the first and second free layer end portions 13b and 13c, respectively, as shown in Fig. 6 . Further, the planar shape of the free magnetic layer 13 of the present invention may be generally as shown in Fig. 7, and the central portion of the free magnetic layer may be formed in comparison with the shape obtained by removing one of the sides from the rectangular shape as described above. The shape of 3 a is curved in the shape of a general U-shape on the outside as a bow. In the case of the "U"-shaped free magnetic layer 13 as shown in Fig. 8, an external magnetic field 施加 is applied along the longitudinal direction of the first and second free magnetic layer end portions 13b, 13c. The free magnetic layer 13 is magnetized in the same direction as the external magnetic field ,, and then the external magnetic field is removed, whereby the magnetic wall 19 is formed in the arc-shaped free magnetic layer central portion 13a. In other words, the planar shape of the free magnetic layer 13 of the present invention may be any shape as long as the magnetic wall 19 can be formed inside. The magnetization directions of the first and second fixed layer portions 11 and 112 and the first and second free layer portions 1 3 and 1 3 of the present invention are not limited to being magnetized as described above. The film thickness direction is perpendicular to the direction of the film thickness direction, and may be magnetized in parallel with the film thickness direction. When it is magnetized to be parallel to the film thickness direction, the planar shape of the free magnetic layer 13 is not limited to the shape which is removed from the rectangular shape as described above or the "L" shape. Or the shape of the "U". -21 - 201143079 A description will be given of the structure of the second example of the multi-turn memory element of the present invention or the configuration of the memory unit. Fig. 9 is a plan view showing the memory element 2 1 of the present invention, and Fig. 10 is a cross-sectional view taken along the line B-B. In Fig. 9, the interlayer insulating films 22a, 22b, and 22c are omitted. The memory element 21 is provided with a strip-shaped upper free magnetic layer 33 and a lower free magnetic layer 37 in a planar shape. Referring to Fig. 9, the planar shape of the upper free magnetic layer 33 is formed into a shape in which one side is removed from a rectangular shape, and includes a band-shaped upper free magnetic layer central portion 33a, and is connected to The end portions of the upper free magnetic layer central portion 33 a in the longitudinal direction are different from each other, and are formed in a strip shape extending in the same direction parallel to the width direction of the upper free magnetic layer central portion 33a. The first and second upper free magnetic layer end portions 33b and 33c and the lower free magnetic layer 37 have a planar shape which is formed by removing one of the rectangular shapes from the rectangular shape, and is provided with a band-shaped lower portion free magnetic property. The layer center portion 37a and the end portions of the lower free magnetic layer central portion 37a which are connected to each other in the longitudinal direction are different from each other, and are in the same direction parallel to the width direction of the lower free magnetic layer central portion 37a. The strip-shaped first and second lower free magnetic layer end portions 37b, 37c formed by the extending method. The magnetization directions in the upper and lower free magnetic layers 33, 37 are oriented in the direction parallel to the longitudinal direction of the strip, as in the above-mentioned t. The arrows in Fig. 9 and Fig. 10 represent the magnetization directions. Referring to Fig. 10, a lower insulating layer 36 is disposed on the surface of the lower free magnetic layer central portion 37a, and the back portion of the upper free magnetic layer central portion 33a is disposed in the lower insulating layer 36. On the surface. In the portion sandwiched by the surface of the upper free magnetic layer 33 and the surface of the lower free magnetic layer 37, and at the outer side of the lower insulating layer 36, an interlayer insulating film is disposed as a filling. 22b, at the interlayer insulating film 22b, the tunneling current to be described later does not flow. The upper insulating layer 32 is disposed on the surface of the upper free magnetic layer central portion 3 3 a, and the fixed layer 31 is disposed on the surface of the upper insulating layer 32. The magnetization direction of the pinned layer 31 is fixed in a direction parallel to the longitudinal direction of the upper and lower free magnetic layer central portions 33a and 37a. The symbol F 〇 2 of Fig. 10 represents the magnetization direction of the fixed layer 31. The portion of the upper insulating layer 32 which is adhered to the fixed layer 31 from the surface to the back surface is referred to as an upper insulating layer portion 32. Further, in the upper free magnetic layer 33, a portion from the surface to the back surface of the portion which is in close contact with the upper insulating layer portion 3 2 is referred to as a first upper free layer portion 3 3 ! The portion from the surface to the back surface of the portion in contact with the lower insulating layer 36 is referred to as a second upper free layer portion 3 3 2 » Further, the lower free magnetic layer 37 and the lower insulating layer 36 are formed. The portion of the dense portion from the surface to the back is referred to as the lower free layer portion 37A. Symbols F12, F22, and F32 of Fig. 10 represent the magnetization directions of the first and second upper free layer portions 33!, 332 and the lower free layer portion 37, respectively. As will be described later, the magnetization directions F1 and F22 of the first and second upper free layer portions 33 and 332 are configured to be able to pass through the upper free magnetic layer 33 at the longitudinal direction of the belt -23-201143079. The write current (upper write current) flowing in the upper direction is reversed, and the magnetization direction F32 of the lower free layer portion 37 is configured to be able to pass through the lower free magnetic layer 37 in the longitudinal direction of the strip. The flowing write current (lower write current) is reversed. The first element 30 is formed by the fixed layer 31, the upper insulating layer portion 32 and the first upper free layer portion 33t, and the second upper free layer portion 332 and the lower insulating layer 36 and the lower free layer portion 37 are formed by the first upper free layer portion 332. The second element 3 02 is formed on the fixed layer 31, and the upper electrode 35 is electrically connected to the first and second upper free magnetic layer end portions 33b and 33c. 1. The second intermediate electrode (first and second upper writing electrodes) 34a and 34b are electrically connected to the first and second lower free magnetic layer end portions 37b and 37c, respectively. 2 lower electrode (first and second lower write electrodes) 38a, 38b. When a voltage is applied between the upper electrode 35 and the first and second lower electrodes 38a and 38b, since the thicknesses of the upper and lower insulating layers 32 and 36 are thin, the tunneling effect is passed through the upper portion. A tunneling current flows through the lower insulating layers 32, 36. Since the tunneling current is smaller than the write current, even if the tunneling current flows, the upper and lower magnetic walls 39 and 3 92, which will be described later, do not move. When the first element 3 0 i flows, there is a resistance 値 when the tunneling current flows, and the magnetization direction F12 of the first upper free layer portion 33 is the same direction as the magnetization direction (fixed direction) F«) 2 of the fixed layer portion 31. It becomes smaller from time to time and becomes larger when it is reversed. The resistance 値 when the second element 302 flows has a tunneling current, and becomes smaller when the magnetization direction F32 of the lower free layer portion 37 is the same direction as the magnetization direction F22 of the second upper free layer portion 332. And when the opposite direction becomes bigger. In the mega element 21, a series connection circuit in which the first and second elements 30 and 302 are connected in series is formed. As will be described later, when both of the first and second elements 3 0 and 3 02 are large, the resistance is large, and the resistance of one of the first and second elements 3th and 302 is large. On the other hand, the hour is the intermediate resistance state, and the resistances of the first and second elements 30, 3, and 2 are both low-resistance states for distinction. Referring to FIGS. 11(a) to 11(d), changes are made to the magnetization directions F12 and F22 of the first 'second upper free layer portion 33, 327, and the magnetization direction F32 of the lower free layer portion 37A. Description. The minimum 値 of the resistances of the first and second elements 3 0 ! and 3 02 are respectively R 1 and R 2 , and the maximum 値 is set to R1 + AR1 and R2 + AR2, respectively. The outer portion of the upper free magnetic layer 33 is the outer portion of the first upper free layer portion 33, and is external to the second upper free layer portion 3 3 2 and is connected to the first and second intermediate electrodes 34a, 34b. The regions are referred to as the first and second upper end portions 41a and 41b, respectively, and the regions between the lower free layer portion 37A and the first and second lower electrodes 38a and 38b are referred to as first and second lower portions, respectively. End portions 42a, 42b Here, by the initialization of the general magnetization direction, as shown in Fig. 1 1 (a), the upper magnetic wall 3 9 and the lower magnetic wall 3 9 2 are respectively positioned at the second position. The upper end portion 41b and the second lower end portion "where the magnetization directions F12 and F22 of the i-th and second upper free layer portions 33! and 332 and the magnetization direction F32 of the lower free layer portion 37" are both fixed and fixed. In the direction in which the direction FQ2 is the same, the resistance 记忆 of the memory element 21 is the minimum 表现 expressed by R1+R2. -25- 201143079 Next, as shown in FIG. 11(b), generally, from the first lower electrode 38a When the pulse current of the predetermined width Iw flows in advance toward the second lower electrode 38b, the lower magnetic wall 392 is from the second lower end portion 42b. Further, moving to the first lower end portion 42a, that is, only the magnetization direction F32 of the lower free layer portion 37 is reversed, and the resistance 记忆 of the memory element 21 is R1 + R2 + ΔR2. 11 (c), generally, when the pulse current of the predetermined width Iw flows from the first intermediate electrode 34a toward the second intermediate electrode 34b, the upper magnetic wall 3 9 is from the second upper end. The portion 4 1 b moves to the first upper end portion 41 a, that is, the magnetization directions F12 and F22 of the first and second upper free layer portions 33! and 3 3 2 are also reversed, and the memory element 21 is reversed. The resistance 値 is R1 + R2 + AR1. Next, as shown in Fig. 11 (d), generally, the pulse width of the predetermined width is flowed from the second lower electrode 38b toward the first lower electrode 38a. When the current Iw is written, the lower magnetic wall 3 92 moves from the first lower end portion 42a to the second lower end portion 42b, that is, the magnetization direction F32 of the lower free layer portion 37 is reversed again, and the memory is rewritten. The resistance 元件 of the component 2 1 is the maximum 値Rl+112+ΔR1+AR2. In this way, the resistance of the billion element 2 is the largest. R1+R2+ Δ R1 + Δ R2 ' The first intermediate 値R 1 +R2 + Δ R 1 , the second intermediate 値Rl+R2+A R2, and the minimum 値R1+R2 are four kinds of resistance 値. When the difference ΔR1 is larger than the second resistance difference ΔR2 (Δ R1 > Δ R2 ), the first intermediate 成为 system becomes a large intermediate 値, and the second intermediate 成为 system becomes a small intermediate 値. When the first resistance difference Δ R1 is smaller than the second resistance difference -26- 201143079 Δ R2 (Δ R1 < Δ R2 ), the second intermediate raft is a relatively large intermediate ridge, and the first intermediate raft is a small intermediate ridge. By setting the first reference 値 between the maximum 値 and the middle 値, and setting the second reference 値 between the middle 値 and the minimum 値, and discriminating the three types of resistances of the maximum 値, the minimum 値, and the middle ,, In order to obtain a memory element 21 of 3 turns, a third reference 设置 is provided between the middle 値 and the middle 値, in addition to the first and second reference 値, and The four types of memory elements 2 1 can be obtained by discriminating four kinds of resistances in the middle of the middle, the middle of the small, and the smallest one. In the present invention, as shown in the cross-sectional view of Fig. 15, in addition to the first and second lower electrodes 38a and 38b, the lower portion of the lower free layer portion 3 7 is electrically connected to the lower portion. Electrode 44. When a voltage is applied between the upper electrode 35 and the read lower electrode 44, a tunneling current flows in the first and second elements 30, 312. Since the tunneling current flows in the upper and lower free magnetic layers 33 and 37 in the film thickness direction, the position is not at the first and second upper end portions 41a and 41b due to the tunneling current. The upper magnetic wall 39 or the lower magnetic wall 3 92 located at the first and second lower end portions 42a and 42b moves. In the memory element 2 1 of the present invention, it is not limited to the configuration in which the first and second upper free layer portions 33, 33, 2 are overlapped with each other as shown in FIG. As shown in Fig. 12, generally, the first and second upper free layer portions 33, 332 are separated from each other. When the first and second upper free layer portions 33, and 33 are separated from each other, the upper magnetic wall 3^ may be positioned at the first -27-201143079 and the second upper free layer portion 33, 332. Between the areas. Further, when the first and second upper free layer portions 33 and 332 are separated from each other, as shown in FIG. 13, it is also possible to set one of the intermediate electrodes (this is the first intermediate electrode). 3 4a ) is electrically connected to the region between the first and second upper free layer portions 33 and 332. The planar shape of the upper and lower free magnetic layers 33 and 37 of the present invention is not limited to the above-described general shape from the rectangular shape as long as the shape of the magnetic walls 39! and 392 can be formed inside. The shape after removal 〇 the magnetization direction of the fixed layer portion 31 and the first and second upper free layer portions 33, 33 2 and the lower free layer portion 37 of the present invention is not limited to the above-described general It is magnetized to be perpendicular to the film thickness direction, and may be magnetized in parallel with the film thickness direction. Next, a configuration of a memory device using the multi-turn memory element of the present invention will be described. Fig. 5 is a cross-sectional view showing an example of a memory device 9 such as MR AM. Here, a description will be given by using a configuration in which three memory elements 1 are used. Instead of the 3" memory element 1, the memory element 21 of the second example can also be used. Each of the memory devices 9 is provided with a plurality of first and second wirings 4 and 5. The first wiring 4 is disposed in parallel with each other at a predetermined interval, and the second wiring 5 is in a plane parallel to and different from the plane on which the first wiring 4 is disposed, and is connected to the first wiring 4 In this way, the first and second wirings 4 and 5 are buried in the interlayer insulating film 2 . In the vicinity of the three-dimensional intersection position of the first wiring 4 and the second wiring 5, the three-dimensional memory element 1 of the present invention is disposed in -28-201143079. Since the intersection of the first wiring 4 and the second wiring 5 is arranged in a matrix, the three memory elements 1 are arranged in a matrix. 3, the first and second upper electrodes 15! and 152 of the memory element 1 are electrically connected to the first wiring 4 that intersects in the vicinity, and the first lower electrode 14a is The second wiring 5 is electrically connected. The first and second wirings 4 and 5 are connected to the control device 7, and the measuring device 8 is connected to the measuring device 8. When the information is read, the control device 7 selects the first and second wirings 4 and 5, and flows the sensing current in the desired three-dimensional element 1, and the measuring device 8 is The conductance of the memory element 1 in which the current is sensed is measured, and the measurement result is transmitted to the control device 7. As described above, the conductance of the three-dimensional memory element 1 of the present invention can be obtained by three types of maximum chirp, minimum chirp, and intermediate chirp, and at the control device 7, at least the maximum chirp and minimum chirp of the conductance are set. The control device 7 compares the measurement result of the measuring device 8 with the measured conductivity, and determines whether the measurement result corresponds to the maximum 値, the minimum 値 or the maximum 値 and the minimum ( (intermediate 値) . The control device 7 associates the determined results with information such as "〇", "1", and "2", and reads them as information. Therefore, in the memory device 9, the first and second wirings 4 and 5, the control device 7, and the measuring device 8 constitute a reading means for reading information. Next, the writing instructions for the information change. In the memory device 9, -29-201143079 is provided with the third wiring 6 extending along the wiring of the second wiring 5. The second lower electrode 14b' of the memory element 1 is electrically connected to the third wiring 6. The control device 7 selects the second and third wirings 5 and 6, and causes the write current to flow to the desired three-dimensional memory element 1. The condition that the conductance of the three-dimensional memory element 1 is set to the maximum 値, the minimum 値, the direction of the write current of the middle 以及, and the length of the pulse width is extracted in advance and set in the control device 7. The control device 7 associates the information to be memorized with the conductance of the memory unit 1 and flows current to the second and third wirings 5 and 6 with an energization condition that is associated with the conductance. And the desired memory information is stored as a conductance in the memory element 1. In this manner, the second and third wirings 5 and 6 and the control device 7 constitute a rewriting means for rewriting the information. In the above description, although the conductance was measured and an electric conductivity of 3 得到 was obtained, the resistance 値 was measured and a resistance of 3 得到 was obtained. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] A plan view of a three-dimensional memory element of the present invention. Fig. 2 is a cross-sectional view taken along line A-A of the 3-inch memory element of the present invention. (Fig. 3) (a) to (d): A diagram for explaining the initialization of the magnetization direction of the free magnetic layer having a shape removed from a rectangular shape. -30- 201143079 [Fig. 4] (a) to (c): diagrams for explaining changes in the magnetization directions of the first and second free layer portions. Fig. 5 is a cross-sectional view showing an example of a memory device using three memory elements. Fig. 6 is a plan view showing an example of the arrangement of the first and second elements. Fig. 7 is a plan view of a three-dimensional element having a "U"-shaped free magnetic layer. Fig. 8 is a view for explaining the initialization of the magnetization direction of the "U"-shaped free magnetic layer. Fig. 9 is a plan view showing a memory element of a 3 値 or 4 本 according to the present invention. Fig. 10 is a cross-sectional view taken along the line B-B of the memory element of the present invention. [Fig. 11] (a) to (d): diagrams for explaining changes in the magnetization directions of the first and second upper free layer portions and the lower free layer portion. Fig. 12 is a cross-sectional view showing a memory element in which the first and second upper free layer portions are separated from each other. Fig. 13 is a cross-sectional view showing a second example of the elements of the first and second upper free layer portions separated from each other. [Fig. 14] A cross-sectional view of a 3-inch memory element having a lower electrode read. Fig. 15 is a cross-sectional view showing a three-dimensional or four-inch element having a lower electrode read. -31 - 201143079 [Fig. 16] A plan view of a 3-inch memory element having a free magnetic layer having an "L" shape. [Description of main component symbols] 1 : 3 値 memory element 1 〇 |, 3 〇 i: 1st element 1 〇 2, 302: 2nd element 111, 112: 1st, 2nd fixed layer part 1 2 : Insulation layer 12 !, 122: first and second insulating layer portions 13: free magnetic layers 13!, 132: first and second free layer portions 14a and 14b: first and second electrodes (first and second lower electrodes) 18a, 18c: first and second end portions 18b: intermediate portion 2 1 : memory element 31 : fixed layer 32 : upper insulating layer 32 〇 : upper insulating layer portion 3 3 : upper free magnetic layer 33, 3 32 : 1. Second upper self-application layer portions 34a and 34b: first and second upper writing electrodes (first and second intermediate electrodes) 3 6 : lower insulating layer - 32 - 201143079 37: lower free magnetic layer 3 7〇 Lower lower free layer portions 38a and 38b: first and second lower write electrodes (first and second lower electric portions 41a' to 41b: first and second upper end portions 42a and 42b: first and second lower end portions -33-